Method for improving compactness of tunneling oxide layer of Topcon battery

Abstract

The invention provides a method for improving the compactness of a Topcon cell tunneling oxide layer, and particularly relates to the technical field of solar cell preparation. According to the method for improving the compactness of the Topcon cell tunneling oxide layer, a pretreated silicon substrate enters a boat in a nitrogen atmosphere, then is heated under a vacuum condition and is oxidized in an oxygen atmosphere, and then is discharged out of the boat in the nitrogen atmosphere after being heated and oxidized in the oxygen atmosphere. According to the method for improving the compactness of the tunneling oxide layer of the Topcon battery, the boat entering and exiting state, the oxidation time and the oxidation temperature are strictly controlled, the vacuum state is kept in time when all technologies are switched, the phenomenon that the purity of the tunneling oxide layer is affected by the reaction of impurity gas and the silicon substrate is reduced, the obtained tunneling oxide layer is higher in purity and better in compactness, the passivation effect is improved, and the service life of the tunneling oxide layer is prolonged. And the conversion efficiency of the battery is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cell preparation, and in particular to a method for improving the density of a tunneling oxide layer of a Topcon cell. Background Art

[0002] Topcon solar cells utilize an ultra-thin tunneling oxide layer as a passivation layer. Topcon solar cells primarily utilize an N-type silicon substrate. On the back of the cell, a thin layer of doped polysilicon is deposited using a wet process to create an ultra-thin tunneling oxide layer. Together, these layers form a passivating contact structure, which is then reinforced by annealing and recrystallization.

[0003] Topcon's back-passivation contact structure provides good surface passivation for the back of the silicon wafer. The ultra-thin oxide layer allows majority carriers (electrons) to tunnel into the polysilicon layer while blocking the recombination of minority carriers (holes). The majority carriers are then transmitted laterally in the polysilicon layer and collected by the metal, thereby greatly reducing the metal contact recombination current and improving the open circuit voltage and short-circuit current of the battery.

[0004] Existing Topcon cells typically use LPCVD low-pressure thermal oxidation and PECVD plasma methods to prepare tunnel oxide layers. Although the tunnel oxide layer prepared by LPCVD low-pressure thermal oxidation is denser than that prepared by PECVD plasma, it still has some shortcomings:

[0005] First, air enters the furnace tube when entering and exiting the boat. The air contains oxygen, moisture, and impurities, which react rapidly with the silicon wafer to form a high-temperature impurity oxide layer. At the same time, the reaction becomes more intense during the heating process due to the increase in temperature, and the high-temperature impurity oxide layer grows faster, which reduces the density of the tunneling oxide layer and the passivation effect.

[0006] Secondly, during oxygen oxidation, the oxygen flow rate is low, and there is a large time difference in the oxygen reaction at different positions in the tube. It takes 450 seconds to complete the filling to near normal pressure, resulting in large differences in the oxygen atmosphere in different areas of the tube. The density of the tunneling oxide layer grown in the area with low oxygen atmosphere decreases, and the passivation effect is reduced.

[0007] Third, the thickness of the tunneling oxide layer prepared by the current LPCVD low-pressure thermal oxidation method is 0.8 to 2.0 nm. After standing for 3 hours, the thickness of the oxide layer increases by 0.3 to 0.5 nm. The large thickness increase is not conducive to controlling the precise thickness of the tunneling oxide layer, affecting the electron penetration performance, and thus affecting the performance of solar cells.

[0008] In view of this, the present invention is proposed. Summary of the Invention

[0009] One of the objectives of the present invention is to provide a method for improving the density of the tunneling oxide layer of a Topcon battery, aiming to solve at least one of the above-mentioned technical problems in the prior art.

[0010] A second object of the present invention is to provide a method for preparing a Topcon battery.

[0011] A third object of the present invention is to provide a Topcon battery.

[0012] In order to achieve the above-mentioned purpose of the present invention, the following technical solutions are adopted:

[0013] A first aspect of the present invention provides a method for improving the density of a tunnel oxide layer in a Topcon cell. A pretreated silicon substrate is placed in a boat under a nitrogen atmosphere, then heated under vacuum and oxidized in an oxygen atmosphere. After completion, the substrate is removed from the boat under a nitrogen atmosphere. Furthermore, a nitrogen atmosphere is created by introducing nitrogen gas, with a nitrogen flow rate of 30 to 100 slm into the boat.

[0014] Preferably, the oxygen atmosphere is obtained by introducing oxygen at a flow rate of 30 slm to 100 slm for a time of less than 100 s.

[0015] Preferably, the oxidation temperature is 600° C. to 800° C., and the oxidation time is 10s to 100s.

[0016] Preferably, a nitrogen atmosphere is obtained by introducing nitrogen gas, and the nitrogen gas flow rate out of the boat is 30 slm to 100 slm.

[0017] Furthermore, the machine for preparing the tunnel oxide layer includes an LPCVD machine, an annealing machine, an oxidation machine or a diffusion machine.

[0018] Furthermore, the thickness of the tunnel oxide layer is 0.8 nm to 2.0 nm, and the thickness of the tunnel oxide layer after standing for 3 hours is 0.9 nm to 2.1 nm.

[0019] Furthermore, the tunnel oxide layer is made of silicon oxide.

[0020] A second aspect of the present invention provides a method for preparing a Topcon battery, comprising the following steps:

[0021] The silicon substrate is textured, and then subjected to a first boron diffusion, SE, a second boron diffusion, and BSG removal in sequence to obtain a pre-treated silicon substrate;

[0022] Continuing to prepare a tunneling oxide layer, deposit an amorphous silicon layer, dope with phosphorus, anneal, passivate and metallize on the pretreated silicon substrate to obtain the Topcon cell;

[0023] Wherein, the method for preparing the tunnel oxide layer adopts the method described in the first aspect.

[0024] Furthermore, the silicon substrate includes N-type crystalline silicon.

[0025] Preferably, the resistivity of the N-type crystalline silicon is 0.5 Ω·cm to 5 Ω·cm.

[0026] Preferably, the thickness of the N-type crystalline silicon is 80 μm to 200 μm.

[0027] Furthermore, the boron source used in the primary boron diffusion and / or the secondary boron diffusion includes boron tribromide or boron trichloride.

[0028] Preferably, the temperature of the first boron diffusion is 800° C. to 950° C., and the time is 1 hour to 2 hours.

[0029] Preferably, the sheet resistance after the first boron diffusion is 100Ω / sqr to 140Ω / sqr.

[0030] Preferably, the temperature of the secondary boron diffusion is 900° C. to 1100° C., and the time is 2 h to 3 h.

[0031] Preferably, the sheet resistance after the secondary boron diffusion is 190Ω / sqr to 250Ω / sqr.

[0032] Furthermore, the deposition temperature of the amorphous silicon layer is 400° C. to 500° C.

[0033] Preferably, the thickness of the amorphous silicon layer is 100 nm to 200 nm.

[0034] Preferably, the phosphorus doping concentration is 10 20 / cm 3 Order of magnitude.

[0035] Preferably, the sheet resistance after annealing is 30Ω / sqr to 50Ω / sqr.

[0036] Preferably, double-sided passivation is performed on the phosphorus-doped silicon substrate, forming a passivation anti-reflection film on the front side and a passivation film on the back side.

[0037] Preferably, the passivation anti-reflection film and / or the passivation film is made of silicon nitride.

[0038] Preferably, the thickness of the passivation anti-reflection film is 60 nm to 100 nm.

[0039] Preferably, the passivation film has a thickness of 70 nm to 120 nm.

[0040] The third aspect of the present invention provides a Topcon battery, which is prepared using the preparation method described in the second aspect.

[0041] Compared with the prior art, the present invention has at least the following beneficial effects:

[0042] The method for improving the compactness of the tunneling oxide layer of a Topcon battery provided by the present invention strictly controls the state of entering and exiting the boat, the oxidation timing and temperature, and promptly maintains a vacuum state when switching between processes, thereby reducing the effect of the reaction between impurity gases and the silicon substrate on the purity of the tunneling oxide layer. The resulting tunneling oxide layer has higher purity and better compactness, thereby improving the passivation effect and the conversion efficiency of the battery.

[0043] The preparation method of the Topcon battery provided by the present invention, in view of the improvement of the density of the above-mentioned tunneling oxide layer, allows majority electrons to tunnel into the polysilicon layer while blocking the recombination of minority holes. Electrons in the polysilicon layer are not easy to spread through the tunneling oxide layer. Electrons are laterally transmitted in the polysilicon layer and collected by metal, thereby greatly reducing the metal contact recombination current and improving the open circuit voltage and fill factor of the battery.

[0044] The Topcon battery provided by the present invention, in view of the advantages brought by the above-mentioned preparation method, enables the Topcon battery prepared therefrom to have better performance and higher efficiency, expands the application scenarios of the Topcon battery, and promotes the development of downstream industries. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in combination with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0046] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present invention, are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0047] The first aspect of the present invention provides a method for improving the density of the tunnel oxide layer of a Topcon battery. The pretreated silicon substrate is placed in a boat under a nitrogen atmosphere, then heated under vacuum conditions and oxidized in an oxygen atmosphere. After completion, the substrate is taken out of the boat under a nitrogen atmosphere.

[0048] The method for improving the compactness of the tunneling oxide layer of a Topcon battery provided by the present invention strictly controls the state of entering and exiting the boat, the oxidation timing and temperature, and promptly maintains a vacuum state when switching between processes, thereby reducing the effect of the reaction between impurity gases and the silicon substrate on the purity of the tunneling oxide layer. The resulting tunneling oxide layer has higher purity and better compactness, thereby improving the passivation effect and the conversion efficiency of the battery.

[0049] When nitrogen is introduced into the boat, some air inevitably enters. The air contains oxygen, water vapor and impurities, which react quickly with the silicon wafer to form an impurity oxide layer. Before the reaction occurs, vacuum is applied as soon as possible to remove these impurities and gases to prevent the formation of more impurity oxide layers. After vacuuming, the temperature is raised, and then oxygen is introduced to carry out an oxidation reaction to prepare a tunnel oxide layer. After the reaction is completed, vacuum is applied in time to prevent excessive growth of the tunnel oxide layer. Finally, nitrogen is introduced to prevent air from contacting the high-temperature silicon wafer to ensure the purity of the tunnel oxide layer.

[0050] Furthermore, nitrogen atmosphere is obtained by introducing nitrogen gas, and the nitrogen flow rate into the boat is 30 slm to 100 slm. The nitrogen flow rate is within the above range to prevent air from entering the furnace tube.

[0051] Typically but not limiting, the nitrogen flow rate into the boat can be, for example, 30 slm, 40 slm, 50 slm, 60 slm, 70 slm, 80 slm, 90 slm or 100 slm, or any value within the range of 30 slm to 100 slm.

[0052] Preferably, the oxygen atmosphere is obtained by introducing oxygen at a flow rate of 30 slm to 100 slm for a time of less than 100 s.

[0053] During the oxidation process, an oxygen flow rate of 30slm to 100slm can quickly fill the furnace tube, and the filling is completed within 100s, reducing the difference in oxygen atmosphere in the tube, and comprehensively improving the density of the oxide layer. It can effectively improve the passivation effect and improve the battery conversion efficiency.

[0054] Typically but not limitatively, the oxygen flow rate may be, for example, 30 slm, 40 slm, 50 slm, 60 slm, 70 slm, 80 slm, 90 slm or 100 slm, or any value within the range of 30 slm to 100 slm.

[0055] Preferably, the oxidation temperature is 600° C. to 800° C., and the oxidation time is 10s to 100s.

[0056] Typically but not limitatively, the oxidation temperature can be, for example, 600°C, 650°C, 700°C, 750°C or 800°C, or any value within the range of 600°C to 800°C; the oxidation temperature can be, for example, 10s, 20s, 30s, 40s, 50s, 60s, 70s, 80s, 90s or 100s, or any value within the range of 10s to 100s.

[0057] Preferably, a nitrogen atmosphere is obtained by introducing nitrogen gas, and the nitrogen gas flow rate out of the boat is 30 slm to 100 slm.

[0058] Typically but not limiting, the nitrogen flow rate out of the boat can be, for example, 30 slm, 40 slm, 50 slm, 60 slm, 70 slm, 80 slm, 90 slm or 100 slm, or any value within the range of 30 slm to 100 slm.

[0059] Furthermore, the machine for preparing the tunnel oxide layer includes an LPCVD machine, an annealing machine, an oxidation machine or a diffusion machine.

[0060] Furthermore, the thickness of the tunnel oxide layer is 0.8 nm to 2.0 nm, and the thickness of the tunnel oxide layer after standing for 3 hours is 0.9 nm to 2.1 nm.

[0061] After the tunneling oxide layer prepared by the present invention is allowed to stand for 3 hours, the oxide layer thickness increases by only 0.05 to 0.15 nm, the density is improved, the stability is better, and the thickness is more accurately controlled, which will not differ much from expectations.

[0062] Typically but not limitatively, the thickness of the tunnel oxide layer before standing may be, for example, 0.8 nm, 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm or 2 nm, or any value within the range of 0.8 nm to 2.0 nm.

[0063] Furthermore, the tunnel oxide layer is made of silicon oxide.

[0064] Silicon oxide is typically, but not limited to, silicon monoxide or silicon dioxide.

[0065] A second aspect of the present invention provides a method for preparing a Topcon battery, comprising the following steps:

[0066] The silicon substrate is textured, and then subjected to a first boron diffusion, SE, a second boron diffusion, and BSG removal in sequence to obtain a pre-treated silicon substrate;

[0067] Continuing to prepare a tunneling oxide layer, deposit an amorphous silicon layer, dope with phosphorus, anneal, passivate and metallize on the pretreated silicon substrate to obtain the Topcon cell;

[0068] Wherein, the method for preparing the tunnel oxide layer adopts the method described in the first aspect.

[0069] The preparation method of the Topcon battery provided by the present invention, in view of the improvement of the density of the tunneling oxide layer, allows majority electrons to tunnel into the polysilicon layer while blocking the recombination of minority holes. Then, electrons are transmitted laterally in the polysilicon layer and collected by the metal, thereby greatly reducing the metal contact recombination current and improving the open circuit voltage and short circuit current of the battery.

[0070] Furthermore, the silicon substrate includes N-type crystalline silicon.

[0071] Preferably, the resistivity of the N-type crystalline silicon is 0.5 Ω·cm to 5 Ω·cm.

[0072] Typically but not limitatively, the resistivity of N-type crystalline silicon can be, for example, 0.5Ω·cm, 1Ω·cm, 1.5Ω·cm, 2Ω·cm, 2.5Ω·cm, 3Ω·cm, 3.5Ω·cm, 4Ω·cm, 4.5Ω·cm or 5Ω·cm, or any value within the range of 0.5Ω·cm to 5Ω·cm.

[0073] Preferably, the thickness of the N-type crystalline silicon is 80 μm to 200 μm.

[0074] Typically but not limitatively, the thickness of the N-type crystalline silicon may be, for example, 80 μm, 100 μm, 120 μm, 140 μm, 160 μm, 180 μm or 200 μm, or any value within the range of 80 μm to 200 μm.

[0075] Furthermore, the boron source used in the primary boron diffusion and / or the secondary boron diffusion includes boron tribromide or boron trichloride.

[0076] Preferably, the temperature of the first boron diffusion is 800° C. to 950° C., and the time is 1 hour to 2 hours.

[0077] Typically but not limitatively, the temperature of a single boron diffusion can be, for example, 800°C, 830°C, 860°C, 890°C, 910°C or 950°C, or any value within the range of 800°C to 950°C; the time of a single boron diffusion can be, for example, 60 min, 70 min, 80 min, 90 min, 100 min, 110 min or 120 min, or any value within the range of 1 h to 2 h.

[0078] Preferably, the sheet resistance after the first boron diffusion is 100Ω / sqr to 140Ω / sqr.

[0079] Typically but not limitatively, the square resistance after one boron diffusion may be, for example, 100Ω / sqr, 110Ω / sqr, 120Ω / sqr, 130Ω / sqr or 140Ω / sqr, or any value within the range of 100Ω / sqr to 140Ω / sqr.

[0080] Preferably, the temperature of the secondary boron diffusion is 900° C. to 1100° C., and the time is 2 h to 3 h.

[0081] Typically but not limitatively, the temperature of the secondary boron diffusion can be, for example, 900°C, 930°C, 960°C, 990°C, 1010°C or 1100°C, or any value within the range of 900°C to 1100°C; the time of the secondary boron diffusion can be, for example, 120min, 130min, 140min, 150min, 160min, 170min or 180min, or any value within the range of 2h to 3h.

[0082] Preferably, the sheet resistance after the secondary boron diffusion is 190Ω / sqr to 250Ω / sqr.

[0083] Typically but not limitatively, the square resistance after secondary boron diffusion may be, for example, 190Ω / sqr, 200Ω / sqr, 210Ω / sqr, 230Ω / sqr or 250Ω / sqr, or any value within the range of 190Ω / sqr to 250Ω / sqr.

[0084] Furthermore, the deposition temperature of the amorphous silicon layer is 400° C. to 500° C.

[0085] Typically but not limiting, the deposition temperature of the amorphous silicon layer may be, for example, 400°C, 420°C, 440°C, 460°C, 480°C or 500°C, or any value within the range of 400°C to 500°C.

[0086] Preferably, the thickness of the amorphous silicon layer is 100 nm to 200 nm.

[0087] Typically but not limitatively, the thickness of the amorphous silicon layer may be, for example, 100 nm, 120 nm, 140 nm, 160 nm, 180 nm or 200 nm, or any value within the range of 100 nm to 200 nm.

[0088] Preferably, the phosphorus doping concentration is 10 20 / cm 3 Order of magnitude.

[0089] Preferably, the sheet resistance after annealing is 30Ω / sqr to 50Ω / sqr.

[0090] Typically but not limitatively, the sheet resistance after annealing may be, for example, 30Ω / sqr, 35Ω / sqr, 40Ω / sqr, 45Ω / sqr or 50Ω / sqr, or any value within the range of 30Ω / sqr to 50Ω / sqr.

[0091] Preferably, double-sided passivation is performed on the phosphorus-doped silicon substrate, forming a passivation anti-reflection film on the front side and a passivation film on the back side.

[0092] Preferably, the passivation anti-reflection film and / or the passivation film is made of silicon nitride.

[0093] Preferably, the thickness of the passivation anti-reflection film is 60 nm to 100 nm.

[0094] Typically, but not limiting, the thickness of the passivation anti-reflection film may be, for example, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm, or any value within the range of 60 nm to 100 nm.

[0095] Preferably, the passivation film has a thickness of 70 nm to 120 nm.

[0096] Typically but not limitatively, the thickness of the passivation film may be, for example, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm or 120 nm, or any value within the range of 70 nm to 120 nm.

[0097] The third aspect of the present invention provides a Topcon battery, which is prepared using the preparation method described in the second aspect.

[0098] The Topcon battery provided by the present invention, in view of the advantages brought by the above-mentioned preparation method, enables the Topcon battery prepared therefrom to have better performance and higher efficiency, expands the application scenarios of the Topcon battery, and promotes the development of downstream industries.

[0099] The present invention is further illustrated below by specific examples and comparative examples. However, it should be understood that these examples are merely for the purpose of further explanation and should not be construed as limiting the present invention in any form. The raw materials used in the examples and comparative examples of the present invention, unless otherwise specified, were prepared under conventional conditions or conditions recommended by the manufacturer. Reagents or instruments used without manufacturer's indication are all commercially available conventional products.

[0100] Example 1

[0101] This embodiment provides a method for improving the density of a Topcon battery tunneling oxide layer, and the specific steps are as follows:

[0102] 1. Velveting:

[0103] N-type crystalline silicon wafers are selected as the substrate material, and a pyramid-shaped velvet structure is formed on its surface using cleaning and texturing technology to increase light absorption efficiency.

[0104] Among them, the resistivity of the N-type crystalline silicon wafer is 0.6Ω·cm and the thickness is 130μm.

[0105] 2. One-time Boron Expansion

[0106] The texturized silicon substrate is placed in a diffusion furnace for B diffusion. The boron source used is boron tribromide. The deposition temperature is 875°C and the deposition time is 1.5 hours to form a BSG layer on the front side. At this time, the square resistance of the silicon wafer is 120Ω / sqr.

[0107] 3. SE

[0108] The silicon substrate after the first boron diffusion is subjected to picosecond laser to propel the boron source in the BSG layer into the silicon substrate to form a heavily doped region.

[0109] 4. Secondary Boron Diffusion

[0110] The silicon substrate with the heavily doped area is placed in an oxidation furnace for oxidation treatment. The gas used is oxygen, the deposition temperature is 1000°C, and the time is 2.5 hours to form a BSG layer on the front side. At this time, the square resistance of the silicon wafer is 220Ω / sqr.

[0111] 5. Go to BSG

[0112] The silicon wafer after secondary boron expansion is placed in the BSG removal equipment to remove the BSG layer on the surface.

[0113] 6. Tunneling oxide layer

[0114] The silicon wafer with the BSG layer removed was placed in the LPCVD machine and N2 with a flow rate of 60 slm was introduced into the boat; then the machine was evacuated and the temperature was raised to 700°C, and O2 with a flow rate of 60 slm was continued to be introduced. The furnace tube was filled within 50 seconds and the oxidation reaction was carried out at the same time. Then the machine was evacuated and N2 with a flow rate of 60 slm was introduced out of the boat to obtain a silicon wafer with a tunnel oxide layer thickness of 1.2 nm.

[0115] During the process, the growth thickness trend of the tunnel oxide layer is monitored by a full-spectrum ellipsometer. Slices are taken from each tube and 5-9 points are tested on each slice. The silicon wafers are left to stand after thermal oxidation, and the oxide layer grows naturally with the standing time. The thickness of the tunnel oxide layer at the test points is measured to obtain the thickness growth trend, thereby monitoring the density of the tunnel oxide layer and obtaining a tunnel oxide layer of the target thickness.

[0116] Example 2

[0117] This embodiment provides a method for improving the density of a Topcon battery tunneling oxide layer, and the specific steps are as follows:

[0118] 1. Velveting:

[0119] N-type crystalline silicon wafers are selected as the substrate material, and a pyramid-shaped velvet structure is formed on its surface using cleaning and texturing technology to increase light absorption efficiency.

[0120] Among them, the resistivity of the N-type crystalline silicon wafer is 0.6Ω·cm and the thickness is 130μm.

[0121] 2. One-time Boron Expansion

[0122] The texturized silicon substrate is placed in a diffusion furnace for B diffusion on the silicon substrate. The boron source used is boron tribromide. The deposition temperature is 800℃ and the time is 2h to form a BSG layer on the front side. At this time, the square resistance of the silicon wafer is 138Ω / sqr.

[0123] 3. SE

[0124] The silicon substrate after the first boron diffusion is subjected to picosecond laser to propel the boron source in the BSG layer into the silicon substrate to form a heavily doped region.

[0125] 4. Secondary Boron Diffusion

[0126] The silicon substrate with the heavily doped area is placed in an oxidation furnace for oxidation treatment. The gas used is oxygen, the deposition temperature is 1100°C, and the time is 2 hours to form a BSG layer on the front side. At this time, the square resistance of the silicon wafer is 190Ω / sqr.

[0127] 5. Go to BSG

[0128] The silicon wafer after secondary boron expansion is placed in the BSG removal equipment to remove the BSG layer on the surface.

[0129] 6. Tunneling oxide layer

[0130] The silicon wafer with the BSG layer removed was placed in the LPCVD machine and N2 with a flow rate of 80 slm was introduced into the boat; then the machine was evacuated and the temperature was raised to 750°C, and O2 with a flow rate of 80 slm was continued to be introduced. The furnace tube was filled within 80 seconds and the oxidation reaction was carried out at the same time. Then the machine was evacuated and N2 with a flow rate of 80 slm was introduced out of the boat to obtain a silicon wafer with a tunnel oxide layer thickness of 1.5 nm.

[0131] During the process, the growth thickness trend of the tunnel oxide layer is monitored by a full-spectrum ellipsometer. Slices are taken from each tube and 5-9 points are tested on each slice. The silicon wafers are left to stand after thermal oxidation, and the oxide layer grows naturally with the standing time. The thickness of the tunnel oxide layer at the test points is measured to obtain the thickness growth trend, thereby monitoring the density of the tunnel oxide layer and obtaining a tunnel oxide layer of the target thickness.

[0132] Example 3

[0133] This embodiment provides a method for improving the density of a Topcon battery tunneling oxide layer, and the specific steps are as follows:

[0134] 1. Velveting:

[0135] N-type crystalline silicon wafers are selected as the substrate material, and a pyramid-shaped velvet structure is formed on its surface using cleaning and texturing technology to increase light absorption efficiency.

[0136] Among them, the resistivity of the N-type crystalline silicon wafer is 0.6Ω·cm and the thickness is 130μm.

[0137] 2. One-time Boron Expansion

[0138] The texturized silicon substrate is placed in a diffusion furnace for B diffusion on the silicon substrate. The boron source used is boron tribromide. The deposition temperature is 910°C and the time is 1 hour to form a BSG layer on the front side. At this time, the square resistance of the silicon wafer is 115Ω / sqr.

[0139] 3. SE

[0140] The silicon substrate after the first boron diffusion is subjected to picosecond laser to propel the boron source in the BSG layer into the silicon substrate to form a heavily doped region.

[0141] 4. Secondary Boron Diffusion

[0142] The silicon substrate with the heavily doped area is placed in an oxidation furnace for oxidation treatment. The gas used is oxygen, the deposition temperature is 1100°C, and the time is 2 hours to form a BSG layer on the front side. At this time, the square resistance of the silicon wafer is 211Ω / sqr.

[0143] 5. Go to BSG

[0144] The silicon wafer after secondary boron expansion is placed in the BSG removal equipment to remove the BSG layer on the surface.

[0145] 6. Tunneling oxide layer

[0146] The silicon wafer with the BSG layer removed was placed in the LPCVD machine and N2 with a flow rate of 40slm was introduced into the boat; then the machine was evacuated and the temperature was raised to 750℃, and O2 with a flow rate of 80slm was continued to be introduced. The furnace tube was filled within 80s and the oxidation reaction was carried out at the same time. Then the machine was evacuated and N2 with a flow rate of 40slm was introduced out of the boat to obtain a silicon wafer with a tunnel oxide layer thickness of 1.4nm.

[0147] During the process, the growth thickness trend of the tunnel oxide layer is monitored by a full-spectrum ellipsometer. Slices are taken from each tube and 5-9 points are tested on each slice. The silicon wafers are left to stand after thermal oxidation, and the oxide layer grows naturally with the standing time. The thickness of the tunnel oxide layer at the test points is measured to obtain the thickness growth trend, thereby monitoring the density of the tunnel oxide layer and obtaining a tunnel oxide layer of the target thickness.

[0148] Example 4

[0149] This embodiment provides a method for improving the density of a tunnel oxide layer of a Topcon battery. Unlike Example 1, the tunnel oxide layer preparation process is performed according to the following steps:

[0150] The silicon wafer with the BSG layer removed was placed in the LPCVD machine and N2 with a flow rate of 30 slm was introduced into the boat; then the machine was evacuated and the temperature was raised to 700°C, and O2 with a flow rate of 30 slm was continued to be introduced. The furnace tube was filled within 100 seconds and the oxidation reaction was carried out at the same time. Then the machine was evacuated and N2 with a flow rate of 30 slm was introduced out of the boat to obtain a silicon wafer with a tunneling oxide layer thickness of 0.9 nm.

[0151] The other steps are the same as those in Example 1 and will not be repeated here.

[0152] Example 5

[0153] This embodiment provides a method for improving the density of a tunnel oxide layer of a Topcon battery. Unlike Example 1, the tunnel oxide layer preparation process is performed according to the following steps:

[0154] The silicon wafer with the BSG layer removed was placed in the LPCVD machine and N2 with a flow rate of 100 slm was introduced into the boat; then the vacuum was evacuated and the temperature was raised to 700°C, and O2 with a flow rate of 100 slm was continued to be introduced. The furnace tube was filled within 50 seconds and the oxidation reaction was carried out at the same time. Then the vacuum was evacuated and N2 with a flow rate of 100 slm was introduced out of the boat to obtain a silicon wafer with a tunnel oxide layer thickness of 1.5 nm.

[0155] The other steps are the same as those in Example 1 and will not be repeated here.

[0156] Example 6

[0157] This embodiment provides a method for improving the density of a tunnel oxide layer of a Topcon battery. Unlike Example 1, the tunnel oxide layer preparation process is performed according to the following steps:

[0158] The silicon wafer with the BSG layer removed was placed in the LPCVD machine and N2 with a flow rate of 10slm was introduced into the boat; then the machine was evacuated and the temperature was raised to 700℃, and O2 with a flow rate of 10slm was continued to be introduced. The furnace tube was filled within 100s and the oxidation reaction was carried out at the same time. Then the machine was evacuated and N2 with a flow rate of 10slm was introduced out of the boat to obtain a silicon wafer with a tunneling oxide layer thickness of 0.8nm.

[0159] The other steps are the same as those in Example 1 and will not be repeated here.

[0160] Examples 7-12

[0161] These embodiments provide a Topcon cell, corresponding to the silicon wafer with a tunneling oxide layer obtained in Examples 1-6 being subjected to the following process:

[0162] 7. Amorphous silicon layer and phosphorus doping

[0163] For the cell with tunnel oxide layer, amorphous silicon is deposited by PECVD method, and PH3 gas is introduced for in-situ doping to obtain poly layer.

[0164] The deposition temperature of the poly layer is 450°C, the thickness of the poly layer is 150nm, and the doping concentration of PH3 gas is 10 20 / cm 3 Magnitude.

[0165] 8. Annealing

[0166] The cell with the poly layer is annealed.

[0167] The annealing temperature is 920°C, the annealing time is 2.5h, and the square resistance of the cell after annealing is 40Ω / sqr.

[0168] 10. Passivation

[0169] The annealed silicon wafers are passivated on both sides. The passivation film is made of silicon nitride. The thickness of the front anti-reflective passivation film is 80nm, and the thickness of the back passivation film is 95nm.

[0170] 11. Metallization

[0171] The passivated silicon wafer is metallized to obtain a Topcon cell.

[0172] Comparative Example 1

[0173] This embodiment provides a method for improving the density of a tunnel oxide layer of a Topcon battery. Unlike Example 1, the tunnel oxide layer preparation process is performed according to the following steps:

[0174] The silicon wafer with the BSG layer removed was placed in the LPCVD machine, and N2 with a flow rate of 10slm was introduced into the boat; then the temperature was raised to 700℃, and O2 with a flow rate of 10slm was introduced. The furnace tube was filled for 450s and the oxidation reaction was carried out at the same time. After the reaction was completed, the vacuum was pumped out, and N2 with a flow rate of 10slm was introduced out of the boat to obtain a silicon wafer with a tunneling oxide layer thickness of 0.8nm.

[0175] The other steps are the same as those in Example 1 and will not be repeated here.

[0176] Comparative Example 2

[0177] This embodiment provides a method for improving the density of a tunnel oxide layer of a Topcon battery. Unlike Example 1, the tunnel oxide layer preparation process is performed according to the following steps:

[0178] The silicon wafer with the BSG layer removed was placed in the LPCVD machine, and N2 with a flow rate of 100 slm was introduced into the boat; then the temperature was raised to 700°C, and O2 with a flow rate of 100 slm was introduced. The furnace tube was filled for 450 seconds and an oxidation reaction was carried out at the same time. After the reaction was completed, the vacuum was pumped out, and N2 with a flow rate of 100 slm was introduced out of the boat to obtain a silicon wafer with a tunneling oxide layer thickness of 0.8 nm.

[0179] The other steps are the same as those in Example 1 and will not be repeated here.

[0180] Comparative Example 3

[0181] This embodiment provides a method for improving the density of a tunnel oxide layer of a Topcon battery. Unlike Example 1, the tunnel oxide layer preparation process is performed according to the following steps:

[0182] The silicon wafer with the BSG layer removed was placed in the LPCVD machine and N2 with a flow rate of 60 slm was introduced into the boat; then the temperature was raised to 700°C, and O2 with a flow rate of 60 slm was continued to be introduced. The furnace tube was filled within 50 seconds and the oxidation reaction was carried out at the same time. Then N2 with a flow rate of 60 slm was introduced out of the boat to obtain a silicon wafer with a tunnel oxide layer thickness of 1.2 nm.

[0183] The other steps are the same as those in Example 1 and will not be repeated here.

[0184] Comparative Example 4

[0185] This embodiment provides a method for improving the density of a tunnel oxide layer of a Topcon battery. Unlike Example 1, the tunnel oxide layer preparation process is performed according to the following steps:

[0186] The silicon wafer with the BSG layer removed was placed in the LPCVD machine and N2 with a flow rate of 60 slm was introduced into the boat; then the machine was evacuated and the temperature was raised to 700°C, and O2 with a flow rate of 60 slm was continued to be introduced. The furnace tube was filled within 50 seconds and the oxidation reaction was carried out at the same time. Then N2 with a flow rate of 60 slm was introduced out of the boat to obtain a silicon wafer with a tunneling oxide layer thickness of 1.2 nm.

[0187] The other steps are the same as those in Example 1 and will not be repeated here.

[0188] Comparative Example 5

[0189] This embodiment provides a method for improving the density of a tunnel oxide layer of a Topcon battery. Unlike Example 1, the tunnel oxide layer preparation process is performed according to the following steps:

[0190] The silicon wafer with the BSG layer removed was placed in the LPCVD machine and N2 with a flow rate of 60 slm was introduced into the boat; then the temperature was raised to 700°C, and O2 with a flow rate of 60 slm was continued to be introduced. The furnace tube was filled within 50 seconds and the oxidation reaction was carried out at the same time. Then the machine was evacuated and N2 with a flow rate of 60 slm was introduced out of the boat to obtain a silicon wafer with a tunnel oxide layer thickness of 1.2 nm.

[0191] The other steps are the same as those in Example 1 and will not be repeated here.

[0192] Comparative Examples 6-10

[0193] These comparative examples provide a Topcon battery, which is prepared by using the silicon wafers with tunneling oxide layers obtained in comparative examples 1-5 according to the preparation methods of examples 7-12.

[0194] Test Example 1

[0195] The thickness stability of the silicon wafers with tunneling oxide layers obtained in Examples 1-6 and Comparative Examples 1-5 was monitored. Specifically, the thickness of the silicon wafers with tunneling oxide layers was measured after standing for 3 hours. The obtained data is shown in Table 1 below.

[0196] Table 1

[0197] Boat thickness / nm Thickness after standing for 3 hours / nm Example 1 1.2 1.25 Example 2 1.5 1.58 Example 3 1.4 1.5 Example 4 0.9 1.05 Example 5 1.5 1.59 Example 6 0.8 0.9 Comparative Example 1 0.8 1.3 Comparative Example 2 0.8 1.28 Comparative Example 3 1.2 1.56 Comparative Example 4 1.2 1.5 Comparative Example 5 1.2 1.6

[0198] As can be seen from Table 1, the thickness growth values ​​of Examples 1 to 6 after standing for 3 hours are 0.05 to 0.15 nm, and the thickness growth values ​​of Comparative Examples 1 to 5 after standing for 3 hours are 0.3 to 0.5 nm. The growth values ​​of the embodiments are smaller than those of the comparative examples, indicating that the tunneling oxide layer of the embodiments of the present invention has higher purity and better density.

[0199] Test Example 2

[0200] The Topcon batteries obtained in Examples 7-12 and Comparative Examples 6-10 were manufactured to the same specifications and subjected to electrical performance tests, including photoelectric conversion efficiency and open circuit voltage.

[0201] Specifically, an IV test was conducted at a temperature of 25° C. and an AM of 1.5G. The obtained data are shown in Table 2 below.

[0202] Table 2

[0203] Eta(%) Uoc(V) Isc(A) FF(%) Example 7 26.76 0.7357 18.506 86.65 Example 8 26.73 0.7356 18.500 86.63 Example 9 26.72 0.7341 18.511 86.69 Example 10 26.73 0.7356 18.500 86.63 Example 11 26.75 0.7356 18.522 86.55 Example 12 26.72 0.7356 18.501 86.59 Comparative Example 6 26.54 0.7333 18.455 86.47 Comparative Example 7 26.49 0.7318 18.516 86.22 Comparative Example 8 26.52 0.7312 18.527 86.32 Comparative Example 9 26.54 0.7326 18.511 86.29 Comparative Example 10 26.53 0.7332 18.484 86.31

[0204] As can be seen in Table 2, the open-circuit voltage and fill factor of the examples are both higher than those of the comparative examples, with the efficiency of the examples ranging from 26.72% to 26.76%, while that of the comparative examples ranges from 26.49% to 26.54%. The Topcon cell preparation method provided by the present invention improves the density of the tunneling oxide layer, allowing majority electrons to tunnel into the polysilicon layer while simultaneously preventing minority hole recombination. Electrons in the polysilicon layer are less likely to diffuse through the tunneling oxide layer, and electrons are transported laterally in the polysilicon layer and collected by the metal, thereby significantly reducing the metal contact recombination current, improving the open-circuit voltage and fill factor of the cell, and ultimately increasing the conversion efficiency of the cell.

[0205] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for improving the density of the tunneling oxide layer of a Topcon battery, characterized in that: The pre-treated silicon substrate is placed in a boat under a nitrogen atmosphere, then heated under vacuum conditions and oxidized under an oxygen atmosphere, and then taken out of the boat under a nitrogen atmosphere after completion.

2. The method according to claim 1, characterized in that A nitrogen atmosphere is obtained by introducing nitrogen gas, with the nitrogen flow rate into the boat being 30slm to 100slm; Preferably, the oxygen atmosphere is obtained by introducing oxygen at a flow rate of 30slm to 100slm for a time of less than 100s; Preferably, the oxidation temperature is 600° C. to 800° C., and the time is 10s to 100s; Preferably, a nitrogen atmosphere is obtained by introducing nitrogen gas, and the nitrogen gas flow rate out of the boat is 30 slm to 100 slm.

3. The method according to claim 1, characterized in that The machine for preparing the tunnel oxide layer includes an LPCVD machine, an annealing machine, an oxidation machine or a diffusion machine.

4. The method according to any one of claims 1 to 3, characterized in that The thickness of the tunnel oxide layer is 0.8 nm to 2.0 nm, and the thickness of the tunnel oxide layer after standing for 3 hours is 0.9 nm to 2.1 nm.

5. The method according to any one of claims 1 to 3, characterized in that The tunnel oxide layer is made of silicon oxide.

6. A method for preparing a Topcon battery, characterized in that: The following steps are involved: The silicon substrate is textured, and then subjected to a first boron diffusion, SE, a second boron diffusion, and BSG removal in sequence to obtain a pre-treated silicon substrate; Continuing to prepare a tunneling oxide layer, deposit an amorphous silicon layer, dope with phosphorus, anneal, passivate and metallize on the pretreated silicon substrate to obtain the Topcon cell; Wherein, the method for preparing the tunnel oxide layer adopts the method according to any one of claims 1 to 5.

7. The preparation method according to claim 6, characterized in that The silicon substrate comprises N-type crystalline silicon; Preferably, the resistivity of the N-type crystalline silicon is 0.5Ω·cm to 5Ω·cm; Preferably, the thickness of the N-type crystalline silicon is 80 μm to 200 μm.

8. The preparation method according to claim 6, characterized in that The boron source used in the primary boron diffusion and / or the secondary boron diffusion includes boron tribromide or boron trichloride; Preferably, the temperature of the first boron diffusion is 800° C. to 950° C., and the time is 1 h to 2 h; Preferably, the sheet resistance after the first boron expansion is 100Ω / sqr to 140Ω / sqr; Preferably, the temperature of the secondary boron diffusion is 900° C. to 1100° C., and the time is 2 h to 3 h; Preferably, the sheet resistance after the secondary boron diffusion is 190Ω / sqr to 250Ω / sqr.

9. The preparation method according to claim 6, characterized in that The deposition temperature of the amorphous silicon layer is 400° C. to 500° C. Preferably, the thickness of the amorphous silicon layer is 100 nm to 200 nm; Preferably, the phosphorus doping concentration is 10 20 / cm 3 Order of magnitude; Preferably, the sheet resistance after annealing is 30Ω / sqr to 50Ω / sqr; Preferably, double-sided passivation is performed on the phosphorus-doped silicon substrate, forming a passivation anti-reflection film on the front side and a passivation film on the back side; Preferably, the passivation anti-reflection film and / or the passivation film is made of silicon nitride; Preferably, the thickness of the passivation anti-reflection film is 60nm to 100nm; Preferably, the passivation film has a thickness of 70 nm to 120 nm.

10. A Topcon battery, characterized in that: The preparation method is described in any one of claims 6 to 8.