Semiconductor device, semiconductor device assembly, and vehicle

Abstract

This semiconductor device is provided with: a support conductor having a first main surface facing one side in the thickness direction; a plurality of four or more semiconductor elements disposed on the first main surface; and a sealing resin covering the plurality of semiconductor elements and the support conductor, the plurality of semiconductor elements being arranged side by side in a first direction orthogonal to a thickness direction, the plurality of semiconductor elements including a first semiconductor element and a second semiconductor element close to a center in the first direction, a first distance, which is a distance between the center of the first semiconductor element and the center of the second semiconductor element, is larger than the center of any one of the first semiconductor element and the second semiconductor element and is adjacent to any one of the first semiconductor element and the second semiconductor element in the first direction. The distance between the centers of the third semiconductor element or the fourth semiconductor element is a second distance.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a semiconductor device assembly, and a vehicle. Background Art

[0002] In the past, a semiconductor device having multiple power switching elements such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) was known. Such semiconductor devices are installed in all electronic devices from industrial equipment to home appliances, information terminals, and automotive equipment. Patent document 1 discloses a conventional semiconductor device. In the semiconductor device described in patent document 1, multiple semiconductor chips (semiconductor elements) are arranged on a lead (conductive portion). The multiple semiconductor chips are arranged in a straight line at predetermined intervals along the x direction perpendicular to the thickness direction of the lead.

[0003] When using the semiconductor device described above, heat is generated from the multiple semiconductor chips. Recently, with the increasing current in semiconductor devices, the amount of heat generated in the multiple semiconductor chips has increased. In the multiple semiconductor chips arranged as described above, the interference of heat generated within the multiple semiconductor chips also causes a temperature rise. Furthermore, in semiconductor chips arranged near the center of the arrangement of the multiple semiconductor chips, i.e., in the x-direction, the thermal interference with adjacent semiconductor chips is significant, potentially leading to heat concentration and a high temperature state. This thermal interference leads to an increase in thermal resistance, hindering the flow of high current through the semiconductor device.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: International Publication No. 2019 / 244372 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] One object of the present disclosure is to provide a semiconductor device that is improved compared to conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, one object of the present disclosure is to provide a semiconductor device that is suitable for suppressing interference of heat generated in a plurality of semiconductor elements and reducing thermal resistance.

[0009] Solutions to Problems

[0010] The semiconductor device provided by the first embodiment of the present disclosure includes: a conductive portion having a first main surface facing one side in the thickness direction and a first back surface facing a side opposite to the first main surface; a plurality of semiconductor elements, four or more, arranged on the first main surface; and a sealing resin covering the plurality of semiconductor elements and at least a portion of the conductive portion. The plurality of semiconductor elements are arranged in a first direction perpendicular to the thickness direction. When the number of the plurality of semiconductor elements is an even number, the plurality of semiconductor elements include a first semiconductor element and a second semiconductor element close to the center in the first direction, and a first distance between the center of the first semiconductor element and the center of the second semiconductor element is greater than a second distance, which is the distance between the center of either the first semiconductor element or the second semiconductor element and the center of the other semiconductor element adjacent to either the first semiconductor element or the second semiconductor element in the first direction. When the number of the plurality of semiconductor elements is an odd number, the plurality of semiconductor elements include: a third semiconductor element close to the center in the first direction; a fourth semiconductor element adjacent to the third semiconductor element on one side of the first direction; and a fifth semiconductor element adjacent to the third semiconductor element on the other side of the first direction, wherein a third distance between the center of the third semiconductor element and the center of the fourth semiconductor element, and a fourth distance between the center of the third semiconductor element and the center of the fifth semiconductor element, are both greater than a fifth distance, which is the distance between the center of either the fourth semiconductor element or the fifth semiconductor element and the center of the other semiconductor element adjacent to either the fourth semiconductor element or the fifth semiconductor element in the first direction.

[0011] According to a second aspect of the present disclosure, a semiconductor device assembly is provided, comprising: the semiconductor device according to the first aspect of the present disclosure; a cooler; and a cooling device for cooling the cooler. The second back surface of the support body is exposed from the sealing resin, and the cooler has a portion in contact with the second back surface.

[0012] According to a third aspect of the present disclosure, a vehicle is provided that includes a power conversion device including the semiconductor device according to the first aspect of the present disclosure.

[0013] Effects of the Invention

[0014] According to the above configuration, thermal interference among the plurality of semiconductor elements can be suppressed, thereby achieving a reduction in thermal resistance.

[0015] Other features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a perspective view showing a semiconductor device according to the first embodiment of the present disclosure.

[0017] Figure 2 It is a plan view showing the semiconductor device according to the first embodiment of the present disclosure.

[0018] Figure 3 It is a plan view showing the semiconductor device according to the first embodiment of the present disclosure.

[0019] Figure 4 It is a bottom view showing the semiconductor device according to the first embodiment of the present disclosure.

[0020] Figure 5 It is along Figure 3 Cross-sectional view of line VV.

[0021] Figure 6 It is along Figure 3 A cross-sectional view taken along line VI-VI.

[0022] Figure 7 It is along Figure 3 A cross-sectional view taken along line VII-VII.

[0023] Figure 8 It is along Figure 3 A cross-sectional view taken along line VIII-VIII.

[0024] Figure 9 This is a schematic plan view showing the arrangement of a plurality of semiconductor elements in the semiconductor device according to the first embodiment of the present disclosure.

[0025] Figure 10 It is a schematic diagram of a vehicle equipped with the semiconductor device according to the first embodiment of the present disclosure.

[0026] Figure 11 This is a cross-sectional view showing a first example of a semiconductor device module including the semiconductor device according to the first embodiment of the present disclosure.

[0027] Figure 12 Yes Figure 11 A block diagram of the structure of a semiconductor device component is shown.

[0028] Figure 13 This is a cross-sectional view showing a second example of a semiconductor device module including the semiconductor device according to the first embodiment of the present disclosure.

[0029] Figure 14 It is a schematic plan view showing a modified example of the arrangement of a plurality of semiconductor elements.

[0030] Figure 15It is a schematic plan view showing a modified example of the arrangement of a plurality of semiconductor elements.

[0031] Figure 16 It is a schematic plan view showing a modified example of the arrangement of a plurality of semiconductor elements.

[0032] Figure 17 It is a schematic plan view showing a modified example of the arrangement of a plurality of semiconductor elements.

[0033] Figure 18 It is a plan view showing a semiconductor device according to a second embodiment of the present disclosure.

[0034] Figure 19 It is along Figure 18 Cross-sectional view along line XIX-XIX.

[0035] Figure 20 It is along Figure 18 Cross-sectional view of line XX-XX.

[0036] Figure 21 It is along Figure 18 Cross-sectional view of line XXI-XXI.

[0037] Figure 22 This is a schematic plan view showing the arrangement of a plurality of semiconductor elements in a semiconductor device according to a second embodiment of the present disclosure.

[0038] Figure 23 It is a plan view showing a semiconductor device according to a third embodiment of the present disclosure.

[0039] Figure 24 This is a schematic plan view showing the arrangement of a plurality of semiconductor elements in a semiconductor device according to a third embodiment of the present disclosure.

[0040] Figure 25 is a schematic diagram of a vehicle including a semiconductor device according to a third embodiment of the present disclosure.

[0041] Figure 26 This is a schematic plan view showing the arrangement of a plurality of semiconductor elements in a semiconductor device according to a first modification of the third embodiment.

[0042] Figure 27 This is a schematic plan view showing the arrangement of a plurality of semiconductor elements in a semiconductor device according to a first modification of the third embodiment.

[0043] Figure 28 This is a schematic plan view showing the arrangement of a plurality of semiconductor elements in a semiconductor device according to a first modification of the third embodiment.

[0044] Figure 29This is a schematic plan view showing the arrangement of a plurality of semiconductor elements in a semiconductor device according to a first modification of the third embodiment. DETAILED DESCRIPTION

[0045] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0046] The terms “first,” “second,” and “third” in the present disclosure are used merely for identification and are not necessarily intended to place a sequence on these objects.

[0047] In the present disclosure, unless otherwise specified, “something A is formed on thing B” and “something A is formed on thing B” include “something A is directly formed on thing B” and “something A is formed on thing B while other objects are interposed between thing A and thing B”. Similarly, unless otherwise specified, “something A is configured on thing B” and “something A is configured on thing B” include “something A is directly configured on thing B” and “something else is interposed between thing A and thing B, and thing A is configured on thing B”. Similarly, “something A is located on thing B”, unless otherwise specified, includes “something A is in contact with thing B, thing A is located on thing B” and “something else is interposed between thing A and thing B, and thing A is located on thing B”. In addition, unless otherwise specified, “something A overlaps with thing B in a certain direction” includes “something A completely overlaps with thing B” and “something A overlaps with part of thing B”. In addition, in the present disclosure, “a certain surface A faces (one side or the other side of) direction B” is not limited to the case where the angle of surface A relative to direction B is 90°, but also includes the case where surface A is inclined relative to direction B.

[0048] First embodiment:

[0049] Figures 1 to 8 The semiconductor device A1 of the present embodiment includes a plurality of leads 1, a plurality of leads 2, a support 3, a support conductor 32, a plurality of semiconductor elements 4, a wiring portion 5, a thermistor 6, a plurality of wires 71, 72, 73, and 74, and a sealing resin 8.

[0050] Figure 1 It is a perspective view showing the semiconductor device A1. Figure 2 It is a top view showing the semiconductor device A1. Figure 3 It is a plan view showing the semiconductor device A1 , and is a view seen through the sealing resin 8 . Figure 4 It is a bottom view showing the semiconductor device A1. Figure 5 It is along Figure 3 Cross-sectional view of line VV. Figure 6 It is along Figure 3 A cross-sectional view taken along line VI-VI. Figure 7 It is along Figure 3 A cross-sectional view taken along line VII-VII. Figure 8 It is along Figure 3 The cross-sectional view of the VIII-VIII line. Figure 3 In FIG, the outer shape of the sealing resin 8 is represented by an imaginary line (two-dot chain line). Figures 5 to 8 , the wire 71 is omitted.

[0051] In the description of the semiconductor device A1, the thickness direction (top view direction) of the support body 3 is an example of the "thickness direction" of the present disclosure, referred to as the "thickness direction z". The direction perpendicular to the thickness direction z is an example of the "first direction" of the present disclosure, referred to as the "first direction x". The direction perpendicular to both the thickness direction z and the first direction x is an example of the "second direction" of the present disclosure, referred to as the "second direction y". Figure 2 、 Figure 3 In the figure, the left side is an example of "one side of the first direction" of the present disclosure, called "x1 side of the first direction x", and the right side is an example of "the other side of the first direction" of the present disclosure, called "x2 side of the first direction x". Figure 2 、 Figure 3 In the figure, the upper side is an example of "one side of the second direction" of the present disclosure, referred to as "y1 side of the second direction y", and the lower side is an example of "the other side of the second direction" of the present disclosure, referred to as "y2 side of the second direction y". Figures 5 to 8 In the figure, the upper side is an example of the "one side in the thickness direction" of the present disclosure, called the "z1 side in the thickness direction z", and the lower side is an example of the "other side in the thickness direction" of the present disclosure, called the "z2 side in the thickness direction z".

[0052] like Figure 3 、 Figures 5 to 8 As shown, the support body 3 and the support conductor 32 support a plurality of semiconductor elements 4. There is no limitation on the specific structure of the support body 3, and it may be, for example, composed of an AMB (Active Metal Brazing) substrate or a DBC (Direct Bonded Copper) substrate. In this embodiment, the support body 3 is defined as being composed of an insulating substrate 31 and a metal layer 33. The support body 3 has a second main surface 3a and a second back surface 3b. The second main surface 3a faces the z1 side in the thickness direction z. The second back surface 3b faces the side opposite to the second main surface 3a (the z2 side in the thickness direction z). The AMB substrate and the DBC substrate constituting the support body 3 include an insulating substrate 31, a support conductor 32 and a metal layer 33. The overall thickness (dimension in the thickness direction z) of the insulating substrate 31, the support conductor 32 and the metal layer 33 of the support body 3 is not particularly limited, and may be, for example, about 0.4 mm to 3.0 mm.

[0053] The insulating substrate 31 is, for example, a ceramic having excellent thermal conductivity. Examples of such ceramics include silicon nitride (SiN) and aluminum oxide (Al2O3). The insulating substrate 31 is not limited to ceramics, but may also be an insulating resin sheet or the like. The shape of the insulating substrate 31 is not particularly limited, and may be, for example, a rectangular shape when viewed from above. In the present embodiment, the insulating substrate 31 is in the shape of a long rectangle with the first direction x as the longitudinal direction when viewed in the thickness direction z. The insulating substrate 31 has a second principal surface 3a. The second principal surface 3a is a plane facing the z1 side of the thickness direction z. The thickness of the insulating substrate 31 is not particularly limited, and may be, for example, about 0.05 mm to 1.0 mm.

[0054] The support conductor 32 is formed on the second main surface 3a of the insulating substrate 31. The constituent material of the support conductor 32 includes, for example, copper (Cu). The constituent material may also include materials other than copper, such as aluminum (Al). By using the above-mentioned DBC substrate, for example, by patterning the copper foil bonded to the second main surface 3a, the support conductor 32 including the first conductor portion 321 to the eighth conductor portion 328 described later can be easily formed. The support conductor 32 has a first main surface 32a and a first back surface 32b. The first main surface 32a faces the z1 side in the thickness direction z. The first back surface 32b faces the side opposite to the first main surface 32a (the z2 side in the thickness direction z) and is opposite to the second main surface 3a. The thickness of the support conductor 32 is not particularly limited and is, for example, about 0.1 mm to 1.5 mm.

[0055] The supporting conductor 32 includes a first conductor portion 321, a second conductor portion 322, a third conductor portion 323, a fourth conductor portion 324, a fifth conductor portion 325, a sixth conductor portion 326, a seventh conductor portion 327, and an eighth conductor portion 328. The surfaces of the first to eighth conductor portions 321 to 328 may be plated with silver (Ag), for example.

[0056] The first conductor portion 321 is arranged on the second principal surface 3a of the insulating substrate 31 near the center in the first direction x. The first conductor portion 321 supports any one of the plurality of semiconductor elements 4. The second conductor portion 322 is arranged on the x2 side in the first direction x relative to the first conductor portion 321 and is adjacent to the first conductor portion 321. The second conductor portion 322 supports any one of the plurality of semiconductor elements 4. The third conductor portion is arranged on the x1 side in the first direction x relative to the first conductor portion 321 and is adjacent to the first conductor portion 321. The third conductor portion 323 supports any one of the plurality of semiconductor elements 4. The fourth conductor portion 324 is arranged on the x1 side in the first direction x relative to the third conductor portion 323 and is adjacent to the third conductor portion 323. The fourth conductor portion 324 supports any one of the plurality of semiconductor elements 4.

[0057] The fifth and sixth conductor portions 325 and 326 are arranged near a corner of the insulating substrate 31 on the x2 side in the first direction x and on the y1 side in the second direction y. A wire 73 is bonded to the fifth conductor portion 325. A wire 72 is bonded to the sixth conductor portion 326. The seventh and eighth conductor portions 327 and 328 are arranged near a corner of the insulating substrate 31 on the x1 side in the first direction x and on the y1 side in the second direction y. The seventh and eighth conductor portions 327 and 328 are located on the x1 side in the first direction x relative to the third conductor portion 323 and on the y1 side in the second direction y relative to the fourth conductor portion 324. The wire 73 is bonded to the seventh conductor portion 327. The wire 72 is bonded to the eighth conductor portion 328. The support conductor 32 that supports the plurality of semiconductor elements 4 is an example of a "conductive portion" in this disclosure.

[0058] The metal layer 33 is bonded to the lower surface of the insulating substrate 31 (the surface facing the z2 side of the thickness direction z). The constituent material of the metal layer 33 is the same as the constituent material of the support conductor 32. The metal layer 33 has a second back surface 3b. The second back surface 3b is a plane facing the z2 side of the thickness direction z. In the present embodiment, the second back surface 3b is exposed from the sealing resin 8. A heat dissipation component (such as a radiator) not shown in the figure can be installed on the second back surface 3b. The heat capacity of the structure (such as an AMB substrate, a DBC substrate) composed of the support conductor 32 and the support body 3 (insulating substrate 31 and metal layer 33) is, for example, 0.01 to 15 J / K. In addition, the thermal resistance of the structure (such as an AMB substrate, a DBC substrate) composed of the support conductor 32 and the support body 3 is, for example, 0.0003 to 1.5 K / W.

[0059] The wiring portion 5 is formed on the second main surface 3a of the insulating substrate 31. The wiring portion 5 is made of a conductive material. The conductive material constituting the wiring portion 5 is not particularly limited. As the conductive material of the wiring portion 5, for example, materials including silver (Ag), copper (Cu), gold (Au), etc. can be cited. In the following description, the case where the wiring portion 5 includes silver is taken as an example. It should be noted that the wiring portion 5 may include copper instead of silver, or gold instead of silver or copper. Alternatively, the wiring portion 5 may also include Ag-Pt or Ag-Pd. The method for forming the wiring portion 5 is not limited, for example, it is formed by firing a paste including these metals. The thickness of the wiring portion 5 is not particularly limited, and is, for example, about 5μm to 30μm. The thickness of the wiring portion 5 is smaller than the thickness of the above-mentioned support conductor 32.

[0060] The shape of the wiring portion 5 is not particularly limited. Figure 3As shown, the wiring portion 5 includes two wirings 501. The two wirings 501 are arranged near a corner of the insulating substrate 31 on the x1 side in the first direction x and on the y1 side in the second direction y. The two wirings 501 are spaced apart and arranged side by side in the second direction y. Each wiring 501 has a pad portion 502. The pad portion 502 is located at the end of the wiring 501 on the x2 side in the first direction x. Each terminal of the thermistor 6 is bonded to the two pad portions 502.

[0061] The multiple leads 1 are composed of metal, for example, having a higher thermal conductivity than the insulating substrate 31. The metal constituting the lead 1 is not particularly limited, and is, for example, copper, aluminum, iron (Fe), oxygen-free copper, or an alloy thereof (for example, Cu-Sn alloy, Cu-Zr alloy, Cu-Fe alloy, etc.). In addition, the multiple leads 1 may also be plated with nickel (Ni). The multiple leads 1 can be formed, for example, by a stamping process in which a mold is pressed against a metal plate, or by patterning the metal plate by etching. In addition, the method for forming the multiple leads 1 is not limited. The thickness of each lead 1 is not particularly limited, and is, for example, about 0.4 mm to 0.8 mm. The leads 1 are separated from each other.

[0062] In this embodiment, the plurality of leads 1 include a lead 11, a lead 12, a lead 13, a lead 14, and a lead 15. The leads 11, the leads 12, the leads 13, the leads 14, and the leads 15 constitute a conductive path to the semiconductor element 4, extending from the sealing resin 8 toward the y2 side in the second direction y (at Figure 2 The side surface (the resin side surface 86 described later) of the lower side in the figure protrudes.

[0063] The lead 11 is arranged on the supporting conductor 32, and in this embodiment, is arranged on the second conductor portion 322. Figure 7 As shown, the lead 11 is bonded to the second conductor 322 via a conductive bonding material 19. The conductive bonding material 19 only needs to bond the lead 11 to the second conductor 322 and electrically connect the lead 11 to the second conductor 322. For example, silver paste, copper paste, or solder is used for the conductive bonding material 19.

[0064] The structure of the lead 11 is not particularly limited. Figure 3 、 Figure 7 As shown, the lead 11 is described by being divided into a connection end portion 111 , a protruding portion 112 , an inclined portion 113 , and a parallel portion 114 .

[0065] The connection end portion 111 is rectangular in a plan view and is the portion that is bonded to the second conductor portion 322. The connection end portion 111 is conductively bonded to the end portion of the second conductor portion 322 on the y2 side in the second direction y via the conductive bonding material 19. The inclined portion 113 and the parallel portion 114 are covered by the sealing resin 8. The inclined portion 113 is connected to the connection end portion 111 and the parallel portion 114 and is inclined relative to the connection end portion 111 and the parallel portion 114. The parallel portion 114 is connected to the inclined portion 113 and the protrusion 112 and is parallel to the connection end portion 111. The protrusion 112 is connected to the end of the parallel portion 114 and is the portion of the lead 11 that protrudes from the sealing resin 8. In the illustrated example, two protrusions 112 are spaced apart in the first direction x. Each protrusion 112 protrudes in the second direction y toward the side opposite to the connection end portion 111. The protrusions 112 are used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the example shown in the drawings, the protruding portion 112 is bent in the thickness direction z toward the side toward which the second main surface 3 a of the insulating substrate 31 faces.

[0066] The lead 12 is arranged on the support conductor 32, and in this embodiment, is arranged on the first conductor portion 321. The lead 12 is bonded to the first conductor portion 321 via a conductive bonding material. The structure of the lead 12 is not particularly limited. In this embodiment, as shown in FIG. Figure 3 As shown, the lead 12 is described by being divided into a connection end portion 121 , a protruding portion 122 , an inclined portion 123 , and a parallel portion 124 .

[0067] The connection end portion 121 is rectangular in a plan view and is the portion joined to the first conductor portion 321. The connection end portion 121 is conductively joined to the end portion of the first conductor portion 321 on the y2 side in the second direction y via a conductive bonding material. The inclined portion 123 and the parallel portion 124 are covered with the sealing resin 8. The inclined portion 123 is connected to the connection end portion 121 and the parallel portion 124 and is inclined relative to the connection end portion 121 and the parallel portion 124. The parallel portion 124 is connected to the inclined portion 123 and the protrusion 122 and is parallel to the connection end portion 121. The wire 71 is joined to the parallel portion 124. The protrusion 122 is connected to the end of the parallel portion 124 and is the portion of the lead 12 that protrudes from the sealing resin 8. The protrusion 122 protrudes in the second direction y to the side opposite to the connection end portion 121. The protrusion 122 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the example shown in the drawings, the protruding portion 122 is bent in the thickness direction z toward the side toward which the second main surface 3 a of the insulating substrate 31 faces.

[0068] The lead 13 is arranged on the support conductor 32, and in this embodiment, is arranged on the third conductor portion 323. Figure 6As shown, the lead 13 is bonded to the third conductor portion 323 via the conductive bonding material 19. The structure of the lead 13 is not particularly limited. Figure 3 、 Figure 6 As shown in FIG. 1 , the lead 13 is described by being divided into a connection end portion 131 , a protruding portion 132 , an inclined portion 133 , and a parallel portion 134 .

[0069] The connection end portion 131 is rectangular in a plan view and is the portion joined to the third conductor portion 323. The connection end portion 131 is conductively joined to the end portion of the third conductor portion 323 on the y2 side in the second direction y via the conductive bonding material 19. The inclined portion 133 and the parallel portion 134 are covered with the sealing resin 8. The inclined portion 133 is connected to the connection end portion 131 and the parallel portion 134 and is inclined relative to the connection end portion 131 and the parallel portion 134. The parallel portion 134 is connected to the inclined portion 133 and the protrusion 132 and is parallel to the connection end portion 131. The wire 71 is joined to the parallel portion 134. The protrusion 132 is connected to the end of the parallel portion 134 and is the portion of the lead 13 that protrudes from the sealing resin 8. The protrusion 132 protrudes in the second direction y to the side opposite to the connection end portion 131. The protrusion 132 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the example shown in the drawings, the protrusion 132 is bent in the thickness direction z toward the side toward which the second main surface 3 a of the insulating substrate 31 faces.

[0070] The lead 14 is arranged on the support conductor 32, and in this embodiment, is arranged on the fourth conductor portion 324. The lead 14 is bonded to the fourth conductor portion 324 via a conductive bonding material. The structure of the lead 14 is not particularly limited. In this embodiment, Figure 3 As shown, the lead 14 is described by being divided into a connection end portion 141 , a protruding portion 142 , an inclined portion 143 , and a parallel portion 144 .

[0071] The connection end portion 141 is rectangular in a plan view and is the portion joined to the fourth conductor portion 324. The connection end portion 141 is conductively joined to the end portion of the fourth conductor portion 324 on the y2 side in the second direction y via a conductive bonding material. The inclined portion 143 and the parallel portion 144 are covered with the sealing resin 8. The inclined portion 143 is connected to the connection end portion 141 and the parallel portion 144 and is inclined relative to the connection end portion 141 and the parallel portion 144. The parallel portion 144 is connected to the inclined portion 143 and the protrusion 142 and is parallel to the connection end portion 141. The wire 71 is joined to the parallel portion 144. The protrusion 142 is connected to the end of the parallel portion 144 and is the portion of the lead 14 that protrudes from the sealing resin 8. The protrusion 142 protrudes in the second direction y to the side opposite to the connection end portion 141. The protrusion 142 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the example shown in the drawings, the protruding portion 142 is bent in the thickness direction z toward the side toward which the second main surface 3 a of the insulating substrate 31 faces.

[0072] In this embodiment, the lead 15 is not arranged on the support conductor 32, but is supported by the sealing resin 8. The lead 15 does not include a portion corresponding to the connection end portion 131 and the inclined portion 133 of the lead 13. In addition, the structure of the lead 15 is not limited to this. In this embodiment, as shown in FIG. Figure 3 As shown, the lead 15 is described by being divided into a protruding portion 152 and a parallel portion 154 .

[0073] Parallel portion 154 is covered with sealing resin 8. Parallel portion 154 is parallel to support conductor 32. Wire 71 is bonded to parallel portion 154. Protrusion 152 is connected to the end of parallel portion 154 and is the portion of lead 15 that protrudes from sealing resin 8. Protrusion 152 protrudes from sealing resin 8 toward the y2 side in the second direction y. Protrusion 152 is used, for example, to electrically connect semiconductor device A1 to an external circuit. In the illustrated example, protrusion 152 is bent in the thickness direction z toward the side toward which second principal surface 3a of insulating substrate 31 faces.

[0074] The multiple leads 2 are composed of metal, for example, the thermal conductivity is higher than that of the insulating substrate 31. The metal constituting the lead 2 is not particularly limited, and is, for example, copper, aluminum, iron (Fe), oxygen-free copper, or an alloy thereof (for example, Cu-Sn alloy, Cu-Zr alloy, Cu-Fe alloy, etc.). In addition, the multiple leads 2 may also be plated with nickel (Ni). The multiple leads 2 can be formed, for example, by a stamping process in which a mold is pressed against a metal plate, or by patterning the metal plate by etching. In addition, the method for forming the multiple leads 2 is not limited. The thickness of each lead 2 is not particularly limited, and is, for example, about 0.4 mm to 0.8 mm. The leads 2 are separated from each other.

[0075] In this embodiment, the plurality of leads 2 include a plurality of leads 21, a plurality of leads 22, and two leads 23. The leads 21 and the leads 22 constitute a conductive path to a source electrode 43 and a gate electrode 44 of the semiconductor element 4, which will be described later. The conductive path extends from the sealing resin 8 toward the y1 side in the second direction y (at the y1 side). Figure 2 The two leads 23 form a conductive path to the thermistor 6 and protrude from the side surface of the sealing resin 8 facing the y1 side in the second direction y.

[0076] The plurality of leads 21 are not arranged on the supporting conductor 32, but are supported by the sealing resin 8. The plurality of leads 21 are arranged at intervals in the first direction x. The structure of the lead 21 is not particularly limited. In this embodiment, as shown in FIG. Figure 3 、 Figure 6 As shown, the lead 21 is described by being divided into a protruding portion 212 and a parallel portion 214 .

[0077] The parallel portion 214 is covered with the sealing resin 8. The parallel portion 214 is parallel to the support conductor 32. The wire 73 is bonded to the parallel portion 214. The protrusion 212 is connected to the end of the parallel portion 214 and is the portion of the lead 21 that protrudes from the sealing resin 8. The protrusion 212 protrudes from the sealing resin 8 toward the y1 side in the second direction y. The protrusion 212 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protrusion 212 is bent in the thickness direction z toward the side toward which the second principal surface 3a of the insulating substrate 31 faces.

[0078] The plurality of leads 22 are not arranged on the support conductor 32, but are supported by the sealing resin 8. The plurality of leads 22 are arranged at intervals in the first direction x. The plurality of leads 22 are arranged close to any one of the plurality of leads 21 in pairs. The structure of the lead 22 is not particularly limited. In this embodiment, as shown in FIG. Figure 3 、 Figure 7 As shown, the lead 22 is described by being divided into a protruding portion 222 and a parallel portion 224 .

[0079] The parallel portion 224 is covered with the sealing resin 8. The parallel portion 224 is parallel to the support conductor 32. The wire 72 is bonded to the parallel portion 224. The protrusion 222 is connected to the end of the parallel portion 224 and is the portion of the lead 22 that protrudes from the sealing resin 8. The protrusion 222 protrudes from the sealing resin 8 toward the y1 side in the second direction y. The protrusion 222 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protrusion 222 is bent in the thickness direction z toward the side toward which the second principal surface 3a of the insulating substrate 31 faces.

[0080] The two leads 23 are not respectively arranged on the supporting conductor 32, but are supported by the sealing resin 8. The two leads 23 are arranged in a row in the first direction x. The structure of the leads 23 is not particularly limited. In this embodiment, as shown in FIG. Figure 3 、 Figure 5 As shown, the lead 23 is divided into a protruding portion 232 and a parallel portion 234 for description.

[0081] The parallel portion 234 is covered with the sealing resin 8. The parallel portion 234 is parallel to the support conductor 32. The wire 74 is bonded to the parallel portion 234. The protrusion 232 is connected to the end of the parallel portion 234 and is the portion of the lead 23 that protrudes from the sealing resin 8. The protrusion 232 protrudes from the sealing resin 8 toward the y1 side in the second direction y. The protrusion 232 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protrusion 232 bends in the thickness direction z toward the side toward which the second principal surface 3a of the insulating substrate 31 faces.

[0082] The plurality of semiconductor elements 4 are electronic components that serve as the functional core of the semiconductor device A1, and in this embodiment, are switching elements. The plurality of semiconductor elements 4 are arranged on the first main surface 32a of the support conductor 32. Specifically, four or more semiconductor elements 4 are arranged separately from each other, and each of the plurality of semiconductor elements 4 is supported by any one of the first conductor portion 321 to the fourth conductor portion 324 of the support conductor 32. In this embodiment, the plurality of semiconductor elements 4 includes semiconductor elements 40A to 40F. In addition, in the example shown in the figure, there are six semiconductor elements 40A to 40F, but this is only an example, and the number of semiconductor elements 4 is not limited as long as it is four or more.

[0083] The semiconductor element 4 (each semiconductor element 40A to 40F) is composed of, for example, at least one of a wide bandgap semiconductor and an ultra-wide bandgap semiconductor. Examples of wide bandgap semiconductors include SiC (silicon carbide) and GaN (gallium nitride). Examples of ultra-wide bandgap semiconductors include Ga2O3 (gallium oxide) and C (diamond). In the present embodiment, the semiconductor element 4 (each semiconductor element 40A to 40F) is, for example, a MOSFET (SiC MOSFET (metal-oxide-semiconductor field-effect transistor)) composed of a SiC (silicon carbide) substrate. In addition, the semiconductor element 4 may be a MOSFET composed of a Si (silicon) substrate instead of a SiC substrate, and may include, for example, an IGBT element. In addition, it may be a MOSFET including GaN (gallium nitride). In addition, the semiconductor element 4 may be a diode instead of the above-mentioned switching element.

[0084] like Figure 3 、 Figures 5 to 8 As shown, the semiconductor element 4 is a rectangular plate in a plan view, and includes an element main surface 41, an element back surface 42, a source electrode 43, a gate electrode 44, and a drain electrode 45. The element main surface 41 and the element back surface 42 face opposite sides in the thickness direction z. The element main surface 41 is a surface facing the z1 side in the thickness direction z. The element back surface 42 is a surface facing the z2 side in the thickness direction z. Figure 3 As shown in FIG, a source electrode 43 and a gate electrode 44 are arranged on the element main surface 41. Figures 5 to 7 As shown, a drain electrode 45 is arranged on the back surface 42 of the element. The shapes and arrangements of the source electrode 43, gate electrode 44, and drain electrode 45 are not limited. In the illustrated example, the source electrode 43 is larger than the gate electrode 44 when viewed in the thickness direction z. Furthermore, the source electrode 43 is composed of two separate regions when viewed in the thickness direction z. The heat capacity of each semiconductor element 4 is, for example, 0.0001 to 0.5 J / K. Furthermore, the thermal resistance of each semiconductor element 4 is, for example, 0.0003 to 1.5 K / W.

[0085] like Figure 3 、 Figure 7 、 Figure 8 As shown, the semiconductor elements 40A, 40B, and 40C are arranged on the second conductor portion 322. Figure 7 、 Figure 8 As shown, the semiconductor elements 40A, 40B, and 40C are bonded to the second conductor portion 322 with the back surface 42 thereof facing the second conductor portion 322 via the conductive bonding material 47. Thus, the drain electrodes 45 of the semiconductor elements 40A, 40B, and 40C are electrically connected to the second conductor portion 322 via the conductive bonding material 47. The conductive bonding material 47 may be made of, for example, silver paste, copper paste, or solder. Figure 3 As shown, source electrode 43 of semiconductor element 40A is conductively connected to lead 12 via wire 71. Source electrode 43 of semiconductor element 40B is conductively connected to lead 13 via wire 71. Source electrode 43 of semiconductor element 40C is conductively connected to lead 14 via wire 71. Wire 71 is made of, for example, aluminum (Al) or copper (Cu). The material, wire diameter, and number of wires 71 are not limited.

[0086] like Figure 3 As shown, the semiconductor element 40D is disposed on the first conductor portion 321. The semiconductor element 40D is bonded to the second conductor portion 322 via a conductive bonding material (not shown) with the element back surface 42 facing the first conductor portion 321. As a result, the drain electrode 45 of the semiconductor element 40D is conductively connected to the first conductor portion 321 via the conductive bonding material. The source electrode 43 of the semiconductor element 40D is conductively connected to the lead 15 via a wire 71.

[0087] like Figure 3 、 Figure 6 、 Figure 8 As shown, the semiconductor element 40E is arranged on the third conductor portion 323. Figure 6 、 Figure 8 As shown, the semiconductor element 40E has its back surface 42 facing the third conductor portion 323 and is bonded to the third conductor portion 323 via a conductive bonding material 47. Thus, the drain electrode 45 of the semiconductor element 40E is conductively connected to the third conductor portion 323 via the conductive bonding material 47. Figure 3 As shown, the source electrode 43 of the semiconductor element 40E is conductively connected to the lead 15 via a wire 71 .

[0088] like Figure 3 、 Figure 5 As shown, the semiconductor element 40F is disposed on the fourth conductor portion 324. Figure 5 As shown, the semiconductor element 40F has its back surface 42 facing the fourth conductor portion 324 and is bonded to the fourth conductor portion 324 via the conductive bonding material 47. Thus, the drain electrode 45 of the semiconductor element 40F is conductively connected to the fourth conductor portion 324 via the conductive bonding material 47. Figure 3 As shown, the source electrode 43 of the semiconductor element 40F is conductively connected to the lead 15 via a wire 71 .

[0089] The gate electrode 44 of the semiconductor element 40A is connected to the sixth conductor portion 326 via a wire 72, and the sixth conductor portion 326 is connected to the lead 22 via the wire 72. The gate electrode 44 of the semiconductor element 40A is conductively connected to the lead 22 via the wire 72 and the sixth conductor portion 326. The lead 22, conductively connected to the gate electrode 44 of the semiconductor element 40A, is a terminal (gate terminal) for inputting drive signals to the semiconductor element 40A. The source electrode 43 of the semiconductor element 40A is connected to the fifth conductor portion 325 via a wire 73, and the fifth conductor portion 325 is connected to the lead 21 via the wire 73. The source electrode 43 of the semiconductor element 40A is conductively connected to the lead 21 via the wire 73 and the fifth conductor portion 325. The lead 22, conductively connected to the source electrode 43 of the semiconductor element 40A, is a terminal (source sense terminal) for detecting source signals of the semiconductor element 40A. The conductive wires 72 and 73 are made of, for example, gold (Au), silver (Ag), copper (Cu), aluminum (Al), etc. The material, wire diameter, and number of the conductive wires 72 and 73 are not limited.

[0090] Gate electrode 44 of semiconductor element 40B is conductively connected to lead 22 via wire 72. Lead 22, conductively connected to gate electrode 44 of semiconductor element 40B, serves as a gate terminal of semiconductor element 40B. Source electrode 43 of semiconductor element 40B is conductively connected to lead 21 via wire 73. Lead 21, conductively connected to source electrode 43 of semiconductor element 40B, serves as a source sense terminal of semiconductor element 40B.

[0091] Gate electrode 44 of semiconductor element 40C is conductively connected to lead 22 via wire 72. Lead 22 conductively connected to gate electrode 44 of semiconductor element 40C serves as a gate terminal of semiconductor element 40C. Source electrode 43 of semiconductor element 40C is conductively connected to lead 21 via wire 73. Lead 21 conductively connected to source electrode 43 of semiconductor element 40C serves as a source sense terminal of semiconductor element 40C.

[0092] Gate electrode 44 of semiconductor element 40D is conductively connected to lead 22 via wire 72. Lead 22 conductively connected to gate electrode 44 of semiconductor element 40D serves as a gate terminal of semiconductor element 40D. Source electrode 43 of semiconductor element 40D is conductively connected to lead 21 via wire 73. Lead 21 conductively connected to source electrode 43 of semiconductor element 40D serves as a source sense terminal of semiconductor element 40D.

[0093] Gate electrode 44 of semiconductor element 40E is conductively connected to lead 22 via wire 72. Lead 22, conductively connected to gate electrode 44 of semiconductor element 40E, serves as a gate terminal of semiconductor element 40E. Source electrode 43 of semiconductor element 40E is conductively connected to lead 21 via wire 73. Lead 21, conductively connected to source electrode 43 of semiconductor element 40E, serves as a source sense terminal of semiconductor element 40E.

[0094] The gate electrode 44 of the semiconductor element 40F is conductively connected to the lead 22 via a wire 72. In this embodiment, one end of the wire 72 is bonded to the gate electrode 44 of the semiconductor element 40F, the middle portion is bonded to the eighth conductor portion 328, and the other end is bonded to the lead 22. The lead 22 conductively connected to the gate electrode 44 of the semiconductor element 40F serves as the gate terminal of the semiconductor element 40F. The source electrode 43 of the semiconductor element 40F is conductively connected to the lead 21 via a wire 73. In this embodiment, one end of the wire 73 is bonded to the source electrode 43 of the semiconductor element 40F, the middle portion is bonded to the seventh conductor portion 327, and the other end is bonded to the lead 21. The lead 21 conductively connected to the source electrode 43 of the semiconductor element 40F serves as the source sense terminal of the semiconductor element 40F.

[0095] The semiconductor device A1 is configured as a half-bridge switching circuit, for example. In this case, lead 12, lead 13, and lead 14 are externally conductively connected, and semiconductor elements 40A, 40B, and 40C constitute the upper arm circuit of the semiconductor device A1, and semiconductor elements 40D, 40E, and 40F constitute the lower arm circuit. In the upper arm circuit, semiconductor elements 40A, 40B, and 40C are connected in parallel to each other, and in the lower arm circuit, semiconductor elements 40D, 40E, and 40F are connected in parallel to each other. Each semiconductor element 40A, 40B, and 40C is connected in series with each semiconductor element 40D, 40E, and 40F to form a bridge layer. In the semiconductor device A1, a DC voltage that becomes the object of power conversion is input to lead 11 and lead 15. Lead 11 is the positive electrode (P terminal) and lead 15 is the negative electrode (N terminal). The AC voltage obtained by power conversion by the semiconductor elements 40A to 40F is output from the lead 12 , the lead 13 , and the lead 14 .

[0096] like Figure 3 、 Figure 9 As shown, in this embodiment, a plurality of semiconductor elements 4 (semiconductor elements 40A to 40F) are arranged in a row in the first direction x. The semiconductor element 40A is located at the end on the x2 side in the first direction x, and the semiconductor element 40F is located at the end on the x1 side in the first direction x. The semiconductor elements 40A to 40F are arranged in order from the x2 side in the first direction x toward the x1 side in the first direction x.

[0097] Semiconductor element 40C and semiconductor element 40D are arranged near the center in the first direction x. Here, "center in the first direction x" refers to the center line CL of the plurality of semiconductor elements 40A to 40F arranged in the first direction x, and this also applies to the various modifications described below. As in this embodiment, when the number of semiconductor elements 4 (semiconductor elements 40A to 40F) is even, two semiconductor elements 40C and 40D are arranged near the center of the plurality of semiconductor elements 4 in the first direction x.

[0098] In the illustrated example, semiconductor elements 40A to 40F are not arranged along the first direction x, but include semiconductor elements positioned differently in the second direction y. Semiconductor element 40B is located on the y1 side of the second direction y relative to semiconductor element 40A, which is adjacent to the x2 side of the first direction x. Semiconductor element 40C is located on the y1 side of the second direction y relative to semiconductor element 40B, which is adjacent to the x2 side of the first direction x. Furthermore, semiconductor element 40C is located on the y1 side of the second direction y relative to semiconductor element 40D, which is adjacent to the x1 side of the first direction x. Semiconductor element 40D is located on the y1 side of the second direction y relative to semiconductor element 40E, which is adjacent to the x1 side of the first direction x. Semiconductor element 40E is located on the y1 side of the second direction y relative to semiconductor element 40F, which is adjacent to the x1 side of the first direction x. Semiconductor element 40E is located on the y1 side of the second direction y relative to semiconductor element 40F, which is adjacent to the x1 side of the first direction x. Semiconductor element 40E is located on the y1 side of the second direction y relative to semiconductor element 40B, which is adjacent to the x1 side of the first direction x. Semiconductor element 40B is located at the same (or substantially the same) position in the second direction y as semiconductor element 40B. Semiconductor element 40F is located at the same (or substantially the same) position as semiconductor element 40A in the second direction y. Among the plurality of semiconductor elements 4 (semiconductor elements 40A to 40F) arranged in this manner, semiconductor element 40D corresponds to an example of the "first semiconductor element" of the present disclosure, and semiconductor element 40C corresponds to an example of the "second semiconductor element" of the present disclosure. The first conductor portion 321 in which semiconductor element 40D (first semiconductor element) is arranged corresponds to an example of the "first portion" of the present disclosure, and the second conductor portion 322 in which semiconductor element 40C (second semiconductor element) is arranged corresponds to an example of the "second portion" of the present disclosure.

[0099] like Figure 9 As shown, for a plurality of semiconductor elements 4 (semiconductor elements 40A to 40F), the distances between the centers of semiconductor elements 4 adjacent to each other in the first direction x are as follows: A first distance D1, the distance between the center C1 of semiconductor element 40D, which is located near the center in the first direction x, and the center C2 of semiconductor element 40C, is greater than a second distance D21, the distance between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E, which is adjacent to semiconductor element 40D in the first direction x. Furthermore, the distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is greater than a second distance D22, the distance between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B, which is adjacent to semiconductor element 40C in the first direction x. Furthermore, in this embodiment, the distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is at least twice the length (length L1) of the side of semiconductor element 4 along the first direction x.

[0100] The distance (first distance D1) between the center C1 of the semiconductor element 40D and the center C2 of the semiconductor element 40C is greater than a sixth distance D61, which is the distance between the centers C3 and C5 of the other semiconductor elements 40E and 40F, which are adjacent to each other in the first direction x, among the plurality of semiconductor elements 4. Furthermore, the first distance D1 is greater than a sixth distance D62, which is the distance between the centers C4 and C6 of the other semiconductor elements 40B and 40A, which are adjacent to each other in the first direction x, among the plurality of semiconductor elements 4.

[0101] The distance (second distance D21) between the center C1 of the semiconductor element 40D and the center C3 of the semiconductor element 40E is greater than the distance (sixth distance D61) between the centers C3 and C5 of the other semiconductor elements 40E and 40F that are adjacent to each other in the first direction x. Furthermore, the distance (second distance D22) between the center C2 of the semiconductor element 40C and the center C4 of the semiconductor element 40B is greater than the distance (sixth distance D62) between the centers C4 and C6 of the other semiconductor elements 40B and 40A that are adjacent to each other in the first direction x.

[0102] Thermistor 6 is a temperature detection element mounted on the second principal surface 3a of the insulating substrate 31. Thermistor 6 is a resistor whose resistance changes significantly with temperature. Its resistance value changes with the ambient temperature, thereby changing the voltage between its terminals. The ambient temperature of thermistor 6 is detected based on the voltage between its terminals. The characteristics of thermistor 6 are not limited. Thermistor 6 can be an NTC (negative temperature coefficient) thermistor, a PTC (positive temperature coefficient) thermistor, or a thermistor with other characteristics.

[0103] The thermistor 6 is used to detect the temperature of the semiconductor device A1. Figure 3 、 Figure 5 As shown, thermistor 6 is arranged across two pad portions 502 of wiring portion 5 (wiring 501). Thermistor 6 is bonded to pad portion 502 via conductive bonding material 63. Conductive bonding material 63 may be any material capable of bonding thermistor 6 to pad portion 502 and electrically connecting thermistor 6 to pad portion 502. Examples of conductive bonding material 63 include silver paste, copper paste, and solder. One terminal of thermistor 6 is conductively bonded to one pad portion 502 via conductive bonding material 63, and the other terminal of thermistor 6 is conductively bonded to the other pad portion 502 via conductive bonding material 63.

[0104] The two pads 502 (wiring 501) are electrically connected to the leads 23 via wires 74. The pads 502 (wiring 501) and wires 74 form a conductive path between the thermistor 6 and the leads 23. The two leads 23 serve as terminals for detecting the temperature of the semiconductor device A1 and output the voltage between the terminals of the thermistor 6.

[0105] In this embodiment, if Figure 5 As shown, the semiconductor device A1 includes an insulating component 62. The insulating component 62 is interposed between the second main surface 3a of the insulating substrate 31 and the thermistor 6 and has electrical insulation properties. The insulating component 62 is an underfill material filled between the second main surface 3a and the thermistor 6 in the thickness direction z. The constituent material of the insulating component 62 is not particularly limited, and is, for example, a synthetic resin with a black epoxy resin as the main agent. Figure 3 As shown, the thermistor 6 is arranged near a corner of the insulating substrate 31 on the x1 side in the first direction x and on the y1 side in the second direction y.

[0106] Semiconductor device A1 may also include other temperature detection elements in place of the thermistor 6. Other temperature detection elements include semiconductor temperature sensors. Semiconductor temperature sensors are silicon diodes, for example, whose forward voltage changes significantly with temperature, and detect the ambient temperature based on the voltage between their terminals when a predetermined current flows. Furthermore, unlike this embodiment, a configuration may be employed that does not include a temperature detection element such as the thermistor 6.

[0107] Sealing resin 8 covers at least semiconductor elements 40A to 40F, wiring portion 5, thermistor 6, wires 71 to 74, portions of each of leads 1 and 2, and a portion of support 3. The material of sealing resin 8 is not particularly limited, and it can be, for example, a black epoxy resin. Sealing resin 8 is formed, for example, by molding.

[0108] The sealing resin 8 has a resin main surface 81, a resin back surface 82, and a plurality of resin side surfaces 83 to 86. Figures 5 to 8 As shown, the resin main surface 81 and the resin back surface 82 are surfaces facing opposite sides in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z. The resin main surface 81 faces the z1 side in the thickness direction z, and the resin back surface 82 faces the z2 side in the thickness direction z. Figure 4 As shown, the resin back surface 82 is frame-shaped in a plan view, surrounding the second back surface 3b of the support body 3 (metal layer 33). The second back surface 3b of the support body 3 is exposed from the resin back surface 82 of the sealing resin 8, for example, flush with the surface of the resin back surface 82. Alternatively, the second back surface 3b of the support body 3 may protrude further toward the z2 side in the thickness direction z than the resin back surface 82 of the sealing resin 8.

[0109] The plurality of resin side surfaces 83 to 86 are connected to both the resin main surface 81 and the resin back surface 82, and are sandwiched by them in the thickness direction z. Figure 2 As shown in FIG. 1 , the resin side surface 83 and the resin side surface 84 are spaced apart in the first direction x. The resin side surface 83 faces the x1 side of the first direction x, and the resin side surface 84 faces the x2 side of the first direction x. Figure 2 As shown in FIG. 1 , the resin side surface 85 and the resin side surface 86 are spaced apart in the second direction y. The resin side surface 85 faces the y1 side of the second direction y, and the resin side surface 86 faces the y2 side of the second direction y. A portion of each of the plurality of leads 2 protrudes from the resin side surface 85. A portion of each of the plurality of leads 1 protrudes from the resin side surface 86. Figures 2 to 4 As shown in FIG. 1 , a recess 831 is formed on resin side surface 83, recessed in the first direction x. A recess 841 is formed on resin side surface 84, recessed in the first direction x. Recesses 831 and 841 are used, for example, for securing semiconductor device A1 during mounting. Furthermore, although detailed description is omitted, multiple recesses are formed on resin side surfaces 85 and 86, recessed in the second direction y.

[0110] Then, based on Figure 10 , an example of using semiconductor device A1 is described. This figure is a schematic diagram of vehicle B1 equipped with semiconductor device A1. Vehicle B1 includes an AC-DC converter 871, a power receiving device 872, a battery 873, a drive system 874, and a DC-DC converter 875. Semiconductor device A1 constitutes a portion (PFC circuit) of AC-DC converter 871. When AC power is supplied to vehicle B1 from a charging facility 870, an AC power source located outdoors, the AC power is converted to high-voltage DC power by AC-DC converter 871. AC-DC converter 871 supplies high-voltage DC power to battery 873. Power receiving device 872 supplies power to battery 873 via a contactless charging system, which receives power from a contactless charger (not shown) located in a parking lot, etc., by electromagnetic induction. The power stored in battery 873 is supplied to drive system 874, which consists of an inverter, an AC motor, and a transmission. Drive system 874 drives vehicle B1. The DC-DC converter 875 supplies power to electrical components other than those used for driving the vehicle B1 and is, for example, a step-down DC-DC converter. The AC-DC converter 871 described above is an example of a "power converter" in the present disclosure.

[0111] Next, the operation of the semiconductor device A1 according to this embodiment will be described.

[0112] Semiconductor device A1 includes a supporting conductor 32, a plurality of semiconductor elements 4 (semiconductor elements 40A to 40F) of four or more, and a sealing resin 8. The plurality of semiconductor elements 40A to 40F include a semiconductor element 40D (first semiconductor element) and a semiconductor element 40C (second semiconductor element) located near the center in a first direction x. The distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is greater than the distance (second distance D21) between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E adjacent to semiconductor element 40D in the first direction x, and is also greater than the distance (second distance D22) between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B adjacent to semiconductor element 40C in the first direction x. This configuration suppresses thermal interference between semiconductor element 40D and semiconductor element 40C located near the center of the plurality of semiconductor elements 40A to 40F. This prevents the concentration of heat generated in the plurality of semiconductor elements 40A to 40F, thereby reducing thermal resistance. As a result, the semiconductor device A1 can easily cope with increased current and improve durability.

[0113] The center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C are located at different positions in a second direction y perpendicular to the first direction x in which the plurality of semiconductor elements 40A to 40F are arranged. This configuration allows heat generated in semiconductor element 40D and semiconductor element 40C, which are arranged near the center of the plurality of semiconductor elements 40A to 40F, to be efficiently dissipated to the surrounding area, further suppressing thermal interference. Furthermore, this configuration prevents the size of semiconductor device A1 from increasing in the first direction x, and increases the distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C.

[0114] As reference Figure 9 Thus, among the plurality of semiconductor elements 4 (semiconductor elements 40A to 40F), the centers of semiconductor elements 4 adjacent to each other in the first direction x are located at different positions in the second direction y. This structure allows heat generated in the plurality of semiconductor elements 40A to 40F to be dissipated to the surroundings more efficiently.

[0115] The distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is at least twice the length (length L1) of the side of semiconductor element 4 along the first direction x. This configuration can appropriately suppress thermal interference between semiconductor element 40D and semiconductor element 40C located near the center of multiple semiconductor elements 40A to 40F. This configuration is more preferable for reducing the thermal resistance of semiconductor device A1.

[0116] The distance between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E (second distance D21) is greater than the distance between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F (sixth distance D61). Furthermore, the distance between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B (second distance D22) is greater than the distance between the center C4 of semiconductor element 40B and the center C6 of semiconductor element 40A (sixth distance D62). With this configuration, the distance between adjacent semiconductor elements 4 in the first direction x decreases as they move away from the center of the semiconductor element 40A in the first direction x. This reduces thermal interference between the semiconductor elements 4 (semiconductor elements 40A to 40F) and reduces the size of semiconductor device A1 in the first direction x.

[0117] The support conductor 32 includes a first conductor portion 321 (first section) and a second conductor portion 322 (second section) separated from each other. Only semiconductor element 40D (first semiconductor element) is disposed on the first conductor portion 321, among the plurality of semiconductor elements 40A to 40F. Semiconductor element 40C (second semiconductor element) and semiconductor element 40B adjacent to semiconductor element 40C are disposed on the second conductor portion 322. The center C1 of semiconductor element 40D (first semiconductor element) is located on the y1 side of the second direction y relative to the centers of semiconductor elements 40A, 40B, 40E, and 40F. The center C2 of semiconductor element 40C (second semiconductor element) is located on the y1 side of the second direction y relative to the center C1 of semiconductor element 40D. Heat generated by semiconductor elements 40C and 40B, which are arranged on the shared second conductor portion 322, tends to accumulate in the second conductor portion 322. This interference between the heat generated by semiconductor elements 40C and 40B easily causes the temperature of the second conductor portion 322 to rise. As described above, since semiconductor element 40C is positioned most toward the y2 side of the second direction y among all semiconductor elements 40A to 40F, heat generated by semiconductor element 40C can be efficiently dissipated to the surrounding area of ​​semiconductor element 40C within the second conductor portion 322 on which semiconductor element 40C is mounted. Consequently, mutual thermal interference between semiconductor elements 40D, 40C, and 40B can be suppressed, reducing the thermal resistance of semiconductor device A1.

[0118] Semiconductor device A1 includes a support body 3. A first back surface 32b of a support conductor 32, on which multiple semiconductor elements 4 (semiconductor elements 40A to 40F) are mounted, is bonded to the second main surface 3a of the support body 3 (insulating substrate 31). The second back surface 3b of the support body 3 (metal layer 33) is exposed from the sealing resin 8. This structure allows heat transferred from the semiconductor elements 4 to the support body 3 (insulating substrate 31) to be efficiently dissipated from the second back surface 3b to the outside, thereby improving the heat dissipation performance of semiconductor device A1.

[0119] A first example of a semiconductor device assembly including the semiconductor device according to the first embodiment:

[0120] Figure 11 、 Figure 12 A first example of a semiconductor device module including a semiconductor device A1 is shown. Figure 11 1 is a cross-sectional view showing the main parts of the semiconductor device package B2 of this example. Figure 12 1 is a block diagram showing the structure of a semiconductor device assembly B2 . The semiconductor device assembly B2 includes a semiconductor device A1 , a cooler 91 , a mounting member 92 , a fastening member 93 , a control unit 94 , a cooling unit 95 , and a heating unit 96 .

[0121] The cooler 91 is a heat dissipation component for cooling the semiconductor device A1. The cooler 91 is made of a metal material with excellent thermal conductivity. The constituent material of the cooler 91 is not particularly limited, and is, for example, aluminum (Al), copper (Cu) or an alloy thereof. The cooler 91 has a mounting surface 911 and a flow path 912. The mounting surface 911 is a flat surface facing the z1 side of the thickness direction z. The flow path 912 is a hollow portion formed inside the cooler 91. Cooling water, for example, as a refrigerant, flows through the flow path 912. The semiconductor device A1 is arranged on the mounting surface 911 of the cooler 91. The mounting surface 911 is opposite to the second back surface 3b of the support body 3 of the semiconductor device A1 and the resin back surface 82 of the sealing resin 8, and is in surface contact with the second back surface 3b and the resin back surface 82.

[0122] The mounting component 92 is used to hold the semiconductor device A1 on the cooler 91. The mounting component 92 is arranged to cross the semiconductor device A1 in the second direction y. The mounting component 92 is, for example, a leaf spring. The mounting component 92 is mounted on the cooler 91 by inserting two fastening components 93 into two mounting holes 913 located on both sides of the semiconductor device A1 in the second direction y. The two fastening components 93 are, for example, bolts. In the press-fit mounting state, the semiconductor device A1 is pressed against the cooler 91 by the spring force of the mounting component 92, and the mounting surface 911 of the cooler 91 is in close contact with the second back surface 3b of the support body 3 of the semiconductor device A1. In addition, in the case where the mounting surface 911 and the second back surface 3b are not in close contact, the cooler 91 can also be constructed to include a TIM (Thermal Interface Material) material not shown. The TIM material is composed of, for example, thermal grease, a heat sink, etc., and is interposed between the mounting surface 911 and the second back surface 3b. The TIM material bonds the mounting surface 911 and the second rear surface 3 b and is in close contact with both the mounting surface 911 and the second rear surface 3 b .

[0123] The cooling unit 95 cools the cooler 91. The cooling unit 95 is configured to include, for example, a cooling water supply source (not shown) and a valve that can be switched on and off. For example, when the cooler 91 is cooled by the cooling unit 95, the valve is opened, and the cooling water supplied from the cooling water supply source flows through the flow path 912. In addition, when the cooling of the cooler 91 is stopped, the valve is closed, and the circulation of the cooling water in the flow path 912 is stopped. In addition, as long as the cooling unit 95 can cool the cooler 91, the specific structure of the cooling unit 95 is not limited.

[0124] Heating unit 96 heats cooler 91. Heating unit 96 may include, for example, a heater (not shown) attached to cooler 91. For example, when heating unit 96 heats cooler 91, the heater operates. The specific structure of heating unit 96 is not limited as long as it can heat cooler 91.

[0125] Control unit 94 controls cooling unit 95 and heating unit 96 based on the temperature detected by thermistor 6 of semiconductor device A1. For example, if the temperature detected by thermistor 6 exceeds a predetermined first temperature, control unit 94 operates cooling unit 95 to cool cooler 91. Alternatively, if the temperature detected by thermistor 6 is lower than a predetermined second temperature (a temperature lower than the first temperature), control unit 94 operates heating unit 96 to heat cooler 91. Control unit 94 does not impose any restrictions on the specific control methods of cooling unit 95 and heating unit 96.

[0126] Next, the operation of the semiconductor device module B2 of this example will be described.

[0127] The semiconductor device assembly B2 of this example includes a semiconductor device A1, a cooler 91, a cooling unit 95 for cooling cooler 91, and a control unit 94. The second back surface 3b of the support body 3 in semiconductor device A1 is exposed from the sealing resin 8, and the cooler 91 has a portion (mounting surface 911 or TIM material) in contact with the second back surface 3b of the support body 3. This structure can suppress temperature increases in semiconductor device A1.

[0128] Semiconductor device assembly B2 includes a control unit 94. Control unit 94 controls cooling unit 95 based on the temperature detected by thermistor 6 of semiconductor device A1. This configuration prevents excessive temperature increases in semiconductor device A1 while monitoring the temperature of semiconductor device A1, allowing for appropriate operation of semiconductor device A1.

[0129] Semiconductor device assembly B2 includes a heating unit 96 for heating cooler 91, and control unit 94 controls heating unit 96 based on the temperature detected by thermistor 6. With this configuration, when semiconductor device A1 is mounted on, for example, automotive equipment, it is possible to prevent an excessive temperature drop in semiconductor device A1 while monitoring the temperature of semiconductor device A1 during use in cold regions, thereby enabling appropriate operation of semiconductor device A1.

[0130] Second example of a semiconductor device assembly including the semiconductor device of the first embodiment:

[0131] Figure 13 A second example of a semiconductor device module including the semiconductor device A1 is shown. Figure 13 This is a cross-sectional view showing the main parts of the semiconductor device assembly B21 of this example. The structure of the semiconductor device assembly B21 is similar to that of the above-mentioned Figure 12 The semiconductor device assembly B2 of the first example shown is the same. Figure 12 、 Figure 13 As shown, semiconductor device assembly B21 includes semiconductor device A1, cooler 91, fastening member 93, control unit 94, cooling unit 95, and heating unit 96. Cooler 91, control unit 94, cooling unit 95, and heating unit 96 are the same as those of semiconductor device assembly B2, and detailed description thereof will be omitted.

[0132] In semiconductor device package B21, semiconductor device A1 is disposed on mounting surface 911 of cooler 91. Mounting surface 911 faces second back surface 3b of support 3 and resin back surface 82 of sealing resin 8 of semiconductor device A1 and is in surface contact with at least second back surface 3b.

[0133] In the semiconductor device assembly B21, the cooler 91 has two mounting holes 913. The two mounting holes 913 are formed at positions corresponding to the recess 831 and the recess 841 of the semiconductor device A1. The semiconductor device A1 is fixed to the cooler 91 by passing two fastening components 93 through the recess 831 and the recess 841 and inserting them into the two mounting holes 913. The two fastening components 93 are, for example, bolts. When the semiconductor device A1 is fixed to the cooler 91, the semiconductor device A1 is pressed against the cooler 91, and the mounting surface 911 of the cooler 91 is in close contact with the second back surface 3b of the support body 3 of the semiconductor device A1. In addition, if the mounting surface 911 is not in close contact with the second back surface 3b, the cooler 91 can also be constructed to include a TIM material (not shown). Regarding this TIM material, it is the same as described above with respect to the semiconductor device assembly B2 of the first example, so the description is omitted.

[0134] The semiconductor device assembly B2 of this example includes a semiconductor device A1, a cooler 91, a cooling unit 95 for cooling cooler 91, and a control unit 94. The second back surface 3b of the support body 3 in semiconductor device A1 is exposed from the sealing resin 8, and the cooler 91 has a portion (mounting surface 911 or TIM material) in contact with the second back surface 3b of the support body 3. This structure can suppress temperature increases in semiconductor device A1.

[0135] Next, the function of the semiconductor device module B21 of this example will be described.

[0136] Semiconductor device assembly B2 in this example includes semiconductor device A1, cooler 91, cooling unit 95 for cooling cooler 91, and control unit 94. In semiconductor device A1, second back surface 3b of support body 3 is exposed from sealing resin 8, and cooler 91 has a portion (mounting surface 911 or TIM material) in contact with second back surface 3b of support body 3. This structure suppresses temperature increases in semiconductor device A1. Otherwise, semiconductor device assembly B21 achieves the same functions and effects as semiconductor device assembly B2 described above.

[0137] Variations of the arrangement of multiple semiconductor elements:

[0138] Figures 14 to 17 A modified example of the arrangement of the plurality of semiconductor elements 4 is shown. Figures 14 to 17 Each of them is a schematic top view showing the arrangement of the plurality of semiconductor elements 4. The structures other than the plurality of semiconductor elements 4 and the support conductor 32 supporting the semiconductor elements 4 (a plurality of leads 1, a plurality of leads 2, a support body 3, a wiring portion 5, a thermistor 6, a plurality of wires 71, 72, 73, 74 and a sealing resin 8) are the same as those of the semiconductor device A1 of the above embodiment, and their description is omitted. Figure 14 In the following drawings, the same or similar elements as those of the semiconductor device A1 of the above embodiment are denoted by the same reference numerals as those of the above embodiment, and the description thereof is omitted as appropriate. Figure 14 The configurations of the various components in the following modifications and the like can be appropriately combined with each other within a range that does not cause technical contradictions.

[0139] exist Figure 14 In the configuration example of the plurality of semiconductor elements 4 shown, the plurality of semiconductor elements 4 includes five semiconductor elements 40G to 40K. The plurality of semiconductor elements 4 (semiconductor elements 40G to 40K) are arranged in a row in the first direction x. The semiconductor element 40G is located at the end on the x2 side of the first direction x, and the semiconductor element 40K is located at the end on the x1 side of the first direction x. The semiconductor elements 40G to 40K are arranged in sequence from the x2 side of the first direction x to the x1 side of the first direction x. Figure 14 As shown, when the number of the plurality of semiconductor elements 4 (semiconductor elements 40G to 40K) is an odd number, the semiconductor element 40I is arranged near the center of the plurality of semiconductor elements 4 in the first direction x.

[0140] In the illustrated example, semiconductor elements 40G to 40K are not arranged along the first direction x, but rather include semiconductor elements positioned differently in the second direction y. Semiconductor element 40H is located on the y1 side of the second direction y relative to semiconductor element 40G, which is adjacent to the x2 side of the first direction x. Semiconductor element 40I is located on the y1 side of the second direction y relative to semiconductor element 40H, which is adjacent to the x2 side of the first direction x. Furthermore, semiconductor element 40I is located on the y1 side of the second direction y relative to semiconductor element 40J, which is adjacent to the x1 side of the first direction x. Semiconductor element 40J is located on the y1 side of the second direction y relative to semiconductor element 40K, which is adjacent to the x1 side of the first direction x. Semiconductor element 40J is located on the y1 side of the second direction y relative to semiconductor element 40K, which is adjacent to the x1 side of the first direction x. Semiconductor element 40J is located at the same (or substantially the same) position as semiconductor element 40H in the second direction y. Semiconductor element 40K is located at the same (or substantially the same) position as semiconductor element 40G in the second direction y. Among the plurality of semiconductor elements 4 (semiconductor elements 40G to 40K) arranged in this manner, semiconductor element 40I corresponds to an example of the “third semiconductor element” of the present disclosure, semiconductor element 40J corresponds to an example of the “fourth semiconductor element” of the present disclosure, and semiconductor element 40H corresponds to an example of the “fifth semiconductor element” of the present disclosure.

[0141] about Figure 14In the illustrated plurality of semiconductor elements 4 (semiconductor elements 40G to 40K), the center distances between adjacent semiconductor elements 4 in the first direction x are as follows: a third distance D3, which is the distance between the center C7 of semiconductor element 40I located near the center in the first direction x and the center C8 of semiconductor element 40J adjacent to the semiconductor element 40I on the x1 side in the first direction x, and a fourth distance D4, which is the distance between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H adjacent to the semiconductor element 40I on the x2 side in the first direction x, are both greater than a fifth distance D51, which is the distance between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K adjacent to semiconductor element 40J in the first direction x. Furthermore, the third distance D3 and the fourth distance D4 are each greater than a fifth distance D52, which is the distance between the center C9 of semiconductor element 40H and the center C11 of semiconductor element 40G adjacent to semiconductor element 40H in the first direction x. In addition, in the example shown in the figure, the distance between the center C7 of the semiconductor element 40I and the center C8 of the semiconductor element 40J (the third distance D3), and the distance between the center C7 of the semiconductor element 40I and the center C9 of the semiconductor element 40H (the fourth distance D4) are more than twice the length of the side of the semiconductor element 4 along the first direction x (the length L1).

[0142] Figure 14 The plurality of semiconductor elements 40G to 40K shown include a semiconductor element 40I (third semiconductor element) located near the center in the first direction x; a semiconductor element 40J (fourth semiconductor element) adjacent to semiconductor element 40I on the x1 side in the first direction x; and a semiconductor element 40H (fifth semiconductor element) adjacent to semiconductor element 40I on the x2 side in the first direction x. The distance between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J (third distance D3) and the distance between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H (fourth distance D4) are both greater than the distance between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K adjacent to semiconductor element 40J in the first direction x (fifth distance D51), and greater than the distance between the center C9 of semiconductor element 40H and the center C11 of semiconductor element 40G (fifth distance D52). This structure can suppress thermal interference between semiconductor element 40I, located near the center of the plurality of semiconductor elements 40G to 40K, and its adjacent semiconductor elements 40J and 40H. This prevents the concentration of heat generated in the plurality of semiconductor elements 40G to 40K, thereby reducing thermal resistance. Consequently, it becomes easier to cope with higher currents in the semiconductor device, improving the durability of the semiconductor device.

[0143] The center C7 of semiconductor element 40I, the center C8 of semiconductor element 40J, and the center C9 of semiconductor element 40H are located at different positions in a second direction y perpendicular to the first direction x in which the plurality of semiconductor elements 40G to 40K are arranged. This configuration allows heat generated in semiconductor element 40I, which is arranged near the center of the plurality of semiconductor elements 40G to 40K, and in the adjacent semiconductor elements 40J and 40H, to be efficiently dissipated to the surrounding area, further suppressing thermal interference. Furthermore, this configuration prevents the semiconductor device from increasing in size in the first direction x, and increases the distance (third distance D3) between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J, and the distance (fourth distance D4) between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H.

[0144] In the plurality of semiconductor elements 4 (semiconductor elements 40G to 40K), centers of semiconductor elements 4 adjacent to each other in the first direction x are located at different positions in the second direction y. This structure allows heat generated in the plurality of semiconductor elements 40G to 40K to be dissipated more efficiently to the surroundings.

[0145] The distance between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J (third distance D3), and the distance between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H (fourth distance D4) are at least twice the length of the side of semiconductor element 4 along the first direction x (length L1). This structure can appropriately suppress thermal interference between semiconductor element 40I located near the center of the plurality of semiconductor elements 40G to 40K and its adjacent semiconductor elements 40J and 40H. This structure is more preferable for reducing the thermal resistance of the semiconductor device.

[0146] exist Figure 15 In the configuration example of the plurality of semiconductor elements 4 shown, the plurality of semiconductor elements 4 includes eight semiconductor elements 40A to 40F, 40L, and 40M. The plurality of semiconductor elements 4 (semiconductor elements 40L, 40A to 40F, and 40M) are arranged in a row in the first direction x. The semiconductor element 40L is located at the end on the x2 side of the first direction x, and the semiconductor element 40M is located at the end on the x1 side of the first direction x. The semiconductor elements 40L, 40A to 40F, and 40M are arranged in sequence from the x2 side of the first direction x toward the x1 side of the first direction x. Figure 15As shown, when the number of the plurality of semiconductor elements 4 (semiconductor elements 40L, 40A to 40F, 40M) is an even number, two semiconductor elements 40D (first semiconductor element) and two semiconductor elements 40C (second semiconductor element) are arranged near the center in the first direction x. In the example shown, the plurality of semiconductor elements 40L, 40A to 40F, 40M are arranged along the first direction x and aligned at the same (or substantially the same) position in the second direction y.

[0147] about Figure 15 In the illustrated plurality of semiconductor elements 4 (semiconductor elements 40L, 40A to 40F, and 40M), the distances between the centers of adjacent semiconductor elements 4 in the first direction x are as follows: A first distance D1, the distance between the center C1 of semiconductor element 40D, which is located near the center in the first direction x, and the center C2 of semiconductor element 40C, is greater than a second distance D21, the distance between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E, which is adjacent to semiconductor element 40D in the first direction x. Furthermore, the distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is greater than a second distance D22, the distance between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B, which is adjacent to semiconductor element 40C in the first direction x. Furthermore, in the illustrated example, the distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is at least twice the length (length L1) of a side of semiconductor element 4 along the first direction x.

[0148] The distance (second distance D21) between the center C1 of the semiconductor element 40D and the center C3 of the semiconductor element 40E is greater than the distance (sixth distance D61) between the centers C3 and C5 of the other semiconductor elements 40E and 40F that are adjacent to each other in the first direction x. Furthermore, the distance (second distance D22) between the center C2 of the semiconductor element 40C and the center C4 of the semiconductor element 40B is greater than the distance (sixth distance D62) between the centers C4 and C6 of the other semiconductor elements 40B and 40A that are adjacent to each other in the first direction x.

[0149] like Figure 15As shown, the distance between the centers C3 and C5 of the semiconductor elements 40E and 40F, which are adjacent to each other in the first direction x (sixth distance D61), is greater than the distance between the centers C5 and C12 of the semiconductor elements 40F and 40M, which are adjacent to each other in the first direction x (sixth distance D63). The semiconductor element 40M is located farther from the center in the first direction x than the semiconductor element 40F. Furthermore, the distance between the centers C4 and C6 of the semiconductor elements 40B and 40A, which are adjacent to each other in the first direction x (sixth distance D62), is greater than the distance between the centers C6 and C13 of the semiconductor elements 40A and 40L, which are adjacent to each other in the first direction x (sixth distance D64). The semiconductor element 40L is located farther from the center in the first direction x than the semiconductor element 40A.

[0150] Figure 15 The illustrated plurality of semiconductor elements 40L, 40A to 40F, and 40M include a semiconductor element 40D (first semiconductor element) and a semiconductor element 40C (second semiconductor element) located near the center in the first direction x. The distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is greater than the distance (second distance D21) between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E adjacent to semiconductor element 40D in the first direction x, and is also greater than the distance (second distance D22) between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B adjacent to semiconductor element 40C in the first direction x.

[0151] This structure suppresses thermal interference between semiconductor element 40D and semiconductor element 40C, which are located near the center of multiple semiconductor elements 40L, 40A to 40F, and 40M. This prevents the concentration of heat generated by multiple semiconductor elements 40L, 40A to 40F, and 40M, thereby reducing thermal resistance. As a result, it facilitates the handling of higher currents in the semiconductor device and improves the durability of the semiconductor device.

[0152] The distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is at least twice the length (length L1) of the side of semiconductor element 4 along the first direction x. This configuration can appropriately suppress thermal interference between semiconductor element 40D and semiconductor element 40C located near the center of the plurality of semiconductor elements 40L, 40A to 40F, and 40M. This configuration is more preferable for reducing the thermal resistance of the semiconductor device.

[0153] The distance between the center C1 of the semiconductor element 40D and the center C3 of the semiconductor element 40E (second distance D21) is greater than the distance between the center C3 of the semiconductor element 40E and the center C5 of the semiconductor element 40F (sixth distance D61). The distance between the centers C3 and C5 of the semiconductor elements 40E and 40F (sixth distance D61) is greater than the distance between the centers C5 and C12 of the semiconductor elements 40F and 40M (sixth distance D63). Furthermore, the distance between the center C2 of the semiconductor element 40C and the center C4 of the semiconductor element 40B (second distance D22) is greater than the distance between the center C4 of the semiconductor element 40B and the center C6 of the semiconductor element 40A (sixth distance D62). The distance between the centers C4 and C6 of the semiconductor elements 40B and 40A (sixth distance D62) is greater than the distance between the centers C6 and C13 of the semiconductor elements 40A and 40L (sixth distance D64). With this configuration, the distance between adjacent semiconductor elements 4 (semiconductor elements 40L, 40A to 40F, 40M) in the first direction x decreases as they move away from the center in the first direction x. This reduces thermal interference between the semiconductor elements 4 (semiconductor elements 40L, 40A to 40F, 40M) and reduces the size of the semiconductor device in the first direction x.

[0154] exist Figure 16 In the configuration example of the plurality of semiconductor elements 4 shown, the plurality of semiconductor elements 4 includes nine semiconductor elements 40G to 40K, 40N, 40P, 40Q, and 40R. The plurality of semiconductor elements 4 (semiconductor elements 40Q, 40N, 40G to 40K, 40P, and 40R) are arranged in a first direction x. The semiconductor element 40Q is located at the end on the x2 side of the first direction x, and the semiconductor element 40R is located at the end on the x1 side of the first direction x. The semiconductor elements 40Q, 40N, 40G to 40K, 40P, and 40R are arranged in order from the x2 side of the first direction x to the x1 side of the first direction x. Figure 16 As shown, when the number of the plurality of semiconductor elements 4 (semiconductor elements 40Q, 40N, 40G to 40K, 40P, 40R) is an odd number, the semiconductor element 40I is arranged near the center in the first direction x. In the example shown, the plurality of semiconductor elements 40Q, 40N, 40G to 40K, 40P, 40R are arranged along the first direction x and aligned at the same (or substantially the same) position in the second direction y.

[0155] about Figure 16In the illustrated plurality of semiconductor elements 4 (semiconductor elements 40Q, 40N, 40G to 40K, 40P, and 40R), the center distances between adjacent semiconductor elements 4 in the first direction x are as follows: a third distance D3, which is the distance between the center C7 of semiconductor element 40I located near the center in the first direction x and the center C8 of semiconductor element 40J located adjacent to the semiconductor element 40I on the x1 side in the first direction x, and a fourth distance D4, which is the distance between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H located adjacent to the semiconductor element 40I on the x2 side in the first direction x, are both greater than a fifth distance D51, which is the distance between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K located adjacent to semiconductor element 40J in the first direction x. Furthermore, the third distance D3 and the fourth distance D4 are each greater than a fifth distance D52, which is the distance between the center C9 of semiconductor element 40H and the center C11 of semiconductor element 40G located adjacent to semiconductor element 40H in the first direction x. In addition, in the example shown in the figure, the distance between the center C7 of the semiconductor element 40I and the center C8 of the semiconductor element 40J (the third distance D3), and the distance between the center C7 of the semiconductor element 40I and the center C9 of the semiconductor element 40H (the fourth distance D4) are more than twice the length of the side of the semiconductor element 4 along the first direction x (the length L1).

[0156] The distance between the center C8 of the semiconductor element 40J and the center C10 of the semiconductor element 40K (fifth distance D51) is greater than the distance between the centers C10 and C14 of the other semiconductor elements 40K and 40P adjacent to each other in the first direction x (seventh distance D71). Furthermore, the distance between the center C9 of the semiconductor element 40H and the center C11 of the semiconductor element 40G (fifth distance D52) is greater than the distance between the centers C11 and C15 of the other semiconductor elements 40G and 40N adjacent to each other in the first direction x (seventh distance D72).

[0157] like Figure 16As shown, the distance between the centers C10 and C14 of the semiconductor elements 40K and 40P, which are adjacent to each other in the first direction x (seventh distance D71), is greater than the distance between the centers C14 and C16 of the semiconductor elements 40P and 40R, which are adjacent to each other in the first direction x (seventh distance D73). The semiconductor element 40R is located farther from the center of the first direction x than the semiconductor element 40P. Furthermore, the distance between the centers C11 and C15 of the semiconductor elements 40G and 40N, which are adjacent to each other in the first direction x (seventh distance D72), is greater than the distance between the centers C15 and C17 of the semiconductor elements 40N and 40Q, which are adjacent to each other in the first direction x (seventh distance D74). The semiconductor element 40Q is located farther from the center of the first direction x than the semiconductor element 40N.

[0158] Figure 16 The illustrated plurality of semiconductor elements 40Q, 40N, 40G to 40K, 40P, and 40R include a semiconductor element 40I (third semiconductor element) positioned near the center in the first direction x, a semiconductor element 40J (fourth semiconductor element) adjacent to semiconductor element 40I on the x1 side in the first direction x, and a semiconductor element 40H (fifth semiconductor element) adjacent to semiconductor element 40I on the x2 side in the first direction x. The distance (third distance D3) between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J, and the distance (fourth distance D4) between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H, are both greater than the distance (fifth distance D51) between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K adjacent to semiconductor element 40J in the first direction x, and are also greater than the distance (fifth distance D52) between the center C9 of semiconductor element 40H and the center C11 of semiconductor element 40G. This structure can suppress thermal interference between semiconductor element 40I, located near the center of the plurality of semiconductor elements 40Q, 40N, 40G to 40K, 40P, and 40R, and its adjacent semiconductor elements 40J and 40H. This prevents the concentration of heat generated in the plurality of semiconductor elements 40G to 40K, thereby reducing thermal resistance. Consequently, it becomes easier to cope with higher currents in the semiconductor device, improving the durability of the semiconductor device.

[0159] The distance between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J (third distance D3), and the distance between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H (fourth distance D4) are at least twice the length of the side of semiconductor element 4 along the first direction x (length L1). This structure can appropriately suppress thermal interference between semiconductor element 40I located near the center of the plurality of semiconductor elements 40Q, 40N, 40G to 40K, 40P, and 40R and its adjacent semiconductor elements 40J and 40H. This structure is more preferable for reducing the thermal resistance of the semiconductor device.

[0160] The distance between the center C8 of the semiconductor element 40J and the center C10 of the semiconductor element 40K (fifth distance D51) is greater than the distance between the center C10 of the semiconductor element 40K and the center C14 of the semiconductor element 40P (seventh distance D71). The distance between the centers C10 and C14 of the semiconductor element 40K and the semiconductor element 40P (seventh distance D71) is greater than the distance between the centers C14 and C16 of the semiconductor element 40P and the semiconductor element 40R (seventh distance D73). Furthermore, the distance between the center C9 of the semiconductor element 40H and the center C11 of the semiconductor element 40G (fifth distance D52) is greater than the distance between the center C11 of the semiconductor element 40G and the center C15 of the semiconductor element 40N (seventh distance D72). The distance between the centers C11 and C15 of the semiconductor element 40G and the semiconductor element 40N (seventh distance D72) is greater than the distance between the centers C15 and C17 of the semiconductor element 40N and the semiconductor element 40Q (seventh distance D74). With this structure, the distance between adjacent semiconductor elements 4 (semiconductor elements 40Q, 40N, 40G to 40K, 40P, and 40R) in the first direction x decreases as they move away from the center in the first direction x. This suppresses thermal interference between the semiconductor elements 4 (semiconductor elements 40Q, 40N, 40G to 40K, 40P, and 40R), and reduces the size of the semiconductor device in the first direction x.

[0161] exist Figure 17 In the configuration example of the plurality of semiconductor elements 4 shown, the plurality of semiconductor elements 4 includes seven semiconductor elements 40G to 40K, 40N, and 40P. The plurality of semiconductor elements 4 (semiconductor elements 40N, 40G to 40K, and 40P) are arranged in a row in the first direction x. The semiconductor element 40N is located at the end on the x2 side of the first direction x, and the semiconductor element 40P is located at the end on the x1 side of the first direction x. The semiconductor elements 40N, 40G to 40K, and 40P are arranged in sequence from the x2 side of the first direction x toward the x1 side of the first direction x. Figure 17As shown, when the number of the plurality of semiconductor elements 4 (semiconductor elements 40N, 40G to 40K, 40P) is an odd number, the semiconductor element 40I is arranged near the center in the first direction x.

[0162] In the illustrated example, semiconductor elements 40N, 40G to 40K, and 40P are not arranged along the first direction x, but rather include semiconductor elements positioned differently in the second direction y. Semiconductor element 40G is located on the y1 side of the second direction y relative to semiconductor element 40N, which is adjacent to the x2 side of the first direction x. Semiconductor element 40H is located on the y2 side of the second direction y relative to semiconductor element 40G, which is adjacent to the x2 side of the first direction x. Semiconductor element 40I is located on the y1 side of the second direction y relative to semiconductor element 40H, which is adjacent to the x2 side of the first direction x. Semiconductor element 40J is located on the y2 side of the second direction y relative to semiconductor element 40I, which is adjacent to the x2 side of the first direction x. Semiconductor element 40K is located on the y1 side of the second direction y relative to semiconductor element 40J, which is adjacent to the x2 side of the first direction x. The semiconductor element 40P is located on the y2 side in the second direction y relative to the semiconductor element 40K adjacent to the x2 side in the first direction x. Figure 17 As shown, the plurality of semiconductor elements 40N, 40G to 40K, and 40P are arranged in a zigzag pattern in the second direction y.

[0163] about Figure 17In the illustrated plurality of semiconductor elements 4 (semiconductor elements 40N, 40G to 40K, and 40P), the center distances between adjacent semiconductor elements 4 in the first direction x are as follows: a third distance D3, which is the distance between the center C7 of semiconductor element 40I located near the center in the first direction x and the center C8 of semiconductor element 40J located adjacent to the semiconductor element 40I on the x1 side in the first direction x, and a fourth distance D4, which is the distance between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H located adjacent to the semiconductor element 40I on the x2 side in the first direction x, are both greater than a fifth distance D51, which is the distance between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K located adjacent to semiconductor element 40J in the first direction x. Furthermore, the third distance D3 and the fourth distance D4 are each greater than a fifth distance D52, which is the distance between the center C9 of semiconductor element 40H and the center C11 of semiconductor element 40G located adjacent to semiconductor element 40H in the first direction x. In addition, in the example shown in the figure, the distance between the center C7 of the semiconductor element 40I and the center C8 of the semiconductor element 40J (the third distance D3), and the distance between the center C7 of the semiconductor element 40I and the center C9 of the semiconductor element 40H (the fourth distance D4) are more than twice the length of the side of the semiconductor element 4 along the first direction x (the length L1).

[0164] The distance between the center C8 of the semiconductor element 40J and the center C10 of the semiconductor element 40K (fifth distance D51) is greater than the distance between the centers C10 and C14 of the other semiconductor elements 40K and 40P adjacent to each other in the first direction x (seventh distance D71). Furthermore, the distance between the center C9 of the semiconductor element 40H and the center C11 of the semiconductor element 40G (fifth distance D52) is greater than the distance between the centers C11 and C15 of the other semiconductor elements 40G and 40N adjacent to each other in the first direction x (seventh distance D72).

[0165] Figure 17The illustrated plurality of semiconductor elements 40N, 40G to 40K, and 40P include a semiconductor element 40I (third semiconductor element) positioned near the center in the first direction x, a semiconductor element 40J (fourth semiconductor element) adjacent to semiconductor element 40I on the x1 side in the first direction x, and a semiconductor element 40H (fifth semiconductor element) adjacent to semiconductor element 40I on the x2 side in the first direction x. The distance (third distance D3) between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J, and the distance (fourth distance D4) between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H, are both greater than the distance (fifth distance D51) between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K adjacent to semiconductor element 40J in the first direction x, and are also greater than the distance (fifth distance D52) between the center C9 of semiconductor element 40H and the center C11 of semiconductor element 40G. This structure can suppress thermal interference between semiconductor element 40I, located near the center of the plurality of semiconductor elements 40N, 40G to 40K, and 40P, and its adjacent semiconductor elements 40J and 40H. This prevents the concentration of heat generated in the plurality of semiconductor elements 40G to 40K, thereby reducing thermal resistance. Consequently, it is easier to cope with higher currents in the semiconductor device, and the durability of the semiconductor device can be improved.

[0166] The distance between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J (third distance D3), and the distance between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H (fourth distance D4) are at least twice the length of the side of semiconductor element 4 along the first direction x (length L1). This structure can appropriately suppress thermal interference between semiconductor element 40I located near the center of the plurality of semiconductor elements 40N, 40G to 40K, and 40P and its adjacent semiconductor elements 40J and 40H. This structure is more preferable for reducing the thermal resistance of the semiconductor device.

[0167] The center C7 of semiconductor element 40I, the center C8 of semiconductor element 40J, and the center C9 of semiconductor element 40H are located at different positions in a second direction y perpendicular to the first direction x in which the plurality of semiconductor elements 40N, 40G to 40K, and 40P are arranged. This configuration allows heat generated in semiconductor element 40I, which is arranged near the center of the plurality of semiconductor elements 40N, 40G to 40K, and 40P, and in the adjacent semiconductor elements 40J and 40H, to be efficiently dissipated to the surrounding area, further suppressing thermal interference. Furthermore, this configuration prevents the semiconductor device from increasing in size in the first direction x, and increases the distance (third distance D3) between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J, and the distance (fourth distance D4) between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H.

[0168] In the plurality of semiconductor elements 4 (semiconductor elements 40N, 40G to 40K, 40P), the centers of the semiconductor elements 4 adjacent to each other in the first direction x are located at different positions in the second direction y. According to such a structure, the heat generated in the plurality of semiconductor elements 40N, 40G to 40K, 40P can be released to the surrounding more efficiently. Figure 17 In the example shown, the plurality of semiconductor elements 40N, 40G to 40K, and 40P are arranged in a zigzag pattern in the second direction y. This configuration allows the centers of the plurality of semiconductor elements 4 (semiconductor elements 40N, 40G to 40K, and 40P) to be kept at a desired distance from each other in the first direction x, while preventing the size of the semiconductor device in the first direction x and the second direction y from increasing.

[0169] The distance between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K (fifth distance D51) is greater than the distance between the center C10 of semiconductor element 40K and the center C14 of semiconductor element 40P (seventh distance D71). Furthermore, the distance between the center C9 of semiconductor element 40H, the center C11 of semiconductor element 40G, and the center C15 of semiconductor element 40N (fifth distance D52) is greater than the distance between the center C11 of semiconductor element 40G and the center C15 of semiconductor element 40N (seventh distance D72). With this configuration, the distance between adjacent semiconductor elements 4 in the first direction x decreases as they move away from the center of the semiconductor element 40N (semiconductor elements 40G to 40K, 40P). This reduces thermal interference between the semiconductor elements 4 (semiconductor elements 40N, 40G to 40K, 40P) and reduces the size of the semiconductor device in the first direction x.

[0170] Second embodiment:

[0171] Figures 18 to 21 A semiconductor device according to a second embodiment of the present invention is shown. Semiconductor device A2 of this embodiment includes a plurality of leads 1 (leads 11 to 15), a plurality of leads 2 (a plurality of leads 21, a plurality of leads 22, and two leads 23), an insulating substrate 30, a plurality of semiconductor elements 4 (semiconductor elements 40A to 40F), a wiring portion 5, a plurality of bonding portions 511 to 515, a bonding portion 521, a thermistor 6, a plurality of wires 71, 72, and 73, and a sealing resin 8. Figure 18 It is a plan view showing the semiconductor device A2 , and is a view seen through the sealing resin 8 . Figure 19 It is along Figure 18 Cross-sectional view along line XIX-XIX. Figure 20 It is along Figure 18 Cross-sectional view of line XX-XX. Figure 21 It is along Figure 18 The sectional view of the XXI-XXI line. Figure 18 In FIG, the outer shape of the sealing resin 8 is represented by an imaginary line (two-dot chain line). Figures 19 to 21 , the wire 71 is omitted. Figure 19 、 Figure 21 , the wires 72 and 73 are omitted.

[0172] In the semiconductor device A2 of this embodiment, the main difference from the above embodiment is that an insulating substrate 30 is provided instead of the support body 3 of the above embodiment, the structure of each part of the multiple leads 1 (leads 11 to 15), the multiple leads 2 (multiple leads 21, multiple leads 22 and two leads 23), and the structure of the wiring part 5.

[0173] The insulating substrate 30 supports the plurality of semiconductor elements 40A to 40F. The material of the insulating substrate 30 is not particularly limited. For example, a material having a higher thermal conductivity than the material of the sealing resin 8 is preferably used for the insulating substrate 30. Examples of the material of the insulating substrate 30 include ceramics such as alumina (Al2O3), silicon nitride (SiN), aluminum nitride (AlN), and zirconium oxide-containing alumina. The thickness of the insulating substrate 30 is not particularly limited, but is, for example, approximately 0.1 mm to 1.0 mm.

[0174] The shape of the insulating substrate 30 is not particularly limited. Figures 18 to 21As shown, in the present embodiment, the insulating substrate 30 has a second main surface 3a and a second back surface 3b. The second main surface 3a faces the z1 side in the thickness direction z. The second back surface 3b faces the side opposite to the second main surface 3a (the z2 side in the thickness direction z). In the present embodiment, the second back surface 3b is exposed from the sealing resin 8. A heat dissipation component (such as a radiator) not shown in the figure can be installed on the second back surface 3b. In the example shown in the figure, the insulating substrate 30 is rectangular when viewed from above. In addition, the insulating substrate 30 is a long rectangular shape with the first direction x as the long side direction when viewed in the thickness direction z. The insulating substrate 30 is an example of a "support body" disclosed in the present invention, and the support body is composed of the insulating substrate 30.

[0175] The wiring portion 5 is formed on the insulating substrate 30. In the present embodiment, the wiring portion 5 is formed on the second main surface 3a of the insulating substrate 30. The wiring portion 5 is made of a conductive material. The conductive material constituting the wiring portion 5 is not particularly limited. As the conductive material of the wiring portion 5, for example, materials including silver (Ag), copper (Cu), gold (Au), etc. can be cited. In the following description, the case where the wiring portion 5 includes silver is taken as an example. It should be noted that the wiring portion 5 may include copper instead of silver, or gold instead of silver or copper. Alternatively, the wiring portion 5 may also include Ag-Pt or Ag-Pd. In addition, the method for forming the wiring portion 5 is not limited, for example, it is formed by firing a paste including these metals. The thickness of the wiring portion 5 is not particularly limited, and is, for example, about 5μm to 30μm.

[0176] The shape of the wiring portion 5 is not particularly limited. Figure 18 、 Figure 19 As shown, the wiring portion 5 includes two wirings 501. The two wirings 501 are arranged near a corner of the insulating substrate 30 on the x1 side in the first direction x and on the y1 side in the second direction y. The two wirings 501 are separated from each other and arranged side by side in the second direction y. Each wiring 501 has a pad portion 502. The pad portion 502 is located at the end of the wiring 501 on the x2 side in the first direction x. Each terminal of the thermistor 6 is bonded to the two pad portions 502.

[0177] like Figures 19 to 21As shown, a plurality of bonding portions 511 to 515, 521 are formed on the insulating substrate 30. In the present embodiment, a plurality of bonding portions 511 to 515, 521 are formed on the second main surface 3a of the insulating substrate 30. The material of the bonding portions 511 to 515, 521 is not particularly limited, and they are made of, for example, a material capable of bonding the insulating substrate 30 to the lead 1. The bonding portions 511 to 515, 521 are made of, for example, a conductive material. The conductive material constituting the bonding portions 511 to 515, 521 is not particularly limited. As conductive materials constituting the bonding portions 511 to 515, 521, for example, materials including silver (Ag), copper (Cu), gold (Au), etc. can be cited. In the following description, the case where the bonding portions 511 to 515, 521 contain silver is used as an example. The bonding portions 511 to 515, 521 in this example include the same material as the conductive material constituting the wiring portion 5. Furthermore, the bonding portions 511-515, 521 may contain copper instead of silver, or gold instead of silver or copper. Alternatively, the bonding portions 511-515, 521 may include Ag-Pt or Ag-Pd. The method for forming the bonding portions 511-515, 521 is not limited; for example, they may be formed by firing a paste containing these metals, similar to the wiring portion 5. The thickness of the bonding portions 511-515, 521 is not particularly limited, but is, for example, approximately 5 μm to 30 μm.

[0178] The plurality of leads 1 are composed of metal, and for example, have better heat dissipation characteristics than the insulating substrate 30. The metal constituting the lead 1 is not particularly limited, and may be, for example, copper (Cu), aluminum, iron (Fe), oxygen-free copper, or alloys thereof (for example, Cu-Sn alloy, Cu-Zr alloy, Cu-Fe alloy, etc.). In addition, the plurality of leads 1 may also be plated with nickel (Ni). The plurality of leads 1 may be formed, for example, by a stamping process in which a mold is pressed against a metal plate, or by patterning a metal plate by etching, but is not limited thereto. The thickness of each lead 1 is not particularly limited, and may be, for example, about 0.4 mm to 0.8 mm. The leads 1 are separated from each other.

[0179] In this embodiment, the plurality of leads 1 include a lead 11, a lead 12, a lead 13, a lead 14, and a lead 15. The leads 11, 12, 13, 14, and 15 constitute a conductive path to the semiconductor element 4, for example.

[0180] The lead 11 is arranged on the insulating substrate 30, and in the present embodiment, is arranged on the second main surface 3a. The lead 11 is bonded to the bonding portion 511 via the bonding material 18. The bonding material 18 only needs to be able to bond the lead 11 to the bonding portion 511. From the perspective of efficiently transferring heat from the lead 11 through the insulating substrate 30, the bonding material 18 is preferably a material with a higher thermal conductivity, such as silver paste, copper paste, solder, etc. However, the bonding material 18 may also be an insulating material such as epoxy resin, silicone resin, etc. In addition, when the bonding portion 511 is not formed on the insulating substrate 30, the lead 11 may also be bonded to the insulating substrate 30.

[0181] The structure of the lead 11 is not particularly limited. In this embodiment, Figure 18 、 Figure 20 、 Figure 21 As shown in FIG. 1 , the lead 11 is described by being divided into a mounting portion 110 , a protruding portion 112 , and an inclined portion 113 .

[0182] The mounting portion 110 is arranged on the second principal surface 3a of the insulating substrate 30, near the x2 side in the first direction x. Semiconductor elements 40A, 40B, and 40C are arranged on the upper surface of the mounting portion 110 (the first principal surface facing the z1 side in the thickness direction z). The mounting portion 110 constitutes a portion of the "conductive portion" of the present disclosure. In addition, unlike the example shown in the figure, the mounting portion 110 may also have a structure having multiple recesses recessed from the upper surface of the mounting portion 110 toward the z2 side in the thickness direction z. The lower surface of the mounting portion 110 (the first rear surface facing the z2 side in the thickness direction z) is bonded to the bonding portion 511 via bonding material 18. The inclined portion 113 is connected to the mounting portion 110 and is inclined relative to the mounting portion 110. The protrusion 112 is connected to the inclined portion 113, and most of it protrudes from the sealing resin 8. In the example shown in the figure, the two protrusions 112 are arranged at intervals in the first direction x. Each protrusion 112 protrudes in the second direction y toward the side opposite to the mounting portion 110. The protrusion 112 is used, for example, to electrically connect the semiconductor device A2 to an external circuit. In the example shown in the figure, the protrusion 112 is bent toward the side toward which the second main surface 3a of the insulating substrate 30 faces in the thickness direction z.

[0183] The lead 12 is arranged on the insulating substrate 30, and in this embodiment, is arranged on the second main surface 3a. The lead 12 is bonded to the bonding portion 512 via the bonding material 18. The structure of the lead 12 is not particularly limited. In this embodiment, Figure 18 、 Figure 21 As shown in FIG. 1 , the lead 12 is described while being divided into a mounting portion 120 , a protruding portion 122 , and an inclined portion 123 .

[0184] The mounting portion 120 is arranged on the x1 side of the first direction x relative to the mounting portion 110 and is adjacent to the mounting portion 110. A semiconductor element 40D is arranged on the upper surface of the mounting portion 120 (the first main surface facing the z1 side of the thickness direction z). The mounting portion 120 constitutes a part of the "conductive portion" of the present disclosure. In addition, unlike the example shown in the figure, the mounting portion 120 can also be a structure having a plurality of recesses recessed from the upper surface of the mounting portion 120 to the z2 side of the thickness direction z. The lower surface of the mounting portion 120 (the first back surface facing the z2 side of the thickness direction z) is bonded to the bonding portion 512 by the bonding material 18. The inclined portion 123 is connected to the mounting portion 120 and is inclined relative to the mounting portion 120. The protrusion 122 is connected to the inclined portion 123, and most of it protrudes from the sealing resin 8. The protrusion 122 protrudes to the side opposite to the mounting portion 120 in the second direction y. The protrusion 122 is used, for example, to electrically connect the semiconductor device A2 to an external circuit. In the example shown in the drawings, the protruding portion 122 is bent in the thickness direction z toward the side toward which the second main surface 3 a of the insulating substrate 30 faces.

[0185] The lead 13 is arranged on the insulating substrate 30, and in this embodiment, is arranged on the second main surface 3a. The lead 13 is bonded to the bonding portion 513 via the bonding material 18. The structure of the lead 13 is not particularly limited. In this embodiment, Figure 18 、 Figure 21 As shown in FIG. 1 , the lead 13 will be described while being divided into a mounting portion 130 , a protruding portion 132 , and an inclined portion 133 .

[0186] The mounting portion 130 is arranged on the x1 side of the first direction x relative to the mounting portion 120 and is adjacent to the mounting portion 120. A semiconductor element 40E is arranged on the upper surface of the mounting portion 130 (the first main surface facing the z1 side of the thickness direction z). The mounting portion 130 constitutes a part of the "conductive portion" of the present disclosure. In addition, unlike the example shown in the figure, the mounting portion 130 can also be a structure having a plurality of recesses recessed from the upper surface of the mounting portion 130 toward the z2 side of the thickness direction z. The lower surface of the mounting portion 130 (the first back surface facing the z2 side of the thickness direction z) is bonded to the bonding portion 513 via the bonding material 18. The inclined portion 133 is connected to the mounting portion 130 and is inclined relative to the mounting portion 130. The protrusion 132 is connected to the inclined portion 133, and most of it protrudes from the sealing resin 8. The protrusion 132 protrudes to the side opposite to the mounting portion 130 in the second direction y. The protrusion 132 is used, for example, to electrically connect the semiconductor device A2 to an external circuit. In the example shown in the drawings, the protrusion 132 is bent in the thickness direction z toward the side toward which the second main surface 3 a of the insulating substrate 30 faces.

[0187] The lead 14 is arranged on the insulating substrate 30, and in this embodiment, is arranged on the second main surface 3a. The lead 14 is bonded to the bonding portion 512 via the bonding material 18. The structure of the lead 12 is not particularly limited. In this embodiment, Figure 18 、 Figure 19 、 Figure 21 As shown in FIG. 1 , the lead 14 is described while being divided into a mounting portion 140 , a protruding portion 142 , and an inclined portion 143 .

[0188] The mounting portion 140 is arranged on the x1 side of the first direction x relative to the mounting portion 130 and is adjacent to the mounting portion 130. A semiconductor element 40F is arranged on the upper surface of the mounting portion 140 (the first main surface facing the z1 side of the thickness direction z). The mounting portion 140 constitutes a part of the "conductive portion" of the present disclosure. In addition, unlike the example shown in the figure, the mounting portion 140 can also be a structure having a plurality of recesses recessed from the upper surface of the mounting portion 140 toward the z2 side of the thickness direction z. The lower surface of the mounting portion 140 (the first back surface facing the z2 side of the thickness direction z) is bonded to the bonding portion 514 by the bonding material 18. The inclined portion 143 is connected to the mounting portion 140 and is inclined relative to the mounting portion 140. The protrusion 142 is connected to the inclined portion 143, and most of it protrudes from the sealing resin 8. The protrusion 142 protrudes to the side opposite to the mounting portion 140 in the second direction y. The protrusion 142 is used, for example, to electrically connect the semiconductor device A2 to an external circuit. In the example shown in the drawings, the protruding portion 142 is bent in the thickness direction z toward the side toward which the second main surface 3 a of the insulating substrate 30 faces.

[0189] The lead 15 is arranged on the insulating substrate 30, and in this embodiment, is arranged on the second main surface 3a. Figure 18 、 Figure 19 As shown, the lead 15 is bonded to the bonding portion 515 via the bonding material 18. The structure of the lead 15 is not particularly limited. Figure 18 、 Figure 19 As shown in FIG. 1 , the lead 15 will be described by being divided into a pad portion 151 , a protruding portion 152 , and an inclined portion 153 .

[0190] The pad portion 151 is covered with a sealing resin 8. The pad portion 151 is parallel to the insulating substrate 30. A wire 71 is bonded to the upper surface of the pad portion 151 (the surface facing the z1 side in the thickness direction z). The lower surface of the pad portion 151 (the surface facing the z2 side in the thickness direction z) is bonded to the bonding portion 515 via a bonding material 18. The inclined portion 153 is connected to the pad portion 151 and is inclined relative to the pad portion 151. The protrusion 152 is connected to the inclined portion 153, and most of it protrudes from the sealing resin 8. The protrusion 152 is used, for example, to electrically connect the semiconductor device A2 to an external circuit. In the example shown in the figure, the protrusion 152 is bent in the thickness direction z toward the side toward which the second main surface 3a of the insulating substrate 30 faces.

[0191] The multiple leads 2 are composed of metal, for example, the thermal conductivity is higher than that of the insulating substrate 31. The metal constituting the lead 2 is not particularly limited, and is, for example, copper, aluminum, iron (Fe), oxygen-free copper, or an alloy thereof (for example, Cu-Sn alloy, Cu-Zr alloy, Cu-Fe alloy, etc.). In addition, the multiple leads 2 may also be plated with nickel (Ni). The multiple leads 2 can be formed, for example, by a stamping process in which a mold is pressed against a metal plate, or by patterning a metal plate using etching. In addition, the method for forming the multiple leads 2 is not limited. The thickness of each lead 2 is not particularly limited, and is, for example, about 0.4 mm to 0.8 mm. The leads 2 are separated from each other.

[0192] The multiple leads 2 are composed of metal, for example, the thermal conductivity is higher than that of the insulating substrate 30. The metal constituting the lead 2 is not particularly limited, and is, for example, copper, aluminum, iron (Fe), oxygen-free copper, or an alloy thereof (for example, Cu-Sn alloy, Cu-Zr alloy, Cu-Fe alloy, etc.). In addition, the multiple leads 2 may also be plated with nickel (Ni). The multiple leads 2 can be formed, for example, by a stamping process in which a mold is pressed against a metal plate, or by patterning a metal plate using etching. In addition, the method for forming the multiple leads 2 is not limited. The thickness of each lead 2 is not particularly limited, and is, for example, about 0.4 mm to 0.8 mm. The leads 2 are separated from each other.

[0193] In this embodiment, the plurality of leads 2 include a plurality of leads 21, a plurality of leads 22, and two leads 23. The leads 21 and 22 form a conductive path to the source electrode 43 and gate electrode 44 of the semiconductor elements 4 (semiconductor elements 40A to 40F). The two leads 23 form a conductive path to the thermistor 6.

[0194] The plurality of leads 21 are respectively arranged on the insulating substrate 30, and in this embodiment, are arranged on the second main surface 3a. The plurality of leads 21 are arranged at intervals in the first direction x. The structure of the leads 21 is not particularly limited. In this embodiment, as shown in FIG. Figure 18 、 Figure 20 As shown in FIG. 1 , the lead 21 is described by being divided into a protruding portion 212 , an inclined portion 213 , and a parallel portion 214 .

[0195] The parallel portion 214 is covered with the sealing resin 8. The parallel portion 214 is parallel to the insulating substrate 30. The lower surface of the parallel portion 214 (the surface facing the z2 side in the thickness direction z) is bonded to the bonding portion 521 through the conductive bonding material 28. The inclined portion 213 is connected to the end of the parallel portion 214 and is inclined relative to the parallel portion 214. The protrusion 212 is connected to the end of the inclined portion 213 and is a portion of the lead 21 that protrudes from the sealing resin 8. The protrusion 212 protrudes from the sealing resin 8 to the y1 side in the second direction y. The protrusion 212 is used, for example, to electrically connect the semiconductor device A2 to an external circuit. In the example shown in the figure, the protrusion 212 is bent in the thickness direction z toward the side toward which the second main surface 3a of the insulating substrate 30 faces.

[0196] The plurality of leads 22 are respectively arranged on the insulating substrate 30, and in this embodiment, are arranged on the second main surface 3a. The plurality of leads 22 are arranged at intervals in the first direction x. The plurality of leads 22 are respectively arranged in pairs with any one of the plurality of leads 21. The structure of the lead 22 is not particularly limited. In this embodiment, as Figure 18 As shown in FIG. 1 , the lead 22 is described by being divided into a protruding portion 222 , an inclined portion 223 , and a parallel portion 224 .

[0197] The parallel portion 224 is covered with the sealing resin 8. The parallel portion 224 is parallel to the insulating substrate 30. The lower surface of the parallel portion 224 (the surface facing the z2 side in the thickness direction z) is bonded to the bonding portion 521 through the conductive bonding material 28. The inclined portion 223 is connected to the end of the parallel portion 224 and is inclined relative to the parallel portion 224. The protrusion 222 is connected to the end of the inclined portion 223 and is a portion of the lead 22 that protrudes from the sealing resin 8. The protrusion 222 protrudes from the sealing resin 8 to the y1 side in the second direction y. The protrusion 222 is used, for example, to electrically connect the semiconductor device A2 to an external circuit. In the example shown in the figure, the protrusion 222 is bent in the thickness direction z toward the side toward which the second main surface 3a of the insulating substrate 30 faces.

[0198] The two leads 23 are respectively arranged on the insulating substrate 30, and in this embodiment, are arranged on the second main surface 3a. The two leads 23 are arranged in a first direction x. The structure of the leads 23 is not particularly limited. In this embodiment, as shown in FIG. Figure 18 、 Figure 19 As shown in FIG. 1 , the lead 23 is described by being divided into a protruding portion 232 , an inclined portion 233 , and a parallel portion 234 .

[0199] The parallel portion 234 is covered with the sealing resin 8. The parallel portion 234 is parallel to the insulating substrate 30. The lower surface of the parallel portion 234 (the surface facing the z2 side in the thickness direction z) is bonded to the wiring 501 through the conductive bonding material 28. The inclined portion 233 is connected to the end of the parallel portion 234 and is inclined relative to the parallel portion 234. The protrusion 232 is connected to the end of the inclined portion 233 and is a portion of the lead 23 that protrudes from the sealing resin 8. The protrusion 232 protrudes from the sealing resin 8 to the y1 side in the second direction y. The protrusion 232 is used, for example, to electrically connect the semiconductor device A2 to an external circuit. In the example shown in the figure, the protrusion 232 is bent in the thickness direction z toward the side toward which the second main surface 3a of the insulating substrate 30 faces.

[0200] like Figure 20 、 Figure 21 As shown, semiconductor elements 40A, 40B, and 40C are bonded to mounting portion 110 with their back surfaces 42 facing mounting portion 110 via conductive bonding material 47. Consequently, drain electrodes 45 of each of semiconductor elements 40A, 40B, and 40C are electrically connected to mounting portion 110 via conductive bonding material 47. Mounting portion 110 is an example of the "second portion" of the present disclosure.

[0201] like Figure 21 As shown, the semiconductor element 40D has its back surface 42 facing the mounting portion 120 and is bonded to the mounting portion 120 via a conductive bonding material 47. Thus, the drain electrode 45 of the semiconductor element 40D is conductively connected to the mounting portion 120 via the conductive bonding material 47. The mounting portion 120 is an example of the "first portion" of the present disclosure. Figure 21 As shown, the semiconductor element 40E is bonded to the mounting portion 130 with the element back surface 42 facing the mounting portion 130 via the conductive bonding material 47. Thus, the drain electrode 45 of the semiconductor element 40E is conductively connected to the mounting portion 130 via the conductive bonding material 47. Figure 19 As shown, semiconductor element 40F is bonded to mounting portion 140 with element back surface 42 facing mounting portion 140 via conductive bonding material 47 .

[0202] like Figure 18 As shown, in this embodiment, the gate electrode 44 of each semiconductor element 4 (semiconductor elements 40A to 40F) is conductively connected to any one of the plurality of leads 21 via a wire 72. The lead 21 is the gate terminal of each semiconductor element 4. The source electrode 43 of each semiconductor element 4 (semiconductor elements 40A to 40F) is conductively connected to any one of the plurality of leads 22 via a wire 73. The lead 22 is the source sense terminal of each semiconductor element 4.

[0203] like Figure 18 、 Figure 22 As shown, in this embodiment, a plurality of semiconductor elements 4 (semiconductor elements 40A to 40F) are arranged in a first direction x. The arrangement of the plurality of semiconductor elements 4 (semiconductor elements 40A to 40F) is the same (or substantially the same) as that of the semiconductor device A1 of the above-mentioned embodiment. The relationship between the center positions of the plurality of semiconductor elements 4 (semiconductor elements 40A to 40F), the distance between adjacent centers, etc., are the same as those in the above-mentioned embodiment. Figure 9 The description is the same (or roughly the same), so in Figure 22 The markings in the above embodiment are Figure 9 The same reference numerals etc. are used and their descriptions are omitted.

[0204] like Figure 18 As shown, the thermistor 6 is arranged near a corner of the insulating substrate 30 on the x1 side in the first direction x and on the y1 side in the second direction y.

[0205] Next, the operation of the semiconductor device A2 according to this embodiment will be described.

[0206] Semiconductor device A2 includes a supporting conductor 32, a plurality of semiconductor elements 4 (semiconductor elements 40A to 40F) of four or more, and a sealing resin 8. The plurality of semiconductor elements 40A to 40F include a semiconductor element 40D (first semiconductor element) and a semiconductor element 40C (second semiconductor element) located near the center in a first direction x. The distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is greater than the distance (second distance D21) between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E adjacent to semiconductor element 40D in the first direction x, and is also greater than the distance (second distance D22) between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B adjacent to semiconductor element 40C in the first direction x. This configuration suppresses thermal interference between semiconductor element 40D and semiconductor element 40C located near the center of the plurality of semiconductor elements 40A to 40F. This prevents the concentration of heat generated in the plurality of semiconductor elements 40A to 40F, thereby reducing thermal resistance. As a result, the semiconductor device A2 can easily cope with increased current and improve durability.

[0207] The center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C are located at different positions in a second direction y perpendicular to the first direction x in which the plurality of semiconductor elements 40A to 40F are arranged. This configuration allows heat generated in semiconductor element 40D and semiconductor element 40C, which are arranged near the center of the plurality of semiconductor elements 40A to 40F, to be efficiently dissipated to the surrounding area, further suppressing thermal interference. Furthermore, this configuration prevents the size of semiconductor device A1 from increasing in the first direction x, and increases the distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C. Furthermore, semiconductor device A2 achieves the same functions and effects as semiconductor device A1 of the aforementioned embodiment.

[0208] Furthermore, similar to the semiconductor device assembly B2 including the semiconductor device A1 described above, the semiconductor device A2 of this embodiment can also be configured as a semiconductor device assembly further including a cooler 91, a mounting member 92, a control unit 94, a cooling unit 95, and a heating unit 96. In this case, the semiconductor device assembly B2 can achieve the same operational effects as described above.

[0209] Third embodiment:

[0210] Figure 23 as well as Figure 24 A semiconductor device according to a third embodiment of the present disclosure is shown. Semiconductor device A3 of this embodiment includes a plurality of leads 1 (leads 11 to 15), a plurality of leads 2 (a plurality of leads 21, a plurality of leads 22, and two leads 23), an insulating substrate 30, a plurality of semiconductor elements 4 (semiconductor elements 40B, 40C, 40D, and 40E), a wiring portion 5, a thermistor 6, a plurality of wires 71, 72, 73, and 74, and a sealing resin 8. Figure 23 It is a plan view showing the semiconductor device A3 , and is a view seen through the sealing resin 8 . Figure 24 1 is a schematic top view showing the arrangement of a plurality of semiconductor elements 4 in the semiconductor device A3. Figure 23 In FIG. 1 , the outer shape of the sealing resin 8 is indicated by an imaginary line (two-dot chain line).

[0211] The semiconductor device A3 of this embodiment differs primarily from the semiconductor device A1 of the aforementioned embodiment in the arrangement of the plurality of semiconductor elements 4. In this embodiment, semiconductor device A3 includes four semiconductor elements 4 (semiconductor elements 40B, 40C, 40D, and 40E). The arrangement of these semiconductor elements 40B-40E is identical (or substantially identical) to that of semiconductor elements 40B-40E in semiconductor device A1. Semiconductor device A3 is configured as a full-bridge switching circuit, for example.

[0212] In a semiconductor device A3 having four (an even number) semiconductor elements 4, semiconductor element 40C and semiconductor element 40D are arranged near the center in the first direction x. As in this embodiment, when the number of semiconductor elements 4 (semiconductor elements 40B to 40E) is an even number, two semiconductor elements 40C and two semiconductor elements 40D are arranged near the center in the first direction x of the plurality of semiconductor elements 4.

[0213] In the illustrated example, semiconductor elements 40B to 40E are not arranged along the first direction x, but include semiconductor elements that are positioned differently in the second direction y. Semiconductor element 40C is located on the y1 side of the second direction y relative to semiconductor element 40B, which is adjacent to the x2 side of the first direction x. Furthermore, semiconductor element 40C is located on the y1 side of the second direction y relative to semiconductor element 40D, which is adjacent to the x1 side of the first direction x. Semiconductor element 40D is located on the y1 side of the second direction y relative to semiconductor element 40E, which is adjacent to the x1 side of the first direction x. Semiconductor element 40E is located on the same (or substantially the same) position as semiconductor element 40B in the second direction y. Of the plurality of semiconductor elements 4 (semiconductor elements 40B to 40E) arranged in this manner, semiconductor element 40D corresponds to an example of a "first semiconductor element" in the present disclosure, and semiconductor element 40C corresponds to an example of a "second semiconductor element" in the present disclosure. The first conductor portion 321 in which the semiconductor element 40D (first semiconductor element) is arranged corresponds to an example of the “first portion” of the present disclosure, and the second conductor portion 322 in which the semiconductor element 40C (second semiconductor element) is arranged corresponds to an example of the “second portion” of the present disclosure.

[0214] like Figure 24 As shown, for a plurality of semiconductor elements 4 (semiconductor elements 40B to 40E), the distances between the centers of semiconductor elements 4 adjacent to each other in the first direction x are as follows: A first distance D1, the distance between the center C1 of semiconductor element 40D, which is located near the center in the first direction x, and the center C2 of semiconductor element 40C, is greater than a second distance D21, the distance between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E, which is adjacent to semiconductor element 40D in the first direction x. Furthermore, the distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is greater than a second distance D22, the distance between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B, which is adjacent to semiconductor element 40C in the first direction x. Furthermore, in this embodiment, the distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is at least twice the length (length L1) of the side of semiconductor element 4 along the first direction x.

[0215] Then, based on Figure 25 , an example of using the semiconductor device A3 is described. This figure is a schematic diagram of a vehicle B11 equipped with a semiconductor device A3. Vehicle B11 includes an AC-DC converter 871, a power receiving device 872, a battery 873, a drive system 874, and a DC-DC converter 875. When AC power is supplied to vehicle B11 from a charging facility 870, an AC power source located outdoors, the AC-DC converter 871 converts the AC power into high-voltage DC power. The AC-DC converter 871 supplies high-voltage DC power to the battery 873. The power receiving device 872 supplies power to the battery 873 via a contactless charging system, which is supplied with power by electromagnetic induction from a contactless charger (not shown) located in a parking lot, etc. The power stored in the battery 873 is supplied to the drive system 874, which is composed of an inverter, an AC motor, and a transmission. The drive system 874 drives the vehicle B11. DC-DC converter 875 supplies power to electrical components other than those used to drive vehicle B11. It is a step-down DC-DC converter, for example. Semiconductor device A3 forms part of DC-DC converter 875. This DC-DC converter 875 is an example of a "power converter" within the present disclosure.

[0216] Next, the operation of the semiconductor device A3 according to this embodiment will be described.

[0217] Semiconductor device A3 includes a supporting conductor 32, a plurality of semiconductor elements 4 (semiconductor elements 40B to 40E) of four or more, and a sealing resin 8. The plurality of semiconductor elements 40B to 40E include a semiconductor element 40D (a first semiconductor element) and a semiconductor element 40C (a second semiconductor element) located near the center in a first direction x. The distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is greater than the distance (second distance D21) between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E adjacent to semiconductor element 40D in the first direction x, and is also greater than the distance (second distance D22) between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B adjacent to semiconductor element 40C in the first direction x. This configuration suppresses thermal interference between semiconductor element 40D and semiconductor element 40C located near the center of the plurality of semiconductor elements 40B to 40E. This prevents the concentration of heat generated in the plurality of semiconductor elements 40B to 40E, thereby reducing thermal resistance. As a result, the semiconductor device A3 can easily cope with increased current and improve durability.

[0218] The center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C are located at different positions in a second direction y that is perpendicular to the first direction x in which the plurality of semiconductor elements 40B to 40E are arranged. This configuration allows heat generated in semiconductor element 40D and semiconductor element 40C, which are arranged near the center of the plurality of semiconductor elements 40B to 40E, to be efficiently dissipated to the surrounding area, further suppressing thermal interference. Furthermore, this configuration prevents the size of semiconductor device A3 in the first direction x from increasing, and increases the distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C.

[0219] As reference Figure 24 Thus, among the plurality of semiconductor elements 4 (semiconductor elements 40B to 40E), the centers of semiconductor elements 4 adjacent to each other in the first direction x are located at different positions in the second direction y. This structure allows heat generated in the plurality of semiconductor elements 40B to 40E to be dissipated to the surroundings more efficiently.

[0220] The distance (first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is at least twice the length (length L1) of the side of semiconductor element 4 along the first direction x. This configuration can appropriately suppress thermal interference between semiconductor element 40D and semiconductor element 40C located near the center of multiple semiconductor elements 40B to 40E. This configuration is more preferable for reducing the thermal resistance of semiconductor device A3.

[0221] The support conductor 32 includes a first conductor portion 321 (first section) and a second conductor portion 322 (second section), which are separated from each other. Only semiconductor element 40D (first semiconductor element) is disposed on the first conductor portion 321, among the plurality of semiconductor elements 40B to 40E. Semiconductor element 40C (second semiconductor element) and semiconductor element 40B adjacent to semiconductor element 40C are disposed on the second conductor portion 322. The center C1 of semiconductor element 40D (first semiconductor element) is located on the y1 side of the second direction y relative to the centers of semiconductor elements 40B and 40E. The center C2 of semiconductor element 40C (second semiconductor element) is located on the y1 side of the second direction y relative to the center C1 of semiconductor element 40D. Heat generated by semiconductor elements 40C and 40B, which are disposed on the shared second conductor portion 322, is easily retained in the second conductor portion 322. This interference of heat generated by semiconductor elements 40C and 40B can easily cause the temperature of the second conductor portion 322 to rise. As described above, due to the arrangement of semiconductor element 40C, which is most offset toward the y2 side in the second direction y among all semiconductor elements 40B to 40E, heat generated by semiconductor element 40C can be efficiently dissipated to the surrounding area of ​​semiconductor element 40C within second conductor portion 322 where semiconductor element 40C is mounted. Consequently, mutual thermal interference among semiconductor elements 40D, 40C, and 40B can be suppressed, thereby reducing the thermal resistance of semiconductor device A3.

[0222] First modification of the third embodiment:

[0223] Figure 26 A semiconductor device according to a first modification of the third embodiment is shown. Figure 26 It is a schematic plan view showing the arrangement of a plurality of semiconductor elements 4 in a semiconductor device A31 according to this modification.

[0224] The semiconductor device A31 of this modified example differs primarily from the semiconductor devices A1 and A3 described above in the arrangement of the plurality of semiconductor elements 4. Semiconductor device A31 includes four semiconductor elements 4 (semiconductor elements 40A, 40B, 40D, and 40E). The arrangement of these semiconductor elements 40A, 40B, 40D, and 40E is the same (or substantially the same) as that of semiconductor elements 40A, 40B, 40D, and 40E in semiconductor device A1.

[0225] In a semiconductor device A31 having four (an even number) semiconductor elements 4, semiconductor element 40B and semiconductor element 40D are arranged near the center in the first direction x. As in this modified example, when the number of semiconductor elements 4 (semiconductor elements 40A, 40B, 40D, 40E) is an even number, two semiconductor elements 40B and two semiconductor elements 40D are arranged near the center of the plurality of semiconductor elements 4 in the first direction x.

[0226] In the illustrated example, semiconductor elements 40A, 40B, 40D, and 40E are not arranged along the first direction x, but rather include semiconductor elements positioned differently in the second direction y. Semiconductor element 40B is located on the y1 side of the second direction y relative to semiconductor element 40A, which is adjacent to the x2 side of the first direction x. Semiconductor element 40D is located on the y1 side of the second direction y relative to semiconductor element 40C, which is adjacent to the x2 side of the first direction x. Furthermore, semiconductor element 40D is located on the y1 side of the second direction y relative to semiconductor element 40E, which is adjacent to the x1 side of the first direction x. Semiconductor element 40E is located at the same (or substantially the same) position as semiconductor element 40B in the second direction y. Among the multiple semiconductor elements 4 (semiconductor elements 40A, 40B, 40D, and 40E) arranged in this manner, semiconductor element 40D corresponds to an example of the "first semiconductor element" of the present disclosure, and semiconductor element 40B corresponds to an example of the "second semiconductor element" of the present disclosure.

[0227] like Figure 26 As shown, for the plurality of semiconductor elements 4 (semiconductor elements 40A, 40B, 40D, and 40E), the distances between the centers of semiconductor elements 4 adjacent to each other in the first direction x are as follows: A first distance D12, the distance between the center C1 of semiconductor element 40D, which is located near the center in the first direction x, and the center C4 of semiconductor element 40B, is greater than a second distance D21, the distance between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E, which is adjacent to semiconductor element 40D in the first direction x. Furthermore, the distance (first distance D12) between the center C1 of semiconductor element 40D and the center C4 of semiconductor element 40B is greater than a second distance D23, the distance between the center C4 of semiconductor element 40B and the center C6 of semiconductor element 40A, which is adjacent to semiconductor element 40B in the first direction x. Furthermore, in this modified example, the distance (first distance D12) between the center C1 of semiconductor element 40D and the center C4 of semiconductor element 40B is at least twice the length (length L1) of the side of semiconductor element 4 along the first direction x.

[0228] In semiconductor device A31, the plurality of semiconductor elements 40A, 40B, 40D, and 40E include a semiconductor element 40D (first semiconductor element) and a semiconductor element 40B (second semiconductor element) located near the center in a first direction x. The distance (first distance D12) between the center C1 of semiconductor element 40D and the center C4 of semiconductor element 40B is greater than the distance (second distance D21) between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E adjacent to semiconductor element 40D in the first direction x, and is also greater than the distance (second distance D23) between the center C4 of semiconductor element 40B and the center C6 of semiconductor element 40A adjacent to semiconductor element 40B in the first direction x. This configuration suppresses thermal interference between semiconductor element 40D and semiconductor element 40B located near the center of the plurality of semiconductor elements 40A, 40B, 40D, and 40E. This prevents the concentration of heat generated by the plurality of semiconductor elements 40A, 40B, 40D, and 40E, thereby reducing thermal resistance. As a result, the semiconductor device A31 can easily cope with increased current and improve durability.

[0229] The center C1 of semiconductor element 40D and the center C4 of semiconductor element 40B are located at different positions in a second direction y that is perpendicular to the first direction x in which the plurality of semiconductor elements 40A, 40B, 40D, and 40E are arranged. This configuration allows heat generated in semiconductor element 40D and semiconductor element 40B, which are arranged near the center of the plurality of semiconductor elements 40A, 40B, 40D, and 40E, to be efficiently dissipated to the surrounding area, further suppressing thermal interference. Furthermore, this configuration prevents the size of semiconductor device A31 in the first direction x from increasing, and increases the distance (first distance D12) between the center C1 of semiconductor element 40D and the center C4 of semiconductor element 40B.

[0230] Among the plurality of semiconductor elements 4 (semiconductor elements 40A, 40B, 40D, and 40E), the centers of semiconductor elements 4 adjacent to each other in the first direction x are located at different positions in the second direction y. This configuration allows heat generated in the plurality of semiconductor elements 40A, 40B, 40D, and 40E to be dissipated more efficiently to the surroundings.

[0231] The distance (first distance D12) between the center C1 of semiconductor element 40D and the center C4 of semiconductor element 40B is at least twice the length (length L1) of the side of semiconductor element 4 along the first direction x. This configuration can appropriately suppress thermal interference between semiconductor element 40D and semiconductor element 40B located near the center of the plurality of semiconductor elements 40A, 40B, 40D, and 40E. This configuration is more preferable for reducing the thermal resistance of semiconductor device A31.

[0232] Second modification of the third embodiment:

[0233] Figure 27 A semiconductor device according to a second modification of the third embodiment is shown. Figure 27 It is a schematic plan view showing the arrangement of a plurality of semiconductor elements 4 in a semiconductor device A32 according to this modification.

[0234] The semiconductor device A32 of this modified example differs primarily from the semiconductor devices A1 and A3 described above in the arrangement of the plurality of semiconductor elements 4. Semiconductor device A32 includes four semiconductor elements 4 (semiconductor elements 40B, 40C, 40E, and 40F). The arrangement of these semiconductor elements 40B, 40C, 40E, and 40F is the same (or substantially the same) as that of semiconductor elements 40B, 40C, 40E, and 40F in semiconductor device A1.

[0235] In semiconductor device A32 having four (an even number) semiconductor elements 4, semiconductor element 40C and semiconductor element 40E are arranged near the center in the first direction x. As in this modified example, when the number of semiconductor elements 4 (semiconductor elements 40B, 40C, 40E, and 40F) is an even number, two semiconductor elements 40C and two semiconductor elements 40E are arranged near the center of the plurality of semiconductor elements 4 in the first direction x.

[0236] In the illustrated example, semiconductor elements 40B, 40C, 40E, and 40F are not arranged along the first direction x, but rather include semiconductor elements positioned differently in the second direction y. Semiconductor element 40C is located on the y1 side of the second direction y relative to semiconductor element 40B, which is adjacent to the x2 side of the first direction x. Furthermore, semiconductor element 40C is located on the y1 side of the second direction y relative to semiconductor element 40E, which is adjacent to the x1 side of the first direction x. Semiconductor element 40E is located on the y1 side of the second direction y relative to semiconductor element 40F, which is adjacent to the x1 side of the first direction x. Semiconductor element 40E is located on the same (or substantially the same) position as semiconductor element 40B in the second direction y. Among the multiple semiconductor elements 4 (semiconductor elements 40B, 40C, 40E, and 40F) arranged in this manner, semiconductor element 40E corresponds to an example of the "first semiconductor element" of the present disclosure, and semiconductor element 40C corresponds to an example of the "second semiconductor element" of the present disclosure.

[0237] like Figure 27As shown, for the plurality of semiconductor elements 4 (semiconductor elements 40B, 40C, 40E, and 40F), the distances between the centers of semiconductor elements 4 adjacent to each other in the first direction x are as follows: A first distance D13, the distance between the center C3 of semiconductor element 40E, which is located near the center in the first direction x, and the center C2 of semiconductor element 40C, is greater than a second distance D24, the distance between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F, which is adjacent to semiconductor element 40E in the first direction x. Furthermore, the distance (first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C is greater than a second distance D22, the distance between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B, which is adjacent to semiconductor element 40C in the first direction x. Furthermore, in this modified example, the distance (first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C is at least twice the length (length L1) of the side of semiconductor element 4 along the first direction x.

[0238] In semiconductor device A32, the plurality of semiconductor elements 40B, 40C, 40E, and 40F include a semiconductor element 40E (first semiconductor element) and a semiconductor element 40C (second semiconductor element) located near the center in the first direction x. The distance (first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C is greater than the distance (second distance D24) between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F adjacent to semiconductor element 40E in the first direction x. Furthermore, the distance (second distance D22) between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B adjacent to semiconductor element 40C in the first direction x is greater. This configuration suppresses thermal interference between semiconductor element 40E and semiconductor element 40C located near the center of the plurality of semiconductor elements 40B, 40C, 40E, and 40F. This prevents the concentration of heat generated by the plurality of semiconductor elements 40B, 40C, 40E, and 40F, thereby reducing thermal resistance. As a result, the semiconductor device A32 can easily cope with increased current and improve durability.

[0239] The center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C are located at different positions in a second direction y that is perpendicular to the first direction x in which the plurality of semiconductor elements 40B, 40C, 40E, and 40F are arranged. This configuration allows heat generated in semiconductor element 40E and semiconductor element 40C, which are arranged near the center of the plurality of semiconductor elements 40B, 40C, 40E, and 40F, to be efficiently dissipated to the surrounding area, further suppressing thermal interference. Furthermore, this configuration prevents the size of semiconductor device A32 in the first direction x from increasing, and increases the distance (first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C.

[0240] Among the plurality of semiconductor elements 4 (semiconductor elements 40B, 40C, 40E, and 40F), the centers of semiconductor elements 4 adjacent to each other in the first direction x are located at different positions in the second direction y. This configuration allows heat generated in the plurality of semiconductor elements 40B, 40C, 40E, and 40F to be dissipated more efficiently to the surroundings.

[0241] The distance (first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C is at least twice the length (length L1) of the side of semiconductor element 4 along the first direction x. This configuration can appropriately suppress thermal interference between semiconductor element 40E and semiconductor element 40C located near the center of the plurality of semiconductor elements 40B, 40C, 40E, and 40F. This configuration is more preferable for reducing the thermal resistance of semiconductor device A32.

[0242] Third modification of the third embodiment:

[0243] Figure 28 A semiconductor device according to a third modification of the third embodiment is shown. Figure 28 It is a schematic plan view showing the arrangement of a plurality of semiconductor elements 4 in a semiconductor device A33 according to this modification.

[0244] The semiconductor device A33 of this modified example differs primarily from the semiconductor devices A1 and A3 described above in the arrangement of the plurality of semiconductor elements 4. Semiconductor device A33 includes four semiconductor elements 4 (semiconductor elements 40A, 40C, 40E, and 40F). The arrangement of these semiconductor elements 40A, 40C, 40E, and 40F is the same (or substantially the same) as that of semiconductor elements 40A, 40C, 40E, and 40F in semiconductor device A1.

[0245] In semiconductor device A32 having four (an even number) semiconductor elements 4, semiconductor element 40C and semiconductor element 40E are arranged near the center in the first direction x. As in this modified example, when the number of semiconductor elements 4 (semiconductor elements 40A, 40C, 40E, 40F) is an even number, two semiconductor elements 40C and two semiconductor elements 40E are arranged near the center of the plurality of semiconductor elements 4 in the first direction x.

[0246] In the illustrated example, semiconductor elements 40A, 40C, 40E, and 40F are not arranged along the first direction x, but rather include semiconductor elements positioned differently in the second direction y. Semiconductor element 40C is located on the y1 side of the second direction y relative to semiconductor element 40A, which is adjacent to the x2 side of the first direction x. Furthermore, semiconductor element 40C is located on the y1 side of the second direction y relative to semiconductor element 40E, which is adjacent to the x1 side of the first direction x. Semiconductor element 40E is located on the y1 side of the second direction y relative to semiconductor element 40F, which is adjacent to the x1 side of the first direction x. Semiconductor element 40F is located on the same (or substantially the same) position as semiconductor element 40A in the second direction y. Among the multiple semiconductor elements 4 (semiconductor elements 40A, 40C, 40E, and 40F) arranged in this manner, semiconductor element 40E corresponds to an example of a "first semiconductor element" in the present disclosure, and semiconductor element 40C corresponds to an example of a "second semiconductor element" in the present disclosure. The third conductor portion 323 where the semiconductor element 40E (first semiconductor element) is arranged corresponds to an example of the “first portion” of the present disclosure, and the second conductor portion 322 where the semiconductor element 40C (second semiconductor element) is arranged corresponds to an example of the “second portion” of the present disclosure.

[0247] like Figure 28As shown, for the plurality of semiconductor elements 4 (semiconductor elements 40A, 40C, 40E, and 40F), the distances between the centers of semiconductor elements 4 adjacent to each other in the first direction x are in the following relationship. A first distance D13, the distance between the center C3 of semiconductor element 40E, which is located near the center in the first direction x, and the center C2 of semiconductor element 40C, is greater than a second distance D24, the distance between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F, which is adjacent to semiconductor element 40E in the first direction x. Furthermore, the distance (first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C is greater than a second distance D25, the distance between the center C2 of semiconductor element 40C and the center C6 of semiconductor element 40A, which is adjacent to semiconductor element 40C in the first direction x. Furthermore, in this modified example, the distance (first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C is at least twice the length (length L1) of the side of semiconductor element 4 along the first direction x.

[0248] In semiconductor device A33, the plurality of semiconductor elements 40A, 40C, 40E, and 40F include a semiconductor element 40E (first semiconductor element) and a semiconductor element 40C (second semiconductor element) located near the center in the first direction x. The distance (first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C is greater than the distance (second distance D24) between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F adjacent to semiconductor element 40E in the first direction x, and is also greater than the distance (second distance D25) between the center C2 of semiconductor element 40C and the center C6 of semiconductor element 40A adjacent to semiconductor element 40C in the first direction x. This configuration suppresses thermal interference between semiconductor element 40E and semiconductor element 40C located near the center of the plurality of semiconductor elements 40A, 40C, 40E, and 40F. This prevents the concentration of heat generated by the plurality of semiconductor elements 40A, 40C, 40E, and 40F, thereby reducing thermal resistance. As a result, the semiconductor device A33 can easily cope with increased current and improve durability.

[0249] The center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C are located at different positions in a second direction y that is perpendicular to the first direction x in which the plurality of semiconductor elements 40A, 40C, 40E, and 40F are arranged. This configuration allows heat generated in semiconductor element 40E and semiconductor element 40C, which are arranged near the center of the plurality of semiconductor elements 40A, 40C, 40E, and 40F, to be efficiently dissipated to the surrounding area, further suppressing thermal interference. Furthermore, this configuration prevents the size of semiconductor device A33 in the first direction x from increasing, and increases the distance (first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C.

[0250] Among the plurality of semiconductor elements 4 (semiconductor elements 40A, 40C, 40E, and 40F), the centers of semiconductor elements 4 adjacent to each other in the first direction x are located at different positions in the second direction y. This configuration allows heat generated in the plurality of semiconductor elements 40A, 40C, 40E, and 40F to be dissipated more efficiently to the surroundings.

[0251] The distance (first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C is at least twice the length (length L1) of the side of semiconductor element 4 along the first direction x. This configuration can appropriately suppress thermal interference between semiconductor element 40E and semiconductor element 40C located near the center of the plurality of semiconductor elements 40A, 40C, 40E, and 40F. This configuration is more preferable for reducing the thermal resistance of semiconductor device A33.

[0252] The support conductor 32 includes a third conductor portion 323 (first portion) and a second conductor portion 322 (second portion) that are separated from each other. Only semiconductor element 40E (first semiconductor element) is disposed in the third conductor portion 323, among the plurality of semiconductor elements 40A, 40C, 40E, and 40F. Semiconductor element 40C (second semiconductor element) and semiconductor element 40A adjacent to semiconductor element 40C are disposed in the second conductor portion 322. The center C3 of semiconductor element 40E (first semiconductor element) is located on the y1 side of the second direction y relative to the centers of semiconductor elements 40A and 40F. The center C2 of semiconductor element 40C (second semiconductor element) is located on the y1 side of the second direction y relative to the center C3 of semiconductor element 40E. Heat generated by semiconductor element 40C and semiconductor element 40A, both of which are arranged on a shared second conductor portion 322, tends to accumulate in second conductor portion 322. This interference between the heat generated by semiconductor element 40C and semiconductor element 40A can easily cause the temperature of second conductor portion 322 to rise. As described above, by arranging semiconductor element 40C most toward the y2 side in the second direction y among all semiconductor elements 40A, 40C, 40E, and 40F, heat generated by semiconductor element 40C can be efficiently dissipated to the surrounding area of ​​semiconductor element 40C within second conductor portion 322, where semiconductor element 40C is mounted. Consequently, mutual thermal interference between semiconductor elements 40E, 40C, and 40A can be suppressed, reducing the thermal resistance of semiconductor device A33.

[0253] Fourth modification of the third embodiment:

[0254] Figure 29 A semiconductor device according to a fourth modification of the third embodiment is shown. Figure 29 It is a schematic plan view showing the arrangement of a plurality of semiconductor elements 4 in a semiconductor device A34 according to this modification.

[0255] The semiconductor device A34 of this modified example differs primarily from the semiconductor devices A1 and A3 described above in the arrangement of the plurality of semiconductor elements 4. Semiconductor device A33 includes four semiconductor elements 4 (semiconductor elements 40A, 40B, 40E, and 40F). The arrangement of these semiconductor elements 40A, 40B, 40E, and 40F is the same (or substantially the same) as that of semiconductor elements 40A, 40B, 40E, and 40F in semiconductor device A1.

[0256] In a semiconductor device A33 having four (an even number) semiconductor elements 4, semiconductor element 40B and semiconductor element 40E are arranged near the center in the first direction x. As in this modified example, when the number of semiconductor elements 4 (semiconductor elements 40A, 40B, 40E, 40F) is an even number, two semiconductor elements 40B and two semiconductor elements 40E are arranged near the center of the plurality of semiconductor elements 4 in the first direction x.

[0257] In the illustrated example, semiconductor elements 40A, 40B, 40E, and 40F are not arranged along the first direction x, but include semiconductor elements positioned differently in the second direction y. Semiconductor element 40B is located on the y1 side of the second direction y relative to semiconductor element 40A, which is adjacent to the x2 side of the first direction x. Semiconductor element 40B is located at the same (or substantially the same) position in the second direction y as semiconductor element 40E, which is adjacent to the x1 side of the first direction x. Semiconductor element 40E is located on the y1 side of the second direction y relative to semiconductor element 40F, which is adjacent to the x1 side of the first direction x. Semiconductor element 40F is located at the same (or substantially the same) position in the second direction y as semiconductor element 40A. Among the plurality of semiconductor elements 4 (semiconductor elements 40A, 40B, 40E, and 40F) arranged in this manner, semiconductor element 40E corresponds to an example of the "first semiconductor element" of the present disclosure, and semiconductor element 40B corresponds to an example of the "second semiconductor element" of the present disclosure.

[0258] like Figure 29 As shown, for the plurality of semiconductor elements 4 (semiconductor elements 40A, 40B, 40E, and 40F), the distances between the centers of semiconductor elements 4 adjacent to each other in the first direction x are in the following relationship. A first distance D14, the distance between the center C3 of semiconductor element 40E, which is located near the center in the first direction x, and the center C4 of semiconductor element 40B, is greater than a second distance D24, the distance between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F, which is adjacent to semiconductor element 40E in the first direction x. Furthermore, the distance (first distance D14) between the center C3 of semiconductor element 40E and the center C4 of semiconductor element 40B is greater than a second distance D23, the distance between the center C4 of semiconductor element 40B and the center C6 of semiconductor element 40A, which is adjacent to semiconductor element 40B in the first direction x. Furthermore, in this modified example, the distance (first distance D14) between the center C3 of semiconductor element 40E and the center C4 of semiconductor element 40B is at least twice the length (length L1) of the side of semiconductor element 4 along the first direction x.

[0259] In semiconductor device A34, the plurality of semiconductor elements 40A, 40B, 40E, and 40F include a semiconductor element 40E (a first semiconductor element) and a semiconductor element 40B (a second semiconductor element) located near the center in a first direction x. The distance (a first distance D14) between the center C3 of semiconductor element 40E and the center C4 of semiconductor element 40B is greater than the distance (a second distance D24) between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F adjacent to semiconductor element 40E in the first direction x, and is also greater than the distance (a second distance D23) between the center C4 of semiconductor element 40B and the center C6 of semiconductor element 40A adjacent to semiconductor element 40B in the first direction x. This configuration suppresses thermal interference between semiconductor element 40E and semiconductor element 40B located near the center of the plurality of semiconductor elements 40A, 40B, 40E, and 40F. This prevents the concentration of heat generated by the plurality of semiconductor elements 40A, 40B, 40E, and 40F, thereby reducing thermal resistance. As a result, the semiconductor device A34 can easily cope with increased current and improve durability.

[0260] The distance (first distance D14) between the center C3 of semiconductor element 40E and the center C4 of semiconductor element 40B is at least twice the length (length L1) of the side of semiconductor element 4 along the first direction x. This configuration can appropriately suppress thermal interference between semiconductor element 40E and semiconductor element 40B located near the center of the plurality of semiconductor elements 40A, 40B, 40E, and 40F. This configuration is more preferable for reducing the thermal resistance of semiconductor device A34.

[0261] The semiconductor device of the present disclosure is not limited to the above-described embodiment, and the specific structure of each part of the semiconductor device of the present disclosure can be freely changed in various designs.

[0262] While the semiconductor device A1 and other embodiments described above utilize a molded module formed by molding the sealing resin 8, the semiconductor device of the present disclosure is not limited thereto. The semiconductor device of the present disclosure may, for example, be comprised of a housing module. In the case of a housing module, the inner space of the housing is filled with an insulating material such as silicone gel as the sealing resin.

[0263] The present disclosure includes the embodiments described in the following supplementary notes.

[0264] Note 1.

[0265] A semiconductor device comprising:

[0266] a conductive portion having a first main surface facing one side in a thickness direction and a first back surface facing a side opposite to the first main surface;

[0267] a plurality of four or more semiconductor elements arranged on the first main surface; and

[0268] a sealing resin covering the plurality of semiconductor elements and at least a portion of the conductive portion,

[0269] The plurality of semiconductor elements are arranged in a first direction perpendicular to the thickness direction.

[0270] When the number of the plurality of semiconductor elements is an even number,

[0271] The plurality of semiconductor elements include a first semiconductor element and a second semiconductor element close to the center in the first direction,

[0272] A first distance between the center of the first semiconductor element and the center of the second semiconductor element is greater than a second distance between the center of either the first semiconductor element or the second semiconductor element and the center of the other semiconductor element adjacent to either the first semiconductor element or the second semiconductor element in the first direction.

[0273] When the number of the plurality of semiconductor elements is an odd number,

[0274] The plurality of semiconductor elements include: a third semiconductor element located near the center in the first direction; a fourth semiconductor element located adjacent to the third semiconductor element on one side in the first direction; and a fifth semiconductor element located adjacent to the third semiconductor element on the other side in the first direction.

[0275] The third distance between the center of the third semiconductor element and the center of the fourth semiconductor element, that is, the distance between the center of the third semiconductor element and the center of the fifth semiconductor element, that is, the fourth distance, are both greater than the fifth distance, which is the distance between the center of either the fourth semiconductor element or the fifth semiconductor element and the center of the other semiconductor element adjacent to either the fourth semiconductor element or the fifth semiconductor element in the first direction.

[0276] Note 2.

[0277] The semiconductor device according to Supplementary Note 1, wherein

[0278] When the number of the plurality of semiconductor elements is an even number,

[0279] The center of the first semiconductor element and the center of the second semiconductor element are located at different positions in a second direction perpendicular to the thickness direction and the first direction.

[0280] When the number of the plurality of semiconductor elements is an odd number,

[0281] The center of the third semiconductor element is located at a different position from the centers of the fourth semiconductor element and the fifth semiconductor element in the second direction.

[0282] Note 3.

[0283] The semiconductor device according to Supplementary Note 2, wherein

[0284] Among the plurality of semiconductor elements, centers of the semiconductor elements adjacent to each other in the first direction are located at different positions in the second direction.

[0285] Note 4.

[0286] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein:

[0287] When the number of the plurality of semiconductor elements is an even number,

[0288] The first distance is greater than a sixth distance between centers of the other semiconductor elements adjacent to each other in the first direction among the plurality of semiconductor elements.

[0289] When the number of the plurality of semiconductor elements is an odd number,

[0290] The third distance and the fourth distance are each greater than a seventh distance between centers of the other semiconductor elements adjacent to each other in the first direction among the plurality of semiconductor elements.

[0291] Note 5.

[0292] The semiconductor device according to Supplementary Note 4, wherein

[0293] When the number of the plurality of semiconductor elements is an even number,

[0294] The second distance is greater than the sixth distance,

[0295] When the number of the plurality of semiconductor elements is an odd number,

[0296] The fifth distance is greater than the seventh distance.

[0297] Note 6.

[0298] The semiconductor device according to Supplementary Note 5, wherein

[0299] When the number of the plurality of semiconductor elements is an even number,

[0300] The sixth distance becomes smaller as the other semiconductor elements adjacent to each other in the first direction are farther away from the center in the first direction.

[0301] When the number of the plurality of semiconductor elements is an odd number,

[0302] The seventh distance becomes smaller as other semiconductor elements adjacent to each other in the first direction are farther away from the center in the first direction.

[0303] Note 7.

[0304] The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein:

[0305] When the number of the plurality of semiconductor elements is an even number,

[0306] The first distance is at least twice the length of the side of the semiconductor element along the first direction.

[0307] When the number of the plurality of semiconductor elements is an odd number,

[0308] The third distance and the fourth distance are each at least twice the length of the side of the semiconductor element along the first direction.

[0309] Note 8.

[0310] The semiconductor device according to Supplementary Note 2, wherein

[0311] The conductive portion includes a first portion and a second portion separated from each other,

[0312] Only the first semiconductor element among the plurality of semiconductor elements is arranged in the first portion.

[0313] The second semiconductor element and the other semiconductor elements adjacent to the second semiconductor element are arranged in the second portion.

[0314] The center of the first semiconductor element is located on one side in the second direction relative to the center of any other semiconductor element among the plurality of semiconductor elements.

[0315] The center of the second semiconductor element is located on one side in the second direction relative to the center of the first semiconductor element.

[0316] Note 9.

[0317] The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein:

[0318] The device further comprises a support having a second main surface facing one side in the thickness direction and a second back surface facing a side opposite to the second main surface.

[0319] The first rear surface of the conductive portion is bonded to the second main surface.

[0320] Note 10.

[0321] The semiconductor device according to Supplementary Note 9, wherein

[0322] The support body includes an insulating substrate having the second main surface; and a metal layer bonded to a surface of the insulating substrate opposite to the second main surface and having the second back surface.

[0323] Note 11.

[0324] The semiconductor device according to Supplementary Note 10, wherein

[0325] The insulating substrate is made of ceramic.

[0326] Note 12.

[0327] The semiconductor device according to Supplementary Note 9, wherein

[0328] The conductive part is composed of a lead wire,

[0329] The support body is composed of an insulating substrate.

[0330] Note 13.

[0331] The semiconductor device according to any one of Supplementary Notes 9 to 12, wherein:

[0332] The plurality of semiconductor elements are respectively switching elements.

[0333] Note 14.

[0334] The semiconductor device according to Supplementary Note 13, wherein

[0335] The plurality of semiconductor elements respectively have: an element main surface facing one side in the thickness direction; an element back surface facing the other side in the thickness direction; a source electrode and a gate electrode arranged on the element main surface; and a drain electrode arranged on the element back surface.

[0336] Note 15.

[0337] The semiconductor device according to Supplementary Note 10 or 11, wherein

[0338] The heat capacity of the structure composed of the conductive part and the support body is 0.01 to 15 J / K.

[0339] The heat capacity of each of the plurality of semiconductor elements is 0.0001 to 0.5 J / K.

[0340] Note 16.

[0341] The semiconductor device according to Supplementary Note 10 or 11, wherein

[0342] The thermal resistance of the structure composed of the conductive part and the support body is 0.0003 to 1.5 K / W.

[0343] The thermal resistance of each of the plurality of semiconductor elements is 0.0003 to 1.5 K / W.

[0344] Note 17.

[0345] The semiconductor device according to Supplementary Note 13 or 14, wherein

[0346] Each of the plurality of semiconductor elements includes at least one of a wide bandgap semiconductor and an ultra-wide bandgap semiconductor.

[0347] Note 18.

[0348] A semiconductor device assembly comprising:

[0349] The semiconductor device according to any one of Supplementary Notes 9 to 17;

[0350] coolers; and

[0351] a cooling unit that cools the cooler,

[0352] The second back surface of the support body is exposed from the sealing resin,

[0353] The cooler has a portion in contact with the second rear surface.

[0354] Note 19.

[0355] The semiconductor device assembly according to Supplementary Note 18, wherein:

[0356] It also has a control unit.

[0357] The semiconductor device includes a temperature detection element disposed on the second main surface of the support body.

[0358] The control unit controls the cooling unit based on the temperature detected by the temperature detection element.

[0359] Note 20.

[0360] The semiconductor device assembly according to Supplementary Note 19, wherein:

[0361] A heating unit is further provided, which heats the cooler.

[0362] The control unit controls the heating unit based on the temperature detected by the temperature detection element.

[0363] Note 21.

[0364] A vehicle including a power conversion device including the semiconductor device according to Supplementary Note 13 or 14.

[0365] Explanation of symbols

[0366] A1, A2, A3, A31, A32, A33, A34—semiconductor device; B1, B11—vehicle; B2, B21—semiconductor device assembly; 1, 11 to 15—leads; 110—mounting portion (conductive portion, second portion); 120—mounting portion (conductive portion, first portion); 130, 140—mounting portion (conductive portion); 18—bonding material; 19—conductive bonding material; 2, 21 to 23—leads; 28—conductive bonding material; 3—support; 3a—second main surface; 3b—second back surface; 30, 31 —Insulating substrate; 32—Supporting conductor (conductive portion); 32a—First main surface; 32b—First back surface; 321—First conductor portion; 322—Second conductor portion; 323—Third conductor portion; 324—Fourth conductor portion; 325—Fifth conductor portion; 326—Sixth conductor portion; 327—Seventh conductor portion; 328—Eighth conductor portion; 33—Metal layer; 4, 40A to 40N, 40P to 40R—Semiconductor element; 41—Element main surface; 42—Element back surface; 43—Source electrode; 44—Gate electrode; 45—Drain electrode; 47—Conductive bonding material; 5—Wiring portion; 501—Wiring; 502—Pad portion; 511-515, 521—Joint portion; 6—Thermistor; 62—Insulating member; 63—Conductive bonding material; 71-74—Wires; 8—Sealing resin; 81—Resin main surface; 82—Resin back surface; 83-86—Resin side surface; 831, 841—Recessed portion; 870—Charging facility; 871—AC-DC converter (power converter); 872—Power receiving device; 873—Battery; 874—Drive system; 875 —DC-DC converter (power converter); 91—cooler; 911—mounting surface; 912—flow path; 913—mounting hole; 92—mounting component; 93—fastening component; 94—control unit; 95—cooling unit; 96—heating unit; D1, D12, D13, D14—first distance; D21, D22, D23, D24, D25—second distance; D3—third distance; D4—fourth distance; D51, D52—fifth distance; D61~D64—sixth distance; D71~D74—seventh distance.

Claims

1. A semiconductor device, characterized in that: have: a conductive portion having a first main surface facing one side in a thickness direction and a first back surface facing a side opposite to the first main surface; a plurality of four or more semiconductor elements arranged on the first main surface; as well as a sealing resin covering the plurality of semiconductor elements and at least a portion of the conductive portion, The plurality of semiconductor elements are arranged in a first direction perpendicular to the thickness direction. When the number of the plurality of semiconductor elements is an even number, The plurality of semiconductor elements include a first semiconductor element and a second semiconductor element close to the center in the first direction, A first distance between the center of the first semiconductor element and the center of the second semiconductor element is greater than a second distance between the center of either the first semiconductor element or the second semiconductor element and the center of the other semiconductor element adjacent to either the first semiconductor element or the second semiconductor element in the first direction. When the number of the plurality of semiconductor elements is an odd number, The plurality of semiconductor elements include: a third semiconductor element located near the center in the first direction; a fourth semiconductor element located adjacent to the third semiconductor element on one side in the first direction; and a fifth semiconductor element located adjacent to the third semiconductor element on the other side in the first direction. The third distance between the center of the third semiconductor element and the center of the fourth semiconductor element, that is, the distance between the center of the third semiconductor element and the center of the fifth semiconductor element, that is, the fourth distance, are both greater than the fifth distance, which is the distance between the center of either the fourth semiconductor element or the fifth semiconductor element and the center of the other semiconductor element adjacent to either the fourth semiconductor element or the fifth semiconductor element in the first direction.

2. The semiconductor device according to claim 1, wherein When the number of the plurality of semiconductor elements is an even number, The center of the first semiconductor element and the center of the second semiconductor element are located at different positions in a second direction perpendicular to the thickness direction and the first direction. When the number of the plurality of semiconductor elements is an odd number, The center of the third semiconductor element is located at a different position from the centers of the fourth semiconductor element and the fifth semiconductor element in the second direction.

3. The semiconductor device according to claim 2, wherein Among the plurality of semiconductor elements, centers of the semiconductor elements adjacent to each other in the first direction are located at different positions in the second direction.

4. The semiconductor device according to any one of claims 1 to 3, wherein When the number of the plurality of semiconductor elements is an even number, The first distance is greater than a sixth distance between centers of the other semiconductor elements adjacent to each other in the first direction among the plurality of semiconductor elements. When the number of the plurality of semiconductor elements is an odd number, The third distance and the fourth distance are each greater than a seventh distance between centers of the other semiconductor elements adjacent to each other in the first direction among the plurality of semiconductor elements.

5. The semiconductor device according to claim 4, wherein When the number of the plurality of semiconductor elements is an even number, The second distance is greater than the sixth distance, When the number of the plurality of semiconductor elements is an odd number, The fifth distance is greater than the seventh distance.

6. The semiconductor device according to claim 5, wherein When the number of the plurality of semiconductor elements is an even number, The sixth distance becomes smaller as the other semiconductor elements adjacent to each other in the first direction are farther away from the center in the first direction. When the number of the plurality of semiconductor elements is an odd number, The seventh distance becomes smaller as other semiconductor elements adjacent to each other in the first direction are farther away from the center in the first direction.

7. The semiconductor device according to any one of claims 1 to 6, wherein: When the number of the plurality of semiconductor elements is an even number, The first distance is at least twice the length of the side of the semiconductor element along the first direction. When the number of the plurality of semiconductor elements is an odd number, The third distance and the fourth distance are each at least twice the length of the side of the semiconductor element along the first direction.

8. The semiconductor device according to claim 2, wherein The conductive portion includes a first portion and a second portion separated from each other, Only the first semiconductor element among the plurality of semiconductor elements is arranged in the first portion. The second semiconductor element and the other semiconductor elements adjacent to the second semiconductor element are arranged in the second portion. The center of the first semiconductor element is located on one side in the second direction relative to the center of any other semiconductor element among the plurality of semiconductor elements. The center of the second semiconductor element is located on one side in the second direction relative to the center of the first semiconductor element.

9. The semiconductor device according to any one of claims 1 to 8, wherein: The device further comprises a support having a second main surface facing one side in the thickness direction and a second back surface facing a side opposite to the second main surface. The first rear surface of the conductive portion is bonded to the second main surface.

10. The semiconductor device according to claim 9, wherein The support body includes an insulating substrate having the second main surface; and a metal layer bonded to a surface of the insulating substrate opposite to the second main surface and having the second back surface.

11. The semiconductor device according to claim 10, wherein The insulating substrate is made of ceramic.

12. The semiconductor device according to claim 9, wherein The conductive part is composed of a lead wire, The support body is composed of an insulating substrate.

13. The semiconductor device according to any one of claims 9 to 12, wherein: The plurality of semiconductor elements are respectively switching elements.

14. The semiconductor device according to claim 13, wherein Each of the plurality of semiconductor elements has: an element main surface facing one side in the thickness direction; an element back surface facing the other side in the thickness direction; a source electrode and a gate electrode arranged on the element main surface; and a drain electrode disposed on the back side of the device.

15. The semiconductor device according to claim 10 or 11, wherein: The heat capacity of the structure composed of the conductive part and the support body is 0.01 to 15 J / K. The heat capacity of each of the plurality of semiconductor elements is 0.0001 to 0.5 J / K.

16. The semiconductor device according to claim 10 or 11, wherein: The thermal resistance of the structure composed of the conductive part and the support body is 0.0003 to 1.5 K / W. The thermal resistance of each of the plurality of semiconductor elements is 0.0003 to 1.5 K / W.

17. The semiconductor device according to claim 13 or 14, wherein: Each of the plurality of semiconductor elements includes at least one of a wide bandgap semiconductor and an ultra-wide bandgap semiconductor.

18. A semiconductor device assembly, characterized in that: have: The semiconductor device according to any one of claims 9 to 17; coolers; and a cooling unit that cools the cooler, The second back surface of the support body is exposed from the sealing resin, The cooler has a portion in contact with the second rear surface.

19. A vehicle, characterized in that: A power conversion device including the semiconductor device according to claim 13 or 14 is provided.

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