Memory device and system and refresh address generation circuit

Abstract

The invention relates to the field of integrated circuits, and discloses a memory device, a memory system and a refresh address generation circuit. The memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of rows of word lines and memory cells coupled to the word lines. The peripheral circuit is coupled to the plurality of rows of word lines. Wherein the peripheral circuit is configured to determine an attack row in the plurality of rows of word lines, and perform non-uniform refreshing on a victim row located on one side of the attack row.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and in particular to a memory device, a system and a refresh address generation circuit. BACKGROUND

[0002] With the gradual improvement of semiconductor manufacturing process level, the integration of memory is increasing, and the physical size of the storage unit is shrinking, and the word lines in the storage unit are physically closer, so the capacitive coupling between adjacent word lines increases, and the data stored on the storage unit is more and more easily affected by the adjacent storage row.

[0003] At the same time, with the improvement of the working frequency of the memory, the word line will be activated more frequently, or activated for a long time, so that the row hammer problem of the memory is becoming more and more serious. How to effectively solve the row hammer problem is a problem to be solved at present. SUMMARY

[0004] The embodiments of the present application provide a memory device, a system and a refresh address generation circuit.

[0005] In a first aspect, the embodiments of the present application provide a memory device, comprising: a storage unit array and a peripheral circuit; the storage unit array comprises: a plurality of word lines, and a storage unit coupled to the word lines; the peripheral circuit is coupled to the plurality of word lines; wherein the peripheral circuit is configured to determine an attack row, and to perform non-uniform refresh on a victim row located on one side of the attack row.

[0006] In some embodiments of the present application, the peripheral circuit comprises: a row hammer refresh control circuit configured to generate a row hammer refresh signal and a non-uniform refresh flag signal according to a refresh command signal and an adjustment signal; an attack row address determination circuit coupled to the row hammer refresh control circuit and configured to output an attack row address in response to the row hammer refresh signal; a row hammer refresh address generation circuit coupled to the row hammer refresh control circuit and the attack row address determination circuit, and configured to generate a row hammer refresh address corresponding to the attack row address in response to the row hammer refresh signal and the non-uniform refresh flag signal; wherein if the non-uniform refresh flag signal indicates that the non-uniform refresh is performed on the victim row located on one side of the attack row, the row hammer refresh address comprises a victim row address located on one side of the attack row.

[0007] In some embodiments of the present application, the adjustment signal represents the proportion of the non-uniform refresh in the row hammer refresh.

[0008] In some embodiments of the application, if the non-uniform refresh flag signal indicates to refresh the victim rows on one side of the attack row, the row hammer refresh address comprises a victim row address on one side of the attack row address.

[0009] In some embodiments of the application, the non-uniform refresh flag signal is at a high level, indicating to perform the non-uniform refresh on the victim rows on one side of the attack row; and the non-uniform refresh flag signal is at a low level, indicating to refresh the victim rows on both sides of the attack row.

[0010] In some embodiments of the application, the row hammer refresh control circuit is further configured to generate a row hammer refresh address generation signal according to the refresh command signal and the adjustment signal; and the row hammer refresh address generation circuit is further configured to generate the row hammer refresh address in response to the row hammer refresh address generation signal, the row hammer refresh signal and the non-uniform refresh flag signal.

[0011] In some embodiments of the application, if the non-uniform refresh flag signal indicates to perform the non-uniform refresh on the victim rows on one side of the attack row, the row hammer refresh address generation signal comprises a single pulse signal corresponding to the row hammer refresh signal; and if the non-uniform refresh flag signal indicates to refresh the victim rows on both sides of the attack row, the row hammer refresh address generation signal comprises a double pulse signal corresponding to the row hammer refresh signal.

[0012] In some embodiments of the application, the peripheral circuit further comprises a normal refresh address generation circuit coupled to the row hammer refresh control circuit and configured to receive the refresh command signal and the row hammer refresh signal and output a normal refresh address according to the refresh command signal and the row hammer refresh signal.

[0013] In some embodiments of the application, the peripheral circuit further comprises a first multiplexer coupled to the row hammer refresh control circuit, the row hammer refresh address generation circuit and the normal refresh address generation circuit respectively and configured to receive the row hammer refresh address, the normal refresh address and the row hammer refresh signal, output the row hammer refresh address in response to the row hammer refresh signal being at a first level, and output the normal refresh address in response to the row hammer refresh signal being at a second level.

[0014] In some embodiments of the present application, the row hammer refresh address generation circuit comprises: a first victim row address generation circuit coupled to the attack row address determination circuit and the row hammer refresh control circuit, configured to receive the attack row address and the row hammer refresh signal, and generate the victim row address located on one side of the attack row address; and a second victim row address generation circuit coupled to the attack row address determination circuit and the row hammer refresh control circuit, configured to receive the attack row address and the row hammer refresh signal, and generate the victim row address located on both sides of the attack row address.

[0015] In some embodiments of the present application, the row hammer refresh address generation circuit further comprises: a second multiplexer coupled to the first victim row address generation circuit, the second victim row address generation circuit, and the row hammer refresh control circuit, respectively, and configured to: in response to the non-uniform refresh flag signal indicating that the non-uniform refresh is performed on the victim row located on one side of the attack row, output the victim row address located on one side of the attack row address; and in response to the non-uniform refresh flag signal indicating that the refresh is performed on the victim row located on both sides of the attack row, output the victim row address located on both sides of the attack row address.

[0016] In some embodiments of the present application, the row hammer refresh control circuit comprises: a counter configured to record the number of pulses of the row hammer refresh signal and output as a count value; and a comparator coupled to the counter and configured to compare the count value and the adjustment signal, and output the corresponding non-uniform refresh flag signal according to the comparison result.

[0017] In some embodiments of the present application, the comparator is further configured to, in the case that the count value matches the adjustment signal, output the non-uniform refresh flag signal indicating that the non-uniform refresh is performed on the victim row located on one side of the attack row, and otherwise, output the non-uniform refresh flag signal indicating that the refresh is performed on the victim row located on both sides of the attack row.

[0018] In some embodiments of the present application, the distance between the word line located on one side of the attack row and the attack row is not equal to the distance between the word line located on the other side of the attack row and the attack row; and the peripheral circuit is further configured to perform the non-uniform refresh on the victim row with the word line closer to the attack row.

[0019] In some embodiments of the present application, the memory device comprises a dynamic random access memory.

[0020] In a second aspect, embodiments of the present application provide a memory system, comprising: one or more memory devices as described in the above-mentioned solutions; and a memory controller coupled to the memory device and configured to control the memory device.

[0021] In a third aspect, an embodiment of the present application provides a refresh address generation circuit, comprising: a row hammer refresh control circuit configured to generate a row hammer refresh signal and a non-uniform refresh flag signal according to a refresh command signal and an adjustment signal; an attack row address determination circuit coupled to the row hammer refresh control circuit and configured to output an attack row address in response to the row hammer refresh signal; and a row hammer refresh address generation circuit coupled to the row hammer refresh control circuit and the attack row address determination circuit and configured to generate a row hammer refresh address corresponding to the attack row address in response to the row hammer refresh signal and the non-uniform refresh flag signal, wherein if the non-uniform refresh flag signal indicates that a victim row located on one side of the attack row is subjected to the non-uniform refresh, the row hammer refresh address comprises a victim row address located on one side of the attack row.

[0022] In some embodiments of the present application, the refresh address generation circuit further comprises a normal refresh address generation circuit coupled to the row hammer refresh control circuit and configured to receive the refresh command signal and the row hammer refresh signal and output a normal refresh address according to the refresh command signal and the row hammer refresh signal.

[0023] In some embodiments of the present application, the refresh address generation circuit further comprises a first multiplexer coupled to the row hammer refresh control circuit, the row hammer refresh address generation circuit and the normal refresh address generation circuit and configured to receive the row hammer refresh address, the normal refresh address and the row hammer refresh signal, output the row hammer refresh address in response to the row hammer refresh signal being at a first level, and output the normal refresh address in response to the row hammer refresh signal being at a second level.

[0024] In a fourth aspect, an embodiment of the present application provides a row hammer refresh method, comprising: receiving an attack row address in response to a row hammer refresh signal; generating a row hammer refresh address corresponding to the attack row address in response to a non-uniform refresh flag signal, wherein if the non-uniform refresh flag signal indicates that a victim row located on one side of the attack row is subjected to non-uniform refresh, the row hammer refresh address comprises a victim row address located on one side of the attack row; and performing row hammer refresh based on the row hammer refresh address.

[0025] In some embodiments of the present application, if the non-uniform refresh flag signal indicates that victim rows located on both sides of the attack row are subjected to refresh, the row hammer refresh address comprises victim row addresses located on both sides of the attack row address. BRIEF DESCRIPTION OF DRAWINGS

[0026] In the drawings, like reference numerals refer to like elements throughout the various drawings. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating principles of the application. It should be understood that the drawings are merely schematic and that the application can be embodied in many different forms.

[0027] Figure 1 A block diagram of an exemplary electronic device of embodiments of the present application;

[0028] Figure 2A A block diagram of an exemplary solid state drive (SSD) or Universal Flash Storage (UFS) of embodiments of the present application;

[0029] Figure 2B A block diagram of an exemplary memory of embodiments of the present application;

[0030] Figure 3 A block diagram of an exemplary dynamic random access memory of embodiments of the present application;

[0031] Figure 4 A block diagram of an exemplary dynamic random access memory of embodiments of the present application;

[0032] Figure 5 A block diagram of an exemplary memory device of embodiments of the present application;

[0033] Figure 6 A block diagram of an exemplary word line distribution of embodiments of the present application;

[0034] Figure 7 A block diagram of an exemplary peripheral circuit of embodiments of the present application Figure 1 ;

[0035] Figure 8 A block diagram of an exemplary peripheral circuit of embodiments of the present application ;

[0036] Figure 9 A block diagram of an exemplary peripheral circuit of embodiments of the present application Figure 3 ;

[0037] Figure 10 A block diagram of an exemplary signal waveform of embodiments of the present application Figure 1 ;

[0038] Figure 11 A block diagram of an exemplary signal waveform of embodiments of the present application

[0039] Figure 12 A block diagram of an exemplary row hammer refresh address generation circuit of embodiments of the present application Figure 1;

[0040] Figure 13 Structure diagram of an exemplary row hammer refresh address generation circuit according to an embodiment of the present application;

[0041] Figure 14 Structure diagram of an exemplary row hammer refresh control circuit according to an embodiment of the present application;

[0042] Figure 15 Implementation flow diagram of an exemplary row hammer refresh method according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] Exemplary embodiments of the present application will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it is to be understood that the present application can be embodied in various forms without being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0044] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail in order to avoid unnecessarily complicating this disclosure. As used herein, the term "exemplary" means "an example of."

[0045] In the drawings, the size of layers, regions, elements, and the relative sizes of the same can be exaggerated for clarity. Like reference numbers in different drawings can represent the same element.

[0046] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected", or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0047] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms "root", "strip" or "piece" of transmission line all represent the same meaning.

[0049] In order to enable more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present application.

[0050] Figure 1 A constituent block diagram of an exemplary electronic device according to embodiments of the present application is shown. The electronic device 1 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage therein. As shown, the electronic device 1 can include a host HOST and a memory system 30 including a memory controller 10 and one or more memory devices 20. The host HOST can be a processor (e.g., a central processing unit (CPU) or a graphic processing unit (GPU)) of the electronic device. The host HOST can be configured to send data to or receive data from the memory device 20. The memory controller 10 is coupled to the memory device 20 and the host HOST, and is configured to control the memory device 20. The memory controller 10 can manage data stored in the memory device 20, and communicate with the host HOST. Figure 1

[0051] The memory controller 10 can be configured to control operations of the memory device 20, such as read, erase, write, and refresh operations. In some implementations, the memory controller 10 is also configured to process error correction codes (ECCs) on data read from or written to the memory device 20. The memory controller 10 can also perform any other suitable functions, such as formatting the memory device 20.

[0052] In some specific embodiments, the memory controller 10 and the one or more memory devices 20 can be integrated into various types of electronic devices, for example, the memory controller 10 can be integrated in a north bridge of a computer motherboard or directly into a computer CPU, and the plurality of memory devices 20 can be integrated into a memory stick. That is, the memory system 30 can be implemented and packaged into different types of terminal electronic products.

[0053] ​The memory controller 10 can transmit / receive data to / from the host HOST and can transmit a command CMD and an address ADDR to the memory device 20. The memory controller 10 can include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 can receive the command CMD and the address ADDR from the host HOST, the command generator 110 can generate an access command, a row hammer refresh command, etc. by decoding the command CMD received from the host HOST, and can provide the access command and the row hammer refresh command to the memory device 20 through the device interface 130. The access command can be a signal instructing the memory device 20 to write or read data by accessing a row of the memory cell array 220 corresponding to the address ADDR. The row hammer refresh command can be a signal commanding the memory device 20 to perform an additional refresh operation on a word line adjacent to a word line that is intensively accessed within a short period. In other words, the additional refresh operation can be performed on a word line adjacent to a word line that is accessed a plurality of times within a short period.

[0054] The address generator 120 in the memory controller 10 can generate a row address and a column address to be accessed in the memory cell array 220 by decoding the address ADDR received from the host interface 140. Also, the memory device 20 can generate an address of a bank to be accessed when the memory cell array 220 includes a plurality of banks.

[0055] Also, the memory controller 10 can control memory operations such as a write and a read by providing various signals to the memory device 20 through the device interface 130. For example, the memory controller 10 can provide a write command to the memory device 20. The write command is used to instruct the memory device 20 to perform a write operation to store data into the memory device 20.

[0056] In some embodiments, the memory device 20 includes a memory cell array 220 and a peripheral circuit 210; wherein the memory cell array 220 includes a plurality of banks, each bank includes a plurality of blocks, each block includes a plurality of memory cell rows and a plurality of memory cell columns, each memory cell row is coupled with a corresponding word line, and each memory cell column is coupled with a corresponding bit line. The peripheral circuit 210 can write data DATA to or read data DATA from the memory cell array 220 based on a command CMD and an address ADDR received from the memory controller 10 and send the data DATA to the memory controller 10, or can provide a control signal CTRL for refreshing memory cells included in the memory cell array 220 to a row decode circuit and a column decode circuit. In other words, the peripheral circuit 210 can perform all operations to process data in the memory cell array 220. The peripheral circuit 210 can include a control circuit corresponding to each block, such as a sensing amplifier (SA) and a word-line driver (WLD), a control circuit corresponding to each bank, such as a row decode circuit and a column decode circuit, and a control circuit corresponding to all banks, such as a command buffer, a command decoder, an address buffer, a data input / output buffer, a mode register, and the like.

[0057] The memory device 20 can be a random access memory (RAM), such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), a double data rate SDRAM (DDR SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and the like. Hereinafter, only the DRAM is described as an example.

[0058] Figure 2A A constituent block diagram of an exemplary SSD / UFS of the embodiments of the present application is shown. Here, the SSD / UFS can be understood as one of the memory systems described above, and in this example, the DRAM can be used as a buffer memory. Figure 1

[0059] As described above, the memory system of the present application can include a memory device 20 and a memory controller 10. The memory device 20 can include a memory cell array 220 and a peripheral circuit 210. The memory controller 10 can include a command buffer 101, a command decoder 102, an address buffer 103, a data input / output buffer 104, a mode register 105, a row decode circuit 106, a column decode circuit 107, a data bus 108, a command bus 109, an address bus 110, a data input / output terminal 111, a command terminal 112, and a mode terminal 113. Figure 2A ​As shown, the SSD / UFS 3001 can include an SSD / UFS controller 1001, a DRAM 2001, and a non-volatile memory 40. The SSD / UFS controller 1001 can provide a physical connection between the host HOST and the SSD / UFS 3001. That is, the SSD / UFS controller 1001 can provide an interface between the host HOST and the SSD / UFS 3001 in the bus format of the host. The SSD controller 1001 can decode an instruction provided from the host HOST. The SSD / UFS controller 1001 can access the non-volatile memory 40 based on the result of the decoding. The DRAM 2001 can temporarily store write data provided from the host HOST, or data read from the non-volatile memory 40. When the host HOST issues a read request, if data existing in the non-volatile memory 40 is cached, the DRAM 2001 can support a cache function for providing the cached data directly to the host HOST. The data transfer rate through the bus format of the host (e.g., SATA or SAS) is much higher than the data transfer rate of the memory channel of the SSD / UFS 3001. That is, when the interface speed of the host is significantly high, the performance reduction due to the speed difference can be minimized by providing a high-capacity DRAM 2001. In addition, the DRAM 2001 can store an address mapping table of the non-volatile memory 40. The DRAM 2001 can include, but is not limited to, a DRAM. The non-volatile memory 40 can be provided as a storage medium of the SSD / UFS 3001. The non-volatile memory 40 can include, but is not limited to, a NAND type memory.

[0060] Figure 2B A block diagram of an exemplary memory for embodiments of the present application; here, the memory can be understood as a kind of memory system as described above Figure 1 In this example, a DRAM can be used as a storage medium.

[0061] As Figure 2B shown, the memory 3002 can be easily attached or mounted to or detached from an electronic device through the illustrated interface. The memory 3002 can include a plurality of volatile memories 2002 (e.g., DRAMs) and a memory controller 1002. The memory module memory 3002 can be used to write data, store data, acquire (or, read) data, and / or erase data under the control of a processor of a computer. In some embodiments, the controller memory controller 1002 can communicate with the DRAM using at least one communication protocol or technical standard commonly associated with, for example, a dual in-line memory module (DIMM), a DIMM with register (RDIMM), a low-profile DIMM (LRDIMM), a DIMM without register (UDIMM), etc.

[0062] It should be noted that Figure 2A The volatile memory 2002 in the middle Figure 2B The volatile memory 2002 in the middle Figure 1 The application scenario of the memory device 20 is shown in the figure, but the application scenario is not limited to this.

[0063] Figure 3 The figure shows the structure of the exemplary dynamic random access memory of the present application.

[0064] Figure 4 The figure shows the connection relationship of the word line, the bit line and the storage unit of the exemplary dynamic random access memory of the present application.

[0065] Figure 3 The right side of the figure shows the circuit of the storage unit in the DRAM. The DRAM includes at least one DRAM chip (Die), and each DRAM chip includes a storage unit array, which includes a plurality of storage units 201 arranged in an array, each storage unit 201 including a transistor T and a capacitor C. The main principle of the storage unit is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The storage units are arranged in an array and can be regarded as a typical mesh structure, which can be referred to in detail in Figure 4 The storage unit array uses rows and columns to specify addresses. By specifying the intersection of the row and the column (by specifying the row address and the column address of the DRAM), the memory controller can independently access each storage unit in the DRAM chip and perform read, write or refresh operations on the data stored therein.

[0066] Figure 3 The left side of the figure shows the storage unit array and part of the peripheral circuit in the DRAM. It should be noted that the row decode circuit selects a word line to select a row of storage units to be accessed in response to an address input to the row decode circuit. The row decode circuit decodes the input address and enables (activates) the word line corresponding to the decoded address. The column decode circuit selects one or more bit lines to input user output data to a portion of the row of storage units corresponding to the selected word line.

[0067] Figure 5 The figure shows the distribution of the storage unit array and the peripheral circuit in the exemplary memory device of the present application. As shown in Figure 5 The memory device includes a storage unit array 220 and a peripheral circuit 210, wherein the storage unit array 220 and the peripheral circuit 210 are coupled.

[0068] In some embodiments of the present application, bonding methods between the memory cell array 220 and the peripheral circuit 210 include but are not limited to hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, etc.

[0069] Combine Figure 4 and Figure 5 , the memory cell array 220 includes: a plurality of rows of word lines WL (eg Figure 4 ) and the memory cells coupled to the word lines. If a row of word lines is frequently activated (e.g., intensively accessed), this row of word lines may become the aggressor row, while the adjacent word lines become the victim rows. For example, if word line WLn becomes the aggressor row, the adjacent word lines WLn-2, ​​WLn-1, WLn+1, and WLn+2 may all become victim rows.

[0070] It should be noted that under the influence of electromagnetic interference, the attacking row is frequently activated, which may cause charge leakage in the memory cells coupled to the victim row, thereby causing the data stored in the memory cells to flip (bit-flip), turning 0 into 1, or vice versa. Therefore, an additional refresh operation, namely, a row hammer refresh, is required for the victim row to replenish the charge of the memory cells coupled to the victim row and prevent data flipping.

[0071] In an embodiment of the present application, the peripheral circuit 210 may determine, among multiple word lines WL, at least one word line with a high number of activations as an attacking row; for example, the top five word lines with the highest number of activations may be determined as attacking rows. Furthermore, the peripheral circuit 210 may send refresh commands to the victim rows adjacent to each attacking row to perform a row hammer refresh.

[0072] In the embodiment of the present application, row hammer refresh can include uniform refresh and non-uniform refresh. Uniform refresh is performed on the victim rows on both sides of the attacking row, while non-uniform refresh is performed on the victim row on one side of the attacking row. For example, if word line WLn becomes the attacking row, then refreshing word lines WLn-1 and WLn+1, or refreshing word lines WLn-1 and WLn+1, or refreshing word lines WLn-2 and WLn+2, is uniform refresh; correspondingly, refreshing only word line WLn-1, or refreshing only word line WLn+1, is non-uniform refresh.

[0073] It can be understood that, compared with uniformly refreshing the victim rows on both sides of the attacking row, performing non-uniform refreshing only on the victim row on one side of the attacking row can save power consumption.

[0074] In some embodiments of the present application, the distances between the word lines on both sides of the attack row and the attack row are not equal; the peripheral circuit 210 is further configured to take the word line on the side closer to the attack row as the victim row to perform the non-uniform refresh.

[0075] Figure 6 A plurality of word lines are shown, and the row addresses of the plurality of word lines are 0000-1001 in sequence. Among them, the distances between the adjacent two word lines are not uniform, and the last digits of the row addresses of the two word lines are mutually exclusive. For example, the distance between the word line 0100 and the word line 0101 is closer, while the distance between the word line 0100 and the word line 0011 is farther, that is, the distances between the word line 0101 and the word line 0011 on both sides of the word line 0100 and the word line 0100 are not equal.

[0076] In the embodiments of the present application, the peripheral circuit 210 is configured to determine the attack row according to the row hammer threshold value. Figure 6 For example, if the word line 0100 is determined as the attack row, then the peripheral circuit 210 only takes the word line 0101 closer to the word line 0100 as the victim row, sends a refresh command to the word line 0101, and performs the non-uniform refresh.

[0077] It can be understood that the influence degree (i.e., the row hammer threshold value) of a certain row of word lines affected by the row hammer is related to the distance between the row of word lines and the attack row, that is, the closer the distance to the attack row, the more likely to be affected by the row hammer. Therefore, taking the word line on the side closer to the attack row as the victim row to perform the non-uniform refresh can more specifically perform the row hammer refresh, so as to ensure the effect of the row hammer refresh and save power consumption.

[0078] In some embodiments of the present application, as shown in Figure 7 , the peripheral circuit 210 includes a row hammer refresh control circuit 510, an attack row address determination circuit 520, and a row hammer refresh address generation circuit 530.

[0079] In the embodiments of the present application, referring to Figure 7 , the row hammer refresh control circuit 510 is configured to generate a row hammer refresh signal RHR and a non-uniform refresh flag signal Uneven_flag according to a refresh command signal CMD (i.e., REF / RFM) and an adjustment signal Uneven_ratio_trim.

[0080] Referring to Figure 10 , the refresh command signal CMD is issued by a memory controller, and each pulse REF / RFM is issued according to a certain period. The row hammer refresh control circuit 510 can generate a pulse in the row hammer refresh signal RHR under the triggering of part of the pulses in the refresh command signal CMD. That is, part of the pulses in the refresh command signal CMD will be used to perform the row hammer refresh.

[0081] Referring toFigure 11 The row hammer refresh control circuit 510 can further generate an uneven refresh flag signal Uneven_flag according to the adjustment signal Uneven_ratio_trim. When the uneven refresh flag signal Uneven_flag is at a first level (e.g., high level in the example), it indicates that uneven refresh is performed. The duration of the first level of the uneven refresh flag signal Uneven_flag is determined by the adjustment signal Uneven_ratio_trim. Figure 11

[0082] In the embodiments of the present application, the adjustment signal Uneven_ratio_trim represents the proportion of uneven refresh in row hammer refresh. That is, the higher the proportion of uneven refresh in row hammer refresh represented by the adjustment signal Uneven_ratio_trim, the longer the duration of the first level of the uneven refresh flag signal Uneven_flag.

[0083] In the embodiments of the present application, the adjustment signal Uneven_ratio_trim is determined according to the number of times of row hammer refresh and the number of times of row hammer refresh in the row hammer refresh. Figure 7 The attack row address determination circuit 520 is coupled to the row hammer refresh control circuit 510. The attack row address determination circuit 520 is configured to determine an attack row in the activated word lines, and output an attack row address RH_ADDR in response to the row hammer refresh signal RHR.

[0084] With reference to the above description, the attack row address determination circuit 520 can receive the row address ACT_ADDR of the activated word lines, determine at least one row of word lines with more activation times as the attack row, and output the attack row address RH_ADDR. Figure 7 The attack row address determination circuit 520 can receive the row address ACT_ADDR of the activated word lines, determine at least one row of word lines with more activation times as the attack row, and output the attack row address RH_ADDR. Figure 11 Since the row hammer refresh signal RHR triggers row hammer refresh once for each pulse, the attack row address determination circuit 520 outputs an attack row address RH_ADDR for each pulse of the row hammer refresh signal RHR to perform row hammer refresh.

[0085] In the embodiments of the present application, the adjustment signal Uneven_ratio_trim is determined according to the number of times of row hammer refresh and the number of times of row hammer refresh in the row hammer refresh. Figure 7 ​The row hammer refresh address generation circuit 530 is coupled to the row hammer refresh control circuit 510 and the attacking row address determination circuit 520. The row hammer refresh address generation circuit 530 is configured to receive the attacking row address RH_ADDR, the row hammer refresh signal RHR, and the non-uniform refresh flag signal Uneven_flag, and generate a row hammer refresh address RHR_ADDR corresponding to the attacking row address RH_ADDR in response to the row hammer refresh signal RHR and the non-uniform refresh flag signal Uneven_flag. If the non-uniform refresh flag signal Uneven_flag indicates that a non-uniform refresh is to be performed on a victim row located on one side of the attacking row, the row hammer refresh address generation circuit 530 outputs the victim row address located on the other side of the attacking row as the row hammer refresh address RHR_ADDR.

[0086] In some embodiments of the present application, the non-uniform refresh flag signal Uneven_flag is at a high level, indicating that a non-uniform refresh is performed on the victim row located on one side of the attacking row.

[0087] refer to Figure 11 For example, when the attack row address RH_ADDR received by the row hammer refresh address generation circuit 530 is C, the non-uniform refresh flag signal Uneven_flag is at the first level ( Figure 11 In the example, the non-uniform refresh flag signal Uneven_flag indicates that a non-uniform refresh is to be performed on the victim row located on the side of the attacking row C. Therefore, the output row hammer refresh address RHR_ADDR is / C, where the victim row / C is located on the side of the attacking row C. When the attacking row address RH_ADDR is D, the non-uniform refresh flag signal Uneven_flag is also at the first level, which can be understood by reference.

[0088] In some embodiments of this application, continue to refer to Figure 7 If the non-uniform refresh flag signal Uneven_flag indicates refreshing the victim rows on both sides of the attacking row, the row hammer refresh address generation circuit 530 outputs the victim row addresses on both sides of the attacking row as row hammer refresh addresses RHR_ADDR for uniform refresh.

[0089] In some embodiments of the present application, when the non-uniform refresh flag signal Uneven_flag is at a low level, it indicates that the victim rows located on both sides of the attack row are to be refreshed.

[0090] refer to Figure 11 For example, when the attack row address RH_ADDR received by the row hammer refresh address generation circuit 530 is A, the uneven refresh flag signal Uneven_flag is at the second level ( Figure 11For example, when the attack row address RH_ADDR is A, and the uneven refresh flag signal Uneven_flag is the second level (i.e., the low level), the uneven refresh flag signal Uneven_flag indicates that the victim rows located on both sides of the attack row A are refreshed; then, the output row hammer refresh address RHR_ADDR includes A-1 and A+1, where the victim rows A-1 and A+1 are located on both sides of the attack row A, respectively. When the attack row address RH_ADDR is B, E or F, the uneven refresh flag signal Uneven_flag is also the second level, which can be understood with reference.

[0091] It can be understood that, for a certain proportion of row hammer refreshes using uneven refresh, the row hammer refresh address generation circuit 530 only outputs the victim row address located on one side of the attack row as the row hammer refresh address RHR_ADDR, so that the effect of the row hammer refresh is ensured, and the power consumption is saved.

[0092] In some embodiments of the present application, as shown in Figure 8 the row hammer refresh control circuit 510 is further configured to generate a row hammer refresh address generation signal RHR_addr_pulse according to the refresh command signal CMD (i.e., REF / RFM) and the adjustment signal Uneven_ratio_trim. The row hammer refresh address generation circuit 530 is further configured to generate the row hammer refresh address RHR_ADDR in response to the row hammer refresh address generation signal RHR_addr_pulse, the row hammer refresh signal RHR and the uneven refresh flag signal Uneven_flag.

[0093] In the embodiments of the present application, with reference to Figure 11 , the row hammer refresh control circuit 510 generates the row hammer refresh signal RHR according to the refresh command signal CMD, and after generating the uneven refresh flag signal Uneven_flag according to the adjustment signal Uneven_ratio_trim, the row hammer refresh control circuit 510 can further generate the row hammer refresh address generation signal RHR_addr_pulse under the trigger of the row hammer refresh signal RHR according to the uneven refresh flag signal Uneven_flag.

[0094] In the embodiments of the present application, when the uneven refresh flag signal Uneven_flag indicates that the victim rows located on one side of the attack row are refreshed unevenly, the row hammer refresh address generation signal RHR_addr_pulse includes a single pulse signal corresponding to the row hammer refresh signal. With reference to Figure 11 , when the uneven refresh flag signal Uneven_flag is the first level (i.e., the low level), the uneven refresh flag signal Uneven_flag indicates that the victim rows located on both sides of the attack row are refreshed; then, the output row hammer refresh address RHR_ADDR includes A-1 and A+1, where the victim rows A-1 and A+1 are located on both sides of the attack row A, respectively. Figure 11 When the uneven refresh flag signal Uneven_flag is the second level (i.e., the high level), the uneven refresh flag signal Uneven_flag indicates that the victim rows located on one side of the attack row are refreshed unevenly, and correspondingly, each pulse in the row hammer refresh signal RHR triggers the generation of a corresponding pulse in the row hammer refresh address generation signal RHR_addr_pulse.

[0095] In the embodiments of the present application, the uneven refresh flag signal Uneven_flag indicates that the victim rows on both sides of the attack row are refreshed, and the row hammer refresh address generation signal RHR_addr_pulse includes a double pulse signal corresponding to the row hammer refresh signal. It is shown in Figure 11 When the uneven refresh flag signal Uneven_flag is at a second level (e.g., low level), the uneven refresh flag signal Uneven_flag indicates that the victim rows on both sides of the attack row are refreshed, and correspondingly, each pulse in the row hammer refresh signal RHR triggers the generation of the corresponding two consecutive pulses in the row hammer refresh address generation signal RHR_addr_pulse. Figure 11

[0096] In the embodiments of the present application, as shown in Figure 11 , the row hammer refresh signal RHR and the row hammer refresh address generation signal RHR_addr_pulse can jointly control the generation of the row hammer refresh address RHR_ADDR and complement each other. On the one hand, when the row hammer refresh signal RHR is within the pulse range (i.e., high level), the row hammer refresh address RHR_ADDR can be generated; when the row hammer refresh signal RHR is outside the pulse range (i.e., low level), no valid row hammer refresh address RHR_ADDR is generated. On the other hand, when the row hammer refresh address generation signal RHR_addr_pulse is a single pulse signal, the victim row address located on one side of the attack row is output as the row hammer refresh address RHR_ADDR; when the row hammer refresh address generation signal RHR_addr_pulse is a double pulse signal, the victim row addresses located on both sides of the attack row are output as the row hammer refresh address RHR_ADDR.

[0097] It can be understood that the row hammer refresh signal RHR and the row hammer refresh address generation signal RHR_addr_pulse are jointly used as the control signals of the row hammer refresh address generation circuit 530, so that the generation of the row hammer refresh address RHR_ADDR can be more accurately controlled, and errors can be avoided.

[0098] In some embodiments of the present application, as shown in Figure 9 , the peripheral circuit 210 further includes a normal refresh address generation circuit 540. The normal refresh address generation circuit 540 is coupled to the row hammer refresh control circuit 510. The normal refresh address generation circuit 540 is configured to receive the refresh command signal CMD (i.e., REF / RFM) and the row hammer refresh signal RHR, and output a normal refresh address NR_ADDR according to the refresh command signal CMD and the row hammer refresh signal RHR.

[0099] In the embodiments of the present application, as shown in Figure 10 ​, outside the pulse range of the row hammer refresh signal RHR, i.e. when the row hammer refresh signal RHR is at a low level, the normal refresh address generating circuit 540 can update the normal refresh address NR_ADDR for normal refresh. The normal refresh address NR_ADDR is generated by the internal counter of the memory, and the normal refresh address NR_ADDR is updated during each REF period. Correspondingly, within the pulse range of the row hammer refresh signal RHR, i.e. when the row hammer refresh signal RHR is at a high level, the row hammer refresh signal RHR masks the refresh command signal CMD, so as to avoid updating the normal refresh address NR_ADDR.

[0100] That is, outside the pulse range of the row hammer refresh signal RHR, i.e. when the row hammer refresh signal RHR is at a low level, the refresh command signal CMD is used to perform normal refresh; and within the pulse range of the row hammer refresh signal RHR, i.e. when the row hammer refresh signal RHR is at a high level, the refresh command signal CMD is used to perform row hammer refresh.

[0101] In some embodiments of the present application, with reference to Figure 9 The peripheral circuit 210 further includes a first multiplexer MUX1. The first multiplexer MUX1 is coupled to the row hammer refresh control circuit 510, the row hammer refresh address generating circuit 530, and the normal refresh address generating circuit 540, respectively. The first multiplexer MUX1 is configured to receive the row hammer refresh address RHR_ADDR, the normal refresh address NR_ADDR, and the row hammer refresh signal RHR, output the row hammer refresh address RHR_ADDR in response to the row hammer refresh signal RHR being at a first level, or output the normal refresh address NR_ADDR in response to the row hammer refresh signal RHR being at a second level.

[0102] In the embodiments of the present application, with reference to Figure 11 Within the pulse range of the row hammer refresh signal RHR, i.e. when the row hammer refresh signal RHR is at a high level (a first level), the first multiplexer MUX1 outputs the row hammer refresh address RHR_ADDR, and performs row hammer refresh. Correspondingly, outside the pulse range of the row hammer refresh signal RHR, i.e. when the row hammer refresh signal RHR is at a low level (a second level), the first multiplexer MUX1 outputs the normal refresh address NR_ADDR, and performs normal refresh.

[0103] It can be understood that, according to the level of the row hammer refresh signal RHR, the normal refresh and the row hammer refresh are performed respectively, so that the row hammer problem is effectively solved, and the regular refresh in the memory is ensured, thereby effectively ensuring the accuracy of the data in the storage unit.

[0104] In some embodiments of the present application, as Figure 12As shown, the row hammer refresh address generation circuit 530 includes a first victim row address generation circuit 531 and a second victim row address generation circuit 532.

[0105] In the embodiments of the present application, the first victim row address generation circuit 531 is coupled to the attack row address determination circuit 520 and the row hammer refresh control circuit 510. The first victim row address generation circuit 531 is configured to receive the attack row address RH_ADDR and the row hammer refresh signal RHR, and generate a victim row address located on one side of the attack row address RH_ADDR.

[0106] In some embodiments of the present application, as shown, the distance between two adjacent word lines is not uniform, and the last digit of the row address of the two word lines whose distance is closest to each other is the complement of each other. Accordingly, the first victim row address generation circuit 531 can take the complement of the lowest digit of the attack row address to obtain the victim row address on the side closest to the attack row address; for example, taking the complement of the lowest digit of the attack row address 0100 to obtain the victim row address 0101 on the side closest to the attack row address 0100. Figure 6

[0107] In some embodiments of the present application, as shown, the distance between two adjacent word lines is not uniform, and the last digit of the row address of the two word lines whose distance is closest to each other is the complement of each other. Accordingly, the first victim row address generation circuit 531 can take the complement of the lowest digit of the attack row address to obtain the victim row address on the side closest to the attack row address; for example, taking the complement of the lowest digit of the attack row address 0100 to obtain the victim row address 0101 on the side closest to the attack row address 0100.

[0108] In the embodiments of the present application, the second victim row address generation circuit 532 is coupled to the attack row address determination circuit 520 and the row hammer refresh control circuit 510. The second victim row address generation circuit 532 is configured to receive the attack row address RH_ADDR and the row hammer refresh signal RHR, and generate a victim row address located on both sides of the attack row address RH_ADDR.

[0109] Referring to Figure 6 , the second victim row address generation circuit 532 can obtain the victim row addresses 0101 and 0011 located on both sides of the attack row address 0100 by taking the attack row address 0100±1; the second victim row address generation circuit 532 can also obtain the victim row addresses 0110 and 0010 located on both sides of the attack row address 0100 by taking the attack row address 0100±2.

[0110] ​Correspondingly, the second victim row address generation circuit 532 can also generate the attack row address RH_ADDR±3, ±4 or ±5, which can be set according to requirements, and is not limited here.

[0111] In some embodiments of the present application, as shown in Figure 12 The row hammer refresh address generation circuit 530 also includes a second multiplexer MUX2 in some embodiments of the present application, as shown in

[0112] In the embodiments of the present application, the second multiplexer MUX2 is configured to receive the uneven refresh flag signal Uneven_flag, and select one of the output result of the first victim row address generation circuit 531 and the output result of the second victim row address generation circuit 532 according to the uneven refresh flag signal Uneven_flag, and output as the row hammer refresh address RHR_ADDR.

[0113] Referring to Figure 11 When the uneven refresh flag signal Uneven_flag is the first level (i.e., high level), the uneven refresh flag signal Uneven_flag indicates that the victim rows located on one side of the attack row are refreshed unevenly, and the second multiplexer MUX2 selects the output result of the first victim row address generation circuit 531 for output, that is, the second multiplexer MUX2 outputs the victim row address located on one side of the attack row address RH_ADDR for uneven refresh.

[0114] Or, when the uneven refresh flag signal Uneven_flag is the second level (i.e., low level), the uneven refresh flag signal Uneven_flag indicates that the victim rows located on both sides of the attack row are refreshed, and the second multiplexer MUX2 selects the output result of the second victim row address generation circuit 532 for output, that is, the second multiplexer MUX2 outputs the victim row address located on both sides of the attack row address RH_ADDR for uniform refresh.

[0115] In some embodiments of the present application, as shown in Figure 13 The second multiplexer MUX2 is also configured to receive the row hammer refresh address generation signal RHR_addr_pulse, and select whether to output the victim row address located on one side of the attack row address or the victim row address located on both sides of the attack row address based on the uneven refresh flag signal Uneven_flag and the row hammer refresh address generation signal RHR_addr_pulse, that is, select one of the output result of the first victim row address generation circuit 531 and the output result of the second victim row address generation circuit 532 as the row hammer refresh address RHR_ADDR.

[0116] It can be understood that the non-uniform refresh flag signal Uneven_flag and the row hammer refresh address generation signal RHR_addr_pulse are taken as the control signals of the second multiplexer MUX2 together, so that the generation of the row hammer refresh address RHR_ADDR can be controlled more accurately, and errors can be avoided.

[0117] In some embodiments of the present application, as shown in Figure 14 The comparator 512 is coupled to the counter 511. The counter 511 is configured to record the number of pulses of the row hammer refresh signal RHR and output as a count value Cnt[N-1:0], wherein the number of bits of the count value Cnt[N-1:0] is N. The comparator 512 is configured to compare the count value Cnt[N-1:0] and the adjustment signal Uneven_ratio_trim, and output the corresponding non-uniform refresh flag signal Uneven_flag according to the comparison result.

[0118] In some embodiments of the present application, with reference to Figure 14 The comparator 512 is further configured to output the non-uniform refresh flag signal Uneven_flag indicating that the victim rows located on one side of the attack row are subjected to non-uniform refresh when the count value Cnt[N-1:0] matches the adjustment signal Uneven_ratio_trim, and otherwise, output the non-uniform refresh flag signal Uneven_flag indicating that the victim rows on both sides of the attack row are subjected to refresh.

[0119] In the embodiments of the present application, each pulse of the row hammer refresh signal RHR causes the count value Cnt[N-1:0] to accumulate by 1. Further, the comparator 512 can compare at least part of the count value Cnt[N-1:0] accumulated each time with the adjustment signal Uneven_ratio_trim, and output the non-uniform refresh flag signal Uneven_flag of the corresponding level according to the comparison result. For example, the adjustment signal Uneven_ratio_trim is set to a binary value 11 of two bits (i.e. 2’b11), if the last two bits Cnt[N-1:0] of the count value Cnt[N-1:0] are equal to 2’b11, then the non-uniform refresh flag signal Uneven_flag of the first level is output, indicating that the victim rows located on one side of the attack row are subjected to non-uniform refresh; otherwise, the non-uniform refresh flag signal Uneven_flag of the second level is output, indicating that the victim rows on both sides of the attack row are subjected to refresh.

[0120] It should be noted that the adjustment signal Uneven_ratio_trim represents the proportion of non-uniform refresh in hammer row refresh, and the proportion of non-uniform refresh in hammer row refresh can be adjusted by changing the adjustment signal Uneven_ratio_trim. For example, the adjustment signal Uneven_ratio_trim is set to 2’b11, because there are four two-bit binary numbers in total, including 2’b00, 2’b01, 2’b10 and 2’b11, and 2’b11 is only one of them, so at this time, the proportion of non-uniform refresh in hammer row refresh is one fourth.

[0121] It can be understood that the non-uniform refresh flag signal Uneven_flag is generated according to the adjustment signal Uneven_ratio_trim, so that a certain proportion of hammer row refresh adopts non-uniform refresh, so that the effect of hammer row refresh is guaranteed, and the power consumption is saved. At the same time, the proportion of non-uniform refresh in hammer row refresh can be adjusted according to the demand, which improves the flexibility of hammer row refresh.

[0122] Figure 15 An implementation flow diagram of a hammer row refresh method provided by an embodiment of the present application is shown, which can be executed by the peripheral circuit 210 shown. Figure 1 As shown in the figure, the hammer row refresh method includes steps S101-S103, which will be described in combination with each step. Figure 15

[0123] S101, in response to the hammer row refresh signal, receiving the attack row address.

[0124] S102, in response to the non-uniform refresh flag signal, generating the hammer row refresh address corresponding to the attack row address. Wherein, if the non-uniform refresh flag signal indicates that the victim row located on one side of the attack row is refreshed non-uniformly, the hammer row refresh address includes the victim row address located on one side of the attack row.

[0125] S103, based on the hammer row refresh address, performing hammer row refresh.

[0126] In the embodiment of the present application, referring to Figure 11 , the peripheral circuit 210 can receive the attack row address RH_ADDR under the trigger of the pulse in the hammer row refresh signal RHR; then, according to the Uneven_flag level of the non-uniform refresh flag signal, the hammer row refresh address RHR_ADDR corresponding to the attack row address RH_ADDR is generated; then, based on the hammer row refresh address RHR_ADDR, the hammer row refresh is performed.

[0127] ​In some embodiments of the present application, if the uneven refresh flag Uneven_flag is at the first level, the row hammer refresh address RHR_ADDR includes the victim row address located at one side of the attack row. For example, referring to Figure 11 , when the attack row address RH_ADDR is C, the uneven refresh flag Uneven_flag is at the first level (e.g., high level in the example shown in Figure 11 ), then the row hammer refresh address RHR_ADDR is / C, where the victim row / C is located at one side of the attack row C.

[0128] In some embodiments of the present application, if the uneven refresh flag Uneven_flag indicates to refresh the victim rows located at both sides of the attack row, the row hammer refresh address RHR_ADDR includes the victim row addresses located at both sides of the attack row address. For example, referring to Figure 11 , when the attack row address RH_ADDR is A, the uneven refresh flag Uneven_flag is at the second level (e.g., low level in the example shown in Figure 11 ), then the row hammer refresh address RHR_ADDR includes A-1 and A+1, where the victim rows A-1 and A+1 are located at both sides of the attack row A.

[0129] It can be understood that, for a certain proportion of row hammer refresh, the non-uniform refresh is adopted, and only the victim row address located at one side of the attack row is taken as the row hammer refresh address RHR_ADDR, so that the effect of the row hammer refresh is ensured, and the power consumption is saved.

[0130] The embodiments of the present application further provide a memory system, including one or more memory devices provided by the embodiments of the present application, and a memory controller. The memory controller is coupled with the memory device and controls the memory device.

[0131] Here, the internal composition of the memory system can be understood with reference to the foregoing Figure 1 , and some application scenarios of the memory system can be understood with reference to the foregoing Figure 2A and Figure 2B , which will not be described herein again.

[0132] The embodiment of the application further provides a refresh address generation circuit, comprising: a row hammer refresh control circuit, an attack row address determination circuit and a row hammer refresh address generation circuit. The row hammer refresh control circuit is configured to generate a row hammer refresh signal and a non-uniform refresh flag signal according to a refresh command signal and an adjustment signal. The attack row address determination circuit is coupled to the row hammer refresh control circuit and is configured to output an attack row address in response to the row hammer refresh signal. The row hammer refresh address generation circuit is coupled to the row hammer refresh control circuit and the attack row address determination circuit and is configured to generate a row hammer refresh address corresponding to the attack row address in response to the row hammer refresh signal and the non-uniform refresh flag signal. If the non-uniform refresh flag signal indicates that the non-uniform refresh is performed on victim rows located on one side of the attack row, the row hammer refresh address comprises victim row addresses located on the one side of the attack row. The adjustment signal represents a proportion of the non-uniform refresh in the row hammer refresh.

[0133] In some embodiments of the application, the distances between the word lines located on two sides of the attack row and the attack row are not equal. The refresh address generation circuit is further configured to perform the non-uniform refresh on the victim rows on the side of the attack row which is closer to the attack row.

[0134] In some embodiments of the application, if the non-uniform refresh flag signal indicates that the refresh is performed on the victim rows on two sides of the attack row, the row hammer refresh address comprises victim row addresses located on two sides of the attack row.

[0135] In some embodiments of the application, the non-uniform refresh flag signal is at a high level, indicating that the non-uniform refresh is performed on the victim rows located on one side of the attack row; and the non-uniform refresh flag signal is at a low level, indicating that the refresh is performed on the victim rows on two sides of the attack row.

[0136] In some embodiments of the application, the row hammer refresh control circuit is further configured to generate a row hammer refresh address generation signal according to the refresh command signal and the adjustment signal. The row hammer refresh address generation circuit is further configured to generate the row hammer refresh address in response to the row hammer refresh address generation signal, the row hammer refresh signal and the non-uniform refresh flag signal.

[0137] In some embodiments of the application, if the non-uniform refresh flag signal indicates that the non-uniform refresh is performed on the victim rows located on one side of the attack row, the row hammer refresh address generation signal comprises a single pulse signal corresponding to the row hammer refresh signal. If the non-uniform refresh flag signal indicates that the refresh is performed on the victim rows on two sides of the attack row, the row hammer refresh address generation signal comprises a double pulse signal corresponding to the row hammer refresh signal.

[0138] In some embodiments of the application, the refresh address generation circuit further comprises: a normal refresh address generation circuit. The normal refresh address generation circuit is coupled to the row hammer refresh control circuit. The normal refresh address generation circuit is configured to receive the refresh command signal and the row hammer refresh signal, and output a normal refresh address according to the refresh command signal and the row hammer refresh signal.

[0139] In some embodiments of the application, the refresh address generation circuit further comprises: a first multiplexer. The first multiplexer is coupled to the row hammer refresh control circuit, the row hammer refresh address generation circuit and the normal refresh address generation circuit, respectively. The first multiplexer is configured to receive the row hammer refresh address, the normal refresh address and the row hammer refresh signal, and output the row hammer refresh address in response to the row hammer refresh signal being at a first level, or output the normal refresh address in response to the row hammer refresh signal being at a second level.

[0140] In some embodiments of the application, the row hammer refresh address generation circuit comprises: a first victim row address generation circuit and a second victim row address generation circuit. The first victim row address generation circuit is coupled to the attack row address determination circuit and the row hammer refresh control circuit, and is configured to receive the attack row address and the row hammer refresh signal, and generate a victim row address located on one side of the attack row address. The second victim row address generation circuit is coupled to the attack row address determination circuit and the row hammer refresh control circuit, and is configured to receive the attack row address and the row hammer refresh signal, and generate a victim row address located on both sides of the attack row address.

[0141] In some embodiments of the application, the row hammer refresh address generation circuit further comprises: a second multiplexer. The second multiplexer is coupled to the first victim row address generation circuit, the second victim row address generation circuit and the row hammer refresh control circuit, respectively. The second multiplexer is configured to output the victim row address located on one side of the attack row address in response to the non-uniform refresh flag signal indicating that the victim row located on one side of the attack row is refreshed non-uniformly, and output the victim row address located on both sides of the attack row address in response to the non-uniform refresh flag signal indicating that the victim row located on both sides of the attack row is refreshed.

[0142] In some embodiments of the application, the row hammer refresh control circuit comprises: a counter and a comparator. The counter is configured to record the number of pulses of the row hammer refresh signal and output a count value. The comparator is coupled to the counter and is configured to compare the count value and the adjustment signal, and output a corresponding non-uniform refresh flag signal according to the comparison result.

[0143] In some embodiments of the application, the comparator is further configured to output the non-uniform refresh flag signal indicating that the victim row located on one side of the attack row is refreshed non-uniformly in the case that the count value matches the adjustment signal, and otherwise output the non-uniform refresh flag signal indicating that the victim row located on both sides of the attack row is refreshed.

[0144] It should be noted that, in the present document, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, such that processes, methods, articles, or apparatuses that comprise a list of elements are not required to comprise only those elements recited, but can also include other elements not expressly listed or inherent to such processes, methods, articles, or apparatuses. Without further limitation, an element preceded by "comprising" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0145] The above-mentioned sequence numbers of the embodiments of the present application are only for description, and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present application can be combined arbitrarily without conflict, to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present application can be combined arbitrarily without conflict, to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present application can be combined arbitrarily without conflict, to obtain new method embodiments or device embodiments.

[0146] The above merely provides a description of the specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, and all such changes and replacements shall be covered within the protection scope of the present application.

Claims

1. A memory device, comprising: The memory cell array and the peripheral circuit; The memory cell array comprises a plurality of word lines and memory cells coupled to the word lines; The peripheral circuit is coupled to the plurality of word lines; The peripheral circuit is configured to determine an attack row and to perform a non-uniform refresh on victim rows located on one side of the attack row.

2. The memory device of claim 1, wherein, The peripheral circuit comprises: The hammer refresh control circuit is configured to generate a hammer refresh signal and a non-uniform refresh flag signal according to a refresh command signal and an adjustment signal; The attack row address determination circuit is coupled to the hammer refresh control circuit and is configured to output an attack row address in response to the hammer refresh signal; and The hammer refresh address generation circuit is coupled to the hammer refresh control circuit and the attack row address determination circuit and is configured to generate a hammer refresh address corresponding to the attack row address in response to the hammer refresh signal and the non-uniform refresh flag signal; if the non-uniform refresh flag signal indicates that the non-uniform refresh is performed on the victim rows located on one side of the attack row, the hammer refresh address comprises victim row addresses located on one side of the attack row.

3. The memory device of claim 2, wherein The adjustment signal represents a proportion of the non-uniform refresh in hammer refresh.

4. The memory device of claim 2, wherein If the non-uniform refresh flag signal indicates that the refresh is performed on the victim rows on both sides of the attack row, the hammer refresh address comprises victim row addresses located on both sides of the attack row address.

5. The memory device of claim 4, wherein The non-uniform refresh flag signal is high, indicating that the non-uniform refresh is performed on the victim rows located on one side of the attack row; and The non-uniform refresh flag signal is low, indicating that the refresh is performed on the victim rows on both sides of the attack row.

6. The memory device of claim 2, wherein The hammer refresh control circuit is further configured to generate a hammer refresh address generation signal according to the refresh command signal and the adjustment signal; and The hammer refresh address generation circuit is further configured to generate the hammer refresh address in response to the hammer refresh address generation signal, the hammer refresh signal, and the non-uniform refresh flag signal.

7. The memory device of claim 6, wherein If the non-uniform refresh flag signal indicates that the non-uniform refresh is performed on the victim rows located on one side of the attack row, the hammer refresh address generation signal comprises a single-pulse signal corresponding to the hammer refresh signal; and If the non-uniform refresh flag signal indicates that the refresh is performed on the victim rows on both sides of the attack row, the hammer refresh address generation signal comprises a double-pulse signal corresponding to the hammer refresh signal.

8. The memory device of claim 2, wherein, The peripheral circuit further comprises: The ordinary refresh address generation circuit is coupled to the hammer refresh control circuit and is configured to receive the refresh command signal and the hammer refresh signal and to output an ordinary refresh address according to the refresh command signal and the hammer refresh signal.

9. The memory device of claim 8, wherein, The peripheral circuit further comprises: A first multiplexer coupled to the row hammer refresh control circuit, the row hammer refresh address generation circuit and the normal refresh address generation circuit, configured to receive the row hammer refresh address, the normal refresh address and the row hammer refresh signal, output the row hammer refresh address in response to the row hammer refresh signal being at a first level, and output the normal refresh address in response to the row hammer refresh signal being at a second level.

10. The memory device of claim 2, wherein, The row hammer refresh address generation circuit comprises: A first victim row address generation circuit coupled to the attack row address determination circuit and the row hammer refresh control circuit, configured to receive the attack row address and the row hammer refresh signal, and generate the victim row address on one side of the attack row address; and A second victim row address generation circuit coupled to the attack row address determination circuit and the row hammer refresh control circuit, configured to receive the attack row address and the row hammer refresh signal, and generate the victim row address on both sides of the attack row address.

11. The memory device of claim 10, wherein, The row hammer refresh address generation circuit further comprises: A second multiplexer coupled to the first victim row address generation circuit, the second victim row address generation circuit and the row hammer refresh control circuit, configured to: output the victim row address on one side of the attack row address in response to the non-uniform refresh flag signal indicating that the non-uniform refresh is performed on the victim row on one side of the attack row; and output the victim row address on both sides of the attack row address in response to the non-uniform refresh flag signal indicating that the refresh is performed on the victim row on both sides of the attack row.

12. The memory device of claim 2, wherein, The row hammer refresh control circuit comprises: a counter configured to record the number of pulses of the row hammer refresh signal and output the number as a count value; and a comparator coupled to the counter and configured to compare the count value and the adjustment signal, and output the corresponding non-uniform refresh flag signal according to the comparison result.

13. The memory device of claim 12, wherein the comparator is further configured to output the non-uniform refresh flag signal indicating that the non-uniform refresh is performed on the victim row on one side of the attack row in case that the count value matches the adjustment signal, and otherwise output the non-uniform refresh flag signal indicating that the refresh is performed on the victim row on both sides of the attack row.

14. The memory device of claim 1, wherein, The distance between the word lines on both sides of the attack row and the attack row is not equal. The peripheral circuit is further configured to perform the non-uniform refresh on the victim row of the word line on the side closer to the attack row.

15. The memory device of any one of claims 1 to 14, wherein, The memory device comprises a dynamic random access memory.

16. A memory system, comprising: one or more memory devices as claimed in any one of claims 1 to 15; and a memory controller coupled to the memory devices and controlling the memory devices.

17. A refresh address generation circuit, comprising: a row hammer refresh control circuit configured to generate a row hammer refresh signal and a non-uniform refresh flag signal according to a refresh command signal and an adjustment signal. ​ An attack row address determination circuit coupled to the row hammer refresh control circuit and configured to output an attack row address in response to the row hammer refresh signal. And A row hammer refresh address generation circuit coupled to the row hammer refresh control circuit and the attack row address determination circuit and configured to generate a row hammer refresh address corresponding to the attack row address in response to the row hammer refresh signal and the non-uniform refresh flag signal, wherein if the non-uniform refresh flag signal indicates that the non-uniform refresh is performed on victim rows located on one side of the attack row, the row hammer refresh address includes victim row addresses located on one side of the attack row.

18. The refresh address generation circuit of claim 17, wherein, The refresh address generation circuit further includes: A normal refresh address generation circuit coupled to the row hammer refresh control circuit and configured to receive the refresh command signal and the row hammer refresh signal and output a normal refresh address according to the refresh command signal and the row hammer refresh signal.

19. The refresh address generation circuit of claim 18, wherein, The refresh address generation circuit further includes: A first multiplexer coupled to the row hammer refresh control circuit, the row hammer refresh address generation circuit, and the normal refresh address generation circuit and configured to receive the row hammer refresh address, the normal refresh address, and the row hammer refresh signal, output the row hammer refresh address in response to the row hammer refresh signal being at a first level, and output the normal refresh address in response to the row hammer refresh signal being at a second level.

20. A row hammer refresh method, comprising: receiving an attack row address in response to a row hammer refresh signal; generating a row hammer refresh address corresponding to the attack row address in response to a non-uniform refresh flag signal, wherein if the non-uniform refresh flag signal indicates that a non-uniform refresh is performed on victim rows located on one side of the attack row, the row hammer refresh address includes victim row addresses located on one side of the attack row; performing a row hammer refresh based on the row hammer refresh address.

21. The row hammer refresh method of claim 20, wherein if the non-uniform refresh flag signal indicates that a refresh is performed on victim rows located on both sides of the attack row, the row hammer refresh address includes victim row addresses located on both sides of the attack row.

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