Semiconductor device

By setting multiple signal paths in the semiconductor device and driving the signal paths in different scanning operations, and using PMOS and NMOS transistors to generate fault detection signals, the problem of difficulty in detecting through-electrode TSV short-circuit faults in the existing technology is solved, and comprehensive detection of connection faults is achieved.

CN120833835APending Publication Date: 2025-10-24SK HYNIX INC
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Patent Information

Application Number
CN202411818041.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Priority Date
2024-04-24
Filing Date
2024-12-11
Publication Date
2025-10-24

AI Technical Summary

Technical Problem

It is difficult to effectively detect short-circuit faults of through-hole electrodes (TSVs) with existing technologies. The scanning operation can only detect open-circuit faults but cannot fully detect connection faults.

Method used

By setting multiple signal paths in a semiconductor device and driving different signal paths respectively in even and odd scan operations, using PMOS and NMOS transistors to generate fault detection signals, and combining logic test circuits and fault detection circuits, connection faults in the signal paths are detected.

Benefits of technology

The invention realizes comprehensive detection of connection faults of through-hole electrodes TSV, including open circuit and short circuit faults, thereby improving the comprehensiveness and accuracy of detection.

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Abstract

The invention relates to a semiconductor device. A semiconductor device includes a base chip and a memory chip stacked by a first signal path, a second signal path, a third signal path, and a fourth signal path, each signal path extending through the memory chip into the base chip. The base chip and the memory chip are configured to simultaneously drive the first signal path and the third signal path after an even scan operation is started, and then simultaneously drive the second signal path and the fourth signal path after an odd scan operation is started. The base chip is configured to generate a first fault detection signal, a second fault detection signal, a third fault detection signal, and a fourth fault detection signal that detect a connection fault of the first, second, third, and fourth signal paths based on logic levels at which the first, second, third, and fourth signal paths are driven.
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Citation Information

Patent Citations

  • Seasoning method

    KR1020240055010A