Manufacturing method of semiconductor device, semiconductor device and electronic equipment

Abstract

The invention discloses a manufacturing method of a semiconductor device, the semiconductor device and electronic equipment, and the method comprises the steps: providing a substrate, and sequentially forming a first insulating layer and a first hard mask layer on the substrate; etching the first hard mask layer to form a plurality of strip-shaped structures distributed along the first direction; the strip-shaped structures are etched to form a plurality of separated segment-shaped structures distributed in an array mode in the second direction and the third direction, and the third direction intersects with the first direction and the second direction; etching the segment-shaped structure to form at least two first columnar structures which are separated from each other; and transferring the plurality of patterns of the first columnar structures to a substrate through a first insulating layer to form a substrate and a plurality of semiconductor columns which are arranged on the substrate and extend along the direction vertical to the substrate. According to the scheme provided by the embodiment of the invention, the high-density semiconductor column can be realized through twice punching, the section shape of the semiconductor column can be controlled, and the process is simple and more flexible.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to, but is not limited to, device design and manufacturing in the technical field of semiconductor, in particular to a manufacturing method of semiconductor device, semiconductor device and electronic equipment. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of the device is increasingly reduced, and the types and quantities of devices contained in a single chip are also increased, so that any slight difference in process production may affect the performance of the device.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs. SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present application provides a manufacturing method of semiconductor device, semiconductor device and electronic equipment, and realizes high-density semiconductor column array.

[0006] The present application provides a manufacturing method of semiconductor device, which comprises:

[0007] A substrate is provided, and a first insulating layer and a first hard mask layer covering the substrate are sequentially formed on the substrate;

[0008] The first hard mask layer is etched to form a plurality of strip-shaped structures spaced apart along a first direction parallel to the substrate, and the strip-shaped structures extend along a second direction parallel to the substrate; the first direction and the second direction are perpendicular;

[0009] The plurality of strip-shaped structures are etched using a first mask plate comprising a plurality of first holes, each strip-shaped structure forms a plurality of segment-shaped structures separated from each other, and the plurality of segment-shaped structures of the plurality of strip-shaped structures are arrayed along the second direction and a third direction parallel to the substrate, the third direction intersects the first direction, and the third direction intersects the second direction;

[0010] The plurality of segment-shaped structures are etched using a second mask plate comprising a plurality of second holes, each segment-shaped structure forms at least two first columnar structures separated from each other;

[0011] The pattern of the plurality of first columnar structures is transferred to the first insulating layer to form a plurality of second columnar structures;

[0012] transferring a pattern of the second columnar structures to the substrate forms a substrate and a plurality of semiconductor columns disposed on the substrate and extending in a direction perpendicular to the substrate.

[0013] In some embodiments, the etching the first hard mask layer to form a plurality of strip structures distributed along a first direction parallel to the substrate comprises:

[0014] forming, on the first hard mask layer, a second hard mask layer, a first anti-reflective layer, a first protective layer, and a second anti-reflective layer in sequence covering the first hard mask layer;

[0015] forming a plurality of first grooves extending through the first protective layer and the second anti-reflective layer along the second direction, the plurality of first grooves being distributed along the first direction;

[0016] forming a second insulating layer covering only sidewalls of the first grooves;

[0017] etching and removing the first protective layer and the second anti-reflective layer;

[0018] transferring a pattern of the second insulating layer to the first anti-reflective layer and the second hard mask layer, and etching and removing the second insulating layer;

[0019] forming a third insulating layer covering only sidewalls of the first anti-reflective layer and the second hard mask layer, and etching and removing the first anti-reflective layer and the second hard mask layer;

[0020] transferring a pattern of the third insulating layer to the first hard mask layer, and etching and removing the third insulating layer.

[0021] In some embodiments, after forming the substrate and the plurality of semiconductor columns disposed on the substrate, the method further comprises:

[0022] depositing a semiconductor thin film covering the plurality of semiconductor columns;

[0023] performing a thermal oxidation treatment on the plurality of semiconductor columns covered with the semiconductor thin film.

[0024] In some embodiments, the semiconductor thin film comprises polysilicon.

[0025] In some embodiments, the etching the plurality of strip structures using a first mask comprising a plurality of first holes, each of the strip structures forming a plurality of segment structures separated from each other comprises:

[0026] forming, on the first hard mask layer, a second protective layer, a third anti-reflective layer, and a third hard mask layer in sequence covering the first hard mask layer and the first insulating layer;

[0027] forming a plurality of first holes through the third hard mask layer, the third anti-reflective layer, the second protective layer and the first hard mask layer, the plurality of first holes separating each of the strip-shaped structures into a plurality of independent segment-shaped structures;

[0028] etching and removing the third hard mask layer, the third anti-reflective layer and the second protective layer.

[0029] In some embodiments, the using includes etching a plurality of the segment-shaped structures using a second mask including a plurality of second holes, each of the segment-shaped structures forming at least two first column-shaped structures separated from each other includes:

[0030] forming, on the first hard mask layer, a third protective layer, a fourth anti-reflective layer and a fourth hard mask layer in sequence covering the first hard mask layer and the first insulating layer;

[0031] forming a plurality of second holes through the fourth hard mask layer, the fourth anti-reflective layer, the third protective layer and the first hard mask layer, the plurality of second holes separating each of the segment-shaped structures into at least two first column-shaped structures separated from each other;

[0032] etching and removing the fourth hard mask layer, the fourth anti-reflective layer and the third protective layer.

[0033] In some embodiments, rows along the third direction formed by the plurality of the second holes are staggered in the orthographic projection of the substrate with rows along the third direction formed by the plurality of the first holes, columns along the second direction formed by the plurality of the second holes are overlapped in the orthographic projection of the substrate with columns along the second direction formed by the plurality of the first holes, and second holes and first holes in the same column are staggered along the second direction.

[0034] In some embodiments, the plurality of the first column-shaped structures are arrayed along the second direction and the third direction.

[0035] In some embodiments, in a direction parallel to the substrate, a cross section of the first hole is square and a cross section of the second hole is square.

[0036] Embodiments of the present disclosure provide a semiconductor device manufactured using the manufacturing method of any of the above-described semiconductor devices. The semiconductor device includes: a substrate, a plurality of semiconductor columns extending along a direction perpendicular to the substrate disposed on the substrate, the plurality of semiconductor columns arrayed along a first direction and a third direction, and the first direction and the third direction being non-perpendicular intersecting directions.

[0037] In some embodiments, a cross section of the semiconductor column along a direction parallel to the substrate is square.

[0038] The present disclosure provides an electronic device including the semiconductor device.

[0039] The present application provides a semiconductor device manufacturing method and a semiconductor device, and an electronic device. The semiconductor device manufacturing method comprises: providing a substrate, sequentially forming a first insulating layer covering the substrate, and a first hard mask layer on the substrate; etching the first hard mask layer to form a plurality of strip-shaped structures distributed along a first direction parallel to the substrate, the strip-shaped structures extending along a second direction parallel to the substrate; the first direction and the second direction are perpendicular; using a first mask plate comprising a plurality of first holes to etch the plurality of strip-shaped structures, each strip-shaped structure forms a plurality of segment-shaped structures separated from each other, and a plurality of segment-shaped structures of the plurality of strip-shaped structures are arrayed along the second direction and a third direction parallel to the substrate, the third direction intersects the first direction, and the third direction intersects the second direction; using a second mask plate comprising a plurality of second holes to etch the plurality of segment-shaped structures, each segment-shaped structure forms at least two first columnar structures separated from each other; transferring the pattern of the plurality of first columnar structures to the first insulating layer to form a plurality of second columnar structures; and transferring the pattern of the plurality of second columnar structures to the substrate to form a substrate and a plurality of semiconductor columns extending along a direction perpendicular to the substrate arranged on the substrate. The scheme provided by the present embodiment can produce high-density semiconductor columns through two punching processes, and the cross-sectional shape of the semiconductor columns can be controlled by changing the shape of the holes of the first mask plate and the second mask plate, which is simple and more flexible.

[0040] Other features and advantages of the present application will be set forth in the following description, and in part will be apparent from the description, or can be learned by practice of the present application. Other advantages of the present application will be realized and attained by the schemes described in the specification and the drawings.

[0041] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0042] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, together with the embodiments of the present application, to explain the technical schemes of the present application, and do not constitute a limitation on the technical schemes of the present application.

[0043] Figure 1A a top view of a stack structure formed by an exemplary embodiment, Figure 1B a front view of a stack structure formed by an exemplary embodiment;

[0044] Figure 2A a top view of a first groove formed by an exemplary embodiment, Figure 2Ba top view after forming a second insulating layer for an exemplary embodiment,

[0045] Figure 3A a top view after etching a second insulating layer for an exemplary embodiment, Figure 3B a top view after etching a second insulating layer for an exemplary embodiment,

[0046] Figure 4A a top view after etching a second insulating layer for an exemplary embodiment, Figure 4B a top view after etching a second insulating layer for an exemplary embodiment,

[0047] Figure 5A a top view after etching a second insulating layer for an exemplary embodiment, Figure 5B a top view after etching a second insulating layer for an exemplary embodiment,

[0048] Figure 6A a top view after etching a second insulating layer for an exemplary embodiment, Figure 6B a top view after etching a second insulating layer for an exemplary embodiment,

[0049] Figure 7A a top view after etching a second insulating layer for an exemplary embodiment, Figure 7B a top view after etching a second insulating layer for an exemplary embodiment,

[0050] Figure 8A a top view after etching a second insulating layer for an exemplary embodiment, Figure 8B a top view after etching a second insulating layer for an exemplary embodiment,

[0051] Figure 9A a top view after etching a second insulating layer for an exemplary embodiment, Figure 9B a top view after etching a second insulating layer for an exemplary embodiment,

[0052] Figure 10A a top view after etching a second insulating layer for an exemplary embodiment, Figure 10B a top view after etching a second insulating layer for an exemplary embodiment,

[0053] Figure 11A a top view after etching a second insulating layer for an exemplary embodiment, Figure 11B a top view after etching a second insulating layer for an exemplary embodiment,

[0054] Figure 12A a top view after forming a second protective layer, a third anti-reflective layer and a third hard mask layer for an exemplary embodiment, Figure 12B a front view after forming a second protective layer, a third anti-reflective layer and a third hard mask layer for an exemplary embodiment;

[0055] Figure 13A a top view after forming a first hole for an exemplary embodiment, Figure 13B a front view after forming a first hole for an exemplary embodiment;

[0056] Figure 14A a top view after removing the third hard mask layer, the third anti-reflective layer and the second protective layer for an exemplary embodiment, Figure 14B a front view after removing the third hard mask layer, the third anti-reflective layer and the second protective layer for an exemplary embodiment;

[0057] Figure 15A a top view after forming a third protective layer, a fourth anti-reflective layer and a fourth hard mask layer for an exemplary embodiment, Figure 15B a front view after forming a third protective layer, a fourth anti-reflective layer and a fourth hard mask layer for an exemplary embodiment;

[0058] Figure 16A a mask diagram of a second hole for an exemplary embodiment, Figure 16B a top view after forming a second hole for an exemplary embodiment, Figure 16C a front view after forming a second hole for an exemplary embodiment;

[0059] Figure 17 a front view after etching the first insulating layer for an exemplary embodiment;

[0060] Figure 18A a top view after forming a semiconductor pillar for an exemplary embodiment, Figure 18B a front view after forming a semiconductor pillar for an exemplary embodiment;

[0061] Figure 19A a top view after etching to remove the first insulating layer for an exemplary embodiment, Figure 19B a front view after etching to remove the first insulating layer for an exemplary embodiment;

[0062] Figure 20A a top view after forming a semiconductor pillar for an exemplary embodiment, Figure 20B a front view after forming a semiconductor pillar for an exemplary embodiment;

[0063] Figure 21A a top view after a thermal oxidation process provided for an exemplary embodiment, Figure 21B a front view after a thermal oxidation process provided for an exemplary embodiment;

[0064] Figure 22A a top view after forming a fourth insulating layer provided for an exemplary embodiment, Figure 22B a front view after forming a fourth insulating layer provided for an exemplary embodiment. DETAILED DESCRIPTION

[0065] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The features of the embodiments of the present disclosure and the embodiments can be arbitrarily combined with each other unless they conflict.

[0066] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as those understood by a person of ordinary skill in the art to which the present disclosure belongs.

[0067] The embodiments of the present disclosure are not necessarily limited to the shapes and sizes of the components shown in the drawings, and the shapes and sizes of the components shown in the drawings can be changed arbitrarily. The components of the embodiments of the present disclosure are not limited to those shown in the drawings, and can include components that are not shown in the drawings. For example, the components of the embodiments of the present disclosure can include a component that is substantially the same as or similar to a component shown in the drawings, even if it is not shown in the drawings.

[0068] In the present disclosure, ordinal numbers such as "first", "second", "third", and the like are set in order to avoid confusion of elements, and do not represent any order, number, or importance.

[0069] In the present disclosure, in order to facilitate the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and thus cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0070] In the present disclosure, unless explicitly defined and limited otherwise, the terms "mount", "connected", and "connection" should be interpreted broadly. For example, it can be a physical connection or a signal connection, can be a contact connection or an integral connection, can be directly connected, or indirectly connected through an intermediate, or the communication between two elements inside. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0071] In the present disclosure, "connection" includes a case where components are connected together through an element having some electrical function. The element having some electrical function is not particularly limited as long as it can perform transmission and reception of an electrical signal between the connected components. Examples of the element having some electrical function include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0072] In the present disclosure, "parallel" means approximately parallel or almost parallel, such as a state where two straight lines form an angle of -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state where two straight lines form an angle of 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0073] In the present disclosure, "A and B are in an integral structure" can mean that there is no obvious fault or gap as an obvious boundary interface in a microscopic structure. Generally, a film layer formed by patterning on one film layer is integral. For example, A and B use the same material to form one film layer and are simultaneously formed into a structure having a connection relationship by the same patterning process.

[0074] In the present disclosure, "the orthographic projection of B is located within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0075] High-density vertical silicon nanowires have a wide range of applications in the fields of high-density memory, sensors, energy conversion, and catalytic systems. Methods for preparing high-density vertical nanowire arrays include chemical synthesis (such as sol-gel method), photolithography and etching, etc. However, the size and uniformity of nanowire arrays prepared by chemical synthesis are difficult to control. In large-scale integrated circuit manufacturing, the method for preparing high-density vertical nanowires is mainly through photolithography and etching. To obtain a closely arranged small-size silicon nanocolumn array, electron beam lithography and etching can be used, but electron beam lithography is low in efficiency and is not suitable for large-scale production. The method using extreme ultraviolet exposure (EUV) is suitable for large-scale production, but the extreme ultraviolet lithography machine is high in cost and complex in equipment, and has not been widely used at present.

[0076] The present disclosure provides a semiconductor device manufacturing method, comprising:

[0077] A substrate is provided, and a first insulating layer and a first hard mask layer covering the substrate are sequentially formed on the substrate.

[0078] etching the first hard mask layer to form a plurality of strip structures spaced along a first direction parallel to the substrate, the strip structures extending along a second direction parallel to the substrate; the first direction and the second direction being perpendicular; i.e., the first hard mask layer is divided into a plurality of strips parallel to each other;

[0079] using a first mask including a plurality of first holes to etch the plurality of strip structures, each of the strip structures forming a plurality of segment structures separated from each other, and the plurality of segment structures of the plurality of strip structures being arrayed along the second direction and a third direction parallel to the substrate, the third direction intersecting the first direction, and the third direction intersecting the second direction; i.e., each strip structure of the first hard mask layer is divided into a plurality of segments;

[0080] using a second mask including a plurality of second holes to etch the plurality of segment structures, each of the segment structures forming at least two first column structures separated from each other; i.e., each segment of the first hard mask layer is further divided into two segments;

[0081] transferring a pattern of the plurality of first column structures to the first insulating layer to form a plurality of second column structures;

[0082] transferring a pattern of the plurality of second column structures to the substrate to form a plurality of semiconductor columns extending along a direction perpendicular to the substrate.

[0083] The scheme provided by the embodiment can realize fabrication of high-density semiconductor columns without a high-resolution photolithography machine through two punching processes, and the cross-sectional shape of the semiconductor columns can be controlled by changing the shape of the holes of the first mask and the second mask, so the process is simple and more flexible.

[0084] In some embodiments, the distance between adjacent strip structures along the first direction can be the same as the distance between semiconductor columns along the second direction, so that the density of the semiconductor columns distributed along the first direction is consistent with the density of the semiconductor columns distributed along the second direction.

[0085] In some embodiments, the etching the first hard mask layer to form a plurality of strip structures spaced along a first direction parallel to the substrate includes:

[0086] forming, on the first hard mask layer, a second hard mask layer, a first antireflection layer, a first protective layer, and a second antireflection layer in sequence, the second hard mask layer covering the first hard mask layer;

[0087] forming a plurality of first grooves extending through the first protective layer and the second antireflection layer along the second direction, the plurality of first grooves being distributed along the first direction;

[0088] forming a second insulating layer covering only sidewalls of the first trench;

[0089] etching to remove the first protective layer and the second anti-reflective layer;

[0090] transferring a pattern of the second insulating layer to the first anti-reflective layer and the second hard mask layer, and etching to remove the second insulating layer;

[0091] forming a third insulating layer covering only sidewalls of the first anti-reflective layer and the second hard mask layer, and etching to remove the first anti-reflective layer and the second hard mask layer;

[0092] transferring a pattern of the third insulating layer to the first hard mask layer, and etching to remove the third insulating layer.

[0093] The scheme provided by the embodiment can form multiple strip-shaped structures arranged in high density through twice self-aligned sidewall transfer technology.

[0094] In some embodiments, after forming a substrate and multiple semiconductor columns disposed on the substrate, the method further comprises:

[0095] depositing a semiconductor thin film covering the multiple semiconductor columns;

[0096] performing thermal oxidation treatment on the multiple semiconductor columns covered with the semiconductor thin film.

[0097] The scheme provided by the embodiment can repair etching damage in the process of etching to form semiconductor columns through thermal oxidation treatment, and improve the quality of semiconductor columns.

[0098] In some embodiments, the semiconductor thin film can include polysilicon. The semiconductor columns can be silicon columns.

[0099] In some embodiments, the rows of the second holes along the third direction in the orthographic projection of the substrate are staggered with the rows of the first holes along the third direction in the orthographic projection of the substrate, and the columns of the second holes along the second direction in the orthographic projection of the substrate are overlapped with the columns of the first holes along the second direction in the orthographic projection of the substrate. That is, the same column of the second holes along the second direction has the same extension direction as the same column of the first holes along the second direction, and the second holes and the first holes in the same column are staggered along the second direction.

[0100] In some embodiments, the segment-shaped structure can form two first columnar structures along the second direction and separated from each other and having the same length. That is, the segment-shaped structure can have two segments along the second direction.

[0101] In some embodiments, the first columnar structures of the plurality of strip structures are arrayed along the second direction and the third direction. Thus, the semiconductor columns formed finally are arrayed along the second direction and the third direction.

[0102] In some embodiments, the angle between the second direction and the third direction can be 30 degrees to 60 degrees. By adjusting the angle between the second direction and the third direction, a honeycomb-shaped semiconductor column array can be obtained, or an array arranged in a different manner can be obtained.

[0103] In some embodiments, in a direction parallel to the substrate, the cross section of the first hole can be square, and the cross section of the second hole can be square. The square can be a rectangle or a square. According to the scheme provided in the embodiments, a semiconductor column with a square cross section can be formed through the square first hole and the square second hole. Compared with a semiconductor column with a rhombus cross section, the semiconductor column with a square cross section can improve the reliability of the device, because the sharp part of the rhombus has a large electric field, which reduces the reliability of the device. However, the embodiments of the present disclosure are not limited thereto. The cross section of the first hole and the cross section of the second hole can be set according to the requirements of the cross section of the semiconductor column, so that a semiconductor column with a different cross section shape can be obtained, such as a semiconductor column with a circular cross section.

[0104] The embodiments of the present disclosure provide a semiconductor device, which can be manufactured by using any of the manufacturing methods of the semiconductor device described above. The semiconductor device can include a substrate, a plurality of semiconductor columns extending in a direction perpendicular to the substrate and arranged in an array along a second direction and a third direction, and the second direction and the third direction are intersected and non-perpendicular.

[0105] The technical scheme of the embodiments is further described below through the manufacturing process of the semiconductor device of the embodiments. The "patterning process" in the embodiments includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, and stripping of photoresist, etc., which are mature manufacturing processes in the related art. The "photolithography process" in the embodiments includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, coating can use known coating processes, and etching can use known methods, which are not specifically limited herein. In the description of the embodiments, it should be understood that "thin film" refers to a thin film of a certain material manufactured on a substrate by deposition or coating process. If the "thin film" does not need patterning process or photolithography process during the entire manufacturing process, the "thin film" can also be referred to as "layer". If the "thin film" still needs patterning process or photolithography process during the entire manufacturing process, it is referred to as "thin film" before the patterning process, and referred to as "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0106] In an exemplary embodiment, the manufacturing process of the semiconductor device can include:

[0107] 1) forming a stack structure;

[0108] performing a thermal oxidation process on the substrate 1 to form a first insulating layer 11;

[0109] depositing a first hard mask film on the first insulating layer 11 to form a first hard mask layer 21;

[0110] depositing a second hard mask film on the first hard mask layer 21 to form a second hard mask layer 22;

[0111] depositing a first anti-reflective film on the second hard mask layer 22 to form a first anti-reflective layer 31;

[0112] depositing a protective layer film on the first anti-reflective layer 31 to form a first protective layer 41;

[0113] depositing a second anti-reflective film on the first protective layer 41 to form a second anti-reflective layer 32, as shown in Figure 1A and Figure 1B the top view of the stack structure provided by an exemplary embodiment, Figure 1A the front view of the stack structure provided by an exemplary embodiment. Figure 1B

[0114] In some embodiments, the substrate 1 can be a semiconductor substrate, such as a silicon substrate, and the first insulating layer 11 can be, for example, silicon dioxide. In some embodiments, the first insulating layer 11 can be formed by depositing a first insulating film on the substrate 1.

[0115] In some embodiments, the first hard mask layer 21 can be, for example, polysilicon.

[0116] In some embodiments, the second hard mask layer 22 can be, for example, amorphous carbon (ACL). The subsequent third hard mask layer 23 and fourth hard mask layer 24 have similar materials, and thus will not be described again.

[0117] In some embodiments, the first anti-reflective layer 31 and the second anti-reflective layer 32 can be, for example, silicon oxynitride (SiON). The subsequent third anti-reflective layer 33 and fourth anti-reflective layer 34 have similar materials, and thus will not be described again.

[0118] In some embodiments, the first protective layer 41 can be, for example, a spin-on hard mask (SOH). The subsequent second protective layer 42 has a similar material, and thus will not be described again.

[0119] ​In some embodiments, the first insulating layer 11 can have a thickness (i.e. a thickness along a direction perpendicular to the substrate 1) of 800 ± 10% angstroms, the first hard mask layer 21 can have a thickness of 850 ± 10% angstroms, the second hard mask layer 22 can have a thickness of 700 ± 10% angstroms, the first anti-reflective layer 31 can have a thickness of 400 ± 10% angstroms, the first protective layer 41 can have a thickness of 700 ± 10% angstroms, and the second anti-reflective layer 32 can have a thickness of 250 ± 10% angstroms.

[0120] 2) Forming the first trenches T1;

[0121] The second anti-reflective layer 32 and the first protective layer 41 are etched along a direction perpendicular to the substrate 1 to form a plurality of first trenches T1; the first trenches T1 extend along the second direction Y, and the plurality of first trenches T1 are spaced apart along the first direction X; the second anti-reflective layer 32 forms a plurality of strip-shaped or planar film layers extending along the second direction Y, and the first protective layer 41 forms a plurality of strip-shaped or planar film layers extending along the second direction Y, as shown in Figure 2A and Figure 2B Figure 2A a top view of an exemplary embodiment after forming the first trenches T1, Figure 2B a front view of an exemplary embodiment after forming the first trenches T1.

[0122] 3) Forming the second insulating layer 12;

[0123] The second insulating layer 12 is formed by depositing a second insulating film on the substrate 1 having the foregoing structure; the second insulating layer 12 covers the bottom wall and the sidewall of the first trenches T1, and covers the surface of the second anti-reflective layer 32 facing away from the substrate 1, as shown in Figure 3A and Figure 3B Figure 3A a top view of an exemplary embodiment after forming the second insulating layer 12, Figure 3B a front view of an exemplary embodiment after forming the second insulating layer 12.

[0124] In some embodiments, the second insulating layer 12 can be a Low-K dielectric layer, such as silicon dioxide, etc.

[0125] 4) Etching the second insulating layer 12;

[0126] The second insulating layer 12 covering the surface of the second anti-reflective layer 32 facing away from the substrate 1 is etched away, and the second insulating layer 12 covering the bottom wall of the first trenches T1 is etched away, as shown in Figure 4A and Figure 4B Figure 4A ​​​A top view of the exemplary embodiment after etching the second insulating layer 12, Figure 4B A front view of the exemplary embodiment after etching the second insulating layer 12. At this time, the second insulating layer 12 only covers the sidewalls of the first trench, i.e. the sidewalls of the second anti-reflective layer 32 and the sidewalls of the first protective layer 41. The second insulating layer 12 forms a plurality of strip-shaped film layers extending along the second direction Y, and the plurality of strip-shaped film layers are spaced apart along the first direction X.

[0127] 5) Etching to remove the second anti-reflective layer 32 and the first protective layer 41, leaving the second insulating layer 12, exposing the first anti-reflective layer 31 covered by the first protective layer 41; and a portion of the first anti-reflective layer 31 not covered by the first protective layer 41 is etched away, but the second hard mask layer 22 covered by the first anti-reflective layer 31 is not exposed; as shown in Figure 5A and Figure 5B Figure 5A A top view of the exemplary embodiment after etching to remove the second anti-reflective layer 32 and the first protective layer 41, Figure 5B A front view of the exemplary embodiment after etching to remove the second anti-reflective layer 32 and the first protective layer 41.

[0128] 6) Etching the first anti-reflective layer 31 and the second hard mask layer 22 with the second insulating layer 12 as a mask, forming a plurality of second trenches T2, the bottom wall of the second trench T2 exposing the first hard mask layer 21; at this time, the pattern of the second insulating layer 12 is transferred to the second hard mask layer 22, i.e. the second hard mask layer 22 forms a plurality of strip-shaped patterns extending along the second direction Y; as shown in Figure 6A and Figure 6B Figure 6A A top view of the exemplary embodiment after the pattern is transferred to the second hard mask layer 22, Figure 6B A front view of the exemplary embodiment after the pattern is transferred to the second hard mask layer 22.

[0129] 7) Removing the second insulating layer 12, at this time, the first hard mask layer 21 only has the strip-shaped pattern formed by the second hard mask layer 22 and the first anti-reflective layer 31, as shown in Figure 7A and Figure 7B Figure 7A A top view of the exemplary embodiment after removing the second insulating layer 12, Figure 7B A front view of the exemplary embodiment after removing the second insulating layer 12. The above steps 3) to 7) achieve a self-aligned sidewall transfer. Subsequently, a second self-aligned sidewall transfer is performed.

[0130] 8) Forming a third insulating layer 13; ​​​

[0131] A third insulating film is deposited on the substrate 1 having the aforementioned structure to form a third insulating layer 13. The third insulating layer 13 covers the bottom wall and side walls of the second trench T2, and covers the surface of the first anti-reflection layer 31 facing away from the substrate 1. Figure 8A and Figure 8B As shown, Figure 8A A top view after forming the third insulating layer 13 is provided for an exemplary embodiment. Figure 8B This is a front view after forming the third insulating layer 13 according to an exemplary embodiment.

[0132] 9) etching the third insulating layer 13;

[0133] The third insulating layer 13 covering the surface of the first anti-reflection layer 31 facing away from the substrate 1 is removed by etching, and the third insulating layer 13 covering the bottom wall of the second trench T2 is removed by etching. Figure 9A and Figure 9B As shown, Figure 9A A top view after etching the third insulating layer 13 is provided for an exemplary embodiment. Figure 9B This is a front view of an exemplary embodiment after etching the third insulating layer 13. At this time, the third insulating layer 13 only covers the side walls of the first anti-reflection layer 31 and the second insulating layer 22.

[0134] 10) etching and removing the first anti-reflection layer 31 and the second hard mask layer 22, retaining the third insulating layer 13, and exposing the first hard mask layer 21 covered by the second hard mask layer 22; Figure 10A and Figure 10B As shown, Figure 10A A top view of an exemplary embodiment after the first anti-reflection layer 31 and the second hard mask layer 22 are removed by etching is provided. Figure 10B This is a front view of an exemplary embodiment after etching away the first anti-reflection layer 31 and the second hard mask layer 22. At this point, the third insulating layer 13 forms a plurality of strip-shaped film layers extending along the second direction Y, and the plurality of strip-shaped film layers are spaced apart along the first direction X.

[0135] 11) etching the first hard mask layer 21;

[0136] The first hard mask layer 21 is etched using the third insulating layer 13 as a mask to transfer the pattern of the third insulating layer 13 to the first hard mask layer 21. The first hard mask layer 21 forms a plurality of strip patterns extending along the second direction Y; the plurality of strip patterns are spaced apart along the first direction X.

[0137] The third insulating layer 13 is removed by etching. Figure 11A and Figure 11B As shown,Figure 11A a top view of the pattern transferred to the first hard mask layer 21 for an exemplary embodiment, Figure 11B a front view of the pattern transferred to the first hard mask layer 21 for an exemplary embodiment. The steps 8) to 11) above realize the second self-aligned sidewall transfer.

[0138] 12) forming a second protective layer 42, a third anti-reflective layer 33 and a third hard mask layer 23;

[0139] depositing a second protective layer film to form a second protective layer 42, which covers the first hard mask layer 21 and the first insulating layer 11;

[0140] depositing a third anti-reflective film to form a third anti-reflective layer 33; the third anti-reflective layer 33 covers the second protective layer 42;

[0141] depositing a third hard mask film to form a third hard mask layer 23; the third hard mask layer 23 covers the third anti-reflective layer 33, as shown in Figure 12A and Figure 12B a top view of the second protective layer 42, the third anti-reflective layer 33 and the third hard mask layer 23 for an exemplary embodiment, Figure 12A a front view of the second protective layer 42, the third anti-reflective layer 33 and the third hard mask layer 23 for an exemplary embodiment. Figure 12B 13) forming a first hole K1;

[0142] forming a plurality of first holes K1 penetrating through the third hard mask layer 23, the third anti-reflective layer 33, the second protective layer 42 and the first hard mask layer 21; the plurality of first holes K1 are arranged along a second direction Y and a third direction X1, the third direction X1 intersects with the second direction Y and is not perpendicular to the second direction Y, and the orthographic projection of the first holes K1 overlaps with the orthographic projection of the first hard mask layer 21 (the first hard mask layer 21 in strip pattern); at this time, each strip pattern of the first hard mask layer 21 can be divided into independent multiple segments by the plurality of first holes K1, such as uniform multiple segments; as shown in

[0143] and Figure 13A a top view of the first hole K1 for an exemplary embodiment, Figure 13B a front view of the first hole K1 for an exemplary embodiment. Figure 13A Figure 13B etching to remove the third hard mask layer 23, the third anti-reflective layer 33 and the second protective layer 42, as shown in and

[0144] a front view of the first hole K1 for an exemplary embodiment. Figure 14A Figure 14B Figure 14A ​​A top view of the third hard mask layer 23, the third anti-reflective layer 33, and the second protective layer 42 removed for an exemplary embodiment, Figure 14B A front view of the third hard mask layer 23, the third anti-reflective layer 33, and the second protective layer 42 removed for an exemplary embodiment.

[0145] In some embodiments, the first hole K1 has a square shape in a planar projection parallel to the substrate 1, but is not limited thereto and can have other shapes such as an oval shape.

[0146] 14) forming a third protective layer 43, a fourth anti-reflective layer 34, and a fourth hard mask layer 24;

[0147] A third protective layer film is deposited to form the third protective layer 43, which covers the first hard mask layer 21 and the first insulating layer 11;

[0148] A fourth anti-reflective film is deposited to form the fourth anti-reflective layer 34, which covers the third protective layer 43;

[0149] A fourth hard mask film is deposited to form the fourth hard mask layer 24, which covers the fourth anti-reflective layer 34; as shown in Figure 15A and Figure 15B Figure 15A A top view of the third protective layer 43, the fourth anti-reflective layer 34, and the fourth hard mask layer 24 formed for an exemplary embodiment, Figure 15B A front view of the third protective layer 43, the fourth anti-reflective layer 34, and the fourth hard mask layer 24 formed for an exemplary embodiment.

[0150] 15) forming a second hole K2;

[0151] A plurality of second holes K2 are formed through the fourth hard mask layer 24, the fourth anti-reflective layer 34, the third protective layer 43, and the first hard mask layer 21; the second holes K2 extend along a direction perpendicular to the substrate, and a plurality of the second holes K2 are arranged along a second direction Y and a third direction X1, which is crossed with the second direction Y and is not perpendicular to the second direction Y, and the planar projection of the second holes K2 overlaps with the planar projection of the first hard mask layer 21 (the first hard mask layer 21 in a strip pattern); at this time, each segment of the first hard mask layer 21 can be divided into two independent and uniform segments (the lengths of the two segments in the boundary region can be different) by the second holes K2, and the first hard mask layer 21 includes a plurality of first columnar structures arranged along the second direction Y and the third direction X1; the rows along the third direction X1 formed by the second holes K2 are staggered with the rows along the third direction X1 formed by the first holes K1.​

[0152] The fourth hard mask layer 24, the fourth anti-reflection layer 34, and the third protective layer 43 are removed by etching. Figure 16A 、 Figure 16B and Figure 16C As shown, Figure 16A A schematic diagram of a mask for a second hole K2 is provided for an exemplary embodiment. Figure 16B A top view of an exemplary embodiment after forming the second hole K2 is provided. Figure 16C This is a front view of an exemplary embodiment after the second hole K2 is formed.

[0153] In some embodiments, on a plane parallel to the substrate 1 , the orthographic projection of the second hole K2 is, for example, a square, but is not limited thereto, and may be other shapes, such as an ellipse.

[0154] 16) etching the first insulating layer 11;

[0155] Using the first hard mask layer 21 as a mask, the first insulating layer 11 is etched to transfer the pattern of the first hard mask layer 21 to the first insulating layer 11, and the first insulating layer 11 forms a plurality of second columnar structures arranged along the second direction Y and the third direction X1; Figure 17 As shown, Figure 17 This is a front view of an exemplary embodiment after etching the first insulating layer 11 .

[0156] 17) forming a semiconductor pillar 10;

[0157] Etching and removing the first hard mask layer 21;

[0158] The substrate 1 is etched using the first insulating layer 11 as a mask to transfer the pattern of the first insulating layer 11 (the second columnar structure) to the substrate 1 to form a plurality of semiconductor pillars 10. The plurality of semiconductor pillars 10 are arrayed along the second direction Y and the third direction X1. Figure 18A and Figure 18B As shown, Figure 18A FIG. 1 is a top view of a semiconductor pillar 10 formed according to an exemplary embodiment. Figure 18B This is a front view of an exemplary embodiment after forming semiconductor pillars 10. At this time, the substrate 1 is divided into two parts, one part serves as the substrate of the device, and the other part forms multiple semiconductor pillars 10. The substrate and semiconductor pillars 10 are an integrated structure.

[0159] 18) Etching and removing the first insulating layer 11, such as Figure 19A and Figure 19B As shown, Figure 19A A top view of an exemplary embodiment after etching and removing the first insulating layer 11 is provided. Figure 19BA front view of the semiconductor pillar 10' after the first insulating layer 11 is etched away is provided in an exemplary embodiment.

[0160] 19) forming a semiconductor pillar 10';

[0161] depositing a semiconductor thin film covering the semiconductor pillar 10, forming a plurality of semiconductor pillars 10' covered with the semiconductor thin film, as shown in Figure 20A and Figure 20B Figure 20A A top view of the semiconductor pillar 10' after formation is provided in an exemplary embodiment, Figure 20B A front view of the semiconductor pillar 10' after formation is provided in an exemplary embodiment. The semiconductor thin film is, for example, polysilicon.

[0162] 20) performing a thermal oxidation process on the semiconductor pillar 10', forming a columnar structure 10" with a semiconductor oxide on the surface and a semiconductor pillar inside, thereby repairing the etching damage of the semiconductor pillar 10, as shown in Figure 21A and Figure 21B Figure 21A A top view after the thermal oxidation process is provided in an exemplary embodiment, Figure 21B A front view after the thermal oxidation process is provided in an exemplary embodiment.

[0163] 21) forming a fourth insulating layer 14;

[0164] depositing a fourth insulating thin film on the substrate with the foregoing structure, forming a fourth insulating layer 14 covering the columnar structure 10", as shown in Figure 22A and Figure 22B Figure 22A A top view after the fourth insulating layer 14 is formed is provided in an exemplary embodiment, Figure 22B A front view after the fourth insulating layer 14 is formed is provided in an exemplary embodiment.

[0165] In some embodiments, the fourth insulating layer 14 can be a Low-k dielectric layer, such as silicon dioxide, etc.

[0166] The disclosure also provides an electronic device including the semiconductor device of any of the foregoing embodiments or the semiconductor device formed by the manufacturing method of any of the foregoing embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, etc. The storage device can include a memory in a computer, etc., which is not limited herein.

[0167] ​​​Although the present application has been described with reference to the above embodiments, the contents described are merely employed embodiments for facilitating the understanding of the present application, and are not intended to limit the present application. Any modification and change in the form and details can be made by any person skilled in the art without departing from the spirit and scope of the present application, and the patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, Comprising: providing a substrate, sequentially forming a first insulating layer covering the substrate, a first hard mask layer on the first insulating layer; etching the first hard mask layer to form a plurality of strip structures distributed along a first direction parallel to the substrate, the strip structures extending along a second direction parallel to the substrate; the first direction and the second direction are perpendicular; using a first mask plate comprising a plurality of first holes to etch a plurality of the strip structures, each of the strip structures forming a plurality of segment structures separated from each other, and a plurality of segment structures of a plurality of the strip structures are arrayed along the second direction and a third direction parallel to the substrate, the third direction intersects the first direction, and the third direction intersects the second direction; using a second mask plate comprising a plurality of second holes to etch a plurality of the segment structures, each of the segment structures forming at least two first columnar structures separated from each other; transferring a pattern of a plurality of the first columnar structures to the first insulating layer to form a plurality of second columnar structures; transferring a pattern of a plurality of the second columnar structures to the substrate to form a substrate and a plurality of semiconductor columns extending along a direction perpendicular to the substrate and arranged on the substrate.

2. The method of manufacturing a semiconductor device according to claim 1, wherein The etching the first hard mask layer to form a plurality of strip structures distributed along a first direction parallel to the substrate comprises: sequentially forming a second hard mask layer covering the first hard mask layer, a first anti-reflection layer, a first protective layer and a second anti-reflection layer on the first hard mask layer; forming a plurality of first grooves extending along the second direction and penetrating the first protective layer and the second anti-reflection layer, a plurality of the first grooves being distributed along the first direction; forming a second insulating layer covering only sidewalls of the first grooves; etching to remove the first protective layer and the second anti-reflection layer; transferring a pattern of the second insulating layer to the first anti-reflection layer and the second hard mask layer, and etching to remove the second insulating layer; forming a third insulating layer covering only sidewalls of the first anti-reflection layer and the second hard mask layer, and etching to remove the first anti-reflection layer and the second hard mask layer; transferring a pattern of the third insulating layer to the first hard mask layer, and etching to remove the third insulating layer.

3. The method of manufacturing a semiconductor device according to claim 1, wherein After forming the substrate and a plurality of semiconductor columns arranged on the substrate, further comprising: depositing a semiconductor thin film covering a plurality of the semiconductor columns; performing thermal oxidation treatment on a plurality of the semiconductor columns covered with the semiconductor thin film.

4. The method of manufacturing a semiconductor device according to claim 3, wherein The semiconductor thin film comprises polysilicon.

5. The method of manufacturing a semiconductor device according to Claim 1, wherein The etching a plurality of the strip structures using a first mask plate comprising a plurality of first holes, each of the strip structures forming a plurality of segment structures separated from each other, comprises: sequentially forming a second protective layer, a third anti-reflection layer and a third hard mask layer covering the first hard mask layer and the first insulating layer on the first hard mask layer; forming a plurality of first holes penetrating the third hard mask layer, the third anti-reflection layer, the second protective layer and the first hard mask layer, the plurality of first holes dividing each of the strip structures into a plurality of independent segment structures; etching to remove the third hard mask layer, the third anti-reflection layer and the second protection layer.

6. The method of manufacturing a semiconductor device according to Claim 1, wherein The using includes etching a plurality of the segment-shaped structures by a second mask plate including a plurality of second holes, each of the segment-shaped structures forms at least two first column-shaped structures separated from each other. forming a third protection layer, a fourth anti-reflection layer and a fourth hard mask layer on the first hard mask layer in sequence, the third protection layer covers the first hard mask layer and the first insulation layer; forming a plurality of second holes penetrating through the fourth hard mask layer, the fourth anti-reflection layer, the third protection layer and the first hard mask layer, the plurality of second holes separate each segment-shaped structure into at least two independent first column-shaped structures; etching to remove the fourth hard mask layer, the fourth anti-reflection layer and the third protection layer.

7. The method of manufacturing a semiconductor device according to any one of claims 1 to 6, wherein The projection of the rows of the second holes on the substrate is staggered with the projection of the rows of the first holes on the substrate, the projection of the columns of the second holes on the substrate overlaps with the projection of the columns of the first holes on the substrate, and the second holes and the first holes in the same column are staggered along the second direction.

8. The method of manufacturing a semiconductor device according to any one of claims 1 to 6, wherein The plurality of the first column-shaped structures are arrayed along the second direction and the third direction.

9. The method of manufacturing a semiconductor device according to any one of claims 1 to 6, wherein In a direction parallel to the substrate, the cross section of the first hole is square, and the cross section of the second hole is square.

10. A semiconductor device, characterized by comprising: The semiconductor device is manufactured by the manufacturing method of the semiconductor device according to any one of claims 1 to 9, and includes: a substrate, a plurality of semiconductor columns extending along a direction perpendicular to the substrate arranged on the substrate, the semiconductor columns are arrayed along a second direction and a third direction, and the second direction and the third direction are non-perpendicular.

11. The semiconductor device of claim 10, wherein, The cross section of the semiconductor column along a direction parallel to the substrate is square.

12. An electronic device, comprising: The semiconductor device includes the semiconductor device according to claim 10 or 11. The semiconductor device includes the semiconductor device according to claim 10 or 11.

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