Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof, and electronic equipment, and the manufacturing method comprises the steps: forming an initial groove, and enabling at least part of the region of the initial groove to be disposed in a first dielectric layer; depositing a second dielectric layer to cover the side wall of the upper part of the initial groove, and exposing the first dielectric layer at the middle lower part of the initial groove; and etching to remove the second dielectric layer and a part of the first dielectric layer at the middle lower part of the initial groove to form a first groove. A second dielectric layer covering the side wall of the upper portion of an initial groove is formed, then the second dielectric layer and a first dielectric layer, exposed by the second dielectric layer, of the lower middle portion of the initial groove are synchronously etched, adjustment and optimization of the shape of the groove are achieved, and the first groove with the shape meeting the expectation is formed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure, a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are also increased, so that any slight difference in process production can affect the performance of the devices.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor device designs and process optimizations to meet people's current product needs. SUMMARY

[0004] Based on this, the present application provides a semiconductor structure, a manufacturing method thereof, and an electronic device.

[0005] To achieve the above-mentioned purpose, in a first aspect, the present application provides a manufacturing method of a semiconductor structure, comprising:

[0006] forming an initial trench, at least part of the initial trench is arranged in a first dielectric layer;

[0007] depositing a second dielectric layer to cover the sidewall of the upper part of the initial trench, and exposing the first dielectric layer of the middle and lower part of the initial trench;

[0008] etching to remove the second dielectric layer and part of the first dielectric layer of the middle and lower part of the initial trench, and forming a first trench.

[0009] Optionally, taking a plane perpendicular to the opening direction of the first trench as a horizontal plane, the sidewall of the first trench is perpendicular to the horizontal plane, or the sidewall of the first trench is inclined at a first angle with respect to the horizontal plane.

[0010] Optionally, the first angle is greater than or equal to 60°, and the first angle is less than 90°.

[0011] Optionally, before forming the second dielectric layer, a sacrificial layer is filled in the middle and lower part of the initial trench;

[0012] After forming the second dielectric layer, the sacrificial layer is removed.

[0013] Optionally, filling the sacrificial layer in the middle and lower part of the initial trench comprises:

[0014] filling the initial trench with a sacrificial material layer;

[0015] etching the remaining sacrificial material layer to a preset height, and etching the remaining sacrificial material layer to form the sacrificial layer.

[0016] Optionally, in the process of forming the second dielectric layer, the second dielectric layer covers the top surface of the sacrificial layer, and before the sacrificial layer is removed, the second dielectric layer on the top surface of the sacrificial layer is etched and removed by using an anisotropic etching process, so as to expose the sacrificial layer.

[0017] Optionally, in the process of depositing the second dielectric layer, the thickness of the second dielectric layer is equal to or greater than the thickness of the first dielectric layer to be removed from the middle and lower part of the initial trench by controlling the deposition parameters.

[0018] Optionally, the manufacturing method comprises:

[0019] providing a substrate, the substrate extending along a horizontal plane;

[0020] forming at least one second trench to divide the substrate into a plurality of semiconductor strips, the second trench extending along a first horizontal direction, and the second trench and the semiconductor strips being spaced apart along a second horizontal direction;

[0021] filling the second trench with a first dielectric layer;

[0022] forming at least one initial trench to divide the semiconductor strips into a plurality of semiconductor pillars, the initial trench extending along the second horizontal direction, and the plurality of semiconductor pillars being arrayed along the first horizontal direction and the second horizontal direction;

[0023] depositing a second dielectric layer to cover the sidewall of the upper part of the initial trench, and expose the first dielectric layer of the middle and lower part of the initial trench;

[0024] etching and removing the second dielectric layer and part of the first dielectric layer of the middle and lower part of the initial trench to form a first trench, the sidewall of the first trench being perpendicular to the substrate, and the first trench being equal in width from top to bottom.

[0025] Optionally, after the first trench is formed, the manufacturing method further comprises:

[0026] forming a plurality of word lines, the word lines extending along the second horizontal direction, each of the word lines intersecting with a row of the semiconductor pillars arranged along the second horizontal direction, covering part of the sidewall of the row of the semiconductor pillars, and adjacent word lines being separated by the first trench.

[0027] In a second aspect, the present disclosure provides a semiconductor structure, which is manufactured by the method for manufacturing a semiconductor structure according to the first aspect, and the semiconductor structure comprises a first trench, at least a part of the first trench is arranged in a first dielectric layer.

[0028] Optionally, a plane perpendicular to the opening direction of the first trench is a horizontal plane, a sidewall of the first trench is perpendicular to the horizontal plane, or the sidewall of the first trench is inclined to the horizontal plane at a first angle.

[0029] Optionally, the first angle is greater than or equal to 60°, and the first angle is less than 90°.

[0030] Optionally, the semiconductor structure further comprises:

[0031] a substrate extending along a horizontal plane, wherein the first trench extends on the substrate along a second horizontal direction, a sidewall of the first trench is perpendicular to the substrate, and the first trench is equal in width from top to bottom;

[0032] a plurality of semiconductor pillars arranged on the substrate along a first horizontal direction and the second horizontal direction, the semiconductor pillars arranged along the first horizontal direction are separated by the first trench;

[0033] a plurality of word lines extending along the second horizontal direction, each of the word lines intersects with a row of the semiconductor pillars arranged along the second horizontal direction, covers part of the sidewalls of the row of the semiconductor pillars, and adjacent word lines are separated by the first trench.

[0034] In a third aspect, the present disclosure provides an electronic device comprising the semiconductor device according to the second aspect.

[0035] The semiconductor structure, the method for manufacturing the semiconductor structure, and the electronic device of the present disclosure can realize adjustment and optimization of the trench morphology and structure by forming a second dielectric layer covering the sidewall of the upper part of the initial trench, and synchronously etching the second dielectric layer and the first dielectric layer of the middle and lower part of the initial trench exposed by the second dielectric layer, so as to form the first trench with a morphology meeting the expectation. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort based on these drawings.

[0037] Figure 1 The process flow chart of the method for manufacturing the semiconductor structure provided in an embodiment.

[0038] Figure 2a Schematic view of an initial trench and a first trench provided in an embodiment.

[0039] Figure 2b Schematic view of an initial trench and a first trench provided in another embodiment.

[0040] Figure 2c Schematic view of an initial trench and a first trench provided in yet another embodiment.

[0041] Figure 2d Schematic view of an initial trench and a first trench provided in yet another embodiment.

[0042] Figure 3 Schematic view of an initial trench provided in an embodiment.

[0043] Figure 4 Schematic view after forming a sacrificial material layer in an embodiment.

[0044] Figure 5 Schematic view after filling a sacrificial layer in a middle and lower portion of the initial trench in an embodiment.

[0045] Figure 6 Schematic view after forming a second dielectric layer in an embodiment.

[0046] Figure 7 Schematic view after forming a second dielectric layer in an embodiment.

[0047] Figure 8 Schematic view after removing the second dielectric layer covering the sacrificial layer in an embodiment.

[0048] Figure 9 Schematic view of a first trench formed in an embodiment.

[0049] Figure 10 Process flow diagram of a method of fabricating a semiconductor structure provided in an embodiment.

[0050] Figure 11 Schematic view of a substrate provided in an embodiment.

[0051] Figure 12 Schematic view of a structure after forming a second trench in an embodiment.

[0052] Figure 13 Schematic view of a structure after forming a second trench in an embodiment. Figure 12 Cross-sectional view along lines a-a', b-b', c-c', d-d' after forming a second trench in an embodiment.

[0053] Figure 14 Schematic view of a structure after forming a second trench in an embodiment. Figure 12Cross-sectional view along lines a-a', b-b', c-c', d-d' after the embodiment forms the first dielectric layer.

[0054] Figure 15 Structure diagram for an embodiment after forming the initial trench.

[0055] Figure 16 For an embodiment Figure 15 Cross-sectional view along lines a-a', b-b', c-c', d-d' after the embodiment forms the initial trench.

[0056] Figure 17 For an embodiment Figure 15 Cross-sectional view along lines a-a', b-b', c-c', d-d' after the embodiment forms the sacrificial material layer.

[0057] Figure 18 For an embodiment Figure 15 Cross-sectional view along lines a-a', b-b', c-c', d-d' after the embodiment forms the sacrificial layer.

[0058] Figure 19 For an embodiment Figure 15 Cross-sectional view along lines a-a', b-b', c-c', d-d' after the embodiment forms the second dielectric layer covering the sidewalls of the upper portion of the initial trench.

[0059] Figure 20 For an embodiment Figure 15 Cross-sectional view along lines a-a', b-b', c-c', d-d' after the embodiment removes the sacrificial layer.

[0060] Figure 21 For an embodiment Figure 15 Cross-sectional view along lines a-a', b-b', c-c', d-d' after the embodiment forms the first trench.

[0061] Figure 22 For an embodiment Figure 15 Cross-sectional view along lines a-a', b-b' after the embodiment forms the isolation portion in the first trench.

[0062] Figure 23 For an embodiment Figure 15 Cross-sectional view along lines a-a', b-b' after the embodiment forms the word line.

[0063] Figure 24 Structure diagram for a semiconductor structure provided by an embodiment.

[0064] 10, first dielectric layer; 11a, initial trench; 11, first trench; SW, sidewall of the first trench; 21, second trench; 20, second dielectric layer; 30, sacrificial layer; 31, sacrificial material layer; 40, substrate; 41, semiconductor strip; 42, semiconductor pillar; 50, isolation portion; 51, third dielectric layer; 52, first isolation layer; 53, second isolation layer; 60, word line; 61, gate dielectric layer;

[0065] D1, first horizontal direction; D2, second horizontal direction; α1, first angle; α2, second angle. DETAILED DESCRIPTION

[0066] For the purposes of this application, reference will be made to the accompanying drawings in which preferred embodiments of the application are shown. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0068] In the exemplary embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided, Figure 1 A flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure is shown in FIG. 1. Figure 1 As shown in FIG. 1, a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure includes the following steps:

[0069] Step S11: Form an initial trench, at least a portion of the initial trench is disposed in the first dielectric layer.

[0070] Step S12: Deposit a second dielectric layer to cover the sidewall of the upper portion of the initial trench, exposing the first dielectric layer of the middle and lower portion of the initial trench.

[0071] Step S13: Etch to remove the second dielectric layer and a portion of the first dielectric layer of the middle and lower portion of the initial trench, forming a first trench.

[0072] The method for manufacturing the semiconductor structure of the exemplary embodiment of the present disclosure adjusts and optimizes the morphology and key size of the initial trench by forming a second dielectric layer covering the sidewall of the upper part of the initial trench, and simultaneously etching the second dielectric layer and the first dielectric layer exposed by the second dielectric layer from the middle and lower part of the initial trench, so as to form a first trench with morphology and structure meeting the expectation; the method for manufacturing the semiconductor structure of the present embodiment can be applied to a three-dimensional semiconductor structure, and is suitable for the development direction of further miniaturization and high integration in the semiconductor field.

[0073] In the plane perpendicular to the opening direction of the first trench 11, the sidewall SW of the first trench 11 is perpendicular to the plane, or the sidewall SW of the first trench 11 is inclined to the plane at a first angle α1.

[0074] The first angle α1 is greater than or equal to 60°, and the first angle α1 is less than 90°. For example, the first angle α1 can be 60°, 70°, 75°, 80°, 85°, 89° or other angles. It can be understood that the first angle α1 can be flexibly selected as other angles according to process requirements, such as 50° or 100°, etc.

[0075] In some examples, the first trench 11 is equal in width from top to bottom; in other examples, the width of the middle and lower part of the first trench 11 is greater than the width of the upper part of the first trench 11; in other examples, the width of the middle and lower part of the first trench 11 is less than the width of the upper part of the first trench 11.

[0076] In some embodiments, referring to FIG. 1A, Figure 2a As shown in FIG. 1A, the sidewall of the initial trench 11a is perpendicular to the plane, and the initial trench 11a is equal in width from top to bottom. The morphology of the initial trench 11a is adjusted to form the first trench 11, and the sidewall SW of the first trench 11 is inclined to the plane at a first angle α1.

[0077] In some embodiments, referring to FIG. 1B, Figure 2b As shown in FIG. 1B, the sidewall of the initial trench 11a is inclined to the plane at a second angle α2, and the second angle α2 is less than the first angle α1. The morphology of the initial trench 11a is adjusted to form the first trench 11, and the sidewall SW of the first trench 11 is inclined to the plane at the first angle α1.

[0078] In some embodiments, referring to FIG. 1C, Figure 2c As shown in FIG. 1C, the sidewall of the initial trench 11a is perpendicular to the plane, and the initial trench 11a is equal in width from top to bottom. The morphology of the initial trench 11a is adjusted to form the first trench 11, and the sidewall SW of the first trench 11 is perpendicular to the plane. The width of the middle and lower part of the first trench 11 is greater than the width of the upper part of the first trench 11.

[0079] In some embodiments, referring to FIG. 1D,Figure 2d As shown, the forming process of the initial trench 11a is affected by etching process or other factors, resulting in different upper and lower groove widths of the initial trench 11a in the first dielectric layer 10, that is, the initial trench 11a presents an upper wide and lower narrow appearance in a plane perpendicular to the extension direction of the initial trench 11a, and even the bottom of the initial trench 11a can present a deep and narrow "V" shaped appearance.

[0080] For example, the initial trench 11a can penetrate through the first dielectric layer 10 and other film layers arranged alternately and spaced apart, the initial trench 11a is formed by etching film layers of two different materials, the etching rates of the film layers of the two different materials are different, resulting in different appearances of the initial trench 11a in the two film layers, and different upper and lower groove widths of the initial trench 11a formed in the first dielectric layer 10.

[0081] In this embodiment, the initial trench 11a is processed to reduce the width difference between the groove width of the upper part and the groove width of the middle and lower part of the initial trench 11a, and the first trench 11 is formed, the sidewall SW of the first trench 11 is perpendicular to the horizontal plane, the groove width of the upper part and the groove width of the middle and lower part of the first trench 11 are the same, the width of the first trench 11 is uniform and high, and the bottom of the initial trench 11a is a smooth wall surface without a deep and narrow "V" shaped appearance.

[0082] It should be noted that "upper and lower equal width", "same groove width" in this disclosure refer to that the widths of the trenches are basically the same.

[0083] Next, the production method of the semiconductor structure of some embodiments of this example will be described with reference to the accompanying drawings. Figure 2d The production method of the semiconductor structure of some embodiments of this example will be described with reference to the accompanying drawings. Figures 3-9 The production method of the semiconductor structure of some embodiments of this example will be described with reference to the accompanying drawings. Figures 3-9 The production method of the semiconductor structure of some embodiments of this example will be described with reference to the accompanying drawings.

[0084] In step S11, the production method of the semiconductor structure of some embodiments of this example will be described with reference to the accompanying drawings. Figure 3 As shown, the initial trench 11a can be a deep trench continuously extending in the first dielectric layer 10; or the initial trench 11a can extend discontinuously in the first dielectric layer 10.

[0085] The initial trench 11a is a trench with an appearance or structure that does not meet process requirements or standards.

[0086] In step S12, the production method of the semiconductor structure of some embodiments of this example will be described with reference to the accompanying drawings. Figure 8As shown, a second dielectric layer 20 is deposited to cover the sidewalls of the upper portion of the initial trench 11a, and the sidewalls of the middle and lower portion of the initial trench 11a are exposed by the second dielectric layer 20. That is, the second dielectric layer 20 only covers the first dielectric layer 10 on both sides of the upper portion of the initial trench 11a, and the width of the sidewalls of the upper portion of the initial trench 11a is increased (the width in the plane perpendicular to the extension direction of the initial trench 11a).

[0087] In an example, the second dielectric layer 20 can be deposited by an atomic layer deposition (ALD) process to precisely control the thickness of the second dielectric layer 20.

[0088] The material of the second dielectric layer 20 is the same as that of the first dielectric layer 10, or the second dielectric layer 20 and the first dielectric layer 10 have the same etching rate.

[0089] In step S13, as shown in FIG. 13, referring to FIG. 13, Figure 9 Figure 8 A wet etching process can be used to etch the second dielectric layer 20 and the first dielectric layer 10 exposed by the middle and lower portion of the initial trench 11a, the etching liquid is injected into the initial trench 11a, and the etching liquid etches and removes all of the second dielectric layer 20 and part of the dielectric layer of the middle and lower portion of the initial trench 11a to adjust the slot width of the middle and lower portion of the initial trench 11a, so as to form the first trench 11 with a morphology and structure meeting the process requirements.

[0090] In some embodiments, before the second dielectric layer 20 is formed, a sacrificial layer 30 is filled in the middle and lower portion of the initial trench 11a. After the second dielectric layer 20 is formed, the sacrificial layer 30 is removed.

[0091] In this embodiment, as shown in FIG. 14, referring to FIG. 14, Figure 5 Figure 3 After the initial trench 11a is formed, the sacrificial layer 30 is formed in the initial trench 11a, and the sacrificial layer 30 is used to define the area of the initial trench 11a that needs to be profiled. In actual production, the height of the sacrificial layer 30 can be flexibly adjusted according to the morphology and profile of the initial trench 11a.

[0092] In an example, the critical dimensions of the upper portion of the initial trench 11a are uniform (the slot widths are basically the same), the slot width of the middle and lower portion of the initial trench 11a is narrower than that of the upper portion, the initial trench 11a has an upper-wide and lower-narrow morphology, and the bottom of the initial trench 11a can have a deep and narrow "V" shape. Then, the sacrificial layer 30 is formed to fill the middle and lower portion of the initial trench 11a, and the upper portion of the initial trench 11a that does not need to be profiled is exposed. Then, the second dielectric layer 20 is formed to cover the sidewalls of the upper portion of the initial trench 11a to protect the upper portion of the initial trench 11a that does not need to be profiled. ​​

[0093] Referring to Figure 6 In the process of forming the second dielectric layer 20, the second dielectric layer 20 covers the top surface of the sacrificial layer 30. Before the sacrificial layer 30 is removed, referring to Figure 7 The second dielectric layer 20 on the top surface of the sacrificial layer 30 is removed by an anisotropic etching process, and the sacrificial layer 30 is exposed.

[0094] For example, referring to Figure 8 、 Figure 9 The second dielectric layer 20 is anisotropically etched by a dry etching process. The etching rate of the etching process in the vertical direction is much greater than that in the horizontal direction. The second dielectric layer 20 on the top surface of the sacrificial layer 30 is etched and removed, and only the second dielectric layer 20 covering the sidewall of the initial trench 11a is reserved. The top surface of the sacrificial layer 30 is exposed to facilitate the removal of the sacrificial layer 30 and the profile control of the middle and lower parts of the initial trench 11a.

[0095] Then, the sacrificial layer 30 is removed to expose the region of the initial trench 11a that needs to be profile-optimized, so as to etch and trim the profile and critical dimensions of the initial trench 11a, and form the first trench 11.

[0096] For example, the atomic layer etching (ALE) can be used to remove the sacrificial layer 30.

[0097] In some embodiments, the sacrificial layer is filled in the middle and lower parts of the initial trench, comprising:

[0098] Step S11-1: fill the initial trench with a sacrificial material layer.

[0099] Step S11-2: etch back the sacrificial material layer to a preset height, and etch the reserved sacrificial material layer to form a sacrificial layer.

[0100] In this embodiment, as shown in Figure 4 The spin coating process is used to form the sacrificial material layer 31 to fill the initial trench 11a. The material of the sacrificial material layer 31 includes spin-on carbon material.

[0101] For example, the spin-on carbon (SOC), spin-on glass (SOG), or spin-on dielectric (SOD) can be used to form the sacrificial material layer 31.

[0102] In other embodiments, the deposition process can be used to deposit the sacrificial material layer 31 to fill the initial trench 11a.

[0103] For example, the sacrificial material layer 31 can be formed by depositing any one of atomic layer deposition, chemical vapor deposition (CVD), physical vapor deposition (PVD), or sputtering. The sacrificial material layer 31 can include silicon oxide, and the deposition process can be adjusted to ensure that the sacrificial material layer 31 and the first dielectric layer 10 and the second dielectric layer 20 have different etching rates.

[0104] like Figure 5 As shown, refer to Figure 4 After the sacrificial material layer 31 fills the initial groove 11a, the preset height of the initial groove 11a that needs to be profile controlled is determined according to the morphology and critical dimensions of the initial groove 11a, and the sacrificial material layer 31 is etched back to the preset height to form a sacrificial layer 30 of the preset height in the initial groove 11a. The sacrificial layer 30 is defined in the initial groove 11a as an area to be profile controlled.

[0105] In some embodiments, reference Figure 6 、 Figure 8 、 Figure 9 During the deposition of the second dielectric layer 20, the deposition parameters are controlled so that the thickness of the second dielectric layer 20 is equal to the thickness of the first dielectric layer 10 to be removed in the middle and lower portion of the initial trench 11 a, or the thickness of the second dielectric layer 20 is greater than the thickness of the first dielectric layer 10 to be removed in the middle and lower portion of the initial trench 11 a.

[0106] Generally speaking, step S13 uses a wet process to etch away the second dielectric layer 20 and a portion of the first dielectric layer 10 in the middle and lower portion of the initial trench 11 a. The etching solution etches the second dielectric layer 20 and the first dielectric layer 10 at the same etching rate. When depositing the second dielectric layer 20, the thickness of the second dielectric layer 20 is adjusted by controlling the deposition parameters. The thickness of the second dielectric layer 20 is equal to the thickness of the first dielectric layer 10 etched away in the middle and lower portion of the initial trench 11 a. In this way, the trench morphology can be precisely controlled by adjusting the thickness of the second dielectric layer 20 during the formation of the second dielectric layer 20.

[0107] In some embodiments, the initial trench 11a is a deep hole with a large depth-width ratio. In the process of etching and removing the second medium layer 20 and the lower part of the initial trench 11a, the etching rate of the second medium layer 20 is greater than the etching rate of the first medium layer 10 in the lower part of the initial trench 11a. The thickness of the second medium layer 20 is adjusted by controlling the deposition parameters when the second medium layer 20 is formed, so that the thickness of the second medium layer 20 is greater than the thickness of the first medium layer 10 etched and removed in the lower part of the initial trench 11a. In this way, it can be ensured that after the second medium layer 20 is completely removed by the etching liquid, the thickness of the first medium layer 10 etched and removed in the lower part of the initial trench 11a is close to the expected removal thickness, so as to realize accurate control of the morphology of the first trench 11, and make the morphology of the formed first trench 11 meet the expected standard.

[0108] Further, the etching precision of the first medium layer 10 in the lower part of the initial trench 11a can be improved by adjusting the etching liquid, so as to realize accurate control of the morphology of the initial trench 11a.

[0109] In some embodiments, the present disclosure provides a method for manufacturing a semiconductor structure, Figure 10 A flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. The present embodiment is not limited to semiconductor devices, and the following will be described by taking a dynamic random access memory (DRAM) as an example.

[0110] As shown in the figure, the present disclosure provides a method for manufacturing a semiconductor structure, which includes the following steps: Figure 10

[0111] Step S21: providing a substrate, the substrate extends along a horizontal plane.

[0112] Step S22: forming at least one second trench to divide the substrate into a plurality of semiconductor strips, the second trench extends along a first horizontal direction, and the second trench and the semiconductor strips are arranged at intervals along a second horizontal direction.

[0113] Step S23: filling the first medium layer in the second trench.

[0114] Step S24: forming at least one initial trench to divide the semiconductor strips into a plurality of semiconductor pillars, the initial trench extends along the second horizontal direction, and the plurality of semiconductor pillars are arranged along the first horizontal direction and the second horizontal direction.

[0115] Step S25: depositing a second medium layer to cover the sidewall of the upper part of the initial trench, and exposing the first medium layer in the lower part of the initial trench.

[0116] ​Step S26: etching to remove the second dielectric layer and part of the first dielectric layer in the middle and lower part of the initial trench, forming a first trench, the sidewall of the first trench being perpendicular to the substrate, and the first trench being equal in width from top to bottom.

[0117] Figures 10-23 The schematic diagrams of various stages of the method for manufacturing the semiconductor structure of the present exemplary embodiment are shown below in combination with Figures 10-23 and in combination with Figure 24 The method for manufacturing the semiconductor structure of the present exemplary embodiment is introduced below.

[0118] In step S21, referring to Figure 11 , the substrate 40 extends along a horizontal plane, and the substrate 40 can be a semiconductor substrate, the material of which can include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III / V semiconductor material or II / VI semiconductor material. Alternatively, for example, the semiconductor substrate can be a layered substrate including, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator.

[0119] In step S22, referring to Figure 12 , Figure 13 , part of the substrate 40 is etched to form at least one second trench 21, the at least one second trench 21 dividing the substrate 40 into a plurality of semiconductor strips 41 extending along a first horizontal direction D1, and the semiconductor strips 41 and the second trench 21 being arranged in a spaced manner along a second horizontal direction D2 different from the first horizontal direction D1. In the present embodiment, the first horizontal direction D1 and the second horizontal direction D2 are perpendicular to each other.

[0120] In step S23, as shown in Figure 14 , referring to Figure 13 , an atomic layer deposition process or a chemical vapor deposition process can be selected to deposit a first dielectric layer 10 to fill the second trench 21, and the first dielectric layer 10 and the semiconductor strips 41 form a complete three-dimensional structure to facilitate etching the semiconductor strips 41 into semiconductor pillars 42; at the same time, the first dielectric layer 10 is also used for electrical isolation of other devices formed subsequently.

[0121] The material of the first dielectric layer 10 can include at least one of silicon oxide or silicon nitride.

[0122] In step S24, as shown in Figure 15 , Figure 16 , referring to Figure 12 , Figure 14The first dielectric layer 10 and the semiconductor strips 41 are etched using a dry process to form at least one initial trench 11a. The initial trenches 11a extend along the second horizontal direction D2 and are spaced apart along the first horizontal direction D1. The initial trenches 11a are alternately formed along the first horizontal direction D1 in the first dielectric layer 10 and the semiconductor pillars 42. The initial trenches 11a divide the semiconductor strips 41 into semiconductor pillars 42 arrayed along the first horizontal direction D1 and the second horizontal direction D2.

[0123] Reference Figure 16 In the process of dry etching the first dielectric layer 10 and the semiconductor strip 41 to form the initial trench 11a, the etching rate of the first dielectric layer 10 and the semiconductor strip 41 are different, resulting in the initial trench 11a being wide at the top and narrow at the bottom, and even the bottom of the initial trench 11a may be deep and narrow "V"-shaped.

[0124] In step S25, first, Figure 17 As shown, refer to Figure 16 , a sacrificial material layer 31 is formed in the initial groove 11a by a spin coating process, referring to Figure 18 , the sacrificial material layer 31 is etched back to a preset height, and the retained sacrificial material layer 31 is etched to form a sacrificial layer 30 .

[0125] Reference Figure 18 The preset height of the sacrificial layer 30 is determined based on the morphology and critical dimensions of the initial trench 11a and the subsequently formed word line 60 (refer to Figure 23 、 Figure 24 ) definition, the preset height should be higher than the height of the subsequently formed word line 60.

[0126] Illustratively, the material of the sacrificial layer 30 includes spin-on carbon.

[0127] Then, refer to Figure 19 , a second dielectric layer 20 is deposited to cover the top surface of the sacrificial layer 30 and the sidewalls of the initial trench 11 a exposed by the top surface of the sacrificial layer 30 .

[0128] In this embodiment, an atomic layer deposition process is used to form the second dielectric layer 20. Atomic layer deposition can precisely control the thickness of the second dielectric layer 20 so that the thickness of the second dielectric layer 20 is equal to the thickness of the first dielectric layer 10 to be removed in the middle and lower portion of the initial trench 11 a, or the thickness of the second dielectric layer 20 is greater than the thickness of the first dielectric layer 10 to be removed in the middle and lower portion of the initial trench 11 a.

[0129] In this embodiment, the material of the second dielectric layer 20 is the same as that of the first dielectric layer 10 , both being silicon oxide.

[0130] Next, continue to refer to Figure 19, anisotropic etching process is used to etch away the second dielectric layer 20 on the top surface of the sacrificial layer 30, exposing the sacrificial layer 30. Figure 20 The sacrificial layer 30 is etched away to expose the sidewalls of the lower middle portion of the initial trench 11 a , that is, the first dielectric layer 10 and the semiconductor pillar 42 on both sides of the lower middle portion of the initial trench 11 a are exposed.

[0131] For example, the sacrificial layer 30 may be removed by atomic layer etching.

[0132] In step S26, Figure 21 Shown, reference Figure 20 An etchant is injected into the initial trench 11a. The etchant has a high etching rate for the first dielectric layer 10 and the second dielectric layer 20, and a low etching rate for the semiconductor pillar 42. In this embodiment, the etching rate of the etchant for the semiconductor pillar 42 is close to zero to prevent damage to the semiconductor pillar 42 during the process of trimming the profile of the initial trench 11a.

[0133] like Figure 21 As shown, in a plane perpendicular to the second horizontal direction D2, the etching solution etches away the entire second dielectric layer 20 and portions of the first dielectric layer 10 located on both sides of the middle and lower portion of the initial trench 11a, thereby increasing the width of the middle and lower portion of the initial trench 11a and correcting the morphology and profile of the middle and lower portion of the initial trench 11a to form the first trench 11. The sidewall SW of the first trench 11 is perpendicular to the substrate 40, and the upper and lower widths of the first trench 11 are equal. The critical dimension uniformity of the first trench 11 is high, and the bottom wall of the first trench 11 is a flat wall surface without "V"-shaped profile defects.

[0134] In some embodiments, after forming the first trench, the manufacturing method further includes:

[0135] Step S27: forming a plurality of word lines, the word lines extending along the second horizontal direction, each word line intersecting a row of semiconductor pillars arranged along the second horizontal direction and covering part of the sidewalls of the row of semiconductor pillars, and adjacent word lines being separated by the first trench.

[0136] To form a plurality of word lines 60, the following embodiments may be used: Figure 21 、 Figure 22 A third dielectric layer 51 is deposited to cover the walls of the first trench 11. The material of the third dielectric layer 51 is the same as that of the first dielectric layer 10, namely silicon oxide. A first isolation layer 52 is deposited in the first trench 11 to cover and completely fill the third dielectric layer 51. The material of the first isolation layer 52 includes silicon nitride.

[0137] Reference Figure 21 , the first dielectric layer 10 and the third dielectric layer 51 are etched back to a first target height to define the top surface position of the word line 60 to be formed.

[0138] Referring to Figure 22 , a second isolation layer 53 is deposited to cover the exposed first isolation layer 52, and the first isolation layer 52 and the second isolation layer 53 form an isolation portion 50 in the first trench 11, the top portion of the isolation portion 50 has a larger size than the middle and lower portions of the isolation portion 50.

[0139] Referring to Figure 22 , the second isolation layer 53 covering the first dielectric layer 10 is removed by anisotropic etching, and then the first dielectric layer 10 and the third dielectric layer 51 are etched back to a second target height, exposing part of the circumferential surface of the semiconductor pillar 42. Among them, the second target height is used to define the bottom surface position of the word line 60 to be formed, in order to ensure that the isolation portion 50 has good isolation effect, the second target height should be higher than the bottom surface of the isolation portion 50, to avoid the short circuit of the bottom of the subsequently formed word line 60.

[0140] Referring to Figure 23 , Figure 24 , the gate dielectric layer 61 and the word line 60 are formed by self-alignment of the structure of the isolation portion 50 which is wide at the top and narrow at the bottom, the gate dielectric layer 61 covers the exposed circumferential surface of the semiconductor pillar 42, and the word line 60 covers the gate dielectric layer 61 and fills the area between adjacent semiconductor pillars 42. The word line 60 extends along the second horizontal direction D2, and the word line 60 is arranged along the first horizontal direction D1, and the two word lines 60 along the first horizontal direction D1 are separated by the isolation portion 50 and the third dielectric layer 51 in the first trench 11. Each word line 60 intersects with and covers part of the circumferential surface of the plurality of semiconductor pillars 42 arranged along the second horizontal direction D2.

[0141] For example, the in-situ steam generation (ISSG) low-pressure rapid oxidation thermal annealing technology can be used to grow the gate dielectric layer 61 on the surface of the semiconductor pillar 42.

[0142] For example, the atomic layer deposition process or the chemical vapor deposition process can be used to deposit and form the word line 60.

[0143] For example, the material of the gate dielectric layer 61 includes silicon oxide; and the material of the word line 60 includes tungsten.

[0144] The method for manufacturing the semiconductor structure of the embodiment divides the semiconductor strip into semiconductor pillars after forming the initial grooves, forms the second dielectric layer to cover the sidewalls of the upper part of the initial grooves, expose the sidewalls of the middle and lower part of the initial grooves, thicken the thickness of the dielectric layer on both sides of the upper part of the initial grooves, and etch the first dielectric layer and the second dielectric layer together, remove the second dielectric layer and the first dielectric layer exposed in the middle and lower part of the initial grooves, so as to control the morphology and profile of the initial grooves, increase the groove width of the middle and lower part of the initial grooves, and form the first grooves with substantially equal upper and lower groove widths, and the bottom of the first grooves has no "V" type defect.

[0145] The method for manufacturing the semiconductor structure of the embodiment forms the word lines after trimming the morphology and profile of the initial grooves to form the first grooves, avoids the short circuit problem caused by the too close distance between the adjacent word line bottoms due to the "V" type defect of the groove bottom; at the same time, the third dielectric layer and the isolation part are formed in the first grooves to isolate the adjacent word lines, so as to provide good electrical isolation effect for the word lines, further avoid the short circuit of the word lines, and improve the electrical performance of the semiconductor structure.

[0146] It can be understood that the method for manufacturing the semiconductor structure of the disclosure is described by taking DRAM as an example, but the embodiment is not limited thereto, and the semiconductor structure in the embodiment can also be other types of memories, such as static random access memory (SRAM), flash EPROM, ferroelectric random access memory (FRAM), and magnetic random access memory (MRAM).

[0147] According to an exemplary embodiment, the embodiment provides a semiconductor structure, which is manufactured by using the method for manufacturing the semiconductor structure of the above-mentioned embodiments, and the semiconductor structure is shown in Figures 2a-2d , Figure 9 or Figure 21 The semiconductor structure of the embodiment includes the first grooves 11 formed by using the method for manufacturing the semiconductor structure of the above-mentioned embodiments, and at least part of the first grooves 11 is arranged in the first dielectric layer 10.

[0148] In some embodiments, the semiconductor structure is DRAM, but is not limited thereto, and the semiconductor structure in the embodiment can also be other types of memories, such as SRAM, NAND, flash EPROM, FRAM, MRAM, etc.

[0149] In some embodiments, the semiconductor structure is DRAM, but is not limited thereto, and the semiconductor structure in the embodiment can also be other types of memories, such as SRAM, NAND, flash EPROM, FRAM, MRAM, etc. Figures 2a-2d, taking a plane perpendicular to the opening direction of the first trench 11 as a horizontal plane, the sidewall SW of the first trench 11 is perpendicular to the horizontal plane, or the sidewall SW of the first trench 11 is inclined at a first angle relative to the horizontal plane.

[0150] The first angle α1 is greater than or equal to 60°, and the first angle α1 is less than 90°. For example, the first angle α1 can be 60°, 70°, 75°, 80°, 85°, 89°, or other angles.

[0151] It is understandable that the first angle α1 can be flexibly selected to other angles according to process requirements, such as 50° or 100°.

[0152] In some examples, the first groove 11 has the same width at the top and bottom; in other examples, the width of the middle and lower parts of the first groove 11 is greater than the width of the upper part of the first groove 11; in other examples, the width of the middle and lower parts of the first groove 11 is less than the width of the upper part of the first groove 11.

[0153] In some examples, the sidewall SW of the first trench 11 is perpendicular to a horizontal plane, and the width of the lower middle portion of the first trench 11 is greater than the width of the upper portion of the first trench 11 .

[0154] In some examples, the sidewall SW of the first trench 11 is inclined at a first angle α1 relative to a horizontal plane, and the width of the lower middle portion of the first trench 11 is greater than the width of the upper portion of the first trench 11 .

[0155] like Figure 22 、 Figure 23 、 Figure 24 As shown, and refer to Figure 21 The semiconductor structure of this embodiment includes a substrate 40, a plurality of semiconductor pillars 42, and a plurality of word lines 60; the substrate 40 extends along a horizontal plane, wherein a first trench 11 extends on the substrate 40 along a second horizontal direction D2, the sidewalls of the first trench 11 are perpendicular to the substrate 40, and the width of the first trench 11 is the same at the top and bottom; a plurality of semiconductor pillars 42 are arrayed on the substrate 40 along the first horizontal direction D1 and the second horizontal direction D2, and the semiconductor pillars 42 arranged along the first horizontal direction D1 are separated by the first trench 11; the word lines 60 extend along the second horizontal direction D2, and each word line 60 intersects with a row of semiconductor pillars 42 arranged along the second horizontal direction D2 and covers a portion of the sidewall of the row of semiconductor pillars 42, and adjacent word lines 60 are separated by the first trench 11.

[0156] The semiconductor structure of the embodiment has no "V" type defects at the bottom of the first groove 11, the distance between the word lines 60 is uniform, and good electrical isolation effect is provided for the word lines 60, thereby avoiding the short circuit problem caused by the too close distance between the bottom of the adjacent word lines 60, avoiding the problems of device leakage, device power consumption increase, device cannot work normally and the like, and being beneficial to improve the electrical performance and working life of the semiconductor structure.

[0157] According to an exemplary embodiment, the embodiment provides an electronic device including the semiconductor device in the above embodiments. The electronic device can be a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0158] The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features of the above embodiments are not described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present disclosure.

[0159] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method of fabricating a semiconductor structure, comprising: The method comprises: forming an initial trench, at least a part of the initial trench being disposed in a first dielectric layer; depositing a second dielectric layer to cover sidewalls of an upper part of the initial trench, exposing the first dielectric layer of a middle and lower part of the initial trench; etching to remove the second dielectric layer and part of the first dielectric layer of the middle and lower part of the initial trench, forming a first trench.

2. The method of fabricating a semiconductor structure of claim 1, wherein, A plane perpendicular to an opening direction of the first trench is a horizontal plane, a sidewall of the first trench is perpendicular to the horizontal plane, or the sidewall of the first trench is inclined to the horizontal plane at a first angle.

3. The method of fabricating a semiconductor structure of claim 2, wherein, The first angle is greater than or equal to 60°, and the first angle is less than 90°.

4. The method of fabricating a semiconductor structure of claim 1, wherein, Before forming the second dielectric layer, a sacrificial layer is filled in the middle and lower part of the initial trench; After forming the second dielectric layer, the sacrificial layer is removed.

5. The method of fabricating a semiconductor structure of claim 4, wherein, The method for filling the sacrificial layer in the middle and lower part of the initial trench comprises: filling the initial trench with a sacrificial material layer; etching back the sacrificial material layer to a preset height, and etching the remaining sacrificial material layer to form the sacrificial layer.

6. The method of fabricating a semiconductor structure of claim 4, wherein, During formation of the second dielectric layer, the second dielectric layer covers a top surface of the sacrificial layer, and before the sacrificial layer is removed, an anisotropic etching process is used to etch and remove the second dielectric layer on the top surface of the sacrificial layer, exposing the sacrificial layer.

7. The method of fabricating a semiconductor structure of claim 1, wherein, During deposition of the second dielectric layer, deposition parameters are controlled so that a thickness of the second dielectric layer is equal to a thickness of the first dielectric layer to be removed from the middle and lower part of the initial trench, or the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer to be removed from the middle and lower part of the initial trench.

8. The method of fabricating a semiconductor structure according to any one of claims 1-7, wherein, The method comprises: providing a substrate, the substrate extending along a horizontal plane; forming at least one second trench to divide the substrate into a plurality of semiconductor strips, the second trench extending along a first horizontal direction, and the second trench and the semiconductor strips being arranged at intervals along a second horizontal direction; filling a first dielectric layer in the second trench; forming at least one initial trench to divide the semiconductor strips into a plurality of semiconductor pillars, the initial trench extending along the second horizontal direction, and the plurality of semiconductor pillars being arranged along the first horizontal direction and the second horizontal direction; depositing a second dielectric layer to cover sidewalls of an upper part of the initial trench, exposing the first dielectric layer of a middle and lower part of the initial trench; etching to remove the second dielectric layer and part of the first dielectric layer of the middle and lower part of the initial trench, forming a first trench, a sidewall of the first trench being perpendicular to the substrate, and the first trench being equal in width from top to bottom.

9. The method of fabricating a semiconductor structure of claim 8, wherein, After forming the first trench, the method further comprises: forming a plurality of word lines, each of the word lines extending along the second horizontal direction, each of the word lines intersecting a row of the semiconductor pillars arranged along the second horizontal direction, covering part of sidewalls of the row of the semiconductor pillars, and adjacent word lines being separated by the first trench.

10. A semiconductor structure, characterized by The semiconductor structure comprises a first trench, at least a part of the first trench being disposed in a first dielectric layer, and is manufactured by using the method for manufacturing the semiconductor structure according to any one of claims 1-9.

11. The semiconductor structure of claim 10, wherein, A plane perpendicular to a direction of the opening of the first trench is a horizontal plane, a sidewall of the first trench is perpendicular to the horizontal plane, or a sidewall of the first trench is inclined to the horizontal plane by a first angle.

12. The semiconductor structure of claim 11, wherein, The first angle is greater than or equal to 60°, and the first angle is less than 90°.

13. The semiconductor structure of claim 10, wherein, The semiconductor structure further comprises: A substrate extending along a horizontal plane, wherein the first trench extends on the substrate along a second horizontal direction, a sidewall of the first trench is perpendicular to the substrate, and the first trench is equal in width above and below; A plurality of semiconductor pillars arranged in an array on the substrate along a first horizontal direction and the second horizontal direction, the semiconductor pillars arranged along the first horizontal direction being separated by the first trench; A plurality of word lines extending along the second horizontal direction, each of the word lines intersecting a row of the semiconductor pillars arranged along the second horizontal direction and covering a portion of sidewalls of the row of the semiconductor pillars, adjacent word lines being separated by the first trench.

14. An electronic device, comprising: A semiconductor device comprising any one of claims 10 to 13.

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