Etching method of semiconductor structure and semiconductor structure

Abstract

The invention relates to the technical field of semiconductor devices, in particular to an etching method of a semiconductor structure and the semiconductor structure. An etching method of a semiconductor structure comprises the following steps: providing a substrate, and forming a dielectric layer, a hard mask layer and a graphical photoetching structure on the substrate; etching the hard mask layer by taking the patterned photoetching structure as a mask to form a hard mask layer with an initial pattern; removing the patterned photoetching structure by using a photoresist removing process, and forming a hard mask layer with a preset pattern; wherein the hard mask layer with the initial pattern is converted into the hard mask layer with the preset pattern by adjusting the radio frequency power and the pressure of the process chamber in the photoresist removing process. The problem that a current etching process window is small can be solved at least, the process window can be widened, and the angle of the side wall of the hard mask can be increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to an etching method of a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] With the continuous development of semiconductor manufacturing technology, the geometry of semiconductor structures is continuously reduced, and the number of metal layers is continuously increased. This results in an increase in metal wire resistance, parasitic capacitance between metal wires, and parasitic capacitance between metal connection layers, and an increase in signal delay time. The signal transmission delay caused by the back-end interconnection of semiconductor devices limits the improvement of the frequency performance of integrated circuits. The use of metal interconnection such as copper interconnection technology can effectively break through this limitation.

[0003] Damascene structure is widely used in semiconductor structures in the back-end-of-line. Metal damascene integrated etching process is a commonly used technology in the manufacture of copper interconnection layer. Damascene integrated etching process mainly includes trench and via etching. In the back-end-of-line process of logic devices, titanium nitride hard mask is used for trench etching process due to its high etching selectivity and mechanical strength, replacing the traditional silicon nitride or oxide mask. Therefore, using titanium nitride film as a hard mask material in the back-end-of-line can improve the speed of the chip, improve the etching selectivity, and optimize the etching directionality.

[0004] In related technologies, dry etching or wet etching methods can be used to etch the titanium nitride hard mask. The critical dimension obtained after the etching process method is an important factor in determining the size of the etching process window. However, the traditional titanium nitride hard mask etching process can easily cause the hard mask sidewall to be inclined and curved or the bottom to be recessed, resulting in a reduction in line width (critical dimension CD) during pattern transfer to damascene etching, causing insufficient critical dimension deviation, incomplete etching in small line width areas, and abnormal electrical parameters, thereby reducing wafer yield. Therefore, an excellent process method is needed to etch the titanium nitride hard mask to increase the etching process window, improve the pattern transfer accuracy of semiconductor devices, and improve process stability. SUMMARY

[0005] The present application aims to provide an etching method of a semiconductor structure and the semiconductor structure, which can at least alleviate the problem of a small etching process window.

[0006] In a first aspect, an etching method of a semiconductor structure is disclosed, which comprises:

[0007] providing a substrate, forming a dielectric layer, a hard mask layer, and a patterned photoresist structure on the substrate;

[0008] Etching the hard mask layer as the mask to form a hard mask layer with an initial pattern;

[0009] Removing the patterned photoetching structure by a de-gluing process to form a hard mask layer with a preset pattern;

[0010] The RF power and the pressure of the process chamber in the de-gluing process are adjusted to make the hard mask layer with the initial pattern change into the hard mask layer with the preset pattern.

[0011] In some embodiments of the present application, the adjustment of the RF power and the pressure of the process chamber in the de-gluing process includes that the RF power is ≥500W and the pressure of the process chamber is ≤30mT.

[0012] In some embodiments of the present application, the adjustment of the RF power and the pressure of the process chamber in the de-gluing process includes that the RF power is 500W-1200W and the pressure of the process chamber is 5mT-30mT.

[0013] In some embodiments of the present application, the process conditions in the de-gluing process further include that the process gas includes oxygen or a mixture of nitrogen and oxygen; the flow rate of the nitrogen ranges from 0sccm to 300sccm; the flow rate of the oxygen ranges from 100sccm to 200sccm; the bias RF voltage ranges from 20V to 200V; and the process time ranges from 30s to 80s.

[0014] In some embodiments of the present application, the hard mask layer includes a titanium nitride hard mask layer.

[0015] In some embodiments of the present application, the etching of the hard mask layer includes that a first plasma etching process is used to perform main etching on the titanium nitride hard mask layer and a second plasma etching process is used to perform over-etching on the titanium nitride hard mask layer.

[0016] In some embodiments of the present application, the process conditions of the first plasma etching process include that the process gas includes methane and chlorine, the flow rate of the methane ranges from 5sccm to 30sccm, the flow rate of the chlorine ranges from 30sccm to 100sccm, the pressure of the process chamber ranges from 3mT to 15mT, the RF power ranges from 400W to 1000W, and the bias RF voltage ranges from 20V to 100V.

[0017] In some embodiments of the present application, the process conditions of the second plasma etching process include: the process gas includes methane and chlorine, the flow rate of the methane ranges from 3sccm to 25sccm, and the flow rate of the chlorine ranges from 30sccm to 100sccm; the pressure of the process chamber ranges from 3mT to 15mT; the radio frequency power ranges from 400W to 1000W; and the bias radio frequency voltage ranges from 20V to 100V.

[0018] In some embodiments of the present application, the patterned photoetching structure includes a patterned photoresist layer and an anti-reflection coating layer, and an oxidation layer is further arranged between the patterned photoetching structure and the hard mask layer, and the patterned photoresist layer, the anti-reflection coating layer, the oxidation layer and the hard mask layer are sequentially arranged; the etching method includes: taking the patterned photoresist layer as a mask, etching the anti-reflection coating layer to form a patterned anti-reflection coating layer; taking the patterned photoresist layer and the patterned anti-reflection coating layer as masks, etching the oxidation layer to form a patterned oxidation layer, and removing the patterned photoresist layer; taking the patterned anti-reflection coating layer and the patterned oxidation layer as masks, etching the hard mask layer to form a hard mask layer with an initial pattern; and removing the patterned anti-reflection coating layer by using a stripping process, and forming a hard mask layer with a preset pattern.

[0019] In some embodiments of the present application, after the stripping process step, the method further includes: taking the hard mask layer with the preset pattern as a mask, etching the dielectric layer to form a hole structure in the dielectric layer; and filling the hole structure with metal to form a metal interconnection structure.

[0020] In a second aspect, the present application discloses a semiconductor structure, which is prepared by using the etching method of the semiconductor structure as described above; the semiconductor structure includes a substrate and a metal interconnection structure arranged on the substrate.

[0021] The above-mentioned at least one technical solution adopted by the embodiments of the present application can achieve the following beneficial effects:

[0022] The etching method of the present application forms a hard mask layer with an initial pattern after etching the hard mask layer, the sidewall of the hard mask layer with the initial pattern can have a curved morphology, the perpendicularity of the sidewall angle is low, and based on this, the present application adjusts the radio frequency power in the degumming process and the pressure of the process chamber to make the hard mask layer with the initial pattern into the final required hard mask layer with a preset pattern. Therefore, through the optimization of the degumming process, the patterned photoetching structure is removed, and at the same time, the morphology of the hard mask layer is adjusted, the perpendicularity of the sidewall of the hard mask layer is improved, the curved morphology of the sidewall of the hard mask layer is eliminated, and then the critical dimension deviation after damascene etching can be increased, thereby improving the pattern transfer accuracy and process stability of the semiconductor device. In addition, the etching method of the present application is simple, low in cost, remarkable in effect, and good in application effect. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0024] Figure 1 A flowchart of the etching method of the semiconductor structure provided by the embodiment of the present application is shown in the figure.

[0025] Figure 2 A comparison diagram of the morphology of the hard mask layer provided by the traditional hard mask layer and the embodiment of the present application is shown in the figure. Figure 2 (a) is the morphology of the traditional hard mask layer, Figure 2 (b) is the morphology of the hard mask layer of the embodiment of the present application.

[0026] Figure 3 A process diagram of step S100 in the etching method of the semiconductor structure of the present application is shown in the figure.

[0027] Figure 4 A process diagram of step S110 in the etching method of the semiconductor structure of the present application is shown in the figure.

[0028] Figure 5 A process diagram of step S120 in the etching method of the semiconductor structure of the present application is shown in the figure.

[0029] Figure 6 A process diagram of step S130 in the etching method of the semiconductor structure of the present application is shown in the figure.

[0030] Figure 7Process diagram of step S140 in the etching method of the semiconductor structure of the present application;

[0031] Figure 8 Process diagram of step S150 in the etching method of the semiconductor structure of the present application.

[0032] Explanation of reference signs:

[0033] 100 - patterned photoresist layer;

[0034] 200 - antireflection coating;

[0035] 300 - oxidation layer;

[0036] 400 - hard mask layer;

[0037] 500 - dielectric antireflection layer;

[0038] 600 - dielectric layer. DETAILED DESCRIPTION

[0039] The technical solutions of the present application will be described clearly and completely below in combination with the drawings. Obviously, the described embodiments are part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0040] The present application will be described in further detail below through specific examples and in combination with the drawings.

[0041] Titanium nitride hard mask has the characteristics of high etching selectivity and mechanical strength. Using titanium nitride (TiN x ) as a hard mask, it can achieve the effect of obtaining smaller size via and trench, and higher etching uniformity. However, in the process of 28nm and below, the traditional titanium nitride hard mask etching process (such as Figure 2(a) shown) easily cause the hard mask sidewall to be inclined and bent (Bow Profile) or under-cut, resulting in line width (CD) shrinkage when the pattern is transferred to Damascene etching, causing insufficient critical dimension deviation (deviation of trench CD and via CD), incomplete etching in small line width area, and abnormal electrical parameters, resulting in wafer yield reduction and affecting product yield. In order to improve the defect, the related art often uses the method of adjusting the thickness of the mask to optimize the profile or using multi-layer hard mask (double-layer etching process of titanium nitride / tantalum nitride hard mask) to improve the precision, but this method cannot solve the simple profile control problem of a single titanium nitride layer. In addition, the method of adjusting the etching gas to improve the above-mentioned defects has the problem that the improvement effect is not obvious. In addition, the profile optimization by adjusting the thickness of the mask or the improvement of precision by using multi-layer hard mask increases the cost.

[0042] Therefore, the present application discloses an etching method of a semiconductor structure and a semiconductor structure. The etching method of the present application mainly adjusts the parameters of a de-gluing process to optimize the profile of an etching hard mask such as a titanium nitride hard mask (as shown in Figure 2 (b)), so as to improve the perpendicularity of the hard mask sidewall, improve the pattern transfer precision of the semiconductor device, and further improve the yield of the product. The method of the present application can alleviate the problems of the traditional method of adjusting the thickness of the mask to optimize the profile or improving the precision by using multi-layer hard mask, such as the problem of the improvement effect being not obvious or the problem of the cost being high.

[0043] As an optional implementation of the disclosure, the present application discloses an etching method of a semiconductor structure, as shown in Figure 1 The etching method comprises the following steps.

[0044] A substrate is provided, and a dielectric layer 600, a hard mask layer 400 and a patterned photoetching structure are formed on the substrate.

[0045] The hard mask layer 400 is etched to form a hard mask layer 400 with an initial pattern by taking the patterned photoetching structure as a mask.

[0046] The patterned photoetching structure is removed by using a de-gluing process, and the hard mask layer 400 with a preset pattern is formed.

[0047] The radio frequency power in the de-gluing process and the pressure of the process chamber are adjusted to convert the hard mask layer 400 with the initial pattern into the hard mask layer 400 with the preset pattern.

[0048] The etching method of the present application is applicable to Damascene process, and can alleviate the shortcomings of the traditional Damascene first trench process. The profile of the etching hard mask such as the titanium nitride hard mask is optimized by adjusting the parameters in the de-gluing process, so as to widen the process window and improve the line width control ability after Damascene etching.

[0049] It should be noted that in the etching method of the embodiments of the present application, the material of the hard mask layer 400 can be selected from titanium nitride, but is not limited thereto. The process compatibility of the method of the present application is relatively strong, and other hard mask materials with similar requirements are also applicable to the present application. For the sake of brevity, the etching method of the present application will be described in detail below mainly taking titanium nitride hard mask as an example.

[0050] In this paper, the hard mask layer 400 with an initial pattern can be understood as the pattern in the hard mask layer 400, such as the side wall and / or the bottom wall of the hole, may have certain defects, such as side wall inclined bending or bottom concave, etc., which still need to be further improved. The hard mask layer 400 with a preset pattern can be understood as the pattern in the hard mask layer 400 is the target pattern or the required pattern, which improves the defects in the initial pattern and can ensure the subsequent pattern transfer accuracy.

[0051] In the etching method of the embodiments of the present application, the hard mask layer with an initial pattern can be formed after etching the hard mask layer. In the etching process, based on the etching gas being inclined to isotropic etching, for example, Cl free radicals are easy to diffuse along the side wall and cause lateral etching with the hard mask such as titanium nitride hard mask, resulting in the side wall being hollowed out to form an inclined bending morphology. Therefore, the side wall of the hard mask layer with an initial pattern may have an inclined bending morphology, and the perpendicularity of the side wall angle is low, which will affect the subsequent pattern transfer accuracy. Based on this, the embodiments of the present application mainly optimize the morphology of the etched titanium nitride hard mask layer by adjusting the parameters of the degreasing process. Specifically, in the degreasing process, the hard mask layer with an initial pattern is changed into the final required hard mask layer with a preset pattern by adjusting the radio frequency power in the degreasing process and the pressure of the process chamber. Thus, by optimizing the degreasing process, the patterned photoetching structure is removed at the same time, and the morphology of the hard mask layer is also adjusted, the perpendicularity of the side wall of the hard mask layer is improved, the bending morphology of the side wall of the hard mask layer is eliminated, and then the key size deviation after damascene etching can be increased, thereby improving the pattern transfer accuracy and process stability of the semiconductor device. In addition, the etching method of the present application is simple, low in cost, and has remarkable effect, and the application effect is good.

[0052] Reference Figure 2 It can be seen that, Figure 2 (a) shows the morphology schematic diagram of the hard mask layer such as titanium nitride hard mask layer formed by the traditional process, Figure 2 (b) shows the morphology schematic diagram of the hard mask layer such as titanium nitride hard mask layer formed by the embodiments of the present application. Figure 2 In (a), the side wall of the traditional hard mask layer 400 has an inclined bending morphology, and Figure 2 In (b), the embodiments of the present application eliminate the bending morphology of the side wall of the hard mask layer 400 and improve the perpendicularity of the side wall of the hard mask layer 400.

[0053] Therefore, by adjusting the parameters of the adhesive removal process to optimize the morphology of the titanium nitride hard mask, the sidewall angle of the hard mask can be increased from 70°-80° in the traditional process to 85°-90°, which widens the process window, significantly improves the line width control capability, and reduces the dependence on etching selectivity. Moreover, the process has strong compatibility and can be extended to other hard mask materials. That is, the etching method of the present application is not only suitable for titanium nitride hard mask, but also suitable for other hard mask materials with similar requirements. In addition, the method of the present application does not require additional equipment modification, and the cost is significantly reduced.

[0054] In some specific embodiments, as shown in Figures 3-8 The etching method of the semiconductor structure includes the following steps:

[0055] S100, providing a substrate, forming a dielectric layer 600, a hard mask layer 400 and a patterned photoresist structure on the substrate.

[0056] Optionally, the material of the substrate can be silicon, or can also be germanium, silicon germanium, silicon carbide, etc., without special limitation.

[0057] In some embodiments, the dielectric layer 600 includes an interlayer dielectric layer or an intermetallic dielectric layer (or interlayer dielectric layer, ILD). Optionally, the material of the interlayer dielectric layer can be a low dielectric constant material commonly used in the art, in particular, a material with a relative dielectric constant in the range of 1.5-2.5, including but not limited to, for example, silicon oxide or black diamond, etc. Optionally, as an example, a semiconductor device layer formed on the substrate by the previous process can also be provided between the substrate and the dielectric layer 600, without special limitation.

[0058] In some embodiments, the hard mask layer 400 includes but is not limited to a titanium nitride hard mask layer 400. As described above, in the etching method of the embodiments of the present application, the material of the hard mask layer 400 can be a titanium nitride hard mask layer 400, which has a formula TiN x (x can be in the range of 0.3-1.1, for example, x can be 1). Of course, the material of the hard mask layer 400 is not limited to this, for example, other hard mask materials such as tantalum nitride can also be used.

[0059] In some embodiments, the patterned photoresist structure includes a patterned photoresist layer 100 (PR) and an anti-reflective coating layer 200 (BARC), and an oxide layer 300 (Oxide) is further provided between the hard mask layer 400 and the patterned photoresist structure; and the patterned photoresist layer 100, the anti-reflective coating layer 200, the oxide layer 300 and the hard mask layer 400 are sequentially arranged from top to bottom.

[0060] According to different semiconductor structures, the stripping process in the embodiments of the present application can be used to remove different coating layers. For example, when the patterned photoresist layer 100, the hard mask layer 400 and the dielectric layer 600 are sequentially arranged; the stripping process is mainly used to remove the patterned photoresist layer 100. When other coating structures are arranged between the patterned photoresist layer 100 and the hard mask layer 400, for example, when the patterned photoresist layer 100, the anti-reflective coating layer 200, the oxide layer 300 and the hard mask layer 400 are sequentially arranged from top to bottom, the stripping process can also be used to remove the anti-reflective coating layer 200 and other coating structures. The actual semiconductor structure can be adjusted adaptively.

[0061] It should be understood that, in the process of the back-end copper interconnection damascene process, the first trench process using titanium nitride (TiN x ) as the hard mask can achieve the purpose of etching small-size through holes and trenches. Alternatively, in the process of making small-size photoresist, in order to avoid the problem of the size accuracy of the photoresist (PR) being reduced due to the reflection of the bottom film layer to the sidewall of the PR during exposure, a bottom anti-reflective coating layer 200 (BARC) is generally coated before the PR is coated to play a bottom anti-reflective role. In addition, since titanium nitride reacts with PR and BARC and other organic substances used for photoresist pattern formation, a layer of oxide layer 300 (Oxide) is needed to be deposited between the titanium nitride and the BARC for blocking.

[0062] In some embodiments, a dielectric anti-reflective layer 500 (DARC) is further arranged between the hard mask layer 400 and the dielectric layer 600. For example, the dielectric anti-reflective layer 500 can be a nitrogen-free dielectric anti-reflective layer 500 (N-free DARC).

[0063] Reference Figure 3 As shown by way of example, in step S100, a substrate is provided, and the dielectric layer 600, the dielectric anti-reflective layer 500, the hard mask layer 400, the oxide layer 300, the anti-reflective coating layer 200 and the patterned photoresist layer 100 are sequentially formed on the substrate from bottom to top.

[0064] S110, etching the anti-reflective coating layer 200 (BARC etching): referring to Figure 4 As shown, the anti-reflective coating layer 200 is etched to form a patterned anti-reflective coating layer 200 using the patterned photoresist layer 100 as a mask.

[0065] Since the anti-reflective coating layer 200 is arranged below the patterned photoresist layer 100, before etching the hard mask layer 400, the anti-reflective coating layer 200 can be etched in step S110 to facilitate the subsequent etching process.

[0066] In an optional embodiment, in the etching step of the anti-reflective coating 200, the etching gas includes oxygen (O2) and chlorine (Cl2), wherein the flow rate of oxygen can range from 5sccm to 100sccm, for example including 5sccm, 10sccm, 20sccm, 30sccm, 50sccm, 80sccm, 100sccm, etc.; the flow rate of chlorine can range from 50sccm to 200sccm, for example including 50sccm, 80sccm, 100sccm, 150sccm, 200sccm, etc.

[0067] In the etching step of the anti-reflective coating 200, the process recipe preferably includes:

[0068] The chamber pressure of the process chamber can range from 3mT to 15mT (mTorr), for example including 3mT, 5mT, 8mT, 10mT, 15mT, etc. The source RF power can range from 500W to 1000W, for example including 500W, 550W, 600W, 650W, 700W, 800W, 1000W, etc. The bias RF voltage can range from 20V to 150V, for example including 20V, 30V, 50V, 80V, 100V, 150V, etc. In addition, the etching time can range from 10s to 40s, for example including 10s, 20s, 30s, 40s, etc.

[0069] Under this process condition, the etching gas has good etching conditions, so that the etching gas can effectively etch the anti-reflective coating 200.

[0070] S120, etching the oxide layer 300 (Oxide ETCH): referring to Figure 5 As shown, the oxide layer 300 is etched to form a patterned oxide layer 300, and the patterned photoresist layer 100 is removed.

[0071] It should be noted that a part of the patterned photoresist layer 100 will be removed in the process of etching the anti-reflective coating 200, and further, the patterned photoresist layer 100 will be completely removed in the process of etching the oxide layer 300.

[0072] Since the oxide layer 300 is further provided between the anti-reflective coating 200 and the hard mask layer 400, after etching the oxide layer 300, before etching the hard mask layer 400, the oxide layer 300 needs to be etched in step S120, so as to facilitate the subsequent etching process.

[0073] In an optional embodiment, in the etching step of the oxidation layer 300, the etching gas includes trifluoromethane (CHF3), methane (CH4) and helium (He), wherein the flow rate of trifluoromethane can range from 5sccm to 100sccm, for example including 5sccm, 10sccm, 20sccm, 30sccm, 50sccm, 80sccm, 100sccm, etc.; the flow rate of methane can range from 50sccm to 200sccm, for example including 50sccm, 80sccm, 100sccm, 150sccm, 200sccm, etc.; the flow rate of helium can range from 40sccm to 150sccm, for example including 40sccm, 50sccm, 60sccm, 80sccm, 100sccm, 150sccm, etc.

[0074] In the etching step of the oxidation layer 300, the more preferred process recipe includes:

[0075] The chamber pressure of the process chamber can range from 3mT to 15mT, for example including 3mT, 5mT, 8mT, 10mT, 15mT, etc. The source radio frequency power can range from 300W to 800W, for example including 300W, 400W, 500W, 600W, 700W, 800W, etc. The bias radio frequency voltage can range from 20V to 150V, for example including 20V, 30V, 50V, 80V, 100V, 150V, etc. In addition, the etching time can range from 10s to 30s, for example including 10s, 20s, 30s, etc.

[0076] Under the process conditions, the etching gas has good etching conditions, so that the etching gas can effectively etch the oxidation layer 300.

[0077] S130, main etching of the titanium nitride hard mask layer 400 (TiN ME ETCH): referring to Figure 6 As shown, the first plasma etching process is used to perform main etching on the titanium nitride hard mask layer 400, taking the patterned anti-reflective coating and the patterned oxidation layer as masks.

[0078] In the embodiment of the present application, the first plasma etching process is used to perform main etching on the titanium nitride hard mask layer 400, and in this step S130, the process gas can include methane (CH4) and chlorine (Cl2).

[0079] In the step S130, chlorine gas can be used as the main etching gas, and the flow rate of the chlorine gas can range from 30sccm to 100sccm, for example, including 30sccm, 50sccm, 60sccm, 70sccm, 80sccm, 90sccm, 100sccm, etc. The plasma generated by the chlorine gas can react with the main component TiN of the electrode, and finally generate TiCl4 and N2 that can be volatilized and pumped away.

[0080] In the step S130, methane can be used as the etching protection gas, and the flow rate of the methane can range from 5sccm to 30sccm, for example, including 5sccm, 10sccm, 15sccm, 20sccm, 30sccm, etc. Under the action of the plasma, the methane can generate difficult-to-volatilize byproducts with Ti, O and other substances in the process chamber, which can be attached to the hard mask layer sidewall and can play a role in protecting the hard mask layer sidewall. However, the more methane is introduced, the more byproducts are generated, and excessive accumulation of byproducts can cause the titanium nitride hard mask layer to be etched non-perpendicularly after etching, affecting the subsequent metal layer etching and even affecting the electrochemical plating process for filling copper.

[0081] In the step S130, the process recipe preferably includes:

[0082] The chamber pressure of the process chamber can range from 3mT to 15mT, for example, including 3mT, 5mT, 8mT, 10mT, 15mT, etc. The source radio frequency power can range from 400W to 1000W, for example, including 400W, 500W, 600W, 700W, 800W, 1000W, etc. The bias radio frequency voltage can range from 20V to 100V, for example, including 20V, 30V, 50V, 80V, 100V, etc. In addition, the etching time can range from 5s to 30s, for example, including 5s, 10s, 20s, 30s, etc.

[0083] In the step of main etching of the titanium nitride hard mask layer 400, after the main etching of the titanium nitride, most of the area can be etched open, but the overall topography is relatively inclined, especially the footing is greatly inclined; therefore, further etching is required.

[0084] S140, over-etching (TiN OE ETCH) of the titanium nitride hard mask layer 400: referring to FIG. 1, the second plasma etching process is used to over-etch the titanium nitride hard mask layer 400. Figure 7 As shown in the figure, the second plasma etching process is used to over-etch the titanium nitride hard mask layer 400.

[0085] In the embodiment of the present application, the second plasma etching process is used to over-etch the titanium nitride hard mask layer 400, and in the step S140, the process gas can include methane (CH4) and chlorine gas (Cl2).

[0086] Similar to step S130, in step S140, chlorine can be used as the main etching gas, and the flow rate of chlorine can be in the range of 30sccm to 100sccm, for example, including 30sccm, 50sccm, 60sccm, 70sccm, 80sccm, 90sccm, 100sccm, etc. Methane can be used as the etching protection gas, and the flow rate of methane can be in the range of 3sccm to 25sccm, for example, including 3sccm, 5sccm, 10sccm, 15sccm, 20sccm, 25sccm, etc.

[0087] In step S140, the process recipe preferably includes:

[0088] The chamber pressure of the process chamber can be in the range of 3mT to 15mT, for example, including 3mT, 5mT, 8mT, 10mT, 15mT, etc. The source RF power can be in the range of 400W to 1000W, for example, including 400W, 500W, 600W, 700W, 800W, 1000W, etc. The bias RF voltage can be in the range of 20V to 100V, for example, including 20V, 30V, 50V, 80V, 100V, etc. In addition, the etching time can be in the range of 5s to 30s, for example, including 5s, 10s, 20s, 30s, etc.

[0089] In the step of over-etching the titanium nitride hard mask layer 400, after over-etching the titanium nitride, all regions can be completely etched. However, after over-etching, the side wall of the titanium nitride hard mask layer will have a curved morphology. It should be understood that since the etching of titanium nitride often uses halogen-based plasma such as Cl2 / BCl3, this gas tends to isotropic etching, and Cl radicals are easy to diffuse along the side wall and cause lateral etching of titanium nitride, resulting in a side wall inclined and curved morphology. In addition, ions will scatter in the groove, and the ion energy will be significantly weakened in the lower part of the side wall, and cannot achieve effective bombardment; thus, the side wall of the titanium nitride hard mask layer will have a curved morphology.

[0090] S150, a resist stripping process (Asher): refer to Figure 8 As shown, the anti-reflective coating 200 is patterned by the resist stripping process, and the hard mask layer 400 with a preset pattern is formed.

[0091] In the embodiment of the present application, the etching of the titanium nitride hard mask layer 400 is first completed, and the hard mask layer 400 with an initial pattern is formed; then, in the resist stripping process step, the parameters of the resist stripping process are adjusted to optimize the morphology of the titanium nitride hard mask layer 400, such as adjusting the RF power in the resist stripping process and the pressure of the process chamber to convert the hard mask layer 400 with the initial pattern into the hard mask layer 400 with the preset pattern.

[0092] Optionally, the radio frequency power (source radio frequency power) in the de-gluing process step can be ≥ 500 W; as a preferred, the radio frequency power ranges from 500 W to 1200 W, for example, including 500 W, 600 W, 700 W, 800 W, 1000 W, 1200 W, etc.

[0093] In the de-gluing process of the embodiment of the application, by increasing the radio frequency power, the O2 and N2 dissociation efficiency can be improved, the titanium nitride sidewall oxidation repair can be accelerated, and the high-density plasma ensures that the dense protective layer is uniformly generated everywhere on the sidewall.

[0094] Optionally, the pressure of the process chamber in the de-gluing process step is ≤ 30 mT; as a preferred, the pressure of the process chamber ranges from 5 mT to 30 mT, for example, including 5 mT, 8 mT, 10 mT, 15 mT, 20 mT, 25 mT, 30 mT, etc.

[0095] In the de-gluing process of the embodiment of the application, by reducing the pressure of the process chamber, the ion and gas molecule collision probability can be reduced, the molecular mean free path is increased, the ion scattering in the tank is reduced to ensure that sufficient ion bombardment is obtained in the middle and lower parts, and further the sidewall recess is avoided.

[0096] Especially prominent is that, in the de-gluing process, by the combined action of pressure and source radio frequency power, as a key means to repair the curved morphology of the sidewall of the hard mask layer. This is because, on the one hand, in a low-pressure environment, the ion and gas molecule collision probability is reduced, the molecular mean free path is increased, the ion scattering in the tank can be reduced to ensure that sufficient ion bombardment is obtained in the middle and lower parts, so that it mainly performs longitudinal etching to avoid sidewall recess. On the other hand, by increasing the source radio frequency power, the O2 and N2 dissociation efficiency can be improved, the titanium nitride sidewall oxidation repair can be accelerated, and the high-density plasma ensures that the dense TiON protective layer (TiN+N + +O + ->TiON) is uniformly generated everywhere on the sidewall, filling the curved or recessed area of the sidewall.

[0097] In this step S140, the process recipe preferably includes:

[0098] The process gas includes oxygen or a mixture of nitrogen and oxygen; the flow rate of the nitrogen ranges from 0 sccm to 300 sccm, for example, 10 sccm, 50 sccm, 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, etc.; the flow rate of the oxygen ranges from 100 sccm to 200 sccm, for example, 100 sccm, 120 sccm, 150 sccm, 150 sccm, 200 sccm, etc. The bias radio frequency voltage ranges from 20 V to 200 V, for example, 20 V, 30 V, 50 V, 80 V, 100 V, 150 V, 200 V, etc. In addition, the etching time ranges from 30 s to 80 s, for example, 30 s, 40 s, 50 s, 60 s, 80 s, etc.

[0099] Exemplarily, in an embodiment, the process recipe in the step S150 of the stripping process can be as follows:

[0100] Nitrogen gas with a flow rate of 150 sccm and oxygen gas with a flow rate of 100 sccm are introduced, the pressure of the process chamber is controlled at 8 mT, the source radio frequency power is controlled at 1000 W, the bias radio frequency voltage is controlled at 100 V, and the time is controlled at 30 s.

[0101] Exemplarily, in another embodiment, the process recipe in the step S150 of the stripping process can be as follows:

[0102] Nitrogen gas with a flow rate of 150 sccm and oxygen gas with a flow rate of 100 sccm are introduced, the pressure of the process chamber is controlled at 5 mT, the source radio frequency power is controlled at 1200 W, the bias radio frequency voltage is controlled at 100 V, and the time is controlled at 30 s.

[0103] Therefore, under the process recipe of the stripping process described above, compared with the conventional etching process, the embodiment of the present application can increase the sidewall angle of the hard mask layer from 70°-80° in the conventional process to 85°-90°, widen the process window, significantly improve the line width control capability, reduce the dependence on the etching selectivity, and improve the pattern transfer precision.

[0104] S160, etching the dielectric layer 600: taking the hard mask layer 400 with the preset pattern as a mask, the dielectric layer 600 is etched to form a hole structure in the dielectric layer 600; further, the hole structure is filled with metal to form a metal interconnection structure.

[0105] The hole structure described above can include a trench and / or a via. The via and the trench can constitute a damascene structure. The damascene structure is subsequently filled with metal to form an interconnection structure.

[0106] Optionally, the medium layer 600 is selectively etched based on the hard mask layer 400 with the preset pattern to form a via hole penetrating through the medium layer 600.

[0107] Optionally, the material of the metal filling in the hole structure can be any suitable metal material, such as ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), copper (Cu), or the like.

[0108] In the embodiment of the present application, after the stripping step is completed, the hard mask layer 400 with the preset pattern can be formed, and then damascene via hole etching can be performed to transfer the vertical hard mask pattern to the medium layer 600, thereby improving the pattern transfer accuracy and further improving the yield of the product.

[0109] It should be noted that the present application does not make special limitations on the specific process conditions for etching the medium layer, and the operating conditions in the related art can be referred to, which will not be described here.

[0110] Therefore, based on the above steps, especially the parameter optimization of the stripping process step, the morphology optimization of the hard mask layer is realized by adjusting the low-cost parameter pressure and source radio frequency power, without the need to add new equipment, the effect is obviously improved, and the cost is relatively low. The etching method of the present application can significantly improve the line width consistency of damascene etching, and is suitable for more advanced processes such as 7nm / 5nm.

[0111] As another optional implementation of the present application, the present application further discloses a semiconductor structure prepared by the above-mentioned etching method.

[0112] Optionally, the semiconductor structure includes a substrate and a metal interconnection structure disposed on the substrate. Optionally, the metal interconnection structure can be a copper interconnection structure.

[0113] It should be noted that the present application does not make special limitations on the specific form of the metal interconnection structure in the semiconductor structure. As an example, in the semiconductor structure, the interconnection structure includes various conductive components to connect various IC devices to an integrated circuit. For example, the interconnection structure includes contacts, metal lines, and vias. The metal lines are distributed in multiple metal layers. For example, the metal lines can include copper, aluminum-copper alloy, other suitable conductive materials, or combinations thereof. The vias can include copper, aluminum-copper alloy, other suitable conductive materials, or combinations thereof. The contacts can include tungsten, silicide, nickel, cobalt, copper, other suitable conductive materials, or combinations thereof. In some examples, the various conductive components can further include barrier layers such as tantalum and tantalum nitride, titanium and titanium nitride, without limitation.

[0114] In semiconductor structures, ILD layers include one or more dielectric materials to provide isolation functions to various device components, such as gates, and various conductive features, such as metal lines, contacts, and vias. The ILD layers include dielectric materials such as silicon oxide, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. In some examples, the low-k dielectric materials include fluorinated silicon glass, carbon-doped silicon oxide, xerogels, aerogels, amorphous fluorinated carbon, poly-para-xylylene, bis-benzocyclobutene, polyimides, and / or other suitable dielectric materials having a dielectric constant substantially less than that of thermal silicon oxide, etc.

[0115] Finally, it should be noted that the above-described embodiments are merely intended to illustrate the technical solutions of the present application, but not to limit the present application; even though the present application has been described in detail with reference to the above-described embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the above-described embodiments, or equivalently replace some or all of the technical features thereof; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of etching a semiconductor structure, comprising: The etching method comprises: providing a substrate, forming a dielectric layer, a hard mask layer and a patterned photoetching structure on the substrate; using the patterned photoetching structure as a mask to etch the hard mask layer to form a hard mask layer with an initial pattern; using a delamination process to remove the patterned photoetching structure and form a hard mask layer with a preset pattern; wherein the radio frequency power in the delamination process and the pressure of the process chamber are adjusted to make the hard mask layer with the initial pattern into the hard mask layer with the preset pattern.

2. The method of claim 1, wherein The adjustment of the radio frequency power in the delamination process and the pressure of the process chamber comprises: the radio frequency power is ≥500W, and the pressure of the process chamber is ≤30mT.

3. The method of claim 2, wherein the etching is performed by a dry etching method. The adjustment of the radio frequency power in the delamination process and the pressure of the process chamber comprises: the radio frequency power is 500W-1200W, and the pressure of the process chamber is 5mT-30mT.

4. The method of claim 1, wherein the semiconductor structure is a semiconductor-on- insulator structure. The process conditions in the delamination process step further comprise: the process gas comprises oxygen or a mixture of nitrogen and oxygen; wherein the flow rate of the nitrogen ranges from 0sccm to 300sccm, and the flow rate of the oxygen ranges from 100sccm to 200sccm; the bias radio frequency voltage ranges from 20V to 200V; the process time ranges from 30s to 80s.

5. The method of claim 1 to 4, wherein The hard mask layer comprises a titanium nitride hard mask layer.

6. The method of claim 5, wherein the etching of the semiconductor structure is performed by a dry etching process. The etching of the hard mask layer comprises: using a first plasma etching process to perform main etching on the titanium nitride hard mask layer; using a second plasma etching process to perform over-etching on the titanium nitride hard mask layer.

7. The semiconductor structure etching method according to claim 6, characterized in that: The process conditions of the first plasma etching process comprise: the process gas comprises methane and chlorine, the flow rate of the methane ranges from 5sccm to 30sccm, the flow rate of the chlorine ranges from 30sccm to 100sccm, the pressure of the process chamber ranges from 3mT to 15mT, the radio frequency power ranges from 400W to 1000W, and the bias radio frequency voltage ranges from 20V to 100V; and / or, the process conditions of the second plasma etching process comprise: the process gas comprises methane and chlorine, the flow rate of the methane ranges from 3sccm to 25sccm, the flow rate of the chlorine ranges from 30sccm to 100sccm, the pressure of the process chamber ranges from 3mT to 15mT, the radio frequency power ranges from 400W to 1000W, and the bias radio frequency voltage ranges from 20V to 100V.

8. The method of claim 1-4, wherein The patterned photoetching structure comprises a patterned photoresist layer and an anti-reflection coating layer, an oxidation layer is further arranged between the patterned photoetching structure and the hard mask layer, and the patterned photoresist layer, the anti-reflection coating layer, the oxidation layer and the hard mask layer are sequentially arranged; the etching method comprises: using the patterned photoresist layer as a mask to etch the anti-reflection coating layer to form a patterned anti-reflection coating layer; using the patterned photoresist layer and the patterned anti-reflection coating layer as masks to etch the oxidation layer to form a patterned oxidation layer and remove the patterned photoresist layer; Etching the hard mask layer to form a hard mask layer with an initial pattern by taking the patterned anti-reflective coating and the patterned oxidation layer as masks; Removing the patterned anti-reflective coating by a stripping process to form a hard mask layer with a preset pattern.

9. The method of claim 1-4, wherein After the stripping process step, the method further comprises: Etching the dielectric layer to form a hole structure in the dielectric layer by taking the hard mask layer with the preset pattern as a mask; Filling the hole structure with metal to form a metal interconnection structure.

10. A semiconductor structure, characterized by The semiconductor structure is prepared by the etching method of any one of claims 1-9. The semiconductor structure comprises a substrate and a metal interconnection structure arranged on the substrate.

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