Single-column and multi-column tag chip die bonding method and system and readable storage medium
By detecting and correcting the deviation between the material tape and the chip in real time during the chip attachment process, the chip transfer deviation problem caused by wafer disc tilt is solved, the precise placement of the chip is achieved, and the finished product quality and production efficiency of single and multi-row labels are improved.
Patent Information
- Application Number
- CN202511341865.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-19
- Publication Date
- 2025-10-24
- Estimated Expiration
- 2045-09-19
AI Technical Summary
In the prior art, the tilt of the wafer plate causes translational deviation and angular deviation after the chip is transferred from the wafer plate to the patch assembly, affecting the quality of the finished product of single and multi-row labels.
By introducing a real-time detection and deviation correction mechanism for the material strip position and chip position during the chip attachment process, the translation and angle deviation data of the material strip and chip are obtained, and the pulling correction component and rotating arm are used to perform translation and angle correction. Combined with FPGA image processing technology, the glue spraying path is dynamically adjusted to ensure accurate chip placement.
Even when the wafer disc has a certain inclination angle, it can still ensure that the chip is accurately mounted on the preset die-bonding position of the tape, improving the quality of the finished product and production yield, reducing the requirements for wafer disc installation accuracy, and enhancing the system's fault tolerance and process stability.
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Figure CN120834053A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of chip die bonding, and in particular relates to a single multi-column label chip die bonding method and system and a readable storage medium. BACKGROUND
[0002] Chip die bonding refers to a process of mounting a chip on a plastic or ceramic material tape, and the quality of chip die bonding technology directly affects the performance of the chip. The current chip die bonding equipment includes a glue spraying assembly, a chip mounting assembly and a curing assembly arranged in sequence along the movement direction of the material tape, and a needle assembly and a turnover assembly arranged in an up-down distribution above the corresponding chip mounting assembly; the chip is ejected from a wafer disc by the needle assembly, and then transferred to the chip mounting assembly by the turnover assembly, and the chip is attached to a preset die bonding position of the material tape by the chip mounting assembly.
[0003] In the prior art, the glue spraying assembly, the chip mounting assembly, the curing assembly, the needle assembly and the turnover assembly are on the same vertical plane to ensure that the chip can be correctly corresponded with the chip mounting assembly below after being turned over by 180 degrees by the turnover assembly; therefore, the horizontal installation precision of the wafer disc is required to be high, and the wafer disc is not allowed to be inclined; otherwise, the chip will have a large translation deviation and an angle deviation after being transferred from the wafer disc to the chip mounting assembly, and thus the chip cannot be accurately mounted on the preset die bonding position of the material tape, affecting the finished product quality of the single multi-column label.
[0004] It should be noted that the above content is only used to assist in understanding the technical solutions of the present application and does not mean that the above content is prior art. SUMMARY
[0005] The main purpose of the present application is to provide a single multi-column label chip die bonding method, system and readable storage medium, which is suitable for wafer disc with inclination, and can eliminate the translation deviation and angle deviation of the chip after being transferred from the wafer disc to the chip mounting assembly as much as possible, so as to ensure that the chip can be accurately mounted on the preset die bonding position of the material tape and ensure the finished product quality of the single multi-column label.
[0006] To achieve the above purpose, the present application provides a single multi-column label chip die bonding method, which comprises the following steps: the chip is ejected from the wafer disc to the turnover assembly by the needle assembly; wherein the wafer disc performs the ejection operation under the condition that the inclination is ≤±30°; the chip is transferred to the chip mounting assembly by the turnover assembly; the preset die bonding position of the material tape is sprayed by the glue spraying assembly; the chip is attached to the preset die bonding position of the material tape by the chip mounting assembly; performing a curing operation on the die tape and the chip by using a curing assembly; In the step of attaching the chip to the preset die bonding position of the die tape by using the die bonding assembly, the following steps are included: comparing the current die tape position of the die tape with the preset die tape position to obtain first translation deviation data of the die tape; comparing the first current chip position of the chip with the preset chip position to obtain second translation deviation data and angle deviation data of the chip; obtaining third translation deviation data according to the combination of the first translation deviation data and the second translation deviation data, performing translation correction on the die tape according to the third translation deviation data; performing angle correction on the chip according to the angle deviation data.
[0007] In an embodiment, in the step of performing translation correction on the die tape according to the third translation deviation data, the following steps are included: performing translation correction on the die tape by using a die tape correction assembly; In addition, the die tape includes a plurality of columns of preset die bonding positions arranged along the Y-axis direction, and the die tape correction assembly can perform Y-axis direction translation on the die tape to realize die bonding operation of the plurality of columns of label chips.
[0008] In an embodiment, the die bonding assembly includes at least one first rotating arm, the die bonding assembly can drive the first rotating arm to rotate to a first die bonding station, a second die bonding station and a third die bonding station, an end portion of the first rotating arm is provided with a first suction nozzle, the first suction nozzle is used for vacuum adsorbing the chip, and the first suction nozzle can axially rotate relative to the first rotating arm; In the step of attaching the chip to the preset die bonding position of the die tape by using the die bonding assembly, the following steps are included: the first rotating arm rotates to the first die bonding station, and the first rotating arm receives the chip from the turnover assembly; the first rotating arm rotates to the second die bonding station, and the steps of obtaining second translation deviation data and angle deviation data of the chip and the step of performing angle correction on the chip according to the angle deviation data are executed; the first rotating arm rotates to the third die bonding station, and the step of attaching the chip to the preset die bonding position of the die tape by using the die bonding assembly is executed.
[0009] In an embodiment, in the step of performing angle correction on the chip according to the angle deviation data, the following steps are included: Adjusting a rotation angle of the first rotating arm relative to the patch assembly to perform angle correction coarse adjustment on the chip; wherein the angle adjustment range of the first rotating arm is ±25°; Adjusting a rotation angle of the first suction nozzle relative to the first rotating arm to perform angle correction fine adjustment on the chip; wherein the angle adjustment range of the first suction nozzle is ±5°.
[0010] In an embodiment, the step of performing translation correction on the tape based on the third translation deviation data comprises the following steps: The first translation deviation data comprises a first X-axis deviation value and / or a first Y-axis deviation value; The second translation deviation data comprises a second X-axis deviation value and / or a second Y-axis deviation value; Subtracting the first X-axis deviation value from the second X-axis deviation value to obtain the third X-axis deviation value; performing X-axis correction on the tape based on the third X-axis deviation value; And / or, subtracting the first Y-axis deviation value from the second Y-axis deviation value to obtain the third Y-axis deviation value; performing Y-axis correction on the tape based on the third Y-axis deviation value.
[0011] In an embodiment, the step of performing glue spraying on the preset die bonding position of the tape by the glue spraying assembly comprises the following steps: Obtaining glue track coordinates of the glue spraying assembly by a correction camera; wherein the correction camera adopts FPGA image processing technology; Transmitting the glue track coordinates to the glue spraying assembly to dynamically adjust the glue spraying path of the glue spraying assembly.
[0012] In an embodiment, before the step of performing glue spraying on the preset die bonding position of the tape by the glue spraying assembly, the following steps are included: Monitoring the first tape tension of the tape by a first electric eye array; Judging whether the current position of the first tape is within a first preset tension range; if not, dynamically buffering the tape by a first vacuum buffer assembly; In an embodiment, before the step of performing curing operation on the tape and the chip by the curing assembly, the following steps are included: Monitoring the second tape tension of the tape by a second electric eye array; Judging whether the current position of the second tape is within a second preset tension range; if not, dynamically buffering the tape by a second vacuum buffer assembly.
[0013] In an embodiment, the curing assembly comprises an upper thermal head and a lower thermal head; in the step of curing the tape and the chip by using the curing assembly, the step comprises: the upper thermal head is lowered to a vertical height of 1.5-2.5 mm from the chip; the lower thermal head is raised to abut a side of the tape away from the preset die bonding position; the upper thermal head continues to be lowered to contact the chip, so that the upper thermal head and the lower thermal head are combined to cure the tape and the chip by using a bidirectional thermal compression cooperative process; wherein each welding head in the upper thermal head and the lower thermal head is independently temperature-controlled, the temperature difference between the actual temperature value of each welding head and the preset temperature value is less than ±1℃, and the pressure difference between the actual pressure value of each welding head and the preset pressure value is less than or equal to ±0.1N.
[0014] To achieve the above object, the present application provides a single multi-column label chip die bonding correction system, comprising a processor and a memory, the memory stores a computer program, the computer program can be executed by the processor to realize the single multi-column label chip die bonding method according to any one of the above.
[0015] To achieve the above object, the present application provides a readable storage medium, which stores a computer program, the computer program can be read to realize the single multi-column label chip die bonding method according to any one of the above.
[0016] The technical scheme of the present application effectively overcomes the chip transfer deviation problem caused by the installation inclination (inclination ≤±30°) of the wafer disc in the prior art by introducing real-time detection and deviation correction mechanism for the position of the tape and the position of the chip during the chip attaching process. Specifically, by respectively acquiring first translation deviation data of the tape, second translation deviation data of the chip and angle deviation data, and then comprehensively calculating third translation deviation data, the tape is translated and corrected, and the chip is angle-corrected, which significantly improves the precision of the chip attaching position. Even in the case that the wafer disc has a certain inclination and the installation precision is insufficient, the chip can still be accurately attached to the preset die bonding position of the tape, thereby improving the finished product quality and production yield of the single multi-column label, reducing the stringent requirements on the installation precision of the wafer disc, and enhancing the fault tolerance and process stability of the system. BRIEF DESCRIPTION OF DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below only show some of the embodiments of the present application, and all other embodiments obtained by those of ordinary skill in the art without creative effort based on these drawings also belong to the protection scope of the present application.
[0018] Figure 1 A step flow chart of an embodiment of the single multi-column label chip die bonding method provided by the present application; Figure 2 A step flow chart of an embodiment of the single multi-column label chip die bonding method provided by the present application; Figure 3 A structural schematic diagram of an embodiment of the single multi-column label chip die bonding device provided by the present application; Figure 4 A structural schematic diagram of an embodiment of the single multi-column label chip die bonding device provided by the present application; Figure 5 A simplified schematic diagram of an embodiment of the single multi-column label chip die bonding device provided by the present application.
[0019] Explanation of reference signs: 10, glue spraying assembly; 20, patch assembly; 30, thimble assembly; 40, turnover assembly; 50, material strip correction assembly; 100, wafer disc; 200, chip; 300, material strip; The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION
[0020] The technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described only shows some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the protection scope of the present application.
[0021] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement condition, etc. between the components in a certain posture (as shown in the drawings). If the certain posture changes, the directional indications also change accordingly.
[0022] Moreover, it needs to be explained that the description involving "first", "second" and the like in the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the fact that the technical solutions can be realized by those skilled in the art. When the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist and is not within the protection scope required by the present application.
[0023] In the prior art, the glue spraying assembly, the patch assembly, the curing assembly, the pin assembly and the turnover assembly are in the same vertical plane to ensure that the chip can correspond to the patch assembly directly below after the turnover assembly turns the chip by 180 degrees; Therefore, the horizontal installation precision of the wafer disc is high, and the wafer disc is not allowed to be inclined; Otherwise, after the chip is transferred from the wafer disc to the patch assembly, there is a large translation deviation and an angle deviation, which further causes the chip to be unable to be accurately mounted on the preset die bonding position of the tape, and affects the quality of the single and multi-column label.
[0024] In order to solve the above technical problems, the present application provides a single and multi-column label chip die bonding method.
[0025] Please refer to Figures 1 to 5 In an embodiment of the present application, the single and multi-column label chip die bonding method comprises the following steps: Step S10: using the pin assembly 30 to eject the chip from the wafer disc 100 to the turnover assembly 40; wherein the wafer disc 100 performs the ejection operation under the condition that the inclination angle is ≤±30°; Step S20: using the turnover assembly 40 to transfer the chip 200 to the patch assembly 20; Step S30: using the glue spraying assembly 10 to perform glue spraying operation on the preset die bonding position of the tape 300; Step S40: using the patch assembly 20 to attach the chip 200 to the preset die bonding position of the tape 300; Step S50: using the curing assembly (not shown in the figure) to perform curing operation on the tape 300 and the chip 200; In step S40, the following steps are included: Step S41: comparing the current tape position of the tape with the preset tape position to obtain the first translation deviation data of the tape; Step S42: comparing the first current chip position of the chip with the preset chip position to obtain the second translation deviation data and the angle deviation data of the chip; Step S43: obtaining third translation deviation data according to the first translation deviation data and the second translation deviation data in combination, Step S44: performing translation correction on the material belt according to the third translation deviation data; Step S45: performing angle correction on the chip according to the angle deviation data.
[0026] The technical scheme of the present application effectively overcomes the chip transfer deviation problem caused by the installation tilt (inclination ≤±30°) of the wafer disc in the prior art by introducing a real-time detection and deviation correction mechanism for the positions of the material belt and the chip during the chip attaching process. Specifically, by respectively obtaining first translation deviation data of the material belt, second translation deviation data of the chip and angle deviation data, and then comprehensively calculating third translation deviation data, the material belt is corrected in translation and the chip is corrected in angle, which significantly improves the precision of the chip attaching position. Even in the case of a certain inclination of the wafer disc and insufficient installation precision, the chip can still be accurately attached to the preset die bonding position of the material belt, thereby improving the finished product quality and production yield of the single multi-column label, reducing the stringent requirements on the installation precision of the wafer disc, and enhancing the fault tolerance and process stability of the system.
[0027] As a preferred scheme of the above embodiment, in step S44, the following steps are included: performing translation correction on the material belt by using the material belt correction assembly; In this way, the material belt passes through the material belt correction assembly during transportation, and the material belt correction assembly can displace in the X-axis direction and the Y-axis direction. In this way, by displacing the material belt correction assembly in the X-axis direction and the Y-axis direction according to the third translation deviation data, the translation correction of the material belt in the X-axis direction and the Y-axis direction can be realized, and the structure is simple and practical.
[0028] In addition, the material belt includes a plurality of columns of the preset die bonding positions arranged along the Y-axis direction, and the material belt correction assembly can displace the material belt in the Y-axis direction to realize the die bonding operation of the multi-column label chip. In this way, by driving the material belt to displace in the Y-axis direction by the material belt correction assembly, the chip attaching assembly can successfully attach the chip to the plurality of columns of the preset die bonding positions arranged along the Y-axis direction of the material belt, thereby improving the parallel processing capability of the multi-column chip and supporting the die bonding operation of the multi-column label chip.
[0029] As a preferred scheme of the above embodiment, the die bonding assembly comprises at least one first rotating arm, the die bonding assembly can drive the first rotating arm to rotate to a first die bonding station, a second die bonding station and a third die bonding station; an end of the first rotating arm is provided with a first suction nozzle, the first suction nozzle is used for vacuum adsorbing the chip, and the first suction nozzle can rotate axially relative to the first rotating arm; In step S40, the following steps are further included: Step S46: the first rotating arm rotates to the first die bonding station, and the first rotating arm receives the chip from the turnover assembly; Step S47: the first rotating arm rotates to the second die bonding station, and the following steps are performed: acquiring second translation deviation data and angle deviation data of the chip, and performing angle correction on the chip according to the angle deviation data; Step S48: the first rotating arm rotates to the third die bonding station, and the following step is performed: attaching the chip to the preset die bonding position of the tape by the die bonding assembly.
[0030] In this way, by sequentially arranging the first die bonding station, the second die bonding station and the third die bonding station on the die bonding assembly, the chip is driven by the first rotating arm to perform the following steps in the second die bonding station: acquiring second translation deviation data and angle deviation data of the chip, and performing angle correction on the chip according to the angle deviation data; and performing the following step in the third die bonding station: attaching the chip to the preset die bonding position of the tape by the die bonding assembly; thereby ensuring the smooth implementation of the technical scheme of the present application, and the structure is simple and practical.
[0031] In other embodiments, the number of first rotating arms can be arranged as three arms, four arms or more. It can be understood that, as the number of first rotating arms increases, the running speed of the die bonding assembly will also increase, thereby improving the die bonding efficiency of the chip.
[0032] Specifically, in step S45, the following steps are included: Adjust the rotation angle of the first rotating arm relative to the die bonding assembly to coarsely adjust the angle of the chip; wherein the angle adjustment range of the first rotating arm is ±25°; Adjust the rotation angle of the first suction nozzle relative to the first rotating arm to finely adjust the angle of the chip; wherein the angle adjustment range of the first suction nozzle is ±5°.
[0033] In this way, when the chip is angle-corrected, there is a priority strategy; specifically, the rotation angle of the first rotating arm relative to the patch assembly is first adjusted to coarsely correct the angle of the chip; then the rotation angle of the first suction nozzle relative to the first rotating arm is adjusted to finely correct the angle of the chip; by first coarse adjustment and then fine adjustment, the angle correction efficiency of the chip is greatly improved.
[0034] As a preferred solution of the above embodiment, in step S44, the following steps are included: The first translation deviation data includes a first X-axis deviation value and / or a first Y-axis deviation value; The second translation deviation data includes a second X-axis deviation value and / or a second Y-axis deviation value; The first X-axis deviation value is subtracted from the second X-axis deviation value to obtain the third X-axis deviation value; the third X-axis deviation value is used to correct the X-axis of the material tape; The first Y-axis deviation value is subtracted from the second Y-axis deviation value to obtain the third Y-axis deviation value; the third Y-axis deviation value is used to correct the Y-axis of the material tape.
[0035] In this way, the first translation deviation data and the second translation deviation data are refined into X and Y axis components, and the third translation deviation data (third X-axis deviation value and third Y-axis deviation value) is obtained by difference method as the correction basis. This method decouples the calculation of material tape error and chip error, avoiding overcompensation or undercompensation caused by simple superposition.
[0036] Understandably, if the first X-axis deviation value of the material tape is 1mm and the second X-axis deviation value of the chip is 1mm, by subtracting the first X-axis deviation value from the second X-axis deviation value, the third X-axis deviation value is 0mm, which means that the material tape and the chip both have X-axis deviation and their deviation values and directions are the same, so it can be considered that the material tape and the chip have synchronous deviation, so that the total deviation value between them is zero, that is, the X-axis correction of the material tape and the chip is not needed.
[0037] As a preferred solution of the above embodiment, in step S30, the following steps are included: Step S31: obtaining the glue path trajectory coordinates of the glue spraying assembly by a correction camera; wherein the correction camera adopts FPGA image processing technology; Step S32: transmitting the glue path trajectory coordinates to the glue spraying assembly to dynamically adjust the glue spraying path of the glue spraying assembly.
[0038] In this way, when the material belt passes through the glue spraying assembly, the correction camera continuously takes pictures of the material belt to generate glue track coordinates of the glue spraying assembly; the data of the glue track coordinates of the material belt are directly connected to the glue spraying assembly, so that the glue spraying path of the glue spraying assembly is dynamically adjusted. Since the glue track coordinate data is directly transmitted to the glue spraying assembly, the traditional "photographing -> calculation -> compensation" process is cancelled, the what-you-see-is-what-you-get is realized, the incoming material / compensation error is avoided, the visual delay bottleneck is broken, the algorithm compensation link is cancelled, and the positioning accuracy and speed are synchronously improved; according to research, the processing delay is reduced from 20 ms to 100 microseconds, and multiple times of improvement are realized.
[0039] Among them, the FPGA image processing technology is to use FPGA (Field-Programmable Gate Array) to collect, preprocess, analyze or output images. By hard-coding the image algorithm originally run by CPU / GPU into a parallel hardware circuit and running it in FPGA, the effects of microsecond-level delay, parallel pipeline, low power consumption and online upgrade are obtained.
[0040] As a preferred solution of the above embodiment, before step S30, the following steps are included: Step S33: monitoring the first material belt tension of the material belt by the first electric eye array; Step S34: determining whether the first material belt tension is within a first preset tension range; if not, dynamically buffering the material belt by the first vacuum buffer assembly; In this way, the running tension of the material belt is detected by the first electric eye array before the glue spraying operation, and when the running tension of the material belt does not meet the first preset tension range, for example, the material belt is too loose at this time, the material belt is dynamically buffered by the first vacuum buffer assembly.
[0041] As a preferred solution of the above embodiment, before step S50, the following steps are included: Step S51: monitoring the second material belt tension of the material belt by the second electric eye array; Step S52: determining whether the second material belt current position is within a second preset tension range; if not, dynamically buffering the material belt by the second vacuum buffer assembly.
[0042] In this way, the running tension of the material belt is detected by the second electric eye array before the curing operation, and when the running tension of the material belt does not meet the second preset tension range, for example, the material belt is too loose at this time, the material belt is dynamically buffered by the second vacuum buffer assembly.
[0043] The first vacuum buffer assembly and the second vacuum buffer assembly are structurally identical, and can instantaneously absorb or release the material belt under the principle of "no shutdown and no breakage", dynamically compensate the speed difference and tension fluctuation between the front and rear sections, and keep all workstations such as glue spraying, patching and curing in a "position-tension" double closed loop controllable state. Since the vacuum buffer assembly is prior art, the structure thereof will not be described herein.
[0044] As a preferred scheme of the above embodiment, the curing assembly comprises an upper hot head and a lower hot head; in step S50, the following steps are included: Step S53: the upper hot head is lowered to a vertical height of 1.5-2.5 mm away from the chip; Step S54: the lower hot head is raised to abut against a side of the material belt away from the preset die bonding position; Step S55: the upper hot head is continuously lowered to contact the chip, so that the upper hot head and the lower hot head are combined to perform a curing operation on the material belt and the chip by a bidirectional hot pressing cooperative process; In this way, the upper hot head is first lowered to a safe height of 1.5-2.5 mm to avoid direct impact of the high-temperature head on the chip and reduce the risk of chip breakage; then the lower hot head supports the back of the material belt as a support surface during the hot pressing and curing process, so that the chip and the glue layer are uniformly pressed; the bidirectional cooperative pressing of the upper hot head and the lower hot head eliminates the material belt deviation during the hot pressing and curing process, avoiding uneven curing, cavities or warping caused by material belt sagging and other adverse conditions.
[0045] In the upper hot head and the lower hot head, each soldering head is independently temperature-controlled, the temperature difference between the actual temperature value and the preset temperature value of each soldering head is less than ±1℃, and the pressure difference between the actual pressure value and the preset pressure value of each soldering head is less than or equal to ±0.1N. Through the above setting, the processing precision of the curing operation is improved.
[0046] The application further provides a single / multi-column label chip die bonding correction system, which comprises a processor and a memory, and the memory stores a computer program which can be executed by the processor to implement the single / multi-column label chip die bonding method according to any one of the above embodiments. For the specific steps of the single / multi-column label chip die bonding method, reference can be made to the above embodiments. Since the single / multi-column label chip die bonding correction system adopts all the technical schemes of the above embodiments, it at least has all the beneficial effects brought by the technical schemes of the above embodiments, which will not be described herein.
[0047] The application further provides a readable storage medium storing a computer program, which can be read to realize the single / multi-column label chip die bonding method according to any one of the above embodiments. For the specific steps of the single / multi-column label chip die bonding method, refer to the above embodiments. Since the readable storage medium adopts all the technical solutions of the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here.
[0048] It should be noted that other contents of the single / multi-column label chip die bonding method, system and readable storage medium disclosed by the application are prior art, which will not be repeated here.
[0049] The above is only optional embodiments of the application, and does not limit the patent scope of the application. Any direct / indirect application of the application in other related technical fields is included in the patent protection scope of the application.
Claims
1. A single multi-row label chip die bonding method, characterized by, The method comprises the following steps: topping out the chip from a wafer disc to a turnover assembly by using a pin assembly; wherein the wafer disc performs the operation of toppling out under the condition that the angle of inclination is less than or equal to ±30°; transferring the chip to a patch assembly by using the turnover assembly; performing the operation of spraying glue on the preset die bonding position of the tape by using a glue spraying assembly; attaching the chip to the preset die bonding position of the tape by using the patch assembly; performing the operation of curing the tape and the chip by using a curing assembly; in the step of attaching the chip to the preset die bonding position of the tape by using the patch assembly, the method comprises the following steps: comparing the current tape position of the tape with the preset tape position to obtain first translation deviation data of the tape; comparing the first current chip position of the chip with the preset chip position to obtain second translation deviation data and angle deviation data of the chip; combining the first translation deviation data and the second translation deviation data to obtain third translation deviation data; performing translation correction on the tape according to the third translation deviation data; performing angle correction on the chip according to the angle deviation data.
2. The single multi-row tag chip die bonding method according to claim 1, wherein: in the step of performing translation correction on the tape according to the third translation deviation data, the method comprises the following steps: performing translation correction on the tape by using a tape pulling correction assembly; and the tape comprises a plurality of columns of preset die bonding positions arranged along the Y-axis direction, and the tape pulling correction assembly can perform Y-axis direction translation on the tape to realize multi-column label chip die bonding operation.
3. The single multi-row tag chip die bonding method according to claim 1, wherein: the patch assembly comprises at least one first rotating arm, and the patch assembly can drive the first rotating arm to rotate to a first patch station, a second patch station and a third patch station; the end of the first rotating arm is provided with a first suction nozzle, the first suction nozzle is used for vacuum adsorbing the chip, and the first suction nozzle can rotate axially relative to the first rotating arm; in the step of attaching the chip to the preset die bonding position of the tape by using the patch assembly, the method further comprises the following steps: the first rotating arm rotates to the first patch station, and the first rotating arm receives the chip from the turnover assembly; the first rotating arm rotates to the second patch station, and the steps of obtaining the second translation deviation data and the angle deviation data of the chip and the step of performing angle correction on the chip according to the angle deviation data are performed; the first rotating arm rotates to the third patch station, and the step of attaching the chip to the preset die bonding position of the tape by using the patch assembly is performed.
4. The single multi-row tag chip die bonding method according to claim 3, wherein: in the step of performing angle correction on the chip according to the angle deviation data, the method comprises the following steps: adjusting the rotation angle of the first rotating arm relative to the patch assembly to coarsely adjust the angle of the chip; wherein the angle adjustment range of the first rotating arm is ±25°; adjusting the rotation angle of the first suction nozzle relative to the first rotating arm to finely adjust the angle of the chip; wherein the angle adjustment range of the first suction nozzle is ±5°.
5. The single multi-row tag chip die bonding method according to claim 1, wherein: in the step of performing translation correction on the tape according to the third translation deviation data, the method comprises the following steps: The first translation deviation data includes a first X-axis deviation value and / or a first Y-axis deviation value; The second translation deviation data includes a second X-axis deviation value and / or a second Y-axis deviation value; The first X-axis deviation value is subtracted from the second X-axis deviation value to obtain a third X-axis deviation value; and the tape is corrected in the X-axis according to the third X-axis deviation value; And / or, the first Y-axis deviation value is subtracted from the second Y-axis deviation value to obtain a third Y-axis deviation value; and the tape is corrected in the Y-axis according to the third Y-axis deviation value.
6. The single multi-row tag chip die bonding method according to claim 1, wherein: In the step of performing glue spraying on the preset die bonding position of the tape by using the glue spraying assembly, the following steps are included: The glue track coordinates of the glue spraying assembly are obtained by a correction camera; wherein the correction camera adopts FPGA image processing technology; The glue track coordinates are transmitted to the glue spraying assembly to dynamically adjust the glue spraying path of the glue spraying assembly.
7. The single multi-row tag chip die bonding method according to claim 1, wherein: Before the step of performing glue spraying on the preset die bonding position of the tape by using the glue spraying assembly, the following steps are included: The first tape tension of the tape is monitored by using a first electric eye array; It is judged whether the current position of the first tape is within a first preset tension range; if not, the tape is dynamically buffered by using a first vacuum buffer assembly; And / or, before the step of performing curing operation on the tape and the chip by using the curing assembly, the following steps are included: The second tape tension of the tape is monitored by using a second electric eye array; It is judged whether the current position of the second tape is within a second preset tension range; if not, the tape is dynamically buffered by using a second vacuum buffer assembly.
8. The single multi-row tag chip die bonding method according to claim 1, wherein: The curing assembly includes an upper hot press head and a lower hot press head; in the step of performing curing operation on the tape and the chip by using the curing assembly, the following steps are included: The upper hot press head is lowered to a vertical height of 1.5-2.5 mm away from the chip; The lower hot press head is raised to abut against one side of the tape away from the preset die bonding position; The upper hot press head is continuously lowered to contact the chip, so that the upper hot press head and the lower hot press head are combined to perform curing operation on the tape and the chip by using a bidirectional hot pressing cooperative process; Wherein, each soldering head in the upper hot press head and the lower hot press head independently controls temperature, the temperature difference between the actual temperature value and the preset temperature value of each soldering head is less than ±1℃, and the pressure difference between the actual pressure value and the preset pressure value of each soldering head is less than or equal to ±0.1N.
9. A single multi-row label chip die bonding correction system comprising a processor and a memory having stored therein a computer program, wherein, The computer program can be executed by a processor to implement the single / multi-column label chip die bonding method of any one of claims 1-8.
10. A readable storage medium, storing a computer program, characterized in that, The computer program can be read to implement the single / multi-column label chip die bonding method of any one of claims 1-8.
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