Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate; forming a shallow trench in the semiconductor substrate; forming an anti-radiation layer on the bottom and the side wall of the shallow trench, wherein the anti-radiation layer comprises a doped polycrystalline silicon layer; and filling an isolation material in the shallow trench to form a shallow trench isolation structure. According to the semiconductor device and the preparation method thereof provided by the invention, the anti-radiation layer is formed in the shallow trench of the semiconductor substrate, and the anti-radiation layer comprises the doped polycrystalline silicon layer, so that holes in the oxide layer caused by radiation cannot induce electrons on the silicon surface, leakage current is prevented from being generated when the device is in an off state, and the reliability of the device is improved. And the anti-radiation capability of the device is enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] With the development of space technology, more and more semiconductor devices are applied to space environment. When the semiconductor device is irradiated by space radiation, the electrical parameters of the device will change, resulting in the device unable to work normally. In order to ensure the normal work of various semiconductor devices in space, the anti-radiation research has important significance.

[0003] Space radiation contains various particles, such as protons, electrons, heavy ions and other high-energy particles. When these high-energy particles irradiate the semiconductor device, electron-hole pairs are formed in the oxide layer. Part of the electron-hole pairs will recombine, and part of the electron-hole pairs will drift and diffuse. Part of the holes are captured by the oxide layer traps and interface state traps to form oxide layer trap charges and interface state trap charges. These trapped holes will change the electrical parameters of the device. When the device is in a normal off state, induced electrons are generated at the junction of the oxide layer and the active region, resulting in threshold voltage drift and increased leakage current. SUMMARY

[0004] In the summary section, a series of simplified concepts are introduced, which will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to try to limit the key features and necessary technical features of the claimed technical solution, nor to try to determine the protection scope of the claimed technical solution.

[0005] The present application provides a preparation method of a semiconductor device, characterized in that it comprises:

[0006] providing a semiconductor substrate;

[0007] forming a shallow trench in the semiconductor substrate;

[0008] forming an anti-radiation layer at the bottom and sidewall of the shallow trench, the anti-radiation layer comprising a doped polysilicon layer;

[0009] filling an isolation material in the shallow trench to form a shallow trench isolation structure.

[0010] Exemplarily, the anti-radiation layer is directly formed by vapor deposition.

[0011] Exemplarily, a well region is formed in the semiconductor substrate, and the ion doping concentration of the anti-radiation layer is greater than the ion doping concentration of the well region.

[0012] Exemplarily, the doping ions of the anti-radiation layer are of the same type as the doping ions of the well region.

[0013] Exemplarily, before forming the anti-radiation layer on the bottom and sidewall of the shallow trench, the method further comprises a step of forming a liner layer on the bottom and sidewall of the shallow trench.

[0014] Exemplarily, the method further comprises a step of forming a metal wire of the anti-radiation layer, so that the anti-radiation layer is grounded.

[0015] The application further provides a semiconductor device, comprising: a semiconductor substrate, wherein a shallow trench isolation structure is formed in the semiconductor substrate, an anti-radiation layer is formed on the bottom and sidewall of the shallow trench isolation structure, and the anti-radiation layer comprises a doped polysilicon layer.

[0016] Exemplarily, a well region is formed in the semiconductor substrate, and the ion doping concentration of the anti-radiation layer is greater than the ion doping concentration of the well region.

[0017] Exemplarily, the doping ions of the anti-radiation layer are of the same type as the doping ions of the well region.

[0018] Exemplarily, the semiconductor device comprises an NMOS device, and the doping ions of the well region and the anti-radiation layer comprise P-type ions.

[0019] According to the semiconductor device and the preparation method thereof provided by the application, by forming an anti-radiation layer in the shallow trench of the semiconductor substrate, the anti-radiation layer comprising a doped polysilicon layer, the holes in the oxide layer caused by radiation cannot generate electrons on the silicon surface, so that the leakage current of the device in the off state is avoided, and the anti-radiation capability of the device is enhanced. BRIEF DESCRIPTION OF DRAWINGS

[0020] The following drawings of the application are hereby incorporated as part of the application for the purpose of understanding the application. The embodiments of the application and the description thereof shown in the drawings are used to explain the principles of the application.

[0021] In the drawings:

[0022] Figure 1 The flow chart of the preparation method of the semiconductor device according to the embodiment of the application;

[0023] Figures 2A-2D The cross-sectional schematic diagram of the structure obtained by sequentially implementing the preparation method of the semiconductor device according to the embodiment of the application;

[0024] Figure 3A The cross-sectional schematic diagram of the semiconductor device according to the embodiment of the application;

[0025] Figure 3B The top view schematic diagram of the semiconductor device according to the embodiment of the application;

[0026] Figures 4A-4B Band diagram of an anti-radiation layer and well region according to an embodiment of the application. DETAILED DESCRIPTION

[0027] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the application. However, it will be apparent to one skilled in the art that the application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail to the extent that the

[0028] It is to be understood that the application can be implemented in various forms without being limited to the embodiments set forth herein; rather, these embodiments are provided so that the disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art. In the drawings, the size and relative sizes of layers and regions can be exaggerated for clarity. Like reference numerals can be used to denote like elements throughout the specification.

[0029] It will be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0030] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptions used herein interpreted accordingly.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] For a thorough understanding of the present application, reference should be made to the following detailed description, in conjunction with the accompanying drawings, in which:

[0033] Under the action of irradiation, there are oxide layer trap charges and interface state trap charges in SiO2, which causes the surface of Si to induce electrons, affecting the performance of the device, especially for NMOS devices. Since NMOS works when electrons are used as carriers to transmit current, the induced electrons will cause the NMOS device to generate a larger leakage current in the off state, resulting in increased power consumption, signal distortion and other problems.

[0034] In order to improve the anti-radiation capability of the semiconductor device, the present application provides a preparation method of a semiconductor device, as shown in the figure, comprising: Figure 1 As shown in the figure, comprising:

[0035] Step S110: providing a semiconductor substrate;

[0036] Step S120: forming a shallow trench in the semiconductor substrate;

[0037] Step S130: forming an anti-radiation layer on the bottom and sidewalls of the shallow trench, wherein the anti-radiation layer includes a doped polysilicon layer;

[0038] Step S140: filling the shallow trench with an isolation material to form a shallow trench isolation structure.

[0039] According to the semiconductor device and preparation method provided by the present invention, an anti-radiation layer is formed in a shallow trench of a semiconductor substrate, and the anti-radiation layer includes a doped polysilicon layer, so that holes in the oxide layer caused by radiation cannot induce electrons on the silicon surface, thereby avoiding leakage current in the device when it is in the off state and enhancing the device's anti-radiation capability.

[0040] In order to fully understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0041] Below, reference Figures 2A to 2D The method for preparing the semiconductor device of the present invention is described in detail, wherein: Figures 2A to 2D The cross-sectional view of the semiconductor device obtained by sequentially implementing the method for preparing the semiconductor device according to the embodiment of the present invention is shown.

[0042] Illustratively, the method for preparing a semiconductor device of the present invention comprises the following steps:

[0043] First, execute step S110 to obtain Figure 2A A semiconductor substrate 200 is provided. Further, a well region 201 is formed in the semiconductor substrate 200.

[0044] The semiconductor substrate 200 can be any suitable semiconductor substrate, such as a silicon substrate. It can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including a multilayer structure composed of these semiconductor materials, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc.

[0045] The semiconductor substrate 200 is formed with a well region 201. Taking the semiconductor device as an example of an NMOS device, the semiconductor substrate 200 is selected as an N-type substrate, specifically, a commonly used N-type substrate in the art can be selected, then a P-well is formed in the N-type substrate, in an embodiment of the present application, a P-well window is first formed on the N-type substrate, ion implantation is performed in the P-well window, and then an annealing step is performed to form the P-well.

[0046] Next, step S120 is performed to obtain a structure as shown in FIG. 2B. A shallow trench 202 is formed in the semiconductor substrate 200. Figure 2B

[0047] Exemplarily, forming the shallow trench 202 in the semiconductor substrate 200 includes forming a patterned hard mask layer (not shown) on the surface of the semiconductor substrate 200, and etching the semiconductor substrate 200 to form the shallow trench 202 in the semiconductor substrate 200 with the hard mask layer as a mask.

[0048] In one embodiment, the hard mask layer includes but is not limited to a silicon oxide layer, a silicon nitride layer, or an ONO structure (i.e., a stacked structure of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer). The hard mask layer can be formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, etc., then a patterned photoresist layer is formed on the hard mask layer, the hard mask layer is etched to form a patterned hard mask layer with the photoresist layer as a mask. Next, the semiconductor substrate 200 is etched to form the shallow trench 202 in the semiconductor substrate 200 with the patterned hard mask layer as a mask, and the bottom of the shallow trench 202 is located in the semiconductor substrate 200. Next, the photoresist layer and the hard mask layer are removed.

[0049] Next, step S130 is performed to obtain a structure as shown in FIG. 2C. A radiation-resistant layer 204 is formed on the bottom and sidewall of the shallow trench 202, and the radiation-resistant layer 204 includes a doped polysilicon layer. Figure 2C

[0050] Exemplarily, before forming the radiation-resistant layer 204 on the bottom and sidewall of the shallow trench 202, a step of forming a liner layer 203 on the bottom and sidewall of the shallow trench 202 is further included.

[0051] In one embodiment, the material of the liner layer 203 includes but is not limited to silicon oxide, and the thickness of the liner layer 203 is less than 10 nm. The liner layer 203 can be formed by a physical vapor deposition process or a chemical vapor deposition process, etc., which is not limited in the present application.

[0052] ​​In one embodiment, the radiation-resistant layer 204 is an ion-doped polysilicon (Poly) layer. The doping ions in the radiation-resistant layer 204 are of the same type as the doping ions in the well region 201, and the ion doping concentration in the radiation-resistant layer 204 is greater than the ion doping concentration in the well region 201. Taking an NMOS device as an example, the doping ions in the radiation-resistant layer 204 and the doping ions in the well region 201 are both P-type ions, including but not limited to boron (B) ions.

[0053] In one embodiment, the anti-radiation layer 204 is directly formed by vapor deposition. Specifically, the anti-radiation layer 204 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In the present invention, chemical vapor deposition (CVD) methods are preferred, such as low-temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), and plasma-enhanced chemical vapor deposition (PECVD).

[0054] In one embodiment, the process conditions for directly forming the radiation-resistant layer 204 by vapor deposition include: the silicon source adopts silane (SiH4) or the like, the boron source adopts diborane or the like, the flow rate of the silicon source gas is 5 sccm to 1000 sccm, the flow rate of the boron source gas is 1 sccm to 50 sccm, the temperature range in the reaction chamber can be 400°C to 600°C, and the pressure in the reaction chamber can be 0 mTorr to 400 mTorr; the reaction gas can also include a buffer gas, and the buffer gas can be helium or nitrogen, and the flow rate range of the helium and nitrogen can be 0.5 slm to 15 slm.

[0055] According to the semiconductor device fabrication method provided by the present invention, the radiation-resistant layer 204 is directly formed by vapor deposition. Compared with P-type doping via ion implantation, this involves fewer thermal processes, thus ensuring that the semiconductor device has excellent radiation resistance. If the semiconductor device fabrication process involves more thermal processes, this can lead to diffusion of the dopant ions. As the ion doping concentration decreases, the device's radiation resistance decreases, or even fails.

[0056] In one embodiment, when the semiconductor device is not powered, Figure 4A As shown, since the ion doping concentration of the anti-irradiation layer 204 is greater than the ion doping concentration of the well region 201, the distance between the Fermi level (Ef) of the anti-irradiation layer 204 and the valence band (Ev) is smaller than the distance between the Fermi level (Ef) and the valence band (Ev) of the well region 201, that is, the Fermi level of the anti-irradiation layer 204 is closer to the valence band than the Fermi level of the well region 201. When the semiconductor device is powered on, as shown in FIG. Figure 4BAs shown, the Fermi level of the anti-radiation layer 204 and the Fermi level of the well region 201 reach a thermal equilibrium state, and electrons flow from the well region 201 to the anti-radiation layer 204, and the Fermi levels of the two are on the same straight line. The Fermi level of the surface of the well region 201 is lowered, and is closer to the valence band, and the surface of the well region 201 is more difficult to be inverted, which effectively increases the difficulty of the electrons generated on the surface of the well region 201 under irradiation, thereby avoiding the generation of leakage current of the NMOS device under irradiation.

[0057] Next, the anti-radiation material on the semiconductor substrate 200 is removed. Specifically, the anti-radiation material on the surface of the semiconductor substrate 200 is etched and removed. The dry etching process includes but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods, and a single etching method can be used, or more than one etching method can be used.

[0058] Next, step S140 is performed to obtain a structure as shown in Figure 2D The isolation material is filled in the shallow trench 202 to form a shallow trench isolation structure 205 in Figure 2D without the identification of 205 in the middle, which is suggested to be added.

[0059] In one embodiment, the isolation material can be an oxide, such as SiO2. As an example, a silicon oxide layer is formed in the shallow trench 202 and on the semiconductor substrate 200 by HDP-CVD (high density plasma chemical vapor deposition), which is a process that simultaneously performs deposition and sputtering reaction in the same reaction chamber. The reaction gases used in the HDP-CVD process include SiH4 and O2, and the sputtering gases include hydrogen and helium. Since the deposition and sputtering processes are performed simultaneously, the sputtering deposition ratio is adjusted to be 1:1 by adjusting the contents of SiH4 and O2 and the hydrogen and helium.

[0060] Next, the isolation material on the semiconductor substrate 200 is planarized to make the surface of the isolation material layer flush with the surface of the semiconductor substrate 200, and the planarization method can be chemical mechanical polishing (CMP). In addition, the hard mask layer formed in step S120 and the anti-radiation material on the semiconductor substrate 200 formed in step S130 can also be removed by this planarization step, which is not limited in the present application.

[0061] In addition, a step of forming a metal wire (not shown) of the anti-radiation layer 204 is also included to make the anti-radiation layer 204 grounded (i.e., the potential is zero).

[0062] So far, the key steps of the method for preparing the semiconductor device of the present application have been introduced, and other processes can be required for the complete device preparation, which will not be described here.

[0063] It is worth mentioning that the order of the above steps is only an example. Under the premise of no conflict, the order of the above steps can also be swapped or performed alternately.

[0064] The present invention also provides a semiconductor device, such as Figure 3A and 3B As shown, it includes a semiconductor substrate 200, in which a shallow trench isolation structure 205 is formed. An anti-radiation layer 204 is formed on the bottom and sidewalls of the shallow trench isolation structure 205, and the anti-radiation layer 204 includes a doped polysilicon layer.

[0065] The semiconductor substrate 200 can be any suitable semiconductor substrate, such as a silicon substrate. It can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including a multilayer structure composed of these semiconductor materials, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc.

[0066] In one embodiment, a well region 201 is formed in the semiconductor substrate 200. Taking the semiconductor device as an NMOS device as an example, the semiconductor substrate 200 is an N-type substrate, and a P-well is formed in the N-type substrate.

[0067] In one embodiment, a liner layer 203 is further formed in the semiconductor substrate 200, and the thickness of the liner layer 203 is less than Specifically, a liner layer 203 is disposed between the semiconductor substrate 200 and the anti-radiation layer 204. The material of the liner layer 203 includes, but is not limited to, silicon oxide.

[0068] In one embodiment, the radiation-resistant layer 204 is disposed between the liner layer 203 and the shallow trench isolation structure 205. The radiation-resistant layer 204 is an ion-doped polysilicon (Poly) layer. The doping ions in the radiation-resistant layer 204 are of the same type as the doping ions in the well region 201, and the ion doping concentration in the radiation-resistant layer 204 is greater than the ion doping concentration in the well region 201. Taking an NMOS device as an example, the doping ions in the radiation-resistant layer 204 and the doping ions in the well region 201 are both P-type ions, including but not limited to boron (B) ions.

[0069] In one embodiment, when the semiconductor device is not powered,Figure 4A As shown, because the ion doping concentration of the anti-radiation layer 204 is greater than that of the well region 201, the distance between the Fermi level (Ef) and the valence band (Ev) of the anti-radiation layer 204 is less than that of the well region 201, i.e., the Fermi level of the anti-radiation layer 204 is closer to the valence band than that of the well region 201. When the semiconductor device is powered on, as shown, Figure 4B As shown, the Fermi level of the anti-radiation layer 204 and the Fermi level of the well region 201 reach a thermal equilibrium state, and electrons flow from the well region 201 to the anti-radiation layer 204, and the Fermi levels of the two are on the same straight line. The Fermi level of the surface of the well region 201 is lowered and is closer to the valence band, and the well region 201 surface is more difficult to be inverted, which effectively increases the difficulty of the well region 201 surface to generate electrons under irradiation, and avoids the generation of leakage current of the NMOS device under irradiation.

[0070] According to the semiconductor device and the preparation method thereof provided by the present application, by forming an anti-radiation layer in the shallow trench of the semiconductor substrate, the anti-radiation layer comprises a doped polysilicon layer, so that the holes in the oxide layer caused by irradiation cannot generate electrons on the silicon surface, avoiding the generation of leakage current of the device in the off state, and enhancing the anti-radiation capability of the device.

[0071] The present application has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of example and illustration, and are not intended to limit the present application to the scope of the described embodiments. In addition, those skilled in the art can understand that the present application is not limited to the above-mentioned embodiments, and more kinds of variations and modifications can be made according to the teachings of the present application, which all fall within the scope of the present application claimed. The protection scope of the present application is defined by the attached claims and their equivalent scope.

Claims

1. A method of manufacturing a semiconductor device, characterized by, Comprising: providing a semiconductor substrate; forming a shallow trench in the semiconductor substrate; forming an anti-radiation layer on the bottom and sidewall of the shallow trench, the anti-radiation layer comprising a doped polysilicon layer; filling an isolation material in the shallow trench to form a shallow trench isolation structure.

2. The production method according to claim 1, wherein The anti-radiation layer is formed directly by vapor deposition.

3. The production method according to claim 1, wherein The semiconductor substrate has a well region formed therein, the ion doping concentration of the anti-radiation layer is greater than the ion doping concentration of the well region.

4. The production method according to claim 3, wherein The doping ion of the anti-radiation layer is the same type as the doping ion of the well region.

5. The production method according to claim 1, wherein Before forming the anti-radiation layer on the bottom and sidewall of the shallow trench, the method further comprises the step of forming a liner layer on the bottom and sidewall of the shallow trench.

6. The production method according to claim 1, wherein The method further comprises the step of forming a metal wire of the anti-radiation layer to ground the anti-radiation layer.

7. A semiconductor device, characterized by Comprising: a semiconductor substrate having a shallow trench isolation structure formed therein, the anti-radiation layer formed on the bottom and sidewall of the shallow trench isolation structure, the anti-radiation layer comprising a doped polysilicon layer.

8. The semiconductor device of claim 7, wherein, The semiconductor substrate has a well region formed therein, the ion doping concentration of the anti-radiation layer is greater than the ion doping concentration of the well region.

9. The semiconductor device of claim 8, wherein, The doping ion of the anti-radiation layer is the same type as the doping ion of the well region.

10. The semiconductor device of claim 9, wherein, The semiconductor device comprises an NMOS device, the doping ion of the well region and the doping ion of the anti-radiation layer comprise P-type ions.

Images