Adapter plate and forming method thereof

Abstract

The invention provides an adapter plate and a forming method thereof, the adapter plate comprises a substrate, an active device is formed in the substrate, the substrate comprises a first surface and a second surface, and a TSV structure penetrating through the substrate is also formed in the substrate; the first dielectric layer is located on the first surface of the substrate, and a plurality of first metal connecting structures electrically connected with the TSV structure and the active device respectively are formed in the first dielectric layer; the oxide layer is located on the second surface of the substrate, and a plurality of flat plate type capacitor structures are formed on the surface of the oxide layer; and the third dielectric layer is located on the surface of the oxide layer and covers the oxide layer and the flat plate type capacitor structure, and a plurality of second metal connecting structures electrically connected with the TSV structure and the flat plate type capacitor structure respectively are formed in the third dielectric layer. According to the technical scheme provided by the invention, part of elements with relatively large nodes or relatively large influence of a mixing process are put into the adapter plate, so that a good processing yield is realized while the integration level of a module device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to an interposer and a forming method thereof. BACKGROUND

[0002] The current Moore's law is slowing down, and 2.5D packaging is an in-die stacking technology that can expand various complex chips, allowing the industry to take a new approach to providing large-scale complex chip integration faster than Moore's law, while reducing power consumption and cost. To solve the problem of insufficient wiring density of organic substrates, silicon substrates with TSV (Through Silicon Via) vertical interconnection holes and high-density metal wiring have emerged. The silicon-based passive platform with TSV is called a TSV interposer. The packaging structure using the TSV interposer is called a 2.5D interposer.

[0003] With smaller device core sizes and increased device densities, the drive strength per unit area in the device increases, meaning higher current density and greater current transients. This results in chips becoming more sensitive to power supply voltage fluctuations, and circuits require decoupling capacitors as a basic tool to reduce PDN (power delivery network) impedance. By suppressing noise through decoupling or bypassing a portion of the circuit or interconnection, it is necessary to control parasitic resistance and inductance, and decoupling capacitors must be physically close to the required circuit, so a large number of DTC capacitors must be integrated in the 2.5D interposer.

[0004] The main application scenario of the current 2.5D interposer is the HPC and AI fields, and the characteristics of high speed and high performance require chips to be more sensitive to power supply voltage fluctuations. Capacitive decoupling is the main method to solve the problem of power supply noise. This method is very effective in improving the response speed of transient current and reducing the impedance of the power distribution system. Compared with traditional ceramic capacitors, DTC has better integration characteristics, and the design is closer to the required circuit, which is more conducive to improving the power integrity of the system. For the same link, the CoWoS system integrated with DTC can significantly reduce the PDN impedance by 93% compared to the system without DTC in the high frequency part; and for the same link, the time domain simulation shows that the system integrated with DTC has a 72% improvement in voltage drop performance compared to the system without DTC.

[0005] The current common technology uses a board containing DTC+TSV structure, and under the requirements of product speed, function and volume, multiple wafers (SOC, HBM) and a small number of passive components are packaged on the board to integrate into a multi-wafer module component. The SoC system wafer is a product of the advanced version, that is, all functions are integrated on a single wafer. In short, it integrates logic, storage, radio frequency and power supply and other different functions on one wafer. The advantage of SoC is that higher performance can be achieved with lower power consumption; the disadvantage is that because many functions are integrated in the same wafer, a larger wafer is formed, the preparation process is complex, and different functional circuits require different processes, so it is not possible to make each circuit function the best. In addition, there are interference and isolation problems, and if a function needs to be upgraded in the future, it cannot be improved separately, so a high cost is required. In addition, the board uses independent wafer processing, and the volume of DTC+TSV (area ratio less than 30%) and circuit used in the final silicon body is limited, resulting in a large waste of space, and the preparation cost is also high.

[0006] Therefore, it is necessary to provide a more effective and reliable technical solution to separate logic, storage, radio frequency, analog and power devices, and place some components with larger nodes or greater impact of mixed processes into the adapter board, and fully utilize the mature process compatible process method for preparation, while improving the integration of the module device, and realizing good processing yield. SUMMARY

[0007] The present application provides an adapter board and a forming method thereof, which can separate logic, storage, radio frequency, analog and power devices, and place some components with larger nodes or greater impact of mixed processes into the adapter board, and fully utilize the mature process compatible process method for preparation, while improving the integration of the module device, and realizing good processing yield.

[0008] One aspect of the present application provides a forming method of an adapter board, comprising: providing a substrate, the substrate having an active device formed therein, the substrate comprising a first surface and a second surface; forming a TSV structure extending into the substrate on the first surface of the substrate; forming a first dielectric layer on the first surface of the substrate, the first dielectric layer having a plurality of first metal connection structures formed therein, each of the first metal connection structures electrically connecting the TSV structure and the active device; forming an oxide layer on the second surface of the substrate; forming a plurality of plate capacitors on the surface of the oxide layer; forming a third dielectric layer covering the oxide layer and the plate capacitors on the surface of the oxide layer, the third dielectric layer having a plurality of second metal connection structures formed therein, each of the second metal connection structures electrically connecting the TSV structure and the plate capacitors.

[0009] In some embodiments of the present application, the substrate includes a semiconductor substrate and an interlayer dielectric layer on a surface of the semiconductor substrate, the surface of the interlayer dielectric layer being a first surface of the substrate, the active device being in the semiconductor substrate and the interlayer dielectric layer, and a contact structure electrically connecting the active device being formed in the interlayer dielectric layer, the first metal connection structure electrically connecting the contact structure.

[0010] In some embodiments of the present application, a resistor is formed in the first dielectric layer, and part of the first metal connection structure electrically connects the resistor.

[0011] In some embodiments of the present application, the method for forming the adapter further includes: forming a second dielectric layer on the surface of the first dielectric layer, a plurality of first metal pads electrically connecting the plurality of first metal connection structures being formed in the second dielectric layer; forming a first passivation layer on the surface of the first metal pad; forming a solder ball penetrating the first passivation layer and electrically connecting the first metal pad on the surface of the first passivation layer; forming a bonding dielectric layer covering the second dielectric layer, the first passivation layer and the solder ball on the surface of the bonding dielectric layer; and forming a carrier wafer on the surface of the bonding dielectric layer.

[0012] In some embodiments of the present application, before forming the oxide layer on the second surface of the substrate, the method further includes: thinning the second surface of the substrate to expose the TSV structure.

[0013] In some embodiments of the present application, the method for forming the semiconductor structure further includes: forming a fourth dielectric layer on the surface of the third dielectric layer, a plurality of second metal pads electrically connecting the plurality of second metal connection structures being formed in the fourth dielectric layer; and forming a second passivation layer on the surface of the second metal pad, the second passivation layer exposing part of the second metal pad.

[0014] Another aspect of the present application also provides an adapter, including: a substrate, an active device being formed in the substrate, the substrate including a first surface and a second surface, and a TSV structure penetrating the substrate being formed in the substrate; a first dielectric layer on the first surface of the substrate, a plurality of first metal connection structures electrically connecting the TSV structure and the active device respectively being formed in the first dielectric layer; an oxide layer on the second surface of the substrate, a plurality of plate capacitor structures being formed on the surface of the oxide layer; and a third dielectric layer on the surface of the oxide layer covering the oxide layer and the plate capacitor structures, a plurality of second metal connection structures electrically connecting the TSV structure and the plate capacitor structures respectively being formed in the third dielectric layer.

[0015] In some embodiments of the present application, the substrate comprises a semiconductor substrate and an interlayer dielectric layer on the surface of the semiconductor substrate, the surface of the interlayer dielectric layer is the first surface of the substrate, the active device is in the semiconductor substrate and the interlayer dielectric layer, a contact structure electrically connected to the active device is also formed in the interlayer dielectric layer, and the first metal connection structure is electrically connected to the contact structure.

[0016] In some embodiments of the present application, a resistor is also formed in the first dielectric layer, and part of the first metal connection structure is electrically connected to the resistor.

[0017] In some embodiments of the present application, the adapter board further comprises: a second dielectric layer on the surface of the first dielectric layer, a plurality of first metal pads electrically connected to the plurality of first metal connection structures are formed in the second dielectric layer; a first passivation layer on the surface of the first metal pad; a solder ball on the surface of the first passivation layer penetrating through the first passivation layer to electrically connect the first metal pad; a bonding dielectric layer on the surface of the second dielectric layer covering the second dielectric layer, the first passivation layer and the solder ball; and a carrier wafer on the surface of the bonding dielectric layer.

[0018] In some embodiments of the present application, the adapter board further comprises: a fourth dielectric layer on the surface of the third dielectric layer, a plurality of second metal pads electrically connected to the plurality of second metal connection structures are formed in the fourth dielectric layer; and a second passivation layer on the surface of the second metal pad to expose part of the second metal pad.

[0019] The present application provides an adapter board and a forming method thereof, which can separate logic, storage, radio frequency, analog and power devices, put some elements with larger nodes or larger mixed process influence into the adapter board, and fully utilize the mature process compatible process method for preparation, so as to improve the integration of module devices and realize good processing yield. BRIEF DESCRIPTION OF DRAWINGS

[0020] The following drawings describe the exemplary embodiments disclosed in the present application in detail. The same reference signs in the drawings represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application, and other ways of embodiments can also achieve the same purpose of the invention in the present application. It should be understood that the drawings are not drawn to scale.

[0021] Wherein:

[0022] Figures 1 to 14 The structure schematic diagram of each step in the forming method of the adapter board described in the embodiments of the present application. DETAILED DESCRIPTION

[0023] The following description provides specific applications and requirements of the present application, which is to enable a person skilled in the art to manufacture and use the contents of the present application. Various local modifications of the disclosed embodiments are obvious to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but is consistent with the widest scope of the claims.

[0024] The technical solutions of the present application will be described in detail below in combination with embodiments and drawings.

[0025] Figures 1 to 14 The structure schematic diagram of each step in the forming method of the adapter plate described in the embodiments of the present application. The forming method of the adapter plate described in the embodiments of the present application will be described in detail below in combination with the drawings.

[0026] Reference Figure 1 As shown, a substrate 100 is provided, in which an active device 103 is formed, the substrate 100 comprising a first surface 10 and a second surface 20 opposite to each other.

[0027] In some embodiments of the present application, the substrate 100 comprises a semiconductor substrate 101 and an interlayer dielectric layer 102 on the surface of the semiconductor substrate 101, the surface of the interlayer dielectric layer 102 being the first surface 10 of the substrate 100, the active device 103 being located in the semiconductor substrate 101 and the interlayer dielectric layer 102, and a contact structure 104 electrically connecting the active device 103 being further formed in the interlayer dielectric layer 102.

[0028] In some embodiments of the present application, the material of the semiconductor substrate 101 comprises (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or indium gallium phosphide, etc.; or (iv) a combination of the above.

[0029] In some embodiments of the present application, the material of the interlayer dielectric layer 102 comprises silicon oxide.

[0030] In some embodiments of the present application, the active device 103 comprises a planar CMOS transistor or the like. The technical solution of the present application is to separate logic, storage, radio frequency, analog and power devices, and to place some components with larger nodes or greater impact of mixed processes (such as the active device 103 in the present application) into the adapter board. Therefore, the active device 103 placed in the adapter board in the present application can be any suitable active device according to actual needs. It should be noted that since the types of the active device 103 are selected according to needs, the structure of the active device 103 is not shown in the drawings of the present application, but is simply replaced by a block to show the position of the active device 103. The active device 103 in the present application can be a structure known to those skilled in the art. For example, taking a CMOS transistor as an example, the active device 103 can include a source and a drain located in the semiconductor substrate 101 and a gate located in the interlayer dielectric layer 102, and the contact structure 104 can be multiple and respectively electrically connected to the source, the drain and the gate.

[0031] In some embodiments of the present application, the number of the active device 103 can be multiple, which is not limited in the present application. In practice, a proper number of active devices 103 can be arranged according to the volume and space of the substrate 100.

[0032] In some embodiments of the present application, the material of the contact structure 104 comprises copper or tungsten or the like.

[0033] Reference Figure 2 As shown, a TSV structure 110 extending into the substrate 100 (specifically extending into the semiconductor substrate 101) is formed on the first surface 10 of the substrate 100. The TSV structure is a common structure in the 3D packaging structure in the art, and therefore its forming method and specific structure are not described here.

[0034] In some embodiments of the present application, the position of the TSV structure 110 is located at the two side edges of the substrate 100, which is to leave more space in the middle of the substrate 100 to accommodate more active devices 103.

[0035] In some embodiments of the present application, the diameter of the TSV structure 110 is 20 to 25 microns, and the depth of the TSV structure is 40 to 60 microns.

[0036] Reference Figure 3As shown, a first dielectric layer 120 is formed on the first surface 10 of the substrate 100, and a plurality of first metal connection structures 121 are formed in the first dielectric layer 120 and electrically connected to the TSV structures 110 and the active devices 103 respectively. Specifically, the first metal connection structures 121 are electrically connected to the active devices 103 by electrically connecting the contact structures 104. The first metal connection structures 121 are independent from each other.

[0037] In some embodiments of the present application, the material of the first dielectric layer 120 includes an insulating dielectric material such as silicon oxide or silicon nitride.

[0038] In some embodiments of the present application, the material of the first metal connection structures 121 includes a metal material such as copper or tungsten or other conductive material.

[0039] In some embodiments of the present application, a plurality of resistors 122 are formed in the first dielectric layer 120, and a part of the first metal connection structures 121 are electrically connected to the resistors 122. The resistors 122 are thin film resistors made of a material such as CrSi or TaN. The technical solution of the present application separates logic, storage, radio frequency, analog and power devices, and places some components with larger nodes or greater impact of mixed processes (such as the resistors 122 in the present application) into a conversion board. Therefore, the resistors 122 placed in the conversion board in the present application can also select other arbitrary suitable resistor types according to actual needs.

[0040] Reference Figure 4 As shown, a second dielectric layer 130 is formed on the surface of the first dielectric layer 120, and a plurality of first metal pads 131 are formed in the second dielectric layer 130 and electrically connected to the plurality of first metal connection structures 121. The number and position of the plurality of first metal pads 131 correspond to the plurality of first metal connection structures 121.

[0041] In some embodiments of the present application, the material of the second dielectric layer 130 includes an insulating dielectric material such as silicon oxide or silicon nitride.

[0042] In some embodiments of the present application, the surface of the plurality of first metal pads 131 is higher than the surface of the second dielectric layer 130.

[0043] In some embodiments of the present application, the material of the plurality of first metal pads 131 includes a metal material such as copper or aluminum.

[0044] Reference Figure 5 As shown, a first passivation layer 141 is formed on the surface of the first metal pads 131.

[0045] In some embodiments of the present application, the material of the first passivation layer 141 includes an insulating dielectric material such as silicon oxide or silicon nitride.

[0046] Referring to Figure 6 As shown, a solder ball 140 is formed on the surface of the first passivation layer 141 to electrically connect the first metal pad 131 through the first passivation layer 141. The solder ball is also a common structure in semiconductor packaging process, and thus the forming process thereof will not be described here.

[0047] Referring to Figure 7 As shown, a bonding dielectric layer 150 is formed on the surface of the second dielectric layer 130 to cover the second dielectric layer 130, the first passivation layer 141 and the solder ball 140.

[0048] In some embodiments of the present application, the material of the bonding dielectric layer 150 includes an insulating dielectric material such as silicon oxide or silicon nitride.

[0049] Referring to Figure 8 As shown, a carrier wafer 160 is formed on the surface of the bonding dielectric layer 150.

[0050] In some embodiments of the present application, the carrier wafer 160 can be a semiconductor wafer such as a silicon wafer, or a carrier wafer commonly used in the field of semiconductor packaging such as a glass wafer.

[0051] In some embodiments of the present application, the method of forming the carrier wafer 160 on the surface of the bonding dielectric layer 150 includes a wafer bonding process or a sticking process.

[0052] Referring to Figure 9 As shown, a chemical mechanical polishing process is used to thin the second surface 20 (i.e. the semiconductor substrate 101) of the substrate 100 to expose the TSV structure 110. After thinning, the thickness of the semiconductor substrate 101 is 35 to 55 microns.

[0053] Referring to Figure 10 As shown, an oxide layer 170 is formed on the second surface 20 of the substrate 100. The oxide layer 170 covers the second surface 20 of the substrate 100 and the TSV structure 110.

[0054] In some embodiments of the present application, the material of the oxide layer 170 includes an insulating dielectric material such as silicon oxide. The thickness of the oxide layer 170 is 50 to 100 nanometers. The method of forming the oxide layer 170 includes a chemical vapor deposition process.

[0055] Referring to Figure 11As shown, a plurality of plate capacitor structures 180 are formed on the surface of the oxide layer 170. For the purpose of simplicity, only one plate capacitor structure 180 is shown in the drawings of the present application, and in practice, the number of the plurality of plate capacitor structures 180 can be set as needed. The plate capacitor structure is a common structure in the semiconductor field, and thus the specific formation process thereof will not be described here.

[0056] In some embodiments of the present application, the plate capacitor structure 180 includes a first electrode plate 181, a capacitor dielectric layer 182, and a second electrode plate 183. It should be noted that the present application here only takes the simplest three-layer capacitor structure as an example, and in practice, a capacitor structure with more electrode plates and capacitor dielectric layers can also be formed as needed.

[0057] In some embodiments of the present application, the materials of the first electrode plate 181 and the second electrode plate 183 include titanium nitride. The material of the capacitor dielectric layer 182 can include ZrO2, HfO2, Al2O3, and other high-dielectric-constant dielectric materials.

[0058] Reference Figure 12 As shown, a third dielectric layer 190 covering the oxide layer 170 and the plate capacitor structure 180 is formed on the surface of the oxide layer 170, and a plurality of second metal connection structures 191 electrically connecting the TSV structure 110 and the plate capacitor structure 180 (specifically, electrically connecting the first electrode plate 181 and the second electrode plate 183 thereof) are formed in the third dielectric layer 190.

[0059] In some embodiments of the present application, the material of the third dielectric layer 190 includes an insulating dielectric material such as silicon oxide or silicon nitride.

[0060] In some embodiments of the present application, the material of the second metal connection structure 191 includes a metal material such as copper or tungsten or other conductive materials.

[0061] Reference Figure 13 As shown, a fourth dielectric layer 200 is formed on the surface of the third dielectric layer 190, and a plurality of second metal pads 201 electrically connecting the plurality of second metal connection structures 191 are formed in the fourth dielectric layer 200. The number and position of the plurality of second metal pads 201 correspond to those of the plurality of second metal connection structures 191.

[0062] In some embodiments of the present application, the material of the fourth dielectric layer 200 includes an insulating dielectric material such as silicon oxide or silicon nitride.

[0063] In some embodiments of the present application, the surface of the plurality of second metal pads 201 is higher than the surface of the fourth dielectric layer 200.

[0064] In some embodiments of the present application, the material of the second metal pads 201 comprises metal materials such as copper or aluminum.

[0065] Referring to Figure 14 As shown, a second passivation layer 210 is formed on the surface of the second metal pads 201 to expose the second metal pads 201. The second metal pads 201 are exposed for subsequent electrical connection and other processes when the adapter plate is bonded with other wafers.

[0066] In some embodiments of the present application, the material of the second passivation layer 210 comprises insulating medium materials such as silicon oxide or silicon nitride.

[0067] In the technical solution of the present application, some elements (such as the active device 103 and the resistor 122 in the present application) in the device wafer in the conventional process and packaging structure are placed in the adapter plate, and the unused space in the adapter plate is utilized to improve the integration of the module device and achieve good processing yield. Moreover, the process flow of the present application is fully compatible with the mature process.

[0068] The present application provides an adapter plate and a forming method thereof, which can separate logic, storage, radio frequency, analog and power devices, place some elements with larger nodes or greater mixed process impact into the adapter plate, and fully utilize the mature process compatible flow method to prepare, improve the integration of the module device, and achieve good processing yield.

[0069] Embodiments of the present application also provide an adapter plate, referring to Figure 14 As shown, the adapter plate comprises a substrate 100, wherein the substrate 100 is formed with an active device 103, the substrate 100 comprises a first surface 10 and a second surface 20, and the substrate 100 is further formed with a TSV structure 110 penetrating through the substrate 100; a first dielectric layer 120 is located on the first surface 10 of the substrate 100, and the first dielectric layer 120 is formed with a plurality of first metal connection structures 121 electrically connecting the TSV structure 110 and the active device 103 respectively; an oxide layer 170 is located on the second surface 20 of the substrate 100, and the surface of the oxide layer 170 is formed with a plurality of plate capacitors 180; and a third dielectric layer 190 is located on the surface of the oxide layer 170 to cover the oxide layer 170 and the plate capacitors 180, and the third dielectric layer 190 is formed with a plurality of second metal connection structures 191 electrically connecting the TSV structure 110 and the plate capacitors 180 respectively.

[0070] Referring to Figure 14As shown, in some embodiments of the present application, the base 100 includes a semiconductor substrate 101 and an interlayer dielectric layer 102 located on the surface of the semiconductor substrate 101, the surface of the interlayer dielectric layer 102 is the first surface 10 of the base 100, the active device 103 is located in the semiconductor substrate 101 and the interlayer dielectric layer 102, and a contact structure 104 electrically connected to the active device 103 is also formed in the interlayer dielectric layer 102.

[0071] In some embodiments of the present application, the material of the semiconductor substrate 101 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0072] In some embodiments of the present application, the thickness of the semiconductor substrate 101 is 35 to 55 microns.

[0073] In some embodiments of the present application, the material of the interlayer dielectric layer 102 includes silicon oxide.

[0074] In some embodiments of the present application, the active device 103 includes a planar CMOS transistor, etc. The technical solution of the present application is to separate devices such as logic, storage, RF, analog, and power, and place some components with larger nodes or greater impact on the mixed process (such as the active device 103 in this application) on an adapter board. Therefore, the active device 103 placed on the adapter board in this application can be any suitable active device according to actual needs. It should be noted that since the type of the active device 103 is selected according to needs, the drawings of this application do not show the structure of the active device 103 here, but only use blocks to simply illustrate the location of the active device 103. The active device 103 in this application can be a structure familiar to those skilled in the art. For example, taking a CMOS transistor as an example, the active device 103 can include a source and a drain located in the semiconductor substrate 101 and a gate located in the interlayer dielectric layer 102. The contact structure 104 can be multiple and electrically connected to the source, drain, and gate respectively.

[0075] In some embodiments of the present application, the number of the active devices 103 can be multiple, which is not limited in the present application. In practice, an appropriate number of active devices 103 can be provided according to the volume and space of the substrate 100.

[0076] In some embodiments of the present application, the material of the contact structure 104 includes copper or tungsten.

[0077] Continue to refer Figure 14As shown, in some embodiments of the present application, the TSV structures 110 are located at the two side edges of the substrate 100, so as to leave more space in the middle of the substrate 100 for accommodating more active devices 103.

[0078] In some embodiments of the present application, the diameter of the TSV structures 110 is 20-25 microns, and the depth of the TSV structures is 40-60 microns.

[0079] Continuing to refer to Figure 14 As shown, the first metal connection structures 121 are electrically connected to the contact structures 104, and thus to the active devices 103. The first metal connection structures 121 are independent from each other.

[0080] In some embodiments of the present application, the material of the first dielectric layer 120 includes an insulating dielectric material such as silicon oxide or silicon nitride.

[0081] In some embodiments of the present application, the material of the first metal connection structures 121 includes a metal material such as copper or tungsten or other conductive material.

[0082] In some embodiments of the present application, the first dielectric layer 120 further includes a resistor 122 and part of the first metal connection structures 121 electrically connected to the resistor 122. The resistor 122 is, for example, a thin-film resistor composed of a material such as CrSi or TaN. The technical solution of the present application is to separate logic, storage, radio frequency, analog and power devices, and to place some components with larger nodes or greater impact of mixed processes (such as the resistor 122 herein) into a conversion board. Therefore, the resistor 122 placed into the conversion board herein can also be selected as any other suitable resistor type according to actual needs.

[0083] Continuing to refer to Figure 14 As shown, the first dielectric layer 120 further includes a second dielectric layer 130, and the second dielectric layer 130 includes a plurality of first metal pads 131 electrically connected to the plurality of first metal connection structures 121. The number and position of the plurality of first metal pads 131 correspond to those of the plurality of first metal connection structures 121.

[0084] In some embodiments of the present application, the material of the second dielectric layer 130 includes an insulating dielectric material such as silicon oxide or silicon nitride.

[0085] In some embodiments of the present application, the surface of the plurality of first metal pads 131 is higher than the surface of the second dielectric layer 130.

[0086] In some embodiments of the present application, the material of the plurality of first metal pads 131 includes a metal material such as copper or aluminum.

[0087] With continued reference to Figure 14 As shown, the first metal pad 131 is formed with a first passivation layer 141 on a surface thereof.

[0088] In some embodiments of the present application, the material of the first passivation layer 141 includes an insulating dielectric material such as silicon oxide or silicon nitride.

[0089] With continued reference to Figure 14 As shown, the first passivation layer 141 is formed with a solder ball 140 on a surface thereof, which electrically connects the first metal pad 131 through the first passivation layer 141.

[0090] With continued reference to Figure 14 As shown, the second dielectric layer 130 is formed with a bonding dielectric layer 150 on a surface thereof, which covers the second dielectric layer 130, the first passivation layer 141 and the solder ball 140.

[0091] In some embodiments of the present application, the material of the bonding dielectric layer 150 includes an insulating dielectric material such as silicon oxide or silicon nitride.

[0092] With continued reference to Figure 14 As shown, the bonding dielectric layer 150 is formed with a carrier wafer 160 on a surface thereof.

[0093] In some embodiments of the present application, the carrier wafer 160 can be a semiconductor wafer such as a silicon wafer, or a glass wafer or other commonly used carrier wafer in the field of semiconductor packaging.

[0094] With continued reference to Figure 14 As shown, the oxide layer 170 covers the second surface 20 of the substrate 100 and the TSV structure 110.

[0095] In some embodiments of the present application, the material of the oxide layer 170 includes an insulating dielectric material such as silicon oxide. The thickness of the oxide layer 170 is 50 to 100 nanometers.

[0096] With continued reference to Figure 14 As shown, only one plate capacitor structure 180 is shown here for the purpose of simplicity, in practice, the number of the plate capacitor structures 180 can be set as needed.

[0097] In some embodiments of the present application, the plate capacitor structure 180 includes a first plate 181, a capacitor dielectric layer 182 and a second plate 183. It is to be noted that only the simplest three-layer capacitor structure is taken as an example here, in practice, a capacitor structure with more plates and capacitor dielectric layers can also be formed as needed.

[0098] In some embodiments of the present application, the material of the first and second electrode plates 181 and 183 comprises titanium nitride. The material of the capacitor dielectric layer 182 can comprise ZrO2, HfO2, Al2O3, or other high dielectric constant dielectric materials.

[0099] In some embodiments of the present application, the material of the third dielectric layer 190 comprises silicon oxide or silicon nitride, or other insulating dielectric materials.

[0100] In some embodiments of the present application, the material of the second metal connection structure 191 comprises copper or tungsten, or other metal materials or other conductive materials.

[0101] Continuing to refer to Figure 14 As shown, the surface of the third dielectric layer 190 is formed with a fourth dielectric layer 200, and the fourth dielectric layer 200 is formed with a plurality of second metal pads 201 electrically connected to the plurality of second metal connection structures 191. The number and position of the plurality of second metal pads 201 correspond to the plurality of second metal connection structures 191.

[0102] In some embodiments of the present application, the material of the fourth dielectric layer 200 comprises silicon oxide or silicon nitride, or other insulating dielectric materials.

[0103] In some embodiments of the present application, the surface of the plurality of second metal pads 201 is higher than the surface of the fourth dielectric layer 200.

[0104] In some embodiments of the present application, the material of the plurality of second metal pads 201 comprises copper or aluminum, or other metal materials.

[0105] Continuing to refer to Figure 14 Figure 14 As shown, the surface of the second metal pad 201 is formed with a second passivation layer 210 exposing part of the second metal pad 201. The exposed second metal pad 201 is used for subsequent processes such as electrical connection when bonding with other wafers.

[0106] In some embodiments of the present application, the material of the second passivation layer 210 comprises silicon oxide or silicon nitride, or other insulating dielectric materials.

[0107] In the technical solution of the present application, some elements (such as the active device 103 and the resistor 122 in the present application) in the conventional process and packaging structure are placed in the adapter plate, and the unused space in the adapter plate is utilized, so that the integration of the module device is improved, and good processing yield is achieved. Moreover, the process flow of the present application is fully compatible with mature processes.

[0108] The present application provides an adapter board and a method for forming the same, which can separate logic, storage, RF, analog, and power devices, place some components with larger nodes or greater impact from mixed processes on the adapter board, and make full use of mature process-compatible process methods to achieve a good processing yield while improving the integration of module devices.

[0109] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0110] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intermediate elements may exist.

[0111] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, the term "directly" indicates that there are no intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0112] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0113] Furthermore, the description herein describes example embodiments by reference to idealized illustrative cross-sectional and / or plan and / or perspective views. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the example embodiments should not be construed as limited to the precise shapes illustrated herein but are to include deviations in shapes that result from such tollerances and / or manufacturing techniques. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the example embodiments.

Claims

1. A method of forming a transition plate, characterized by, The method comprises: providing a substrate, the substrate having a first surface and a second surface, and having a TSV structure formed therein; forming a first dielectric layer on the first surface of the substrate, the first dielectric layer having a plurality of first metal connection structures formed therein, each of the first metal connection structures electrically connecting the TSV structure and an active device; forming an oxide layer on the second surface of the substrate; forming a plurality of plate capacitors on the surface of the oxide layer; forming a third dielectric layer on the surface of the oxide layer, the third dielectric layer covering the oxide layer and the plate capacitors, the third dielectric layer having a plurality of second metal connection structures formed therein, each of the second metal connection structures electrically connecting the TSV structure and the plate capacitors. The substrate comprises a semiconductor substrate and an interlayer dielectric layer on the surface of the semiconductor substrate, the surface of the interlayer dielectric layer being the first surface of the substrate, the active device being formed in the semiconductor substrate and the interlayer dielectric layer, and a contact structure being formed in the interlayer dielectric layer and electrically connecting the active device, the first metal connection structure electrically connecting the contact structure.

2. The method of claim 1, wherein The first dielectric layer further has a resistor formed therein, and a portion of the first metal connection structure electrically connecting the resistor.

3. The method of claim 1, wherein The method further comprises:

4. The method for forming an adapter plate according to claim 1, wherein: forming a second dielectric layer on the surface of the first dielectric layer, the second dielectric layer having a plurality of first metal pads formed therein, each of the first metal pads electrically connecting a corresponding one of the first metal connection structures; forming a first passivation layer on the surface of the first metal pads; forming a solder ball on the surface of the first passivation layer, the solder ball penetrating the first passivation layer and electrically connecting the first metal pads; forming a bonding dielectric layer on the surface of the second dielectric layer, the bonding dielectric layer covering the second dielectric layer, the first passivation layer and the solder ball; and forming a carrier wafer on the surface of the bonding dielectric layer. Before forming the oxide layer on the second surface of the substrate, the method further comprises: thinning the second surface of the substrate to expose the TSV structure.

5. The method of claim 1, wherein The method further comprises:

6. The method of claim 1, wherein forming a fourth dielectric layer on the surface of the third dielectric layer, the fourth dielectric layer having a plurality of second metal pads formed therein, each of the second metal pads electrically connecting a corresponding one of the second metal connection structures; and forming a second passivation layer on the surface of the second metal pads, the second passivation layer exposing a portion of the second metal pads. The method comprises:

7. An adapter plate, characterized by providing a substrate, the substrate having a first surface and a second surface, and having a TSV structure formed therein; forming a first dielectric layer on the first surface of the substrate, the first dielectric layer having a plurality of first metal connection structures formed therein, each of the first metal connection structures electrically connecting the TSV structure and an active device; forming an oxide layer on the second surface of the substrate, the surface of the oxide layer having a plurality of plate capacitors formed thereon; forming a third dielectric layer on the surface of the oxide layer, the third dielectric layer covering the oxide layer and the plate capacitors, the third dielectric layer having a plurality of second metal connection structures formed therein, each of the second metal connection structures electrically connecting the TSV structure and the plate capacitors. ​ 8. The adapter plate of claim 7, wherein, The substrate includes a semiconductor substrate and an interlayer dielectric layer on the surface of the semiconductor substrate, the surface of the interlayer dielectric layer being a first surface of the substrate, the active device being in the semiconductor substrate and the interlayer dielectric layer, a contact structure electrically connecting the active device being further formed in the interlayer dielectric layer, the first metal connection structure electrically connecting the contact structure.

9. The adapter plate of claim 7, wherein, The first dielectric layer further has a resistor and part of the first metal connection structure electrically connecting the resistor.

10. The adapter plate according to claim 7, wherein: Further comprising: a second dielectric layer on the surface of the first dielectric layer, the second dielectric layer having a plurality of first metal pads electrically connected to the plurality of first metal connection structures; a first passivation layer on the surface of the first metal pad, a solder ball on the surface of the first passivation layer and penetrating the first passivation layer to electrically connect the first metal pad, a bonding dielectric layer on the surface of the second dielectric layer covering the second dielectric layer, the first passivation layer and the solder ball, and a carrier wafer on the surface of the bonding dielectric layer.

11. The adapter plate of claim 7, wherein, Further comprising: a fourth dielectric layer on the surface of the third dielectric layer, the fourth dielectric layer having a plurality of second metal pads electrically connected to the plurality of second metal connection structures; a second passivation layer on the surface of the second metal pad, exposing part of the second metal pad.

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