Adapter plate and forming method thereof
By separating logic, memory, RF, analog, and power devices in the adapter board and utilizing TSV and trench capacitor structures, the problems of power supply voltage fluctuation and noise in 2.5D adapter boards are solved, improving chip integration and processing yield, and reducing costs.
Patent Information
- Application Number
- CN202410495387.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-23
- Publication Date
- 2025-10-24
AI Technical Summary
Existing 2.5D adapter boards suffer from power supply voltage fluctuation sensitivity and circuit noise issues when integrating multiple complex chips. Furthermore, traditional manufacturing processes are complex, costly, and cannot effectively utilize space, resulting in low chip integration and low processing yield.
By separating logic, memory, RF, analog, and power components, and integrating DTC capacitors in the adapter board using mature process-compatible methods, and optimizing circuit connections through TSV and trench capacitor structures, the module's component integration is improved and power supply noise is reduced.
It achieves higher chip integration and processing yield, reduces power supply noise and manufacturing costs, optimizes circuit performance, and improves system power integrity.
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Figure CN120834073A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, and in particular to an interposer and a forming method thereof. BACKGROUND
[0002] The current Moore's law is slowing down, and 2.5D packaging is an in-die stacking technology that can expand various complex chips, allowing the industry to take a new approach to providing large-scale complex chip integration faster than Moore's law, while reducing power consumption and cost. To solve the problem of insufficient wiring density of organic substrates, silicon substrates with TSV (Through Silicon Via) vertical interconnection holes and high-density metal wiring have emerged. The silicon-based passive platform with TSV is called a TSV interposer. The packaging structure using the TSV interposer is called a 2.5D interposer.
[0003] With smaller device core sizes and increased device densities, the drive strength per unit area in the device increases, meaning higher current density and greater current transients. This results in chips becoming more sensitive to power supply voltage fluctuations, and circuits require decoupling capacitors as a basic tool to reduce PDN (power delivery network) impedance. By suppressing noise through decoupling or bypassing a portion of the circuit or interconnection, it is necessary to control parasitic resistance and inductance, and decoupling capacitors must be physically close to the required circuit, so a large number of DTC capacitors must be integrated in the 2.5D interposer.
[0004] The main application scenario of the current 2.5D interposer is the HPC and AI fields, and the characteristics of high speed and high performance require chips to be more sensitive to power supply voltage fluctuations. Capacitive decoupling is the main method to solve the problem of power supply noise. This method is very effective in improving the response speed of transient current and reducing the impedance of the power distribution system. Compared with traditional ceramic capacitors, DTC has better integration characteristics, and the design is closer to the required circuit, which is more conducive to improving the power integrity of the system. For the same link, the CoWoS system integrated with DTC can significantly reduce the PDN impedance by 93% compared to the system without DTC in the high frequency part; and for the same link, the time domain simulation shows that the system integrated with DTC has a 72% improvement in voltage drop performance compared to the system without DTC.
[0005] The current common technology uses a board containing DTC+TSV structure, and under the requirements of product speed, function and volume, multiple wafers (SOC, HBM) and a small number of passive elements are packaged on the board to integrate into a multi-wafer module element. The SoC system wafer is a product of advanced version, that is, all functions are integrated on a single wafer. In short, it integrates different functions such as logic, storage, radio frequency and power supply on a wafer. The advantage of SoC is that higher performance can be obtained with lower power consumption; the disadvantage is that because many functions are integrated in the same wafer, a larger wafer is formed, the preparation process is complex, and different circuits require different processes, so each circuit function cannot be optimized at the same time. In addition, there are interference and isolation problems, and if a function needs to be upgraded in the future, it cannot be improved separately, so a high cost is required. In addition, the board uses independent wafer processing, and the volume of DTC+TSV (area ratio less than 30%) and circuit used in the final silicon body is limited, resulting in a large waste of space, and the preparation cost is also high.
[0006] Therefore, it is necessary to provide a more effective and reliable technical solution to separate logic, storage, radio frequency, analog and power devices, and place some elements with larger nodes or greater impact of mixed processes into the adapter board, and fully utilize the mature process compatible process method for preparation, so as to improve the integration of module devices while realizing good processing yield. SUMMARY
[0007] The present application provides an adapter board and a forming method thereof, which can separate logic, storage, radio frequency, analog and power devices, and place some elements with larger nodes or greater impact of mixed processes into the adapter board, and fully utilize the mature process compatible process method for preparation, so as to improve the integration of module devices while realizing good processing yield.
[0008] One aspect of the present application provides a forming method of an adapter board, comprising: providing a substrate, the substrate having an active device formed therein, the substrate comprising a first surface and a second surface; forming a TSV structure extending into the substrate on the first surface of the substrate; forming a first dielectric layer on the first surface of the substrate, the first dielectric layer having a plurality of first metal connection structures formed therein and respectively electrically connected to the TSV structure and the active device; forming an oxide layer on the second surface of the substrate; forming a plurality of capacitor trenches extending into the substrate through the oxide layer on the second surface of the substrate; forming an insulating layer on the bottom and sidewall of the capacitor trenches; forming a plurality of trench capacitors in the capacitor trenches and on the surface of the oxide layer; forming a third dielectric layer covering the oxide layer and the trench capacitors on the surface of the oxide layer, the third dielectric layer having a plurality of second metal connection structures formed therein and respectively electrically connected to the TSV structure and the trench capacitors.
[0009] In some embodiments of the application, the substrate comprises a semiconductor substrate and an interlayer dielectric layer on a surface of the semiconductor substrate, the surface of the interlayer dielectric layer is a first surface of the substrate, the active device is in the semiconductor substrate and the interlayer dielectric layer, a contact structure electrically connecting the active device is also formed in the interlayer dielectric layer, the first metal connection structure electrically connects the contact structure.
[0010] In some embodiments of the application, a resistor is also formed in the first dielectric layer, and part of the first metal connection structure electrically connects the resistor.
[0011] In some embodiments of the application, the method for forming the adapter plate further comprises: forming a second dielectric layer on the surface of the first dielectric layer, a plurality of first metal pads electrically connecting the plurality of first metal connection structures are formed in the second dielectric layer; forming a first passivation layer on the surface of the first metal pad; forming a solder ball penetrating the first passivation layer and electrically connecting the first metal pad on the surface of the first passivation layer; forming a bonding dielectric layer covering the second dielectric layer, the first passivation layer and the solder ball on the surface of the second dielectric layer; forming a carrier wafer on the surface of the bonding dielectric layer.
[0012] In some embodiments of the application, before forming the oxide layer on the second surface of the substrate, the method further comprises: thinning the second surface of the substrate to expose the TSV structure.
[0013] In some embodiments of the application, the method for forming the semiconductor structure further comprises: forming a fourth dielectric layer on the surface of the third dielectric layer, a plurality of second metal pads electrically connecting the plurality of second metal connection structures are formed in the fourth dielectric layer; forming a second passivation layer exposing part of the second metal pads on the surface of the second metal pad.
[0014] Another aspect of the application also provides an adapter plate, comprising: a substrate, an active device is formed in the substrate, the substrate comprises a first surface and a second surface, a TSV structure penetrating the substrate is also formed in the substrate; a first dielectric layer is on the first surface of the substrate, a plurality of first metal connection structures electrically connecting the TSV structure and the active device respectively are formed in the first dielectric layer; an oxide layer is on the second surface of the substrate; a plurality of capacitor trenches are on the second surface of the substrate, extending to the substrate through the oxide layer; an insulating layer is on the bottom and sidewall of the capacitor trench; a plurality of trench capacitor structures are in the capacitor trench and on the surface of the oxide layer; a third dielectric layer is on the surface of the oxide layer, covering the oxide layer and the trench capacitor structure, a plurality of second metal connection structures electrically connecting the TSV structure and the trench capacitor structure respectively are formed in the third dielectric layer.
[0015] In some embodiments of the present application, the substrate comprises a semiconductor substrate and an interlayer dielectric layer on the surface of the semiconductor substrate, the surface of the interlayer dielectric layer being the first surface of the substrate, the active device being in the semiconductor substrate and the interlayer dielectric layer, a contact structure electrically connecting the active device being formed in the interlayer dielectric layer, the first metal connection structure electrically connecting the contact structure.
[0016] In some embodiments of the present application, a resistor is formed in the first dielectric layer, and part of the first metal connection structure electrically connects the resistor.
[0017] In some embodiments of the present application, the adapter board further comprises: a second dielectric layer on the surface of the first dielectric layer, a plurality of first metal pads electrically connecting the plurality of first metal connection structures being formed in the second dielectric layer; a first passivation layer on the surface of the first metal pad; a solder ball on the surface of the first passivation layer penetrating the first passivation layer to electrically connect the first metal pad; a bonding dielectric layer on the surface of the second dielectric layer covering the second dielectric layer, the first passivation layer and the solder ball; and a carrier wafer on the surface of the bonding dielectric layer.
[0018] In some embodiments of the present application, the adapter board further comprises: a fourth dielectric layer on the surface of the third dielectric layer, a plurality of second metal pads electrically connecting the plurality of second metal connection structures being formed in the fourth dielectric layer; and a second passivation layer on the surface of the second metal pad exposing part of the second metal pad.
[0019] The present application provides an adapter board and a forming method thereof, which can separate logic, storage, radio frequency, analog and power devices, put some elements with larger node or mixed process into the adapter board, and fully utilize the mature process compatible process method to prepare, improve the integration of the module device, and realize good processing yield. BRIEF DESCRIPTION OF DRAWINGS
[0020] The following drawings in detail describe the exemplary embodiments disclosed in the present application. The same reference signs in the drawings represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application, and other ways of embodiments can also achieve the same purpose of the invention in the present application. It should be understood that the drawings are not drawn to scale.
[0021] Wherein:
[0022] Figures 1 to 15 The structure schematic diagram of each step in the forming method of the adapter board described in the embodiments of the present application. DETAILED DESCRIPTION
[0023] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.
[0024] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.
[0025] Figures 1 to 15 The following is a structural diagram of each step in the method for forming the adapter plate according to the embodiment of the present application. The method for forming the adapter plate according to the embodiment of the present application is described in detail with reference to the accompanying drawings.
[0026] refer to Figure 1 As shown, a substrate 100 is provided, in which an active device 103 is formed. The substrate 100 includes a first surface 10 and a second surface 20 opposite to each other.
[0027] In some embodiments of the present application, the base 100 includes a semiconductor substrate 101 and an interlayer dielectric layer 102 located on the surface of the semiconductor substrate 101, the surface of the interlayer dielectric layer 102 is the first surface 10 of the base 100, the active device 103 is located in the semiconductor substrate 101 and the interlayer dielectric layer 102, and a contact structure 104 electrically connected to the active device 103 is also formed in the interlayer dielectric layer 102.
[0028] In some embodiments of the present application, the material of the semiconductor substrate 101 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.
[0029] In some embodiments of the present application, the material of the interlayer dielectric layer 102 includes silicon oxide.
[0030] In some embodiments of the present application, the active device 103 comprises a FINFET device or the like. The technical solution of the present application is to separate logic, storage, radio frequency, analog and power devices, and to place some nodes with larger components or mixed process impact (such as the active device 103 in the present application) into the adapter board. Therefore, the active device 103 placed in the adapter board in the present application can be any suitable active device according to actual needs. It should be noted that since the type of the active device 103 is selected according to needs, the structure of the active device 103 is not shown in the drawings of the present application, but is simply replaced by a block to show the position of the active device 103. The active device 103 in the present application can be a structure well known to those skilled in the art. For example, taking a CMOS transistor as an example, the active device 103 can include a source and a drain located in the semiconductor substrate 101 and a gate located in the interlayer dielectric layer 102, and the contact structure 104 can be multiple and respectively electrically connected to the source, the drain and the gate.
[0031] In some embodiments of the present application, the number of the active device 103 can be multiple, which is not limited in the present application. In practice, a proper number of active devices 103 can be arranged according to the volume and space of the substrate 100.
[0032] In some embodiments of the present application, the material of the contact structure 104 comprises copper or tungsten or the like.
[0033] Reference Figure 2 As shown, a TSV structure 110 extending into the substrate 100 (specifically into the semiconductor substrate 101) is formed on the first surface 10 of the substrate 100. The TSV structure is a common structure in the 3D packaging structure in the art, and therefore its forming method and specific structure are not described here.
[0034] In some embodiments of the present application, the position of the TSV structure 110 is located at the two side edges of the substrate 100, so as to leave more space in the middle of the substrate 100 to accommodate more active devices 103.
[0035] In some embodiments of the present application, the diameter of the TSV structure 110 is 20 to 25 microns, and the depth of the TSV structure is 40 to 60 microns.
[0036] Reference Figure 3As shown, a first dielectric layer 120 is formed on the first surface 10 of the substrate 100, and a plurality of first metal connection structures 121 are formed in the first dielectric layer 120 and electrically connected to the TSV structures 110 and the active devices 103 respectively. Specifically, the first metal connection structures 121 are electrically connected to the active devices 103 by electrically connecting the contact structures 104. The first metal connection structures 121 are independent from each other.
[0037] In some embodiments of the present application, the material of the first dielectric layer 120 includes an insulating dielectric material such as silicon oxide or silicon nitride.
[0038] In some embodiments of the present application, the material of the first metal connection structures 121 includes a metal material such as copper or tungsten or other conductive material.
[0039] In some embodiments of the present application, a plurality of resistors 122 are formed in the first dielectric layer 120, and a part of the first metal connection structures 121 are electrically connected to the resistors 122. The resistors 122 are thin film resistors made of a material such as CrSi or TaN. The technical solution of the present application separates logic, storage, radio frequency, analog and power devices, and places some components with larger nodes or greater impact of mixed processes (such as the resistors 122 in the present application) into a conversion board. Therefore, the resistors 122 placed in the conversion board in the present application can also select other arbitrary suitable resistor types according to actual needs.
[0040] Reference Figure 4 As shown, a second dielectric layer 130 is formed on the surface of the first dielectric layer 120, and a plurality of first metal pads 131 are formed in the second dielectric layer 130 and electrically connected to the plurality of first metal connection structures 121. The number and position of the plurality of first metal pads 131 correspond to the plurality of first metal connection structures 121.
[0041] In some embodiments of the present application, the material of the second dielectric layer 130 includes an insulating dielectric material such as silicon oxide or silicon nitride.
[0042] In some embodiments of the present application, the surface of the plurality of first metal pads 131 is higher than the surface of the second dielectric layer 130.
[0043] In some embodiments of the present application, the material of the plurality of first metal pads 131 includes a metal material such as copper or aluminum.
[0044] Reference Figure 5 As shown, a first passivation layer 141 is formed on the surface of the first metal pads 131.
[0045] In some embodiments of the present application, the material of the first passivation layer 141 includes an insulating dielectric material such as silicon oxide or silicon nitride.
[0046] Referring to Figure 6 As shown, a solder ball 140 is formed on the surface of the first passivation layer 141 to electrically connect the first metal pad 131 through the first passivation layer 141. The solder ball is also a common structure in semiconductor packaging process, and thus the forming process thereof will not be described here.
[0047] Referring to Figure 7 As shown, a bonding dielectric layer 150 is formed on the surface of the second dielectric layer 130 to cover the second dielectric layer 130, the first passivation layer 141 and the solder ball 140.
[0048] In some embodiments of the present application, the material of the bonding dielectric layer 150 includes an insulating dielectric material such as silicon oxide or silicon nitride.
[0049] Referring to Figure 8 As shown, a carrier wafer 160 is formed on the surface of the bonding dielectric layer 150.
[0050] In some embodiments of the present application, the carrier wafer 160 can be a semiconductor wafer such as a silicon wafer, or a carrier wafer commonly used in the field of semiconductor packaging such as a glass wafer.
[0051] In some embodiments of the present application, the method of forming the carrier wafer 160 on the surface of the bonding dielectric layer 150 includes a wafer bonding process or a sticking process.
[0052] Referring to Figure 9 As shown, a chemical mechanical polishing process is used to thin the second surface 20 (i.e. the semiconductor substrate 101) of the substrate 100 to expose the TSV structure 110. After thinning, the thickness of the semiconductor substrate 101 is 35 to 55 microns.
[0053] Referring to Figure 10 As shown, an oxide layer 170 is formed on the second surface 20 of the substrate 100. The oxide layer 170 covers the second surface 20 of the substrate 100 and the TSV structure 110.
[0054] In some embodiments of the present application, the material of the oxide layer 170 includes an insulating dielectric material such as silicon oxide. The thickness of the oxide layer 170 is 50 to 100 nanometers. The method of forming the oxide layer 170 includes a chemical vapor deposition process.
[0055] Referring to Figure 11As shown, a plurality of capacitor trenches 184 extending through the oxide layer 170 into the substrate 100 (specifically into the semiconductor substrate 101) are formed on the second surface 20 of the substrate 100. The size of the capacitor trenches 184 is set according to the size of the trench capacitor structure as required.
[0056] In some embodiments of the present application, the method for forming the semiconductor structure further comprises: forming an insulating layer (not shown in the figure) on the bottom and sidewall of the capacitor trench 184. The insulating layer is used to insulate and isolate the substrate 100 and the trench capacitor structure.
[0057] Reference is made to Figure 12 As shown, a plurality of trench capacitor structures 180 are formed in the capacitor trenches 184 and on the surface of the oxide layer 170. For the purpose of brevity, only one trench capacitor structure 180 is shown in the figure, and in practice, the number of the plurality of trench capacitor structures 180 can be set according to the requirement. The trench capacitor structure is a common structure in the semiconductor field, and thus its specific formation process is not described here.
[0058] In some embodiments of the present application, the trench capacitor structure 180 comprises a first electrode plate 181, a capacitor dielectric layer 182, and a second electrode plate 183. It is to be noted that the present application here only takes the simplest three-layer capacitor structure as an example, and in practice, a capacitor structure with more electrode plates and capacitor dielectric layers can also be formed according to the requirement.
[0059] In some embodiments of the present application, the material of the first electrode plate 181 and the second electrode plate 183 comprises titanium nitride. The material of the capacitor dielectric layer 182 can comprise ZrO2, HfO2, Al2O3, and other high-dielectric-constant dielectric materials.
[0060] Reference is made to Figure 13 As shown, a third dielectric layer 190 covering the oxide layer 170 and the trench capacitor structure 180 is formed on the surface of the oxide layer 170, and a plurality of second metal connection structures 191 electrically connecting the TSV structure 110 and the trench capacitor structure 180 (specifically electrically connecting the first electrode plate 181 and the second electrode plate 183 thereof) are formed in the third dielectric layer 190.
[0061] In some embodiments of the present application, the material of the third dielectric layer 190 comprises silicon oxide or silicon nitride, and other insulating dielectric materials.
[0062] In some embodiments of the present application, the material of the second metal connection structure 191 comprises copper or tungsten, and other metal materials or other conductive materials.
[0063] Reference is made to Figure 14As shown, a fourth dielectric layer 200 is formed on the surface of the third dielectric layer 190, and a plurality of second metal pads 201 electrically connected to the plurality of second metal connection structures 191 are formed in the fourth dielectric layer 200. The number and position of the plurality of second metal pads 201 correspond to those of the plurality of second metal connection structures 191.
[0064] In some embodiments of the present application, the material of the fourth dielectric layer 200 includes an insulating dielectric material such as silicon oxide or silicon nitride.
[0065] In some embodiments of the present application, the surface of the plurality of second metal pads 201 is higher than the surface of the fourth dielectric layer 200.
[0066] In some embodiments of the present application, the material of the plurality of second metal pads 201 includes a metal material such as copper or aluminum.
[0067] Reference Figure 15 As shown, a second passivation layer 210 is formed on the surface of the second metal pad 201 to expose a portion of the second metal pad 201. The exposed second metal pad 201 is used for subsequent electrical connection and other processes when the adapter plate is bonded to other wafers.
[0068] In some embodiments of the present application, the material of the second passivation layer 210 includes an insulating dielectric material such as silicon oxide or silicon nitride.
[0069] In the technical solution of the present application, some elements (such as the active device 103 and the resistor 122 in the present application) in the device wafer in the conventional process and packaging structure are placed in the adapter plate. The unused space in the adapter plate is utilized to improve the integration of the module device and achieve a good processing yield.
[0070] The present application provides an adapter plate and a forming method thereof. The logic, storage, radio frequency, analog and power devices are separated, and some elements with larger node or mixed process are placed in the adapter plate. The mature process compatible process method is used for preparation, the integration of the module device is improved, and a good processing yield is achieved.
[0071] The embodiments of the present application also provide an adapter plate, which will be described below with reference to Figure 15As shown, the semiconductor device includes: a substrate 100 having an active device 103 formed therein, the substrate 100 including a first surface 10 and a second surface 20, the substrate 100 further having a TSV structure 110 formed therethrough; a first dielectric layer 120 located on the first surface 10 of the substrate 100, the first dielectric layer 120 having a plurality of first metal connection structures 121 formed therein, each of the first metal connection structures 121 electrically connecting the TSV structure 110 and the active device 103; an oxide layer 170 located on the second surface 20 of the substrate 100; a plurality of capacitor trenches 184 extending through the oxide layer 170 and into the substrate 100 at the second surface 20 of the substrate 100; an insulating layer (not shown) located at the bottom and sidewalls of the capacitor trenches 184; a plurality of trench capacitor structures 180 located in the capacitor trenches 184 and on the surface of the oxide layer 170; and a third dielectric layer 190 located on the surface of the oxide layer 170, the third dielectric layer 190 covering the oxide layer 170 and the trench capacitor structures 180, the third dielectric layer 190 having a plurality of second metal connection structures 191 formed therein, each of the second metal connection structures 191 electrically connecting the TSV structure 110 and the trench capacitor structures 180.
[0072] Reference Figure 15 As shown, in some embodiments of the present application, the substrate 100 includes a semiconductor substrate 101 and an interlayer dielectric layer 102 located on the surface of the semiconductor substrate 101, the surface of the interlayer dielectric layer 102 being the first surface 10 of the substrate 100, the active device 103 being located in the semiconductor substrate 101 and the interlayer dielectric layer 102, and the interlayer dielectric layer 102 further having a contact structure 104 formed therein, the contact structure 104 electrically connecting the active device 103.
[0073] In some embodiments of the present application, the material of the semiconductor substrate 101 includes (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, etc.; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or indium gallium phosphide, etc.; or (iv) a combination thereof.
[0074] In some embodiments of the present application, the thickness of the semiconductor substrate 101 is 35 to 55 microns.
[0075] In some embodiments of the present application, the material of the interlayer dielectric layer 102 includes silicon oxide.
[0076] In some embodiments of the present application, the active device 103 comprises a FINFET device or the like. The technical solution of the present application is to separate logic, storage, radio frequency, analog and power devices, and to place some components with larger nodes or greater impact of mixed processes (such as the active device 103 in the present application) into the adapter board. Therefore, the active device 103 placed in the adapter board in the present application can select any suitable active device according to actual needs. It should be noted that since the type of the active device 103 is selected according to needs, the structure of the active device 103 is not shown in the drawings of the present application, but is simply replaced by a block to show the position of the active device 103. The active device 103 in the present application can be a structure well known to those skilled in the art. For example, taking a CMOS transistor as an example, the active device 103 can include a source and a drain located in the semiconductor substrate 101 and a gate located in the interlayer dielectric layer 102, and the contact structure 104 can be multiple and respectively electrically connected to the source, the drain and the gate.
[0077] In some embodiments of the present application, the number of the active device 103 can be multiple, which is not limited in the present application. In practice, a proper number of active devices 103 can be arranged according to the volume and space of the substrate 100.
[0078] In some embodiments of the present application, the material of the contact structure 104 comprises copper or tungsten or the like.
[0079] With reference to Figure 15 As shown, in some embodiments of the present application, the position of the TSV structure 110 is located at the two side edges of the substrate 100, so as to leave more space in the middle of the substrate 100 to accommodate more active devices 103.
[0080] In some embodiments of the present application, the diameter of the TSV structure 110 is 20 to 25 microns, and the depth of the TSV structure is 40 to 60 microns.
[0081] With reference to Figure 15 As shown, the first metal connection structure 121 is electrically connected to the active device 103 by electrically connecting the contact structure 104. And the first metal connection structure 121 is independent of each other.
[0082] In some embodiments of the present application, the material of the first dielectric layer 120 comprises silicon oxide or silicon nitride or the like insulating dielectric material.
[0083] In some embodiments of the present application, the material of the first metal connection structure 121 comprises copper or tungsten or other metal materials or other conductive materials.
[0084] In some embodiments of the present application, the first dielectric layer 120 further forms a resistor 122 and part of the first metal connection structure 121 electrically connecting the resistor 122. The resistor 122 is, for example, a thin-film resistor made of CrSi or TaN, etc. The technical solution of the present application is to separate logic, storage, radio frequency, analog and power devices, and to put some components with larger nodes or greater impact of mixed processes (such as the resistor 122 herein) into a conversion board. Therefore, the resistor 122 herein placed in the conversion board can also select other any suitable resistance type according to actual needs.
[0085] With reference to Figure 15 As shown, the surface of the first dielectric layer 120 further forms a second dielectric layer 130, and the second dielectric layer 130 forms a plurality of first metal pads 131 electrically connecting the plurality of first metal connection structures 121. The number and position of the plurality of first metal pads 131 correspond to the plurality of first metal connection structures 121.
[0086] In some embodiments of the present application, the material of the second dielectric layer 130 includes an insulating dielectric material such as silicon oxide or silicon nitride.
[0087] In some embodiments of the present application, the surface of the plurality of first metal pads 131 is higher than the surface of the second dielectric layer 130.
[0088] In some embodiments of the present application, the material of the plurality of first metal pads 131 includes a metal material such as copper or aluminum.
[0089] With reference to Figure 15 As shown, the surface of the first metal pad 131 forms a first passivation layer 141.
[0090] In some embodiments of the present application, the material of the first passivation layer 141 includes an insulating dielectric material such as silicon oxide or silicon nitride.
[0091] With reference to Figure 15 As shown, the surface of the first passivation layer 141 forms a solder ball 140 electrically connecting the first metal pad 131 through the first passivation layer 141.
[0092] With reference to Figure 15 As shown, the surface of the second dielectric layer 130 forms a bonding dielectric layer 150 covering the second dielectric layer 130, the first passivation layer 141 and the solder ball 140.
[0093] In some embodiments of the present application, the material of the bonding dielectric layer 150 includes an insulating dielectric material such as silicon oxide or silicon nitride.
[0094] With reference toFigure 15 As shown, the bonding medium layer 150 is formed on the surface of the carrier wafer 160.
[0095] In some embodiments of the present application, the carrier wafer 160 can be a semiconductor wafer, such as a silicon wafer, or the like; or a glass wafer, or the like commonly used in the field of semiconductor packaging.
[0096] Continuing to refer to Figure 15 As shown, the oxide layer 170 covers the second surface 20 of the substrate 100 and the TSV structure 110.
[0097] In some embodiments of the present application, the material of the oxide layer 170 includes an insulating medium material, such as silicon oxide, or the like. The thickness of the oxide layer 170 is 50 to 100 nanometers.
[0098] In some embodiments of the present application, the size of the capacitor trench 184 is set according to the size of the trench capacitor structure as required.
[0099] In some embodiments of the present application, the insulating layer is used to insulate and isolate the substrate 100 and the trench capacitor structure 180.
[0100] Continuing to refer to Figure 15 As shown, only one trench capacitor structure 180 is shown here for the purpose of brevity, and in fact, the number of the plurality of trench capacitor structures 180 can be set as required.
[0101] In some embodiments of the present application, the trench capacitor structure 180 includes a first electrode plate 181, a capacitor medium layer 182, and a second electrode plate 183. It should be noted that only the simplest three-layer capacitor structure is taken as an example here, and in fact, a capacitor structure with more electrode plates and capacitor medium layers can also be formed as required.
[0102] In some embodiments of the present application, the material of the first electrode plate 181 and the second electrode plate 183 includes titanium nitride. The material of the capacitor medium layer 182 can include ZrO2, HfO2, Al2O3, or the like high dielectric constant dielectric material.
[0103] In some embodiments of the present application, the material of the third medium layer 190 includes an insulating medium material, such as silicon oxide or silicon nitride, or the like.
[0104] In some embodiments of the present application, the material of the second metal connection structure 191 includes a metal material, such as copper or tungsten, or the like, or other conductive material.
[0105] Continuing to refer to Figure 15As shown, the third dielectric layer 190 is formed with a fourth dielectric layer 200 on the surface thereof, and the fourth dielectric layer 200 is formed with a plurality of second metal pads 201 electrically connected to the plurality of second metal connection structures 191. The number and position of the plurality of second metal pads 201 correspond to the plurality of second metal connection structures 191.
[0106] In some embodiments of the present application, the material of the fourth dielectric layer 200 includes an insulating dielectric material such as silicon oxide or silicon nitride.
[0107] In some embodiments of the present application, the surface of the plurality of second metal pads 201 is higher than the surface of the fourth dielectric layer 200.
[0108] In some embodiments of the present application, the material of the plurality of second metal pads 201 includes a metal material such as copper or aluminum.
[0109] Continuing to refer to As shown, the second metal pads 201 are formed with a second passivation layer 210 on the surface thereof, exposing a portion of the second metal pads 201. The exposed second metal pads 201 are used for subsequent processes such as electrical connection when bonding with other wafers.
[0110] In some embodiments of the present application, the material of the second passivation layer 210 includes an insulating dielectric material such as silicon oxide or silicon nitride.
[0111] In the technical solution of the present application, some elements (such as the active device 103 and the resistor 122 in the present application) in the device wafer in the conventional process and packaging structure are placed in the adapter plate, and the unused space in the adapter plate is utilized, so that the integration of the module device is improved, and a good processing yield is achieved. Moreover, the process flow of the present application is fully compatible with the mature process.
[0112] The present application provides an adapter plate and a forming method thereof, which can separate logic, storage, radio frequency, analog and power devices, place some elements with larger nodes or greater mixed process impact into the adapter plate, and fully utilize the process flow method compatible with the mature process to prepare, so that the integration of the module device is improved, and a good processing yield is achieved.
[0113] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content can be presented only in an exemplary manner and can not be limiting. Although it is not explicitly stated here, those skilled in the art can understand that the present application intends to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of the present application.
[0114] It should be understood that the term "and / or" as used herein encompasses all possible combinations of one or more of the associated listed items. It should be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "coupled" to another element, it can be directly on or coupled to the other element or intervening elements can also be present.
[0115] Similarly, it should be understood that, when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, the term "directly on" means that there are no intervening elements present. It will also be understood that, when a term is used in this specification such as "comprises", "comprising", "includes", "including", or "contains", it is taken to indicate, in addition to the stated features, that other features can also be present. Such terms encompass the terms "comprising", "comprises", "includes", "including", and "contains", as well as "containing".
[0116] It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or same reference designators denote the same elements throughout the specification.
[0117] In addition, the present description describes example embodiments by reference to idealized illustrative cross-sectional and / or plan and / or elevation views. Consequently, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, the example embodiments should not be construed as limited to the precise shapes and regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the example embodiments.
Claims
1. A method of forming a transition plate, characterized by, The method comprises: providing a substrate, the substrate having a first surface and a second surface, and having a TSV structure formed therein; forming a first dielectric layer on the first surface of the substrate, the first dielectric layer having a plurality of first metal connection structures formed therein, each of the first metal connection structures electrically connecting the TSV structure and the active device; forming an oxide layer on the second surface of the substrate; forming a plurality of capacitor trenches in the second surface of the substrate, each of the capacitor trenches extending through the oxide layer and into the substrate; forming an insulating layer on the bottom and sidewalls of the capacitor trenches; forming a plurality of trench capacitors in the capacitor trenches and on the surface of the oxide layer; forming a third dielectric layer on the surface of the oxide layer, the third dielectric layer covering the oxide layer and the trench capacitors, the third dielectric layer having a plurality of second metal connection structures formed therein, each of the second metal connection structures electrically connecting the TSV structure and the trench capacitors. The substrate comprises a semiconductor substrate and an interlayer dielectric layer on the surface of the semiconductor substrate, the surface of the interlayer dielectric layer being the first surface of the substrate, the active device being formed in the semiconductor substrate and the interlayer dielectric layer, and a contact structure being formed in the interlayer dielectric layer and electrically connecting the active device, the first metal connection structure electrically connecting the contact structure.
2. The method of claim 1, wherein The first dielectric layer further has a resistor formed therein, and a portion of the first metal connection structure electrically connecting the resistor.
3. The method of claim 1, wherein The method further comprises:
4. The method of claim 1, wherein forming a second dielectric layer on the surface of the first dielectric layer, the second dielectric layer having a plurality of first metal pads formed therein, each of the first metal pads electrically connecting one of the plurality of first metal connection structures; forming a first passivation layer on the surface of the first metal pads; forming a solder ball on the surface of the first passivation layer, the solder ball electrically connecting the first metal pads through the first passivation layer; forming a bonding dielectric layer on the surface of the second dielectric layer, the bonding dielectric layer covering the second dielectric layer, the first passivation layer, and the solder ball; forming a carrier wafer on the surface of the bonding dielectric layer. Before forming the oxide layer on the second surface of the substrate, the method further comprises: thinning the second surface of the substrate.
5. The method of claim 1, wherein The method further comprises:
6. The method of claim 1, wherein forming a fourth dielectric layer on the surface of the third dielectric layer, the fourth dielectric layer having a plurality of second metal pads formed therein, each of the second metal pads electrically connecting one of the plurality of second metal connection structures; forming a second passivation layer on the surface of the second metal pads, the second passivation layer exposing a portion of each of the second metal pads. The method comprises:
7. An adapter plate, characterized by providing a substrate, the substrate having a first surface and a second surface, and having a TSV structure formed therein; forming a first dielectric layer on the first surface of the substrate, the first dielectric layer having a plurality of first metal connection structures formed therein, each of the first metal connection structures electrically connecting the TSV structure and the active device; forming an oxide layer on the second surface of the substrate; forming a plurality of capacitor trenches in the second surface of the substrate, each of the capacitor trenches extending through the oxide layer and into the substrate; forming an insulating layer on the bottom and sidewalls of the capacitor trenches; forming a plurality of trench capacitors in the capacitor trenches and on the surface of the oxide layer; A third dielectric layer is located on the surface of the oxide layer to cover the oxide layer and the trench capacitor structure, and a plurality of second metal connection structures electrically connected to the TSV structures and the trench capacitor structure are formed in the third dielectric layer.
8. The adapter plate of claim 7, wherein, The substrate includes a semiconductor substrate and an interlayer dielectric layer located on the surface of the semiconductor substrate, and the surface of the interlayer dielectric layer is a first surface of the substrate. The active device is located in the semiconductor substrate and the interlayer dielectric layer, and a contact structure electrically connected to the active device is formed in the interlayer dielectric layer. The first metal connection structure is electrically connected to the contact structure.
9. The adapter plate of claim 7, wherein, The first dielectric layer further includes a resistor and part of the first metal connection structure electrically connected to the resistor.
10. The adapter plate of claim 7, wherein, Further comprising: A second dielectric layer is located on the surface of the first dielectric layer, and a plurality of first metal pads electrically connected to the plurality of first metal connection structures are formed in the second dielectric layer. A first passivation layer is located on the surface of the first metal pad, and a solder ball is located on the surface of the first passivation layer to penetrate the first passivation layer and electrically connect the first metal pad. A bonding dielectric layer is located on the surface of the second dielectric layer to cover the second dielectric layer, the first passivation layer and the solder ball. A carrier wafer is located on the surface of the bonding dielectric layer.
11. The adapter plate of claim 7, wherein, Further comprising: A fourth dielectric layer is located on the surface of the third dielectric layer, and a plurality of second metal pads electrically connected to the plurality of second metal connection structures are formed in the fourth dielectric layer. A second passivation layer is located on the surface of the second metal pad to expose part of the second metal pad.