Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, and the method comprises the steps: forming a dielectric layer on a substrate, and etching the dielectric layer to form a channel. A barrier layer is formed on the surface of a dielectric layer, impurities are adsorbed on the surface of the barrier layer, and the impurities are etching byproducts formed when the dielectric layer is etched and can be volatilized and adsorbed on the surface of the barrier layer in the process of forming the barrier layer. The high-energy ions are controlled by the first bias voltage to remove the impurities, that is, the ions are accelerated to have high energy by using the first bias voltage to form the high-energy ions, and then the high-energy ions are utilized to bombard the surface of the barrier layer to remove the impurities. A transition layer is formed while impurities are removed, then a seed layer is formed, and the seed layer covers the transition layer. The high-energy ions are controlled by the first bias voltage to remove the impurities, so that the influence of the impurities on the transition layer and the seed layer can be reduced, and the performance of the semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a manufacturing method of semiconductor structure. BACKGROUND

[0002] In the current semiconductor manufacturing process, deposition and etching process of a dielectric layer are included. In order to reduce the dielectric constant of the semiconductor structure, an ultra-low dielectric constant material is usually used as the dielectric layer. The ultra-low dielectric constant material is usually a porous structure, which can accommodate water vapor or organic matter, etc. Therefore, when etching the ultra-low dielectric constant material, the etching byproducts such as organic matter or small molecules generated during etching may be adsorbed into the porous structure and cannot be completely removed. These etching byproducts will continue to volatilize in subsequent other processes, thereby being adsorbed on the surface of the film layer formed by other processes, and then affecting the performance of the film layer formed by other processes, and finally leading to the decline of the overall performance of the semiconductor structure. SUMMARY

[0003] Therefore, the purpose of the present application is to provide a semiconductor structure and a manufacturing method thereof, which can remove the etching byproducts adsorbed on the surface of the film layer formed by other processes, reduce the continuous influence of the etching byproducts, and thus improve the performance of the semiconductor structure.

[0004] The present application provides a manufacturing method of semiconductor structure, which comprises:

[0005] providing a substrate, forming a dielectric layer on the substrate, and etching the dielectric layer to form a channel;

[0006] forming a barrier layer on the surface of the dielectric layer, the barrier layer covering at least the bottom and sidewall of the channel;

[0007] controlling high-energy ion bombardment on the surface of the barrier layer with a first bias voltage, and forming a transition layer on the surface of the barrier layer at the same time;

[0008] forming a seed layer, the seed layer covering at least the transition layer.

[0009] Optionally, the transition layer and the seed layer both comprise an element corresponding to the high-energy ion.

[0010] Optionally, the element corresponding to the high-energy ion comprises copper, tungsten or molybdenum.

[0011] Optionally, the forming of the seed layer comprises:

[0012] forming a first seed layer with a second bias voltage, the thickness of the first seed layer on the bottom of the channel being greater than the thickness of the first seed layer on the sidewall of the channel;

[0013] The high-energy ions bombard the first seed layer under a third bias voltage to form a second seed layer, the thickness of the second seed layer at the bottom of the channel and the thickness of the second seed layer at the sidewall of the channel are substantially equal; wherein the power range of the third bias voltage is greater than the power range of the second bias voltage.

[0014] Optionally, the power range of the first bias voltage is greater than the power range of the second bias voltage, and the power range of the first bias voltage is greater than or equal to the power range of the third bias voltage.

[0015] Optionally, the power range of the first bias voltage is 650W-800W, the power range of the second bias voltage is 120W-200W, and the power range of the third bias voltage is 600W-800W.

[0016] Optionally, the method further comprises: forming a conductive layer on the surface of the seed layer, the conductive layer filling the channel.

[0017] Optionally, the forming a barrier layer on the surface of the dielectric layer comprises: sequentially forming a first barrier layer and a second barrier layer on the surface of the dielectric layer, the second barrier layer covering the first barrier layer; wherein the first barrier layer is a metal nitride layer, the second barrier layer is a metal layer, and the first barrier layer and the second barrier layer contain the same metal element.

[0018] The present application provides a semiconductor structure, which is characterized by being prepared by the method according to any one of the preceding embodiments, and the structure comprises:

[0019] a substrate, and a dielectric layer on the surface of the substrate, a channel being formed in the dielectric layer;

[0020] a barrier layer covering at least the bottom and the sidewall of the channel;

[0021] a transition layer covering at least the surface of the barrier layer;

[0022] a seed layer covering at least the surface of the transition layer.

[0023] Optionally, the transition layer comprises at least a first metal element same as the barrier layer, and comprises a second metal element same as the seed layer, the first metal element and the second metal element being different.

[0024] The application provides a manufacturing method of a semiconductor structure, the method comprising: providing a substrate, forming a dielectric layer on the substrate, etching the dielectric layer to form a channel, and forming an etching byproduct in the dielectric layer during the etching process. A barrier layer is formed on the surface of the dielectric layer, the barrier layer covering the bottom and sidewall of the channel, and the surface of the barrier layer possibly adsorbing impurities, the impurities being the etching byproduct formed during the etching of the dielectric layer and volatilized to be adsorbed on the surface of the barrier layer during the process of forming the barrier layer. The surface of the barrier layer is bombarded by high-energy ions under the control of a first bias voltage, that is, the ions are accelerated to have higher energy by the first bias voltage to form high-energy ions, and then the surface of the barrier layer is bombarded by the high-energy ions to remove the impurities. The transition layer is formed on the barrier layer while the impurities are removed, and then a seed layer is formed, the seed layer covering the transition layer. The application removes the impurities by the high-energy ions under the control of the first bias voltage, and thus the influence of the impurities on the transition layer and the seed layer is reduced, and the performance of the semiconductor structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0026] Figure 1 A manufacturing process schematic diagram of a semiconductor structure is shown;

[0027] Figure 2 A flowchart schematic diagram of a manufacturing method of a semiconductor structure provided by an embodiment of the present application is shown;

[0028] Figures 3-9 A structure schematic diagram of a semiconductor structure manufactured by a manufacturing method of a semiconductor structure provided by an embodiment of the present application is shown;

[0029] Figure 10 A structure schematic diagram of a semiconductor structure provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] In order to make the personnel in the technical field better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort are within the scope of protection of the present application.

[0031] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced without the specific details. In other instances, well-known methods have not been described in detail in order not to unnecessarily obscure aspects of the present application.

[0032] The present application is described in detail below with reference to the accompanying drawings. In the description below, the cross-sectional views of the device structure are partially enlarged without the general scale for the convenience of illustration, and the schematic views are only examples and should not limit the scope of protection of the present application. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in actual production.

[0033] To reduce the dielectric constant of the semiconductor structure, an ultra-low dielectric constant material is usually used as the dielectric layer. The ultra-low dielectric constant material is usually a porous structure, which can accommodate water vapor or organic matter, etc. Therefore, when etching the ultra-low dielectric constant material or when wet cleaning the dielectric layer, by-products 10, which can include etching by-products or cleaning by-products, such as fluorine-containing organic matter, small molecule by-products, etc. can be adsorbed into the porous structure and cannot be completely removed. These by-products 10 continue to volatilize in subsequent other processes, such as in the process of forming the barrier layer 20, which causes the by-products 10 to be adsorbed on the surface of the barrier layer 20, as shown, thereby affecting the performance of the barrier layer 20, causing the adhesion between the barrier layer 20 and the seed layer 30 formed on the surface of the barrier layer 20 to decrease, and the by-products 10 also pollute the seed layer 30, causing the effective electroplating deposition to be unable to be formed when the conductive layer 40 is formed on the seed layer 30 by using the electroplating process, and holes 50 are formed in the conductive layer 40, ultimately causing the overall performance of the semiconductor structure to decrease. Figure 1 As shown, thereby affecting the performance of the barrier layer 20, causing the adhesion between the barrier layer 20 and the seed layer 30 formed on the surface of the barrier layer 20 to decrease, and the by-products 10 also pollute the seed layer 30, causing the effective electroplating deposition to be unable to be formed when the conductive layer 40 is formed on the seed layer 30 by using the electroplating process, and holes 50 are formed in the conductive layer 40, ultimately causing the overall performance of the semiconductor structure to decrease.

[0034] Based on this, the embodiments of the present application provide a semiconductor structure manufacturing method. A first bias voltage is used to control high-energy ions to remove impurities, that is, the ions are accelerated to have a higher energy by using the first bias voltage to form high-energy ions, and then the surface of the barrier layer is bombarded by the high-energy ions to remove the impurities. The transition layer is formed at the same time as the impurities are removed, and then the seed layer is formed, which covers the transition layer. By using the first bias voltage to control the high-energy ions to remove the impurities, the present application can reduce the influence of the impurities on the transition layer and the seed layer, thereby improving the performance of the semiconductor structure.

[0035] In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0036] Referring to Figure 2 , the figure is a flowchart of a semiconductor structure manufacturing method provided by the embodiments of the present application.

[0037] The method for manufacturing a semiconductor structure provided in this embodiment includes the following steps:

[0038] S101, providing a substrate, forming a dielectric layer on the substrate, and etching the dielectric layer to form a channel.

[0039] In an embodiment of the present application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate. The substrate 110 may also be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.

[0040] As an example, a highly doped well region can be formed by implanting impurities into a bulk silicon substrate and then annealing to achieve the desired well depth. The doping type of the substrate 110 varies for different device types. For a P-type semiconductor structure, the highly doped well region is an N-well, and the implanted impurities are n-type impurity ions, such as phosphorus (P) ions. For an N-type semiconductor structure, the highly doped well region is a p-well, and the implanted impurities are p-type impurity ions, such as boron (B) ions.

[0041] A dielectric layer 120 can be formed on substrate 110 using a deposition process. The material of dielectric layer 120 is an ultra-low dielectric constant material, which can reduce capacitance-resistance delay (RC delay). Dielectric layer 120 is also a porous material. For example, dielectric layer 120 can be made of SiCOH, which has a good affinity for organic matter. Water vapor or organic matter may be adsorbed in porous materials.

[0042] The dielectric layer 120 can be etched to form a channel 130, referring to Figure 3 As shown, channel 130 can be filled with metal material to form metal interconnects. When etching dielectric layer 120, a dry etching process can be used, which forms etching byproducts. These etching byproducts are impurities 140, which are adsorbed in the porous material, that is, impurities 140 are adsorbed in dielectric layer 120. Impurities 140 may subsequently volatilize during other processes and adhere to the surfaces of other film layers. Channel 130 can be a via or a trench.

[0043] S102, forming a barrier layer on the surface of the dielectric layer, wherein the barrier layer at least covers the bottom and sidewalls of the channel.

[0044] With the continuous advancement of semiconductor manufacturing processes, the material of metal interconnects can be changed from aluminum to copper to reduce the delay caused by the resistance of metal interconnects. Copper also has better electromigration resistance than aluminum. Considering that copper cannot be etched to form metal interconnects like aluminum, the copper Damascus process is used to form copper-based metal interconnects.

[0045] In practical applications, the material of the metal interconnection line can also be tungsten (W) or molybdenum (Mo).

[0046] In the embodiments of the present application, whether the copper-based metal interconnection line is formed by using the copper damascene process or the tungsten or molybdenum-based metal interconnection line is formed by using other processes, the barrier layer 150 can be first formed on the surface of the dielectric layer 120, the barrier layer 150 at least covering the bottom and sidewall of the channel 130, as shown in the figure, so as to subsequently form the seed layer of copper, tungsten or molybdenum on the barrier layer 150. Figure 4

[0047] Specifically, the barrier layer 150 can be formed by using physical vapor deposition. Since the impurities 140 are adsorbed in the dielectric layer 120, the impurities 140 can volatilize in the process of forming the barrier layer 130 and then be adsorbed on the surface of the barrier layer 150, that is, the impurities 140 are adsorbed on the surface of the barrier layer 150. The impurities 140 can cause the adhesion between the barrier layer 150 and the seed layer of copper, tungsten or molybdenum to decrease when the seed layer of copper, tungsten or molybdenum is subsequently formed on the barrier layer 150.

[0048] In the embodiments of the present application, the barrier layer 150 includes a first barrier layer and a second barrier layer. Therefore, the barrier layer 150 is formed on the surface of the dielectric layer 120, that is, the first barrier layer and the second barrier layer are sequentially formed on the surface of the dielectric layer 120, and the second barrier layer covers the first barrier layer. The first barrier layer is a metal nitride layer, the second barrier layer is a metal layer, and the first barrier layer and the second barrier layer include the same metal element.

[0049] As an example, the material of the first barrier layer is tantalum nitride or titanium nitride, and the material of the second barrier layer is tantalum or titanium. S103, the surface of the barrier layer is bombarded by high-energy ions under the control of the first bias, and a transition layer is formed on the surface of the barrier layer.

[0050] In the embodiments of the present application, in order to remove the impurities 140 adsorbed on the surface of the barrier layer 150, the high-energy ions can be used to remove the impurities 140 under the control of the first bias, that is, the ions are accelerated to have higher energy under the control of the first bias to form high-energy ions, and then the surface of the barrier layer 150 is bombarded by the high-energy ions to remove the impurities 140.

[0051] Specifically, the power range of the first power can be 650W-800W. That is, the power of the first bias is high, and the ions have higher energy under the first bias. If the power of the first bias is too high, the other film layers can be damaged in the process of removing the impurities. If the power of the first bias is too low, the impurities 140 can not be completely removed, resulting in the residual impurities 140.

[0052] ​In practical applications, the high-energy ions are usually incident in a direction perpendicular to the surface of the barrier layer 150 under the first bias, thus mainly directly cleaning the impurities 140 located on the planar barrier layer 150 and on the bottom of the channel 130. As for the impurities 140 on the sidewall of the channel 130, the barrier layer 150 on the bottom of the channel 130 is bombarded by the high-energy ions, the barrier layer 150 on the bottom of the channel 130 is sputtered by the high-energy ions to particles, the particles are sputtered to the sidewall of the channel 130, thus removing the impurities 140 on the sidewall of the channel 130, that is, the impurities 140 on the sidewall of the channel 130 are indirectly removed by the high-energy ions.

[0053] In the embodiments of the present application, considering that the effects of removing the impurities 140 and the time points of forming the transition layer 160 are different due to different materials of the high-energy ions, the following will be specifically introduced:

[0054] As a possible implementation manner, the transition layer 160 does not include the element corresponding to the high-energy ions. The high-energy ions are argon ions, and the material of the transition layer 160 includes copper, tungsten or molybdenum. That is, the impurities 140 are removed by argon ions, as shown in FIG. 2, and then the transition layer 160 is formed on the surface of the barrier layer 150, as shown in FIG. 3. Figure 5 Figure 6

[0055] As an example, considering that the barrier layer 150 includes a first barrier layer and a second barrier layer, the transition layer 160 directly contacts the second barrier layer, and since the transition layer 160 is formed on the surface of the second barrier layer after the impurities 140 are removed, the transition layer 160 fills the gap formed after the second barrier layer removes the impurities 140, and the material of the transition layer 160 not only includes copper, tungsten or molybdenum, but also includes the material of the second barrier layer, i.e., tantalum or titanium, that is, the material of the transition layer 160 is tantalum copper, tantalum tungsten or tantalum molybdenum, or the material of the transition layer 160 is titanium copper, titanium tungsten or titanium molybdenum.

[0056] As another possible implementation manner, the transition layer 160 includes the element corresponding to the high-energy ions, that is, the material of the transition layer 160 is at least partially the same as the material of the high-energy ions, and the element corresponding to the high-energy ions can include copper, tungsten or molybdenum. For example, the high-energy ions are copper ions, and the material of the transition layer 160 includes copper, for another example, the high-energy ions are tungsten ions, and the material of the transition layer 160 includes tungsten, and for another example, the high-energy ions are molybdenum ions, and the material of the transition layer 160 includes molybdenum. That is, the impurities 140 are removed by copper ions, tungsten ions or molybdenum ions, and in the process of removing the impurities 140, the copper ions, tungsten ions or molybdenum ions also form the transition layer 160 on the surface of the barrier layer 150 at the same time, that is, the copper ions, tungsten ions or molybdenum ions are used to simultaneously etch and remove the impurities 140 and form the transition layer 160, as shown in FIG. 4. Figure 6 ​​As shown, the damage to the surface of the barrier layer 150 is less. Compared with etching using argon ions, the embodiment uses copper ions, tungsten ions or molybdenum ions to etch and clean the wafer surface, and the etching process of copper ions, tungsten ions or molybdenum ions is etching while depositing, so the damage to the wafer surface is much smaller than that of argon ion etching.

[0057] As an example, considering that the barrier layer 150 includes a first barrier layer and a second barrier layer, the transition layer 160 is directly in contact with the second barrier layer, and since the transition layer 160 is formed on the surface of the second barrier layer while removing the impurities 140, the copper ions, tungsten ions or molybdenum ions fill the gap formed after the second barrier layer removes the impurities 140 while removing the impurities 140, and the material of the transition layer 160 at this time includes not only copper, tungsten or molybdenum, but also the material of the second barrier layer, i.e. tantalum, i.e. the material of the transition layer 160 is tantalum copper, tantalum tungsten or tantalum molybdenum.

[0058] S104, forming a seed layer.

[0059] In the embodiment of the present application, after the impurities 140 are removed by high-energy ions, a seed layer 170 can be formed on the surface of the transition layer 160, that is, the seed layer 170 covers at least the transition layer 160. The seed layer 170 can serve as a base film layer for the subsequent formation of the conductive layer 180, making it easier to form the conductive layer 180.

[0060] Considering that when forming the seed layer 170, a film layer with uniform thickness needs to be formed, it can be formed in two processes, the first process forms a first seed layer 171, and the second process forms a second seed layer, which will be described in detail below:

[0061] The first seed layer 171 is formed by using a second bias, and reference is made to FIG. 4. Figure 7 As shown, the thickness of the first seed layer 171 at the bottom of the channel 130 is greater than the thickness at the sidewall of the channel 130, that is, when depositing the first seed layer 171 by using the second bias, the thickness of the bottom of the channel 130 is greater than the thickness of the sidewall of the channel 130, which can ensure that the bottom of the channel 130 and the first seed layer 171 on the plane have a certain thickness, meeting the needs of the subsequent formation of the conductive layer 180. The power range of the second bias is lower than that of the first bias. The power range of the second bias and the power range of the first bias do not overlap, and the maximum value of the power range of the second bias is less than the minimum value of the power range of the first bias.

[0062] As an example, the power range of the second power is 120W-200W.

[0063] The third bias is used to control the high-energy ion bombardment of the first seed layer to form a second seed layer, and reference is made to FIG. 5. Figure 8As shown, the thickness of the seed layer 170 at the bottom of the channel 130 and the thickness at the side wall of the channel 130 are less than the thickness threshold, that is, after the second seed layer is formed using the third bias voltage, the thickness of the entire seed layer 170 at the side wall of the channel 130 and the thickness at the bottom of the channel 130 are relatively small, the thickness is basically equal, and the thickness is relatively uniform.

[0064] The power range of the third bias is greater than the power range of the second bias, and the power range of the first bias is greater than or equal to the power range of the third bias. In this way, the third bias can also be used to accelerate ions to form high-energy ions, thereby bombarding the surface of the first seed layer 171. The power range of the third bias is, for example, 600W to 800W. In this way, after reaching the bottom of the channel 130, the high-energy ions can bombard the surface of the first seed layer 171 and sputter particles of the first seed layer 171. The ions are sputtered to the sidewalls of the channel 130, thereby increasing the thickness of the seed layer 170 on the sidewalls of the channel 130, thereby achieving uniform thickness of the entire seed layer 170 at the sidewalls of the channel 130 and at the bottom of the channel 130.

[0065] In the embodiments of the present application, considering that the seed layer 170 is formed on the transition layer 160, the material of the transition layer 160 includes the material of the seed layer 170, and the transition layer 160 includes the element corresponding to the high-energy ions, that is, the seed layer 170 also includes the element corresponding to the high-energy ions. For example, if the element corresponding to the high-energy ions is copper, then the seed layer 170 includes copper. For another example, if the element corresponding to the high-energy ions is tungsten, then the seed layer 170 includes tungsten. For another example, if the element corresponding to the high-energy ions is molybdenum, then the seed layer 170 includes molybdenum.

[0066] In the embodiment of the present application, after the seed layer 170 is formed, a conductive layer 180 may be formed on the surface of the seed layer 170 by electroplating, and the conductive layer 180 fills the channel 130. Figure 9 As shown, since the impurities 140 are removed by high-energy ions, the influence of the impurities 140 can be avoided, the adhesion between the seed layer 170 and the barrier layer 150 is improved, the electroplating process will not be affected, and the formed conductive layer 180 will not have holes.

[0067] As an example, the material of the first barrier layer is tantalum nitride, the material of the second barrier layer is tantalum, the material of the transition layer 160 is tantalum copper, the material of the seed layer 170 is copper, the material of the conductive layer 180 is copper, and the high-energy ions are copper ions. Then the copper ions are used to remove the impurities 140 adhered to the surface of tantalum. Since the energy of the copper ions is high, the tantalum at the bottom of the channel 130 can be sputtered to the sidewall of the channel 130. Not only the impurities 140 on the sidewall of the channel 130 are removed, but also the transition layer 160 is formed together with the copper ions. Finally, the seed layer 170 is formed on the surface of the transition layer 160. In this way, the film layer structure on the sidewall of the channel 130 is a tantalum nitride / tantalum / tantalum copper / copper stacked structure, which can well improve the adhesion of the seed layer 170 on the sidewall of the channel 130. The adhesion between the copper grown on the cleaned tantalum surface and the tantalum is good. When entering the copper electroplating solution for electroplating, it is not easy to be corroded by the electroplating solution, and a good non-porous electroplated copper can be formed.

[0068] As another example, the material of the first barrier layer is titanium nitride, the material of the second barrier layer is titanium, the material of the transition layer 160 is titanium tungsten, the material of the seed layer 170 is tungsten, the material of the conductive layer 180 is tungsten, and the high-energy ions are tungsten ions. Then the tungsten ions are used to remove the impurities 140 adhered to the surface of titanium. Since the energy of the tungsten ions is high, the titanium at the bottom of the channel 130 can be sputtered to the sidewall of the channel 130. Not only the impurities 140 on the sidewall of the channel 130 are removed, but also the transition layer 160 is formed together with the tungsten ions. Finally, the seed layer 170 is formed on the surface of the transition layer 160. In this way, the film layer structure on the sidewall of the channel 130 is a titanium nitride / titanium / titanium tungsten / tungsten stacked structure, which can well improve the adhesion of the seed layer 170 on the sidewall of the channel 130. The adhesion between the tungsten grown on the cleaned titanium surface and the titanium is good, which is conducive to enhancing the adhesion between the tungsten seed layer and the subsequent formed tungsten seed layer, and forming a good conductive metal interconnection structure.

[0069] As another example, the material of the first barrier layer can be tantalum nitride or titanium nitride, the material of the second barrier layer can be tantalum or titanium, the material of the transition layer 160 can be tantalum molybdenum or titanium molybdenum, the material of the seed layer 170 can be molybdenum, the material of the conductive layer 180 can be molybdenum, and the high-energy ions are molybdenum ions. Then, the impurities 140 attached to the surface of tantalum or titanium are removed by using molybdenum ions. Since the energy of the molybdenum ions is high, the tantalum or titanium at the bottom of the channel 130 can be sputtered to the sidewall of the channel 130. Not only the impurities 140 on the sidewall of the channel 130 are removed, but also the transition layer 160 is formed together with the molybdenum ions. Finally, the seed layer 170 is formed on the surface of the transition layer 160. In this way, the film layer structure on the sidewall of the channel 130 is a tantalum nitride / tantalum / tantalum molybdenum / molybdenum stacked structure or a titanium nitride / titanium / titanium molybdenum / molybdenum stacked structure, which can well improve the adhesion of the seed layer 170 on the sidewall of the channel 130. The adhesion between the molybdenum grown on the cleaned surface of tantalum or titanium and the tantalum or titanium is good, which is conducive to enhancing the adhesion between the molybdenum seed layer and the subsequent molybdenum seed layer, and forming a good conductive metal interconnection structure.

[0070] Based on the manufacturing method of the semiconductor structure provided in the above embodiments, the embodiment of the present application further provides a semiconductor structure, which will be described in detail below with reference to the accompanying drawings.

[0071] Referring to Figure 10 FIG. 1 is a structural schematic diagram of a semiconductor structure provided by an embodiment of the present application.

[0072] The semiconductor structure provided by the embodiment can be prepared by using the manufacturing method described in the above embodiments. The semiconductor structure provided by the embodiment includes a substrate 110, a dielectric layer 120, a channel 130, a barrier layer 150, a transition layer 160, and a seed layer 170.

[0073] The dielectric layer 120 is located on the surface of the substrate 110, and the channel 130 is formed in the dielectric layer 120. The barrier layer 150 covers at least the bottom and sidewall of the channel 130, and the barrier layer 150 is located on the surface of the dielectric layer 120. The transition layer 160 covers at least the surface of the barrier layer 150, and the transition layer 160 is located at least on the bottom and sidewall of the channel 130. The seed layer 170 covers at least the surface of the transition layer 160, and the seed layer 170 is also located at least on the bottom and sidewall of the channel 130.

[0074] In the embodiment of the present application, the transition layer 170 is a transition film layer between the barrier layer 150 and the seed layer 170. Therefore, the transition layer 170 at least includes the same first metal element as the barrier layer 150, and includes the same second metal element as the seed layer 170, and the first metal element and the second metal element are different.

[0075] As an example, the first metal element included in the barrier layer 150 is tantalum, the second metal element included in the seed layer 170 is copper, tungsten or molybdenum, and the material of the transition layer 170 is tantalum copper, tantalum tungsten or tantalum molybdenum.

[0076] As another example, the first metal element included in the barrier layer 150 is titanium, the second metal element included in the seed layer 170 is copper, tungsten or molybdenum, and the material of the transition layer 170 is titanium copper, titanium tungsten or titanium molybdenum.

[0077] In the embodiments of the present application, the semiconductor structure further includes an electrically conductive layer 180, and the electrically conductive layer 180 fills the channel 130. The present application removes the impurities by bombarding the surface of the barrier layer with high-energy ions, and forms the transition layer on the barrier layer at the same time. Then, the seed layer is formed, and the seed layer covers the transition layer. By controlling the removal of the impurities by the high-energy ions with the first bias, the influence of the impurities on the transition layer and the seed layer can be reduced, and the performance of the semiconductor structure is improved. Moreover, due to the existence of the transition layer, the interface between the seed layer and the barrier layer has better adhesion, and the electrically conductive metal interconnection structure formed has better electrical performance.

[0078] The above description is only the preferred embodiments of the present application, and the present application is disclosed above with the preferred embodiments, but is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solutions of the present application, or modify equivalent embodiments with the disclosed methods and technical contents without departing from the scope of the technical solutions of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solutions of the present application, are still within the scope of protection of the technical solutions of the present application.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, The method comprises: providing a substrate, forming a dielectric layer on the substrate, etching the dielectric layer to form a channel; forming a barrier layer on the surface of the dielectric layer, the barrier layer covering at least the bottom and sidewall of the channel; controlling high-energy ion bombardment on the surface of the barrier layer with a first bias voltage, while forming a transition layer on the surface of the barrier layer; forming a seed layer covering at least the surface of the transition layer.

2. The method of claim 1, wherein, The transition layer and the seed layer both comprise elements corresponding to the high-energy ions.

3. The method according to claim 1 or 2, characterized in that, The elements corresponding to the high-energy ions comprise copper, tungsten or molybdenum.

4. The method according to claim 1 or 2, characterized in that, The forming of the seed layer comprises: forming a first seed layer with a second bias voltage, the thickness of the first seed layer on the bottom of the channel being greater than the thickness of the first seed layer on the sidewall of the channel; controlling the high-energy ion bombardment on the first seed layer with a third bias voltage to form a second seed layer, the thickness of the second seed layer on the bottom of the channel being substantially equal to the thickness of the second seed layer on the sidewall of the channel; wherein the power range of the third bias voltage is greater than the power range of the second bias voltage.

5. The method of claim 4, wherein, The power range of the first bias voltage is greater than the power range of the second bias voltage, and the power range of the first bias voltage is greater than or equal to the power range of the third bias voltage.

6. The method of claim 5, wherein, The power range of the first bias voltage is 650W-800W, the power range of the second bias voltage is 120W-200W, and the power range of the third bias voltage is 600W-800W.

7. The method of claim 1 or 2, wherein, The method further comprises: forming a conductive layer on the surface of the seed layer, the conductive layer filling the channel.

8. The method of claim 1 or 2, wherein, The forming of the barrier layer on the surface of the dielectric layer comprises: sequentially forming a first barrier layer and a second barrier layer on the surface of the dielectric layer, the second barrier layer covering the first barrier layer; wherein the first barrier layer is a metal nitride layer, the second barrier layer is a metal layer, and the first barrier layer and the second barrier layer comprise the same metal element.

9. A semiconductor structure, characterized by The structure is prepared by the method of any one of claims 1-8, and comprises: a substrate and a dielectric layer on the surface of the substrate, a channel being formed in the dielectric layer; a barrier layer covering at least the bottom and sidewall of the channel; a transition layer covering at least the surface of the barrier layer; a seed layer covering at least the surface of the transition layer.

10. The structure of claim 9, wherein The transition layer comprises at least a first metal element same as the barrier layer and a second metal element same as the seed layer, the first metal element and the second metal element being different.

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