Formation method of semiconductor device structure, semiconductor device structure and electronic device

Abstract

The invention relates to a semiconductor device structure forming method, a semiconductor device structure and an electronic device.The semiconductor device structure forming method comprises the steps that a semiconductor structure and a wafer slide are provided, the semiconductor structure comprises a substrate, a front face structure located on the first face of the substrate and a bonding layer located on the front face structure, the bonding layer is a layer structure formed by using a preset metal material, pressurizing the semiconductor structure and the wafer slide with a preset pressure under a preset temperature and a first humidity environment so as to bond the bonding layer and the wafer slide, forming a back surface structure on the second surface of the substrate, and de-bonding the bonding layer and the wafer slide under a second humidity environment so as to form a back surface structure on the second surface of the substrate. And obtaining the separated semiconductor structure. According to the embodiment of the invention, on the basis of the bonding layer formed by the preset metal material, bonding and de-bonding of the bonding layer and the wafer slide are realized in the first humidity environment and the second humidity environment, reversible bonding control is realized, and damage is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a forming method of a semiconductor device structure, a semiconductor device structure and an electronic device. BACKGROUND

[0002] Nano-through-silicon vias (nTSVs) are sub-micron metal-filled vias that can provide an efficient power delivery network through the backside of a device wafer. The use of nTSVs and backside power delivery networks helps free up space on the front side of the wafer. In high-performance computing and artificial intelligence hardware, nTSVs can also enable significantly higher density interconnects, thereby increasing data bandwidth between wafers bonded directly together. nTSVs depend on the formation of wafer bonding and wafer thinning.

[0003] Wafer bonding technology refers to the process of tightly bonding two mirror-polished wafers of the same or different materials through chemical and physical action. After the wafers are bonded, the atoms at the interface are subjected to external forces and react to form covalent bonds to form a whole, and the bonding interface achieves a specific bonding strength.

[0004] The conventional forming method of a wafer semiconductor device structure, semiconductor device structure and electronic device bonding method is to bond through high-temperature melting and cooling of the oxide layer between the two wafers. This process involves high-temperature processing of several thousand degrees, which is likely to cause damage to the device structure. For example, the metal wiring structure in the device structure may have a sharp increase in capacitance resistance after high-temperature annealing, thereby causing loss to the device structure, resulting in a decrease in the yield of the final semiconductor device structure. SUMMARY

[0005] To solve the above technical problems, the present application provides a forming method of a semiconductor device structure, a semiconductor device structure and an electronic device.

[0006] In a first aspect, the embodiments of the present application disclose a forming method of a semiconductor device structure, comprising:

[0007] providing a semiconductor structure and a wafer carrier; the semiconductor structure comprises a substrate, a front surface structure on a first surface of the substrate, and a bonding layer on the front surface structure; wherein the bonding layer is a layer structure formed by using a preset metal material;

[0008] bonding the bonding layer and the wafer carrier under a preset temperature and a first humidity environment with a preset pressure;

[0009] forming a back surface structure on a second surface of the substrate;

[0010] The bonding layer and the wafer carrier are unbonded under a second humidity environment to obtain a separated semiconductor structure; wherein the humidity corresponding to the first humidity environment is lower than the humidity corresponding to the second humidity environment.

[0011] In a second aspect, the embodiments of the present application disclose a semiconductor device structure, which is formed by the forming method.

[0012] In a third aspect, the embodiments of the present application disclose an electronic device, which comprises the semiconductor device structure.

[0013] The technical scheme provided by the embodiments of the present application has the following technical effects:

[0014] The semiconductor structure and the wafer carrier are provided, the semiconductor structure comprises a substrate, a front surface structure on a first surface of the substrate and a bonding layer on the front surface structure, wherein the bonding layer is a layer structure formed by using a preset metal material, the semiconductor structure and the wafer carrier are pressed under a preset pressure in a first humidity environment at a preset temperature, so that the bonding layer and the wafer carrier are bonded, a back surface structure is formed on a second surface of the substrate, and the bonding layer and the wafer carrier are unbonded under a second humidity environment to obtain a separated semiconductor structure, wherein the humidity corresponding to the first humidity environment is lower than the humidity corresponding to the second humidity environment. In the embodiments of the present application, the bonding layer formed by using the preset metal material is used as the basis, the bonding and unbonding of the bonding layer and the wafer carrier are realized in the first humidity environment and the second humidity environment, reversible adhesion control is realized, and damage to the device structure caused by bonding through high-temperature melting and cooling is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, and the advantages thereof, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0016] Figure 1 FIG. 1 is a flow diagram of a forming method of a semiconductor device structure provided by the embodiments of the present application;

[0017] Figures 2-7 FIG. 2 is a structure diagram in the forming process of the semiconductor device structure provided by the embodiments of the present application. DETAILED DESCRIPTION

[0018] With reference to the drawings and the embodiments described herein, it will be understood that the drawings and embodiments are illustrative of the application and are not limiting of the present application. Numerous specific details are described to provide a thorough understanding of the present application. However, in certain instances, well-known methods, procedures, components and circuits have been omitted in order to not

[0019] It should be noted that the terms "one embodiment", "an embodiment", "some embodiments", "one specific embodiment", "some specific embodiments" and "one particular embodiment" as used herein are not used to limit or restrict the number of embodiments otherwise described herein, but are intended to mean "at least one". It should also be noted that the terms "a" and "an" as used herein are defined as "one or more" unless explicitly stated otherwise.

[0020] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application are further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present application and should not be used to limit the embodiments of the present application.

[0022] In the related art, the bonding between wafers can be achieved by fusion bonding between wafers and wafers. However, in the process of fusion bonding, high temperature is needed to assist in achieving the bonding between wafers and wafers, which may cause damage to the equipment and semiconductor device structure in the process of fusion bonding, thereby reducing the yield of the semiconductor device structure.

[0023] Therefore, the embodiments of the present application provide a forming method of a semiconductor device, which provides a semiconductor structure and a wafer carrier, wherein the semiconductor structure comprises a substrate, a front surface structure on a first surface of the substrate, and a bonding layer on the front surface structure, wherein the bonding layer is a layer structure formed by using a preset metal material. Then, the semiconductor structure and the wafer carrier are pressurized at a preset pressure in a preset temperature and first humidity environment to bond the bonding layer and the wafer carrier, and then a back surface structure is formed on a second surface of the substrate, and the bonding layer and the wafer carrier are debonded in a second humidity environment to obtain a separated semiconductor structure, wherein the humidity corresponding to the first humidity environment is lower than the humidity corresponding to the second humidity environment.

[0024] The bonding layer formed by the preset metal material is used as a basis to realize bonding and debonding of the bonding layer and the wafer carrier in the first humidity environment and the second humidity environment. Specifically, because the van der Waals force between the bonding layer and the wafer carrier in the first humidity environment is greater than the van der Waals force between the bonding layer and the wafer carrier in the second humidity environment, the bonded bonding layer and wafer carrier can be tightly combined and are not easy to peel off because of the greater van der Waals force between the bonding layer and the wafer carrier in the first humidity environment. At the same time, because the van der Waals force between the bonding layer and the wafer carrier in the second humidity environment is smaller, the bonding layer and the wafer carrier can be peeled off, so that reversible adhesion control can be realized.

[0025] The semiconductor device structure of the embodiment of the present application can be used to form a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device, a Fin Field-Effect Transistor (FinFET) device, a Gate-All-Around Field-Effect Transistor (GAAFET) device, etc.

[0026] Please refer to Figure 1 which shows a flowchart of a forming method of a semiconductor device structure provided by the embodiment of the present application. The forming method of the semiconductor device structure provided by the embodiment of the present application will be described in detail below with reference to Figures 2-7 The forming method of the semiconductor device structure provided by the embodiment of the present application will be described in detail below with reference to

[0027] In step S101, a semiconductor structure and a wafer carrier are provided; the semiconductor structure includes a substrate, a front surface structure on a first surface of the substrate, and a bonding layer on the front surface structure; wherein the bonding layer is a layer structure formed by using a preset metal material.

[0028] The substrate in the embodiment of the present application can be referred to as a semiconductor substrate, which includes a bulk semiconductor or a Silicon-On-Insulator (SOI) substrate, etc. The substrate can be doped (for example, doped with p-type dopants or n-type dopants) or undoped. The SOI substrate is a semiconductor material layer formed on an insulator layer, which can be, for example, a buried oxide (BOX) layer or a silicon oxide layer, etc., and the insulator layer is disposed on a silicon substrate or a glass substrate.

[0029] In a specific implementation, the semiconductor material of the substrate can include one or more of silicon, germanium, a compound semiconductor, or an alloy semiconductor, wherein the compound semiconductor can be one or more of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and the alloy semiconductor can be one or more of silicon germanium, arsenic phosphide gallium, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide.

[0030] Optionally, the substrate can include a region for forming a P-type field effect transistor, and of course, can also include a region for forming an N-type field effect transistor.

[0031] In an optional embodiment, the preset metal material forming the bonding layer includes copper Cu, or the preset metal material forming the bonding layer includes gold Au. The preset metal material can realize reversible bonding and debonding under low temperature conditions.

[0032] In the embodiments of the present application, reversible adhesion control can be realized by forming the bonding layer with gold Au, and realizing bonding and debonding of the bonding layer and the wafer carrier in a first humidity environment and a second humidity environment, thereby avoiding damage to the device structure caused by high-temperature melting and cooling during bonding. In this way, the yield of the finally formed semiconductor device structure can be improved.

[0033] Figure 2 FIG. 1 is a structural diagram of a semiconductor device structure in a forming process according to an exemplary embodiment, which mainly includes a substrate 201 and a front surface structure 202 on a first surface of the substrate.

[0034] Specifically, after obtaining the provided substrate, a front surface structure can be formed on the first surface of the substrate. In some optional embodiments, the substrate 201 can include a support substrate, an oxide buried layer on the support substrate, and an N / P well region.

[0035] In the embodiments of the present application, the front surface structure on the first surface of the substrate can be a front-end structure formed above the substrate. For example, if the semiconductor device structure is a MOSFET device, the front surface structure on the first surface of the substrate can be a front-end structure formed by a MOS manufacturing process.

[0036] In an optional embodiment, the semiconductor structure can include a bonding layer on the front surface structure in addition to the substrate and the front surface structure on the first surface of the substrate. In some optional embodiments, the bonding layer is a layer structure formed by using a metal element gold Au.

[0037] Figure 3is a structural diagram in a forming process of a semiconductor device structure according to an exemplary embodiment, which comprises a substrate 201 and a front structure 202 on a first surface of the substrate, and further comprises a sealing layer 203 and a bonding layer 204.

[0038] In a specific embodiment, after the substrate is provided, the front structure 202 can be formed on the first surface of the substrate 201, and the sealing layer 203 can be formed on the front structure 202, and then the bonding layer 204 can be formed on the sealing layer 203 by gold Au. The formed bonding layer 204 is prepared for subsequent wafer bonding.

[0039] In the embodiment of the application, the wafer bonding technology refers to that two mirror-polished homogeneous or heterogeneous wafers are tightly combined through chemical and physical effects. After the wafers are bonded, the atoms at the interface are subjected to external force to react and form covalent bond to be integrated, and the bonding interface reaches a specific bonding strength.

[0040] The internal factors affecting the bonding quality are the chemical adsorption state, flatness and roughness of the wafer surface; and the external factors are mainly the bonding temperature and time. Usually, pressure is also needed to overcome the surface relief and increase the bonding density between the surface atoms to achieve the purpose of improving the bonding strength.

[0041] The basic conditions for determining the success or failure of the bonding can be seen below:

[0042] Geometric condition: the lattice mismatch problem can be effectively solved by using the bonding technology, and the difference between the surface flatness and elastic modulus of the two bonded wafers needs to be small.

[0043] Mechanical condition: the surface required for bonding needs to be very smooth, and the roughness of the surface needs to be more than 2 nm, which is usually achieved by chemical mechanical polishing.

[0044] Physical condition: the process of epitaxy or crystal growth often has some defects, such as large grain boundary, lattice dislocation and double peak, which also need to be removed by CMP.

[0045] Chemical condition: the cleanliness of the two surfaces to be bonded is very important, and the surface metal, organic matter and other impurities need to be removed during bonding.

[0046] Energy condition: in the process of heat treatment, the temperature may cause chemical reaction of the surface residual substances, and the introduction of thermal stress during the bonding process may cause deformation and other adverse results to the device.

[0047] Based on the above content, the influence of the above conditions on the application also needs to be considered in the process of forming the bonding layer. In the embodiment of the application, there are many methods for forming the bonding layer on the sealing layer by gold Au, and two optional implementation manners are introduced below.

[0048] In an alternative embodiment, the bonding layer can be formed on the sealing layer using gold (Au) based on a deposition process.

[0049] In the embodiments of the present application, the deposition process includes a vapor deposition process and an atomic layer deposition (ALD) process.

[0050] The vapor deposition technology is a new technology that uses physical and chemical processes in the gas phase to change the composition of the workpiece surface and form a metal or compound coating layer with special properties (such as super-hard wear-resistant layer or special optical and electrical properties) on the surface. Vapor deposition generally covers a layer of transition element compounds with carbon, nitrogen, oxygen, and boron on the surface of the workpiece. According to the nature of the process, vapor deposition can be divided into two categories: chemical vapor deposition (CVD) and physical vapor deposition (PVD).

[0051] Among them, the chemical vapor deposition (CVD) technology is a chemical technology that mainly uses one or more gas phase compounds or elements containing thin film elements to perform a chemical reaction on the substrate surface to generate a thin film.

[0052] Among them, the physical vapor deposition (PVD) technology refers to a technology that uses physical methods to vaporize the surface of a material source (solid or liquid) into gaseous atoms or molecules, or partially ionize into ions, and then deposit a thin film with certain special functions on the substrate surface through a low-pressure gas (or plasma) process. Physical vapor deposition is one of the main surface treatment technologies.

[0053] Optionally, the PVD coating technology is mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating, and vacuum ion coating. The main methods of physical vapor deposition include vacuum evaporation, sputtering coating, arc plasma coating, ion coating, and molecular beam epitaxy. The corresponding vacuum coating equipment includes vacuum evaporation coating machine, vacuum sputtering coating machine, and vacuum ion coating machine. With the improvement of deposition methods and technology, physical vapor deposition technology can not only deposit metal films and alloy films, but also deposit compounds, ceramics, semiconductors, and polymer films.

[0054] The atomic layer deposition (ALD) process is a special vacuum thin film deposition method with high technical barriers. Due to the self-limiting nature of the surface chemical reaction of the ALD technology, it also has many unique thin film deposition characteristics such as wide applicability to different shaped substrates, good uniformity of large area film formation, and sub-nanometer level thickness control.

[0055] In the embodiments of the present application, the surface roughness of the bonding layer formed by Au metal can be controlled by adjusting the deposition process of Au metal. Taking physical vapor deposition (PVD) technology as an example, the surface roughness of the bonding layer formed by Au metal can be adjusted by adjusting the type, incident energy, incident angle, and target material of incident ions in the physical sputtering technology. According to the adhesion formula (1), the larger the surface roughness, the smaller the effective contact area between the two objects, resulting in smaller adhesion. The smaller the surface roughness, the larger the effective contact area between the two objects, resulting in larger adhesion. The adhesion is proportional to the van der Waals force, that is, the adhesion is larger, and the van der Waals force is also larger.

[0056]

[0057] wherein F ad is the adhesion; A is the contact area; A H is the Hamaker constant, which is a parameter for characterizing the size of the van der Waals attractive energy between substances; H0 is the cut-off distance; p is the density; r is the radius of a single rough body; y max is the maximum roughness.

[0058] Therefore, in order to achieve a larger van der Waals force between the bonding layer and the wafer carrier after bonding, the surface roughness of the bonding layer formed by Au metal can be adjusted as small as possible, that is, the surface roughness is low, and the effective contact area between the two objects is large.

[0059] In the embodiments of the present application, in order to pursue better surface flatness, that is, lower surface roughness, in another alternative embodiment, a bonding layer can be formed on the sealing layer by using Au in a multi-film transfer process.

[0060] In an alternative embodiment, a template substrate can be prepared, which includes a silicon substrate, a silicon dioxide layer on the silicon substrate, and a gold (Au) film on the silicon dioxide layer. Subsequently, the side with the Au film in the template substrate is aligned with the sealing layer, and pressure is applied so that the Au film on the silicon dioxide layer is transferred to the sealing layer. In this way, a bonding layer can be obtained.

[0061] Alternatively, after the side with the Au film in the template substrate is aligned with the sealing layer and pressure is applied so that the Au film on the silicon dioxide layer is transferred to the sealing layer, the operation can be repeated multiple times based on multiple template substrates to stack the Au films layer by layer on the sealing layer to obtain a bonding layer.

[0062] The above embodiment is to form the bonding layer on the sealing layer by using gold Au directly through the multi-film transfer process. Alternatively, the bonding layer on the sealing layer can also be formed by using gold Au through the deposition process and the multi-film transfer process in combination.

[0063] In the embodiment of the present application, the plurality of template substrates can be cycled 3 to 9 times to reduce the roughness of the surface of the bonding layer as much as possible, thereby increasing the effective contact area between the bonding layer and the object to be bonded.

[0064] Alternatively, the present application can also use the deposition process to form a rough Au surface on the sealing layer, and then prepare the template substrate Template Substrate, align the gold Au film side of the template substrate with the sealing layer, pressurize, so that the gold Au film on the silicon dioxide layer is transferred to the sealing layer, and the plurality of template substrates are cycled multiple times, so that the gold Au film is stacked on the sealing layer layer by layer to obtain the bonding layer.

[0065] In step S103, the semiconductor structure and the wafer carrier are pressurized at a preset pressure in a preset temperature and first humidity environment to bond the bonding layer and the wafer carrier.

[0066] In the embodiment of the present application, the semiconductor structure can be flipped before step S103 to align the bonding layer with the wafer carrier, in preparation for the subsequent bonding of the bonding layer and the wafer carrier under certain pressure in a temperature and humidity environment.

[0067] Figure 4 is a structure diagram in the process of forming a semiconductor device structure according to an exemplary embodiment, which includes forming a bonding layer on a sealing layer of a semiconductor structure by Figures 2-3 The semiconductor structure and the wafer carrier 205 are formed.

[0068] Alternatively, the preset temperature includes 80 degrees Celsius to 300 degrees Celsius during the bonding of the bonding layer and the wafer carrier. For example, the semiconductor structure and the wafer carrier can be pressurized at a preset pressure in an 80-degree Celsius and first humidity environment to bond the bonding layer and the wafer carrier. Alternatively, the semiconductor structure and the wafer carrier can be pressurized at a preset pressure in a 300-degree Celsius and first humidity environment to bond the bonding layer and the wafer carrier. Alternatively, the semiconductor structure and the wafer carrier can be pressurized at a preset pressure in a 195-degree Celsius and first humidity environment to bond the bonding layer and the wafer carrier.

[0069] Compared with the high-temperature melting bonding method in the prior art involving several thousand degrees of high-temperature processing, the temperature involved in the embodiment of the present application can be controlled within 300 degrees Celsius, so that the implementation of the present application is low-temperature and controllable, which can greatly reduce or even eliminate the damage to the semiconductor device structure.

[0070] Optionally, the first humidity environment represents a solvent-free environment. That is, the semiconductor structure and the wafer carrier can be pressurized at a preset pressure in a preset temperature and a solvent-free environment to bond the bonding layer and the wafer carrier.

[0071] Optionally, the preset pressure includes 5 kiloPascal to 40 kiloPascal during the bonding of the bonding layer and the wafer carrier. Optionally, the preset pressure can be 5 kiloPascal, the preset pressure can be 40 kiloPascal, and the preset pressure can be 25 kiloPascal.

[0072] In the embodiments of the present application, the wafer carrier needs to be kept clean before the bonding of the bonding layer and the wafer carrier, or in other words, the wafer carrier needs to be kept from being contaminated, because the contamination will affect the contact area of the bonding layer and the wafer carrier, thereby causing the adhesion to be small.

[0073] In step S105, a back surface structure is formed on the second surface of the substrate.

[0074] Figure 5 and Figure 6 is a structure diagram in a forming process of a semiconductor device structure according to an exemplary embodiment, as shown in Figure 5 After the bonding of the bonding layer and the wafer carrier in the semiconductor structure, the substrate can be thinned, as shown in Figure 6 A back surface structure 206 is formed on the second surface of the thinned substrate.

[0075] In a specific implementation, the thickness of the substrate 201 can be reduced by etching the surface of the substrate 201, and the thickness of the substrate 201 can also be reduced by mechanically grinding the surface of the substrate 201.

[0076] In step S107, the bonding layer and the wafer carrier are debonded in a second humidity environment to obtain a separated semiconductor structure; wherein the humidity corresponding to the first humidity environment is lower than the humidity corresponding to the second humidity environment.

[0077] Figure 7 is a structure diagram in a forming process of a semiconductor device structure according to an exemplary embodiment, as shown in Figure 7 The bonding layer and the wafer carrier are debonded in a second humidity environment to obtain a separated semiconductor structure, as shown in

[0078] In the embodiments of the present application, the second humidity environment represents a solvent environment during the debonding of the bonding layer and the wafer carrier. Exemplarily, the solvent in the solvent environment includes water, isopropyl alcohol, glycerol, and / or honey. These solvents have different viscosities, surface tensions, and boiling points. The solvent in the solvent environment can also include other solvents not listed herein as long as the requirements of the present application are met.

[0079] In the embodiments of the present application, the van der Waals force between the bonding layer and the wafer carrier in the first humidity environment is greater than the van der Waals force between the bonding layer and the wafer carrier in the second humidity environment. That is, the van der Waals force between the bonding layer and the wafer carrier in the solvent-free environment is greater than the van der Waals force between the bonding layer and the wafer carrier in the solvent environment.

[0080] Through experiments, it is found that the van der Waals force between the wafer carrier and gold Au in the solvent environment is 3.66nN, and the van der Waals force between the wafer carrier and gold Au in the solvent-free environment can reach 11.8nN. It can be seen that the change of the van der Waals force in the solvent-free environment and the solvent environment is obvious, and experiments prove that the van der Waals force distribution in the solvent-free environment is stronger and more uniform.

[0081] In summary, the bonding layer and the wafer carrier can be bonded in a controllable low-temperature environment in a dry environment, and the back structure is formed. After the back structure is completed, a humid environment is given, so that the van der Waals force between the bonding layer and the wafer carrier becomes weak, and then the separation of the two becomes easy, thereby realizing a new type of reversible wafer bonding method in a low-temperature controllable environment, avoiding serious thermal damage and mechanical damage to the device.

[0082] In the embodiments of the present application, the process of forming the substrate, the front structure and the back structure (including materials, temperature, thickness, etc.) can refer to the forming process in the prior art, which will not be described here.

[0083] It should be noted that the method and structure embodiments provided in the above embodiments belong to the same concept, and the specific implementation process is described in detail in the structure embodiments, which will not be described here.

[0084] Correspondingly, the present application also provides a conductor device structure formed by using the forming method of any one of the above embodiments.

[0085] Correspondingly, the present application also provides an electronic device including the semiconductor device structure described above.

[0086] The electronic device described in the embodiments of the present application can be a smart phone, a desktop computer, a tablet computer, a notebook computer, a digital assistant, an augmented reality (AR) / virtual reality (VR) device, a smart voice interaction device, a smart home appliance, a smart wearable device, a vehicle terminal device, etc. Any electronic product or device, or any intermediate product including the above-mentioned memory device.

[0087] It should be noted that the above-mentioned order of the embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments. And the above describes the specific embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than the order in which they are recited and still achieve desirable results. In addition, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous or necessary.

[0088] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiments.

[0089] A person of ordinary skill in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by program instructing relevant hardware to complete, and the program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk.

[0090] The above only describes the preferred embodiments of the present application, and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of forming a semiconductor device structure, characterized by, The application relates to a semiconductor structure and a wafer carrier. The semiconductor structure comprises a substrate, a front surface structure on a first surface of the substrate, and a bonding layer on the front surface structure; wherein the bonding layer is a layer structure formed by a preset metal material; The semiconductor structure and the wafer carrier are pressurized at a preset pressure in a preset temperature and first humidity environment, so that the bonding layer and the wafer carrier are bonded; A back surface structure is formed on a second surface of the substrate; The bonding layer and the wafer carrier are debonded in a second humidity environment, and a separated semiconductor structure is obtained; wherein the humidity corresponding to the first humidity environment is lower than the humidity corresponding to the second humidity environment. The preset metal material comprises gold Au.

2. The method of forming a semiconductor device structure according to claim 1, wherein The semiconductor structure is provided by the following steps:

3. The method of forming a semiconductor device structure according to claim 2, wherein The substrate is provided; The front surface structure is formed on the first surface of the substrate; A sealing layer is formed on the front surface structure; The bonding layer is formed on the sealing layer by using the gold Au. The bonding layer is formed on the sealing layer by using the gold Au, which comprises:

4. The method of forming a semiconductor device structure according to claim 3, wherein The bonding layer is formed on the sealing layer by using the gold Au based on a deposition process or a multi-film transfer process. The van der Waals force between the bonding layer and the wafer carrier in the first humidity environment is greater than the van der Waals force between the bonding layer and the wafer carrier in the second humidity environment.

5. The method of forming a semiconductor device structure of claim 1, wherein, The back surface structure is formed on the second surface of the substrate by the following steps:

6. The method of forming a semiconductor device structure of claim 1, wherein, The substrate is thinned; The back surface structure is formed on the second surface of the thinned substrate. During the bonding of the bonding layer and the wafer carrier, the preset temperature comprises 80-300 DEG C.

7. The method of forming a semiconductor device structure according to any one of claims 1 to 6, wherein During the bonding of the bonding layer and the wafer carrier, the first humidity environment represents a solvent-free environment.

8. The method of forming a semiconductor device structure according to any one of claims 1 to 6, wherein During the bonding of the bonding layer and the wafer carrier, the preset pressure comprises 5-40 kPa.

9. The method of forming a semiconductor device structure according to any one of claims 1-6, wherein During the debonding of the bonding layer and the wafer carrier, the second humidity environment represents a solvent environment.

10. The method of forming a semiconductor device structure according to any one of claims 1-6, wherein The solvent in the solvent environment comprises isopropyl alcohol, glycerol and / or honey.

11. The method of forming a semiconductor device structure of claim 10, wherein, The electronic device comprises a semiconductor device structure formed by any one of the forming methods in claims 1-11.

12. A semiconductor device structure, characterized by, The electronic device comprises a semiconductor device structure formed by any one of the forming methods in claims 1-11.

13. An electronic device, comprising: ​

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