Electronic device and method for manufacturing electronic device

Abstract

The invention relates to electronic equipment and a method for manufacturing the electronic equipment, and the method comprises the following steps: providing a structure, comprising a semiconductor substrate, conductive elements over the semiconductor substrate, a first intermetallic dielectric layer between the conductive elements, a cavity in the first intermetallic dielectric layer between two adjacent conductive elements, and a second intermetallic dielectric layer over the first intermetallic dielectric layer and the cavity, the cavities are coupled together to form a continuously extending cavity between two adjacent conductive elements; forming first and second ports through the second intermetallic dielectric layer, respectively, the first and second ports extending to the cavity and the conductive element, respectively; the first and second ports are filled with a conductive material, the filling of the first port fills the cavity, forms conductive regions coupled together, thereby forming a conductive track, and forms a first conductive via coupled to the conductive track, and the filling of the second port forms a second conductive via coupled to the conductive element.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to French Patent Application No. 2404022, filed on April 18, 2024, which is incorporated herein by reference TECHNICAL FIELD

[0003] The present disclosure relates generally to semiconductor-based electronic devices and methods of manufacturing semiconductor-based electronic devices.

[0004] In particular, the present disclosure relates to interconnect structures in electronic devices. BACKGROUND

[0005] Semiconductor-based electronic devices generally comprise electronic components on top of and / or inside a semiconductor substrate layer. The substrate layer can be for example a solid semiconductor substrate or a silicon-on-insulator or SOI layer. The electronic components are generally manufactured during a front-end-of-line (FEOL) process. Once the FEOL process is completed, the manufacturing of the electronic device proceeds by forming an interconnect structure comprising a network of conductive paths intended to be coupled to the electronic components. In the technical field, this is referred to as a back-end-of-line (BEOL) process.

[0006] The routing of the conductive paths in the BEOL process requires forming a plurality of metallization levels (or metallization layers) above the substrate layer comprising the electronic components formed during the FEOL process. The metallization comprises metal vias extending perpendicularly to the upper surface of the substrate layer and metal lines extending parallel to the upper surface of the substrate layer, the vias being able to couple metal lines of two different metallization levels. It is conventional practice to use copper (Cu) as the metal material for the vias and the metal lines, although it is also known to use other metal materials such as aluminum (Al) for the metal lines and / or tungsten (W) for the vias, and possibly for the barrier layers. The interconnect structure generally comprises dielectric material at and / or between each metallization level, the vias and the metal lines being surrounded by the dielectric material and electrically insulated from each other.

[0007] As the electronic components are getting smaller and the electronic devices are getting more complex, the complexity of the BEOL metallization also corresponds to increase, in particular to connect an increasing number of electronic components, and in particular this can require increasing the number of metallization levels. At the same time, it can be sought to have an increasingly small interconnect structure to reduce the size of the electronic device. SUMMARY

[0008] There is a need to improve semiconductor-based electronic devices, in particular to improve the interconnection of electronic components in electronic devices.

[0009] Embodiments overcome all or part of the drawbacks of known electronic devices.

[0010] Embodiments provide a method of fabricating an electronic device, the method comprising: providing a structure comprising a semiconductor substrate having electronic components formed on a top and inside, first conductive elements above the semiconductor substrate, a first intermetallic dielectric layer between the first conductive elements, cavities in the first intermetallic dielectric layer between two first adjacent ones of the first conductive elements, and a second intermetallic dielectric layer above the first intermetallic dielectric layer and the cavities, the cavities being coupled together to form a continuously extending cavity between the two first adjacent ones of the first conductive elements; forming first and second ports through the second intermetallic dielectric layer, the first ports extending all the way into one of the cavities, respectively, and the second ports extending all the way into one of the first conductive elements, respectively; filling the first and second ports with a conductive material, filling the first ports being performed to fill the cavities, forming conductive regions coupled together, thereby forming a conductive track, filling the first ports also forming first conductive vias coupled to the conductive track, and filling the second ports forming second conductive vias coupled to the first conductive elements.

[0011] According to embodiments, providing the structure comprises forming the cavities comprising: forming a third port through the first intermetallic dielectric layer between the two first adjacent ones of the first conductive elements, forming the third port comprising etching, e.g. anisotropic etching and / or dry etching; widening the third port to form open cavities coupled together in the first intermetallic dielectric layer, widening the third port comprising etching, e.g. isotropic etching and / or wet etching; forming the second intermetallic dielectric layer over the open cavities and the first intermetallic dielectric layer to close the open cavities.

[0012] According to embodiments, the method comprises, prior to forming the third port, depositing a first protective layer over the first intermetallic dielectric layer and the first conductive elements, then forming a first opening in the first protective layer, the third port being formed in alignment with the first opening, forming the first opening comprising etching, e.g. anisotropic etching and / or dry etching.

[0013] According to embodiments, forming the first and second ports comprises anisotropic etching and / or dry etching.

[0014] According to embodiments, the provided structure comprises further cavities in the first intermetallic dielectric layer between two further first adjacent ones of the first conductive elements, the second intermetallic dielectric layer also extending over the further cavities, the further cavities being coupled together and not filled with the conductive material to form a continuously extending cavity between the two further first adjacent ones of the first conductive elements.

[0015] Embodiments provide an electronic device comprising: a semiconductor substrate having electronic components arranged on top and inside; first conductive elements above the semiconductor substrate; a first intermetal dielectric layer between the first conductive elements; conductive regions extending at least through a thickness of the first intermetal dielectric layer between two first adjacent ones of the first conductive elements, the conductive regions being coupled together in a shape of a conductive track; a second intermetal dielectric layer above the first intermetal dielectric layer, the first conductive elements and the conductive track; a first conductive via through the second intermetal dielectric layer and coupled to the conductive track; a second conductive via through the second intermetal dielectric layer and coupled to the first conductive elements.

[0016] According to embodiments, the electronic device further comprises other cavities in the first intermetal dielectric layer between two other first adjacent ones of the first conductive elements, the second intermetal dielectric layer also extending over the other cavities, the other cavities being coupled together to form a continuously extending cavity between the two other first adjacent ones of the first conductive elements.

[0017] The following embodiments can be applicable to the device or the method.

[0018] According to embodiments, the first conductive elements are insulated from each other by the first intermetal dielectric layer in a first direction of a plane substantially parallel to a plane of the semiconductor substrate, and the conductive regions are coupled together in a second direction of the plane perpendicular to the first direction.

[0019] According to embodiments, the conductive regions are also coupled together in the first direction of the plane.

[0020] According to embodiments, lateral edges of the first conductive elements are protected by a second protective layer.

[0021] According to embodiments, the conductive regions further extend in a pre-metal dielectric layer between the semiconductor substrate and the first intermetal dielectric layer, for example between the electronic components and the first intermetal dielectric layer.

[0022] According to embodiments, contacts through the pre-metal dielectric layer are coupled to the electronic components and the first conductive elements, the conductive regions also extending between the contacts.

[0023] According to embodiments, the conductive material comprises tungsten and / or the first conductive elements comprise copper or aluminum.

[0024] According to embodiments, the first conductive elements and the first intermetal dielectric layer form a first metallization level of an interconnect structure.

[0025] According to embodiments, a second metallization level comprises second conductive elements coupled to the first conductive elements through the second conductive vias and other second conductive elements coupled to the conductive track through the first conductive vias.

[0026] According to embodiments, the electrically conductive tracks and the first electrically conductive via are comprised in an electrical circuit for controlling the electrical continuity between the electrically conductive areas. BRIEF DESCRIPTION OF DRAWINGS

[0027] The foregoing features and advantages, as well as others, will be described in detail in the remainder of the present disclosure with reference to specific embodiments, given by way of non-limiting illustration, with reference to the accompanying drawings, in which:

[0028] Figure 1 is a longitudinal sectional view schematically and partially illustrating an example of an electronic device;

[0029] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 is a longitudinal sectional view schematically and partially illustrating a structure obtained at the end of a successive intermediate step of a method example of manufacturing an electronic device according to embodiments;

[0030] Figure 11 is a top view schematically and partially illustrating a structure obtainable at the end of the step shown in Figure 9 ;

[0031] Figure 12 is a top view schematically and partially illustrating an electronic device obtainable at the end of the step shown in Figure 10 ;

[0032] Figure 13A and Figure 13B are a top view and a three-dimensional view schematically and partially illustrating an electronic device according to embodiments, such as the electronic device of Figure 12 , additionally having a second metallization level; and

[0033] Figure 14 is a longitudinal sectional view schematically and partially illustrating an electronic device according to another embodiment. DETAILED DESCRIPTION

[0034] In the various drawings, like features are designated by like reference numerals. In particular, structural and / or functional features common to the various embodiments can have the same reference numerals and can be provided with the same structural, dimensional and material properties.

[0035] For clarity, only those steps and elements that are useful in understanding the embodiments so described are shown and described in detail. In particular, details of manufacturing steps and electronic components (e.g. drain, source and gate regions of MOS transistors) are not described in detail, as they can be formed using general electronic component manufacturing methods. Further, manufacturing steps and details of interconnect structures are not described, as they can be formed using general interconnect structure manufacturing methods.

[0036] Unless indicated otherwise, when referring to two elements connected together, this means a direct connection without any intermediate element other than a conductor, and when referring to two elements coupled together, this means that the two elements can be connected, or they can be coupled via one or more other elements.

[0037] In the following description, unless otherwise specified, reference is made to the orientation of the drawings when referring to absolute position qualifiers (such as "front", "back", "top", "bottom", "left", "right", etc.) or relative position qualifiers (such as "top", "bottom", "upper", "lower", etc.) or orientation qualifiers (such as "horizontal", "vertical", etc.).

[0038] Unless indicated otherwise, the expressions "around", "approximately", "substantially" and "about" mean plus or minus 10% or 10°, preferably plus or minus 5% or 5°.

[0039] In the following description, unless otherwise specified, the terms "insulated" and "conductive" mean electrically insulated and electrically conductive, respectively.

[0040] In the following description, when referring to a substrate, unless otherwise specified, a semiconductor substrate is referred to. In the following description, when referring to a via, unless otherwise specified, a conductive via, such as a metal via, is referred to.

[0041] In the following description, unless otherwise specified, a length corresponds to a dimension in a first direction, which corresponds to the longitudinal X-direction indicated in the drawings, a width corresponds to a dimension in a second direction orthogonal to the first X-direction, which corresponds to the transversal Y-direction indicated in the drawings, and a thickness or depth corresponds to a dimension in a direction perpendicular to the first and second directions, which corresponds to the vertical Z-direction indicated in the drawings. In the case of MOSFET type transistors, the longitudinal X-direction corresponds to the direction of the channel length between the source and drain regions of the transistor.

[0042] Figure 1 is a longitudinal cross-sectional view schematically and partially showing an example of an electronic device 100.

[0043] Figure 1 The electronic device 100 of can be formed with respect to Figures 2 to 10Initial structure of the described method.

[0044] The electronic device 100 comprises a plurality of MOSFET transistors 110 formed on top and inside of a semiconductor substrate 102. In certain embodiments, the substrate 102 is made of silicon, or is a silicon-on-insulator or SOI layer. The substrate 102 extends along a plane XY or principal plane.

[0045] Although two transistors are illustrated in Figure 1 any number of transistors and / or other electronic components can be formed on top and / or inside of the substrate 102. The transistors (or more generally, the electronic components) can be placed adjacent to each other in the X and / or Y direction.

[0046] Each transistor 110 comprises a gate region 111 covering a channel formation region 103 or channel region formed in the substrate 102. The channel region 103 is located between two doped semiconductor regions of the substrate 102, forming a drain region 104 and a source region 105 of the transistor 110, respectively, or a source region 104 and a drain region 105 of the transistor 110.

[0047] The gate region 111 can be made of polysilicon and / or an electrically conductive material, such as a rare earth silicide (e.g. titanium or cobalt silicide) or a combination of multiple of these materials. The gate region 111 can be multilayered, e.g. a polysilicon layer and one (or more) layer(s) made of an electrically conductive material. The gate region 111 is insulated from the substrate 102 by a gate insulator 112. A gate insulator or another insulating layer can also cover the sidewalls of the gate region 111. The gate insulator 112 can be made of silicon oxide, such as silicon dioxide (SiO2).

[0048] The sidewalls of the gate region 111 are covered by a gate spacer 113. The gate spacer 113 comprises one or more dielectric layers. In certain embodiments, the gate spacer 113 comprises silicon oxide, silicon dioxide, silicon nitride (e.g. Si3N4) or a combination of multiple of these materials. For example, the gate spacer 113 can comprise a first layer of silicon nitride, a second layer of silicon dioxide on the first layer and a third layer of silicon nitride on the second layer. As Figure 1 illustrated, the gate spacer 113 can comprise a first layer and a second layer each having an L-shaped profile in the longitudinal cross-sectional view.

[0049] In certain embodiments, a capping layer 114 covers the upper surface of the gate region 111. The capping layer 114 comprises a suitable electrically conductive material, such as for example titanium, titanium nitride, tantalum, tantalum nitride, cobalt silicide (CoSi2) or a combination of multiple of these materials.

[0050] In certain embodiments, a metal silicide layer 108 or silicide layer is formed on each of the drain region 104 and the source region 105. Such a silicide layer can significantly reduce the electrical access resistance of the contacts 120 described below, i.e., the resistance between the drain and source regions and the contacts.

[0051] An etch stop layer 106 is formed on the transistor 110, i.e., at least on the gate region 111, the source and drain regions 104, 105, and the gate spacers 113. The etch stop layer 106 can be used to control subsequent etching steps, such as the formation of the contacts 120. The etch stop layer 106 can comprise a nitride, such as silicon nitride (e.g., Si3N4), carbon silicon nitride, or any other suitable material.

[0052] A metal pre-dielectric layer 107 or PMD layer is formed on the etch stop layer 106. In certain embodiments, the PMD layer 107 comprises silicon oxide, such as silicon dioxide (SiO2). In other embodiments, the PMD layer 107 comprises a phosphosilicate glass abbreviated as “PSG” or a borophosphosilicate glass abbreviated as “BPSG”. However, the PMD layer 107 can comprise a combination of multiple of these materials or any other suitable material.

[0053] The contacts 120 are formed through the PMD layer 107 and the etch stop layer 106 to physically and electrically contact the source and drain regions 104, 105.

[0054] To form these contacts 120, openings are generally formed through the PMD layer 107 and the etch stop layer 106 at least up to the silicide layer 108 (if present) or up to the source and drain regions 104, 105 by suitable masking techniques, such as photolithography, and then by suitable etching techniques. A barrier layer 121 is then conformally deposited on the inner walls and bottom of these openings. The barrier layer 121 comprises a suitable conductive material, such as tantalum, tantalum nitride, titanium, titanium nitride, or a combination of multiple of these materials. The barrier layer 121 is formed by suitable methods, such as chemical vapor deposition (CVD) techniques, physical vapor deposition (PVD) techniques, atomic layer deposition (ALD) techniques, or electroplating. A conductive filler material 122 is then formed on the barrier layer 121 to fill the openings. In certain embodiments, the conductive filler material 122 comprises tungsten, cobalt, copper, or a combination of multiple of these materials. The conductive filler material 122 is formed by suitable methods, such as CVD, PVD, ALD, or electroplating. The upper portions of the barrier layer 121 and the conductive filler material 122 can be removed with suitable planarization techniques, such as chemical mechanical polishing (CMP).

[0055] Accordingly, the electrical contacts 120 penetrate the PMD layer 107 to couple the drain region 104 and the source region 105 to the interconnect structure, which can be seen in Figure 1 The first metallization level 130 of the interconnect structure can be seen in

[0056] The first metallization level 130 comprises electrically conductive elements 132, such as metal lines (elongated in the Y-direction), which are insulated from each other by dielectric elements or insulating elements 1310. These dielectric elements 1310 collectively form an intermetal dielectric layer 131 (first intermetal dielectric layer) or IMD layer 131. The electrically conductive elements 132 are coupled to the contacts 120, preferably positioned substantially in alignment with the contacts 120.

[0057] The first metallization level 130 can be formed by a subtractive process, for example of aluminum lines, or by a damascene-type process, for example of copper lines.

[0058] An example of a subtractive process is described in the following. An electrically conductive layer, for example made of aluminum, is deposited on the PMD layer 107 and the contacts 120. The deposition of the electrically conductive layer is performed by a suitable method, such as a CVD, PVD or ALD technique or electroplating. Then, the electrically conductive layer is etched through an etch mask, for example obtained by lithography, which etching forms openings through the electrically conductive layer all the way down to the PMD layer 107. The etch mask is sized such that the remaining part of the electrically conductive layer forming the electrically conductive elements 132 is positioned substantially in alignment with the contacts 120. Then, the etch mask is removed. A protective layer 133 can then be deposited to cover the upper surfaces and sidewalls of the electrically conductive elements 132 and it generally also covers the exposed surface of the opening bottom PMD 107 layer. The protective layer 133 can be made of nitride, such as silicon nitride, or any other suitable material. The protective layer 133 can be deposited by a CVD technique or any other suitable technique. Then, the part of the protective layer located on the exposed surface of the opening bottom PMD layer 107 can be removed. Then, the IMD layer 131 is formed to at least fill the openings between the electrically conductive elements 132, forming the insulating elements 1310. The IMD layer 131 comprises, for example, silicon oxide, such as silicon dioxide (SiO2), or any other dielectric material. The IMD layer 131 is deposited by a suitable technique, such as a CVD technique. The excess part of the IMD 131 layer can be removed by means of planarization, such as CMP.

[0059] According to a variant of the described subtractive process, an initial protective layer can be formed on the electrically conductive layer before etching the electrically conductive layer to protect the underlying layers during etching, the etching of the electrically conductive layer comprising etching the initial protective layer through the etch mask such that the initial protective layer remains only on the electrically conductive elements after etching.

[0060] An example of a damascene process is described hereafter. The IMD layer 131 is deposited on the PMD layer 107 and the contacts 120. The IMD layer 131 can be similar to the IMD layers described above, the IMD layer deposition techniques being the same. The IMD layer 131 is then etched through an etch mask, obtained for example by lithography, forming openings through the IMD layer 131. The remaining part of the IMD layer 131 forms the insulating elements 1310. The etch mask is sized so that the openings in the IMD layer 131 are positioned in substantial alignment with the contacts 120. The etch mask is removed. A protective layer 133 can then be deposited in the openings, to cover the sidewalls of the openings, and it also covers the bottom of the openings and the insulating elements 1310 in general. The protective layer 133 can be similar to the protective layers described above, the techniques for depositing a protective layer being the same. The part of the protective layer 133 located on the bottom of the openings and on the insulating elements 1310 can then be removed. A barrier layer 134 is then deposited in the openings, to cover the sidewalls and the bottom of the openings, and it also covers the insulating elements 1310 in general. The barrier layer 134 comprises a suitable electrically conductive material, such as tantalum, tantalum nitride, titanium, titanium nitride or a combination of several of these materials. The barrier layer 134 is formed by a suitable method, such as CVD, PVD, ALD or electroplating. A conductive material, for example copper, is then formed to fill at least the openings between the insulating elements 1310, so as to form the conductive elements 132 with the barrier layer 134. The excess of the conductive layer and of the barrier layer 134 located above the insulating elements 1310 can be removed by means of planarization, such as CMP.

[0061] According to a variant of the described damascene process, an initial protective layer 135 can be formed on the PMD layer 107 and the contacts 120, before the deposition of the IMD layer, to protect the underlying layers during the etching of the IMD layer 131, the etching of the IMD layer 131 comprising the etching of the initial protective layer 135 through the etch mask, the initial protective layer 135 remaining under the non-etched part of the IMD layer 131.

[0062] In both techniques, the protective layer 133 is present on the sides of the conductive elements 132, which can protect the conductive elements 132 during subsequent manufacturing steps, such as etching to form cavities described hereafter.

[0063] As an illustration, Figure 1 The conductive copper elements 132 are shown as obtained by a damascene process. They can also be aluminum conductive elements obtained by a subtractive process. The same reference signs are used for similar elements when describing both processes.

[0064] As Figure 1 As can be seen in Figure 1 1, a protective layer 141 is formed on the first metallization level 130, i.e. on the conductive elements 132 and on the IMD layer 131. The protective layer 141 can be similar to the protective layers described above in relation with the damascene process, the techniques for depositing a protective layer being the same. Figure 1The deposition techniques of the protective layers 133, 141 described are the same.

[0065] Concerning Figures 2 to 10 The initial structure of the manufacturing method described can not comprise the protective layer 141, the deposition of which can form part of the manufacturing method.

[0066] Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 and Figure 10 are longitudinal cross-sectional views that schematically and partially illustrate structures obtained at the end of successive intermediate steps of an example of a method of manufacturing an electronic device according to an embodiment.

[0067] Figure 2 illustrates a structure obtained at the end of the formation of the etching mask 142 on the protective layer 141. The etching mask 142 can be obtained by means of photolithography techniques.

[0068] The etching mask 142 is intended to be used to form cavities 150 in the IMD layer 131 and the PMD layer 107, between the conductive elements 132 and optionally between the contacts 120, as described hereafter with respect to Figures 3 to 7 The openings 142A in the etching mask 142 can be formed at the desired locations for the formation of these cavities, such as for example above the gate region 111 of the transistor 110.

[0069] Figure 3 illustrates a structure obtained at the end of the etching of a portion of the protective layer 141 through the openings 142A of the etching mask 142, the etching forming openings 141A (first openings) in the protective layer 141. This etching is for example a dry etching of the plasma etching type.

[0070] Figure 4 illustrates a structure obtained at the end of the etching of a port 143 (third port) through the IMD layer 131 and up to the PMD layer 107, between two conductive elements 132. The etching is performed through the openings 142A of the etching mask 142 and the openings 141A of the protective layer 141. The port 143 can be formed by means of a suitable anisotropic etching, such as a dry etching of the plasma etching type. The diameter of the port 143 can substantially correspond to the diameter of the openings 141A in the protective layer 141.

[0071] Figure 3 and 4 The etching of the ports 143, 144, 145 can be performed in a single etching step.

[0072] The etching mask 142 is then removed.​​​​​​​

[0073] Figure 5 The structure obtained at the end of the widening of the port 143 by etching is shown to form an open cavity 151 in the IMD layer 131 and the PMD layer 107 between the two conductive elements 132 and possibly between the two contacts 120. The opening of the open cavity 151 corresponds to the opening 141A of the protective layer 141. The open cavity 151 can be formed by means of a suitable isotropic etching, the materials of the IMD layer 131 and the PMD layer 107 being advantageously chosen with respect to the material of the protective layer 141 to avoid etching the protective layer 141. In certain embodiments, the isotropic etching is a wet etching, for example performed with hydrofluoric acid (HF), hydrochloric acid (HC1), potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), sodium hydroxide (NaOH), nitric acid (HNO3), buffered oxide etch (BOE) or a mixture of several of these products, which can be in the form of a vapor.

[0074] The diameter of the port 143 can be able to define the size of the open cavity 151. For example, the greater the diameter of the port 143, the greater the average diameter of the open cavity 151.

[0075] The protective layer 133 located on the side wall or side of the conductive element 132 can advantageously protect the conductive element 132 during the anisotropic etching and / or the isotropic etching.

[0076] The widening of the port 143 is advantageously performed in such a way that all or part of the open cavities 151 can be coupled together, thereby forming a continuous open cavity along one or more directions of the XY plane, for example at least in the Y direction, between the conductive elements 132.

[0077] Figure 5 and 6 The longitudinal cross-section of Figure 2A illustrates a single port 143 between two adjacent conductive elements 132 in the X direction, then a single open cavity 151 by widening the port 143 between the two adjacent conductive elements 132 in the X direction. This cross-section corresponds to one example and a plurality of ports 143 can be formed between two adjacent conductive elements in the X direction, then a plurality of adjacent open cavities 151 coupled together along the X direction, then a plurality of cavities 150 coupled together as illustrated in Figure 11 Figure 2B.

[0078] Figure 6The structure obtained at the end of the formation of the intermetal dielectric layer 144 (second intermetal dielectric layer) or IMD layer 144 on the protective layer 141 and on the openings of the open cavities 151 to close these open cavities 151, thereby forming closed cavities 150, which will be designated as cavities (air gaps), is shown. The IMD layer 144 can be formed by using similar materials and methods as the IMD layer 131 described above. Through the openings 141A through the protective layer 141, the dielectric material of the IMD layer 144 can cover the inner surfaces of the cavities 150 before closing the open cavities 151, thereby forming an inner coating 152 in the cavities 150.

[0079] In certain embodiments, the cavities 150 are located above the gate regions 111 of the transistors 110, and their width can be greater than the combined width of the gate regions 110 and the gate spacers 113.

[0080] Preferably, the cavities 150 located between two adjacent conductive elements 132 are coupled together in one or more directions, forming one or more continuously extending cavities. In other words, the cavities 150 positioned between the same pair of adjacent conductive elements 132 can form a continuously extending cavity, while other cavities 150 positioned between another pair of adjacent conductive elements 132 can form another continuously extending cavity. For example, as described below Figure 11 and Figure 12 As illustrated, the cavities can be coupled together in the lateral direction Y, or even in the longitudinal direction X.

[0081] Figure 7 The structure obtained at the end of the formation of the planarization layer 145 (layer made of silicon oxide, for example) is shown. This planarization layer is optional and can be omitted.

[0082] As a variant, instead of the electronic device 100 Figure 1 , the manufacturing method can start from the structure shown in any one of Figures 2 to 7 , for example from the structure shown in Figure 6 (without planarization layer) or Figure 7 (with planarization layer).

[0083] Figure 8 The structure obtained at the end of the formation of the etching mask 146 on the planarization layer 145 is shown. The etching mask 146 can be obtained by photolithography techniques.

[0084] The openings 146A in the etching mask 146 can be formed at desired locations to form the ports 147 in the IMD layer 144 coupled to the cavities 150 and the conductive elements 132.

[0085] Figure 9The structure obtained at the end of the etching of the planarization layer 145, the IMD layer 144 and the protection layer 141 to form ports 147 through these layers, the etching being performed through the openings 146A of the etching mask 146, is shown. The openings 147 comprise first ports 147A formed in alignment with the cavities 150 and second ports 147B formed in alignment with the conductive elements 132. The first ports 147A enable the reopening of the cavities 150, their filling with conductive material, thereby filling the continuously extending cavities, as described hereafter. The filled first ports form first vias, as described hereafter. For example, the first ports 147A are centered with the openings 141A of the protection layer 141. Once filled with conductive material, the second ports 147B form second vias, as described hereafter.

[0086] Not all of the cavities 150 of the same continuously extending cavity have to be coupled to a first port 147A. Indeed, since the cavities 150 in a single continuously extending cavity are coupled together, it can be sufficient to have only two first ports 147A to fill the cavities 150 with conductive material, for example a first inlet port for the conductive material and a first outlet port for the conductive material. However, more than two first ports can be provided, for example depending on the length of the continuously extending cavity, so that it can be properly filled.

[0087] Figure 10 The structure obtained at the end of the filling of the ports 147 with conductive material 148, for example comprising tungsten, thereby forming conductive vias 149, is shown.

[0088] The filling is performed by means of a suitable deposition technique, such as an ALD technique or a PVD or CVD technique or electroplating.

[0089] The first ports 147A enable the filling of the cavities 150 with conductive material 148, thereby forming conductive regions 155, and the first ports 147A, once filled, form first vias 149A, each coupled to one of the conductive regions 155.

[0090] Since the cavities 150 are coupled together in one or more directions between the conductive elements 132, thereby forming continuously extending cavities, the conductive regions 155 are also coupled together, thereby forming a continuous conductive track or conductive tracks (examples of conductive tracks are shown in Figs. 13A and 13B). In other words, the conductive regions 155 positioned between the same pair of adjacent conductive elements 132 can form a conductive track, while other conductive regions 155 positioned between another pair of adjacent conductive elements 132 can form another conductive track. Each first via 149A is coupled to the conductive track. Figure 12 、 13A and 13B). In other words, the conductive regions 155 positioned between the same pair of adjacent conductive elements 132 can form a conductive track, while other conductive regions 155 positioned between another pair of adjacent conductive elements 132 can form another conductive track. Each first via 149A is coupled to the conductive track.

[0091] The vias 149 also include a second via 149B that is coupled to the conductive element 132 and participates in interconnecting the conductive element 132 of the first metallization level 130 with the conductive element of the second metallization level (eg, Figure 13A and 13B shown).

[0092] In About Figures 8 to 10 The description of the manufacturing method described above takes into account the presence of the planarization layer 145, but the manufacturing method can be easily adapted without the planarization layer. For example, a planarization layer 145 is then formed on the IMD layer 144. Figure 8 The etching mask 146 is formed, and the port 147 and the via 149 penetrate the IMD layer 144 and the protection layer 141.

[0093] Described below Figure 11 and 12 The top view is along Figure 9 and 10 The horizontal cross-sectional plane AA shown is taken in the IMD layer 131 of the first metallization level 130 .

[0094] Figure 11 is schematically and partially shown in Figure 9 A top view of the structure that can be obtained at the end of the steps is shown.

[0095] Figure 11 An embodiment is shown in which a plurality of cavities 150 are formed between two conductive elements 132 in an IMD layer 131 and are coupled together in the longitudinal X direction and the lateral Y direction. A continuously extending cavity 1150 is obtained between the two conductive elements 132. For example, the continuously extending cavity 1150 extends substantially parallel to the conductive elements 132. An opening 141A of the protective layer 141 is shown within each cavity 150.

[0096] exist Figure 11 Only two conductive elements 132 are shown, although there may be other conductive elements 132, such as Figure 9 There may then be multiple continuously extending cavities 1150 . Figure 9 can correspond to along Figure 11 The cross section of the cross-sectional plane BB shown only passes through the opening 141A between the two conductive elements 132. Figure 9 As seen in Figure 11 Likewise, each opening 141A is not necessarily centered in the X direction relative to the continuously extending cavity 1150. Figure 9 The cavity 150 in may in fact correspond to a portion of the continuously extending cavity 1150 seen in the cross-sectional plane BB.

[0097] In certain embodiments, the length LI of the IMD layer 131 between the conductive elements 132, measured in the X direction, is in the range of 0.2 pm to 5 pm. The IMD layer 131 can include forbidden zones 1130 adjacent to each conductive element 132, which are preferably not etched to form the cavities 150 to avoid damaging the conductive elements 132. For example, the length L2 of the forbidden zones 1130, measured in the X direction, is in the range of 0.01 pm to 1 pm.

[0098] The illustrated openings 141A have a square shape. In certain embodiments, the dimension L3 of the openings 141A, measured in each of the X and Y directions, is in the range of 50 nm to 300 nm. The illustrated shape is not limiting and the openings 141A can have any appropriate shape, such as rectangular, circular, elliptical, triangular, hexagonal, octagonal, etc., and all of the openings 141A can not have the same shape.

[0099] The openings 141A are illustrated as being arranged in a staggered manner. In general, the arrangement of the ports 143 corresponds to the arrangement of the openings 141A, so the ports 143 can also be arranged in a staggered manner. This staggered shape of the ports 143 can be advantageous so that the cavities 150 formed during the isotropic etching are coupled together and form a continuously extending cavity 1150. In the illustrated example, the openings 141A are arranged in two columns between the conductive elements 132, although they can be arranged in any appropriate number of columns, for example from one to five columns. Further, in the illustrated example, the openings 141A of one column are offset in the Y direction relative to the openings 141A of the other column. In certain embodiments, the openings 141A are arranged with a pitch PI in the range of 50 nm to 300 nm or 50 nm to 200 nm. However, the openings 141A can be arranged according to any appropriate pattern. Thus, the illustrated configuration is not limiting and other configurations are possible as this enables the formation of a continuously extending cavity.

[0100] Each cavity 150 is illustrated in a simplified form with a circular cross-section centered with respect to the openings 141A of the protection layer 141, the circles overlapping. In certain embodiments, the distance L4 between the openings 141A and the walls of the cavities 150 is in the range of 0 to 500 nm, for example resulting from the isotropic etching time. In practice, the cross-section of each cavity can have a different shape, which is not perfectly circular, and it can not be perfectly centered with respect to the openings 141A of the protection layer 141. More generally, the cavities 150 can have various shapes, the cross-section of which is not necessarily uniform along the horizontal of the cross-sectional plane.

[0101] In certain embodiments, the continuously extending cavity 1150 has a length L5, measured in the X direction, in the range of 0.1 pm to 5 pm.

[0102] Anisotropic etching for forming the ports 143 and isotropic etching for widening the ports 143 and thus forming the cavities 150 can be performed such that the length L5 of the continuously extending cavity 1150 is less than or equal to the length LI of the IMD layer 131 between the conductive elements 132 minus the added length L2 of the two exclusion zones 1130. Further, the ports 143 can be positioned such that the continuously extending cavity 1150 is substantially located in the center of the IMD layer 131 between the conductive elements 132.

[0103] Thus, Figure 11 The illustrated cavities 150 are distributed and overlap in a staggered manner in the X and Y directions, but other configurations are conceivable as the continuously extending cavity is formed in the longitudinal X direction and / or the transverse Y direction.

[0104] Figure 12 is schematically and partially shown in Figure 10 A top view of an electronic device that can be obtained at the end of the illustrated steps.

[0105] Figure 12 The electronic device of Figure 11 corresponds to the structure of Figure 11 after filling the cavities 150 with conductive material, forming conductive regions 155 that together form a conductive track 1155. Figure 12 .

[0106] It can be seen that the conductive track 1155 extends substantially parallel to the conductive elements 132.

[0107] In Figure 12 only two conductive elements 132 are shown, although there can be further conductive elements 132 as illustrated in Figure 10 . There can then be multiple conductive tracks 1155. Figure 10 may correspond to a cross-section along the cross-sectional plane B-B illustrated in Figure 12 that runs through a single opening 141A between two conductive elements 132. As can indeed be seen in Figure 10 , as in Figure 12 , each opening 141A is not necessarily centered in the X direction with respect to the conductive track 1155. Thus, Figure 10 The conductive regions 155 of Figure 12 may in fact correspond to a portion of the conductive track 1155 as seen in the cross-sectional plane B-B of

[0108] Figure 13A and Figure 13B are schematically and partially shown electronic devices according to embodiments, such as Figure 12a top view and a three-dimensional view of an electronic device of Figure 1, additionally having a second metallization level.

[0109] More precisely, Figure 13A and 13B It is shown that Figure 12 the electronic device of Figure 1, additionally having a second metallization level 230 (M2) comprising second metal lines 232 located above the first metallization level 130 (M1) comprising the first metal lines 132 in the IMD layer 131. Second vias 149B couple the first metal lines 132 with some of the second metal lines 232, while first vias 149A can couple other second metal lines 232 together via the conductive tracks 1155, thereby creating the interconnect circuit 300. Thus, the metallization of the cavity 150 enables to create an additional interconnect level.

[0110] Figure 14 is a longitudinal sectional view schematically and partially showing an electronic device according to another embodiment.

[0111] In this embodiment, the electronic device comprises other cavities 150' located between two other adjacent conductive elements, i.e. between Figures 1 to 10 a pair of conductive elements 132, 132' different from the pair of conductive elements 132 described in Figure 1. Only one other cavity 150' is shown, but there are multiple cavities at least in the lateral Y direction. As shown in Figure 14 the two pairs of different conductive elements can comprise the same conductive elements 132. As a variant, the two pairs of different conductive elements can not comprise the same conductive elements. The other cavities 150' are coupled together at least in the Y direction, but they are not filled with conductive material 148.

[0112] In other words, in this method, no port 147 is formed up to these other cavities 150'. Figure 8 The etching mask 146 of Figure 1 can be adapted so that it does not comprise an opening 146A aligned with the other cavities 150'.

[0113] Thus, the electronic device can comprise two conductive regions 155 coupled together to form a conductive track between two conductive elements and cavities 150' not filled with conductive material and coupled together to form a continuously extending cavity between two other conductive elements.

[0114] It can thus be seen that embodiments enable forming additional interconnect levels by using each conductive track and the first via coupled to that track, and by adapting standard electronic device manufacturing processes. In particular, by adapting etching parameters to obtain cavities coupled together, thereby obtaining a continuous extension cavity, the air gap formation process can be used, and by modifying the etching mask used to form ports to form conductive vias between two metallization levels, so that some ports are used to reopen cavities to fill them with metal while forming the conductive vias, the BEOL process can be used.

[0115] The application of embodiments relates to the control of the formation of cavities. By metalizing the cavities and coupling them to conductive vias, circuits can be formed, and the continuity of the metalized cavities can be controlled, for example by controlling the conductivity of the circuits formed by the conductive tracks and vias.

[0116] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these various embodiments and variants can be combined, and will think of other variants. In particular, in embodiments, MOSFET transistors have been shown as electronic components in electronic devices. This is not limiting, and the described embodiments can be adapted to electronic devices comprising other electronic components, for example other types of transistors and / or diodes. More generally, the described embodiments can be adapted to any electronic device comprising electronic components and interconnect structures.

[0117] Finally, actual implementation of the described embodiments and variants is within the capabilities of the person skilled in the art, based on the functional indications given above.

Claims

1. A method of fabricating an electronic device, the method comprising: providing a structure including a semiconductor substrate having electronic components formed at a top and an interior, first conductive elements above the semiconductor substrate, a first intermetallic dielectric layer between the first conductive elements, cavities in the first intermetallic dielectric layer between two first adjacent conductive elements among the first conductive elements, the cavities coupled together to form a continuously extending cavity between the two first adjacent conductive elements, and a second intermetallic dielectric layer over the first intermetallic dielectric layer and the cavities; forming first ports and second ports through the second intermetallic dielectric layer, the first ports each extending to one of the cavities, and the second ports each extending to one of the first conductive elements; filling the first and second ports with a conductive material, the filling the first ports performed to fill the cavities, forming conductive regions coupled together, forming a conductive track, the filling the first ports also forming first conductive vias coupled to the conductive track, and the filling the second ports forming second conductive vias coupled to the first conductive elements.

2. The method of claim 1, wherein the providing the structure includes forming the cavities, including: forming third ports through the first intermetallic dielectric layer between the two first adjacent conductive elements, the forming the third ports including a first anisotropic etch and / or a first dry etch; widening the third ports to form open cavities in the first intermetallic dielectric layer coupled together, the widening the third ports including an isotropic etch and / or a wet etch; and forming the second intermetallic dielectric layer over the open cavities and the first intermetallic dielectric layer to close the open cavities.

3. The method of claim 2, including, prior to the forming the third ports, depositing a first protective layer over the first intermetallic dielectric layer and the first conductive elements, then forming first openings in the first protective layer, the third ports formed in alignment with the first openings, the forming the first openings including a second anisotropic etch and / or a second dry etch.

4. The method of claim 1, wherein the forming the first and second ports includes an anisotropic etch and / or a dry etch.

5. The method of claim 1, wherein the provided structure includes other cavities in the first intermetallic dielectric layer between two other first adjacent conductive elements among the first conductive elements, the second intermetallic dielectric layer also extending over the other cavities, the other cavities coupled together and not filled with the conductive material to form a second continuously extending cavity between the two other first adjacent conductive elements. ​ ​ 6. The method of claim 1, wherein the first conductive elements are insulated from each other by the first intermetal dielectric layer in a first direction of a plane of the semiconductor substrate, the first direction being substantially parallel to the plane of the semiconductor substrate, and the conductive regions are coupled together in a second direction of the plane, the second direction being perpendicular to the first direction.

7. The method of claim 1, wherein lateral edges of the first conductive elements are protected by a second protective layer.

8. The method of claim 1, wherein the conductive regions also extend in a pre-metal dielectric layer, the pre-metal dielectric layer being between the semiconductor substrate and the first intermetal dielectric layer.

9. The method of claim 1, wherein the conductive tracks and the first conductive via are disposed in a circuit for controlling electrical continuity between the conductive regions.

10. An electronic device comprising: a semiconductor substrate having electronic components arranged on top and inside; first conductive elements above the semiconductor substrate; a first intermetal dielectric layer between the first conductive elements; conductive regions extending at least through a thickness of the first intermetal dielectric layer between two first adjacent ones of the first conductive elements, the conductive regions being coupled together in a shape of a conductive track; a second intermetal dielectric layer over the first intermetal dielectric layer, the first conductive elements, and the conductive track; a first conductive via through the second intermetal dielectric layer and coupled to the conductive track; and a second conductive via through the second intermetal dielectric layer and coupled to the first conductive elements.

11. The device of claim 10, further comprising other cavities in the first intermetal dielectric layer between two other first adjacent ones of the first conductive elements, the second intermetal dielectric layer also extending over the other cavities, the other cavities being coupled together to form a continuously extending cavity between the two other first adjacent ones of the first conductive elements.

12. The device of claim 10, wherein the first conductive elements are insulated from each other by the first intermetal dielectric layer in a first direction of a plane of the semiconductor substrate, the first direction being substantially parallel to the plane of the semiconductor substrate, and the conductive regions are coupled together in a second direction of the plane, the second direction being perpendicular to the first direction.

13. The device of claim 12, wherein the conductive regions are also coupled together in the first direction of the plane.

14. The device of claim 10, wherein lateral edges of the first conductive elements are protected by a second protective layer.

15. The device of claim 10, wherein the conductive regions also extend in a pre-metal dielectric layer, the pre-metal dielectric layer being between the semiconductor substrate and the first intermetal dielectric layer. ​ 16. The apparatus of claim 15, wherein contacts through the metal pre-dielectric layer are coupled to the electronic components and the first conductive elements, the conductive regions also extending between the contacts.

17. The apparatus of claim 10, wherein the conductive regions comprise tungsten and / or the first conductive elements comprise copper or aluminum.

18. The apparatus of claim 10, wherein the first conductive elements and the first intermetal dielectric layer are a first metallization level of an interconnect structure.

19. The apparatus of claim 10, wherein the second metallization level comprises: second conductive elements coupled to the first conductive elements through the second conductive vias, and other second conductive elements coupled to the conductive tracks through the first conductive vias.

20. The apparatus of claim 10, wherein the conductive tracks and the first conductive vias are disposed in a circuit for controlling electrical continuity between the conductive regions.

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