Low inrush current power converter circuit

Abstract

The invention relates to a low inrush current power converter circuit. In an example, a circuit (104) includes a transformer (216) including a first winding (238) and a second winding (262) forming an isolation barrier. The circuit includes a first controller (244) coupled to the second winding, a rectifier (248), and an output of the circuit, the first controller configured to generate a signal indicative of a voltage on the output. The circuit includes a second controller (220) coupled to the first winding and a switch (222) and separated from the first controller by the isolation barrier, the second controller configured to operate the switch to have a variable duty cycle with an upper limit in response to the signal, to have a variable duty cycle without an upper limit, and to operate the switch to have a variable duty cycle without an upper limit in response to the signal. Or maintaining the voltage within a hysteresis band.

Description

TECHNICAL FIELD

[0001] The present application relates to a low inrush current power converter circuit. BACKGROUND

[0002] Power converter circuits convert electrical energy from one form to another. For example, a DC-DC power converter circuit receives an input DC voltage and provides an output DC voltage that is different from the input DC voltage. For example, a buck converter can lower the voltage, while a boost converter can raise the voltage. Power converter circuits can be implemented in various systems to meet the particular power requirements of those systems. SUMMARY

[0003] In an example, a circuit includes a transformer including a first winding and a second winding forming an isolation barrier. The circuit includes a first controller coupled to the second winding, a rectifier, and an output of the circuit, the first controller configured to generate a signal indicative of a voltage on the output. The circuit includes a second controller coupled to the first winding and a switch and separated from the first controller by the isolation barrier, the second controller configured to operate the switch to have a variable duty cycle with an upper limit, have a variable duty cycle without an upper limit, or maintain the voltage within a hysteresis band in response to the signal. BRIEF DESCRIPTION OF DRAWINGS

[0004] Figure 1 A block diagram of an electronic device implementing a low inrush current power converter circuit according to various examples.

[0005] Figure 2 A schematic diagram of a low inrush current power converter circuit according to various examples.

[0006] Figure 3 A schematic diagram of a set of switches in a low inrush current power converter circuit according to various examples.

[0007] Figure 4 A block diagram of a controller in a low inrush current power converter circuit according to various examples.

[0008] Figure 5 A schematic diagram of a rectifier in a low inrush current power converter circuit according to various examples.

[0009] Figure 6 A block diagram of a controller in a low inrush current power converter circuit according to various examples.

[0010] Figure 7 A flowchart of a method for operating a low inrush current power converter circuit according to various examples.

[0011] Figure 8A timing diagram indicating behavior of signals produced by a low inrush current power converter circuit according to various examples.

[0012] Figure 9 A schematic diagram of a voltage comparison circuit in a low inrush current power converter circuit according to various examples.

[0013] Figure 10 A schematic diagram of a transformer switching detection circuit in a low inrush current power converter circuit according to various examples.

[0014] Figure 11 A schematic diagram of an encoding circuit in a low inrush current power converter circuit according to various examples.

[0015] Figure 12 A schematic diagram of a decoding circuit in a low inrush current power converter circuit according to various examples.

[0016] Figure 13 A schematic diagram of a decoding circuit in a low inrush current power converter circuit according to various examples.

[0017] Figure 14 And 15 A plot indicating operation of a low inrush current power converter circuit according to various examples. DETAILED DESCRIPTION

[0018] In many power converter circuits, a capacitor is coupled across the output terminals of the circuit to smooth the output voltage provided by the circuit. More particularly, the capacitor is adapted to filter high frequency noise or ripple present in the output voltage that can be introduced, for example, by switching action of the circuit. While the maximum charge that the capacitor can hold during steady state operation is limited, during startup of the circuit, the capacitor can not hold any charge. Thus, the capacitor is able to charge quickly, with the circuit output voltage rising quickly and the input current to the circuit also rising quickly. The input current can rise so high during startup of the circuit (e.g., up to three times the input current drawn during steady state operation) that an oversized front end power supply is needed to provide the input current to the power converter circuit. Providing an oversized front end power supply is undesirable at least because it increases manufacturing costs and product size. In addition, the large inrush current can damage circuitry in the front end power supply, in the power converter, or both.

[0019] Prior attempts to mitigate high inrush current in power converter circuits have failed. Some of these attempts have reduced inrush current to a modest degree, but results have been inconsistent and high inrush current remains a technical challenge, especially before the power converter circuit has reached a regulation mode (e.g., an operating mode in which the power converter circuit periodically enables and disables switching action to maintain an output voltage within a defined hysteresis band). In other attempts, startup of the power converter circuit remains a technical challenge because startup can occur shortly after the power converter is turned off and capacitors have not fully discharged. In such cases, the controller of the power converter circuit operates at startup under the assumption that capacitors are fully discharged, but because capacitors still retain some charge from previous use, the circuit suffers from output voltage overshoot. Such overshoot can damage components that receive power from the power converter circuit. Prior attempts to mitigate high inrush current are also technically flawed because their implementation requires a high quiescent current cross-isolation barrier communication scheme, which results in low operating efficiency, especially when the power converter circuit is lightly loaded.

[0020] Prior attempts have also failed to adequately react to a short circuit in a power converter circuit. In the case of a short circuit, the power converter circuit will operate normally, resulting in a large inrush current, and the attendant technical shortcomings described above.

[0021] The present disclosure describes various examples of low inrush current power converter circuits that mitigate the technical challenges described above. More particularly, each example power converter circuit described herein includes a controller that assesses the state of the power converter circuit (e.g., the output voltage of the power converter circuit) immediately after startup and selectively enables different operating modes of the power converter circuit depending on the assessment. The circuit can enter any of the various operating modes directly after the assessment, without having to sequentially go through the modes. Because the power converter circuit enables its operating modes based on output voltage measurements rather than on assumptions about the output voltage, the circuit mitigates the various technical challenges described above.

[0022] For example, immediately after startup, the controller of the power converter circuit can assess the state of the circuit and determine that no state indicator is available. Accordingly, the controller can enable a first operating mode in which the controller strictly controls the power converter circuit switching duty cycle. Limiting the duty cycle in this way prevents overcharging of the output capacitor (which can result in high inrush current) and further prevents high inrush current in the setup of a short circuit in the power converter circuit.

[0023] After start-up, the controller can determine that the status indicator is indicating that the output voltage is above the first threshold but below the second threshold. The fact that the output voltage has exceeded the first threshold implies that there is likely no short-circuit in the power converter circuit, and thus it is safe to remove the constraint on the switching duty cycle. Accordingly, the controller can enable a second operating mode in which the switching duty cycle continues to increment, but now there is no duty cycle constraint. As long as the status indicator indicates that the output voltage remains between the first threshold and the second threshold, the power converter circuit continues to operate in the second operating mode.

[0024] After start-up, the controller can determine that the status indicator is indicating that the output voltage is above the second threshold voltage. This means that the output voltage has reached the regulation mode, such that the output voltage is approaching the target steady-state output voltage. Accordingly, the controller enables a third operating mode in which the switching action is enabled when the output voltage reaches the lower boundary of the hysteresis band, and the switching action is disabled when the output voltage reaches the upper boundary of the hysteresis band. In this way, the output voltage is maintained within the hysteresis band. By dynamically and selectively enabling the operating mode of the power converter circuit based on the output voltage immediately after start-up, the situations that typically result in large inrush currents, such as those common to the prior solutions described above, are completely avoided.

[0025] Figure 1 A block diagram of an electronic device implementing a low inrush current power converter circuit according to various examples. In particular, Figure 1 An electronic device 100 is depicted, which can be any suitable type of electronic device, such as a smartphone, a laptop computer, a desktop computer, a notebook computer, a tablet computer, an appliance (e.g., a kitchen appliance), a television, a heating or cooling product, an automobile, a boat, an airplane, a spacecraft, etc. The device 100 can include a printed circuit board (PCB) 102 to which various circuitry is coupled. A low inrush current power converter circuit (PCC) 104 can be coupled to the PCB 102. Examples of the power converter circuit 104 are described herein.

[0026] Figure 2is a schematic diagram of a PCC 104 according to various examples. The PCC 104 can include a primary side 200 and a secondary side 202 separated by a transformer isolation barrier 204. A power source 206, such as a voltage source, is coupled to the primary side 200 and provides voltage (and current) to the primary side 200. The power source 206 is coupled to a positive terminal 207 and a ground terminal 208. A capacitor 210 is coupled to the secondary side 202. For example, the capacitor 210 can be coupled in parallel with a load (not explicitly shown) coupled to a positive terminal 212 and a ground terminal 209. The capacitor 210 can have any suitable capacitance depending on the particular application in which the PCC 104 is deployed. The primary side 200 provides power to the secondary side 202 by way of a transformer 216, as described in detail below. The secondary side 202 transmits data to the primary side 200 by way of a transformer 218, as described in detail below.

[0027] The primary side 200 can include a controller 220. The controller 220 can include any combination of analog circuitry, digital circuitry, processors, memory, and / or executable instructions that can be suitable for performing the actions attributed herein to the controller 220. Example content of the controller 220 is described below. The primary side 200 can include a set of switches 222 (e.g., in a bridge topology configuration) and gate drivers 224 coupled to the controller 220 and to the gates of the switches 222 (e.g., gate terminals of field effect transistor (FET) switches 222). In addition, the primary side 200 can include a demodulator 225 coupled to the controller 220. Any suitable connection topology can be suitable for coupling the components of the primary side 200 to one another. In at least some examples, a connection 226 couples the demodulator 225 to the controller 220, a connection 228 couples the controller 220 to the gate drivers 224, and a connection 230 couples the gate drivers 224 to the switches 222. Each connection described herein can include one or more physical connections (e.g., metal traces). The connection 226 provides a signal FB_SIGNAL_RX from the demodulator 225 to the controller 220. The connection 228 provides a signal ON / OFF-PRIM from the controller 220 to the gate drivers 224. The connection 230 provides switching signals from the gate drivers 224 to the switches 222. A winding 232 of the transformer 218 is coupled to the demodulator 225 by way of terminals 234 and 236. A winding 238 of the transformer 216 is coupled to the switches 222 by way of terminals 240 and 242.

[0028] Briefly referring to Figure 3An example circuit diagram of the switch 222 is shown in FIG. 22. The switch 222 includes switches (e.g., FETs) 222a-d coupled, for example, in a bridge topology. The switches 222a and 222b can be coupled at a node 300. The switches 222a and 222c can be coupled at a node 302. The switches 222b and 222d can be coupled at a node 304. The switches 222c and 222d can be coupled at a node 306. The nodes 300 and 306 can be considered "switching nodes," with the node 300 coupled to the terminal 240 Figure 2 ) and the node 306 coupled to the terminal 242 Figure 2 ). The node 302 is coupled to the positive terminal 207 Figure 2 and 3 , and the node 304 is coupled to the ground terminal 208 Figure 2 and 3 . Figure 2 and 3 The connection 230 shown in FIG. 22 is a single connection, but in examples, the connection 230 can be multiple connections, one for each gate terminal of the switches 222a-d. In this way, the switches 222a-d can be controlled individually. In an example, the switches 222a and 222d can be on, while the switches 222b and 222c are off, thereby connecting the terminal 240 Figure 2 ) to the positive terminal 207 and the terminal 242 Figure 2 ) to the ground terminal 208. Similarly, the switches 222a and 222d can be off, while the switches 222b and 222c are on, thereby connecting the terminal 240 Figure 2 ) to the ground terminal 208 and the terminal 242 Figure 4 ) to the positive terminal 207. In this way, the voltage across the terminals 240, 242 alternates in polarity back and forth, inducing an alternating current in the winding 238 to generate an electromagnetic field.

[0029] Referring briefly to FIG. 20, Figure 4 a block diagram of an example controller 220 is shown. As mentioned above, the controller 220 can include any combination of analog circuitry, digital circuitry, processors, memories, and / or executable instructions that can be suitable for performing the actions attributed herein to the controller 220. In the example of FIG. 20, Figure 4 The controller 220 includes a processor 400, a memory 402 (e.g., a non-transitory computer-readable medium such as a random access memory (RAM)), executable instructions 404 stored on the memory 402, and a decoding circuit 406. A connection 408 couples the processor 400 to the memory 402. A connection 410 couples the processor 400 to the decoding circuit 406. The controller 220 receives the signal FB_SIGNAL_RX and provides the signal ON / OFF-PRIM, as shown.Figure 2 Any combination of the components shown in FIG. 2 can perform some or all of the actions attributed herein to controller 220. Example content of decode circuit 406 and example operations of controller 220 are described below.

[0030] Referring again to Figure 2 , in operation, current induced in winding 232 (described below) is provided to demodulator 225, which demodulates the current to determine data encoded in the current. Demodulator 225 produces a signal FB_SIGNAL_RX indicative of the data. Controller 220 receives FB_SIGNAL_RX and decodes the signal to produce a signal ON / OFF-PRIM, and controller 220 uses ON / OFF-PRIM to control gate driver 224 accordingly. Gate driver 224 controls individual ones of switches 222 based on ON / OFF-PRIM. Switching actions of switches 222 energize winding 238, forming an electromagnetic field in transformer 216 and providing power across isolation barrier 204.

[0031] Still referring to Figure 5 , secondary side 202 can include a controller 244. Controller 244 can include any combination of analog circuitry, digital circuitry, processors, memories, and / or executable instructions, which can be suitable for performing the actions attributed herein to controller 244. Example content of controller 244 is described below. Secondary side 202 further includes a modulator 246, a rectifier 248, a voltage comparison circuit 250 having a reference voltage (V REF ) input coupled to connection 252, and a transformer switching detection circuit 254. Connection 256 couples voltage comparison circuit 250 to controller 244 and provides a signal ON / OFF-SEC, and connection 257 couples voltage comparison circuit 250 to controller 244 to provide a signal COMM_ENABLE. Connection 258 couples transformer switching detection circuit 254 to controller 244 and provides a signal SEC_SW_DET. Connection 260 couples controller 244 to modulator 246 and provides a signal FB_SIGNAL_TX. Various components in secondary side 202 are coupled to positive terminal 212 and / or ground terminal 209, including secondary rectifier 248 and voltage comparison circuit 250, as described below. Secondary side 202 can further include a winding 262 of transformer 216, which is coupled to secondary rectifier 248 by way of terminals 264 and 266 and also to transformer switching detection circuit 254 by way of terminals 264 and 266. Secondary side 202 further includes a winding 268 of transformer 218, which is coupled to modulator 246 by way of terminals 270 and 272.

[0032] Briefly referring toFigure 2 The rectifier 248 can include a plurality of diodes (e.g., diodes 500a-500d) configured in a bridge topology. Diodes 500a and 500b can be coupled through a node 502, and diodes 500c and 500d can be coupled through a node 504. Diodes 500a and 500c can be coupled through a node 506, and diodes 500b and 500d can be coupled through a node 508. Nodes 502 and 504 can be coupled to terminals 264 and 266, respectively. Figure 6 When the polarity of the voltage across nodes 502, 504 is positive, diodes 500a and 500d turn on, while diodes 500b and 500c turn off, thereby providing a voltage having a positive polarity across terminals 212, 209. Conversely, when the polarity of the voltage across nodes 502, 504 is negative, diodes 500a and 500d turn off, while diodes 500b and 500c turn on, thereby again providing a voltage having a positive polarity across terminals 212, 209. Thus, the polarity of the voltage across terminals 212, 209 remains positive regardless of the polarity of the voltage across nodes 502, 504, which repeatedly changes during the switching action of switch 222 to generate an electromagnetic field in transformer 216.

[0033] Briefly referring to Figure 6 a block diagram of an example controller 244 is shown. As mentioned above, controller 244 can include any combination of analog circuitry, digital circuitry, processors, memories, and / or executable instructions, which can be suitable for performing the actions attributed herein to controller 244. In the example shown, Figure 6 Controller 244 includes a processor 600, a memory 602 (e.g., a non-transitory computer-readable medium such as a random access memory (RAM)), executable instructions 604 stored on memory 602, and a decoding circuit 606. A connection 608 couples processor 600 to memory 602. A connection 610 couples processor 600 to decoding circuit 606. Controller 244 receives signals ON / OFF-SEC and SEC_SW_DET and provides signal FB_SIGNAL_TX, as shown. Figure 2 Any combination of the components shown in

[0034] Briefly referring to Figure 7In operation, current induced in winding 262 is provided to rectifier 248. Due to the switching action of switch 222, the current induced in winding 262 is alternating current, and rectifier 248 converts the alternating current to direct current (DC). Rectifier 248 provides a DC voltage across positive terminal 212 and ground terminal 209. This DC voltage is the output voltage V CC of PCC 104. CC A DC voltage is provided across and charges capacitor 210. Since V CC is the DC voltage provided by rectifier 248, capacitor 210 is continuously charged while switch 222 is switching, regardless of the polarity of the voltage provided at terminals 240, 242 or the direction of current through winding 238. When switch 222 ceases to switch, capacitor 210 is continuously discharged. As described above, the controller (e.g., controllers 220, 244) of PCC 104 enables a particular operating mode of PCC 104 based on an evaluation of output voltage V CC . Voltage comparison circuit 250 detects V CC , compares V CC to one or more reference voltages V REF , and provides ON / OFF-SEC to controller 244 accordingly. Voltage comparison circuit 250 also provides signal COMM_ENABLE to controller 244, which indicates whether a status indicator signal is available from secondary side 202 to primary side 200. Transformer switching detection circuit 254 determines whether transformer 216 is switching current direction at a given time (i.e., whether switch 222 is actively switching), with SEC_SW_DET indicating to controller 244 whether transformer 216 is switching. Based on ON / OFF-SEC, COMM_ENABLE, and SEC_SW_DET, controller 244 prepares signal FB_SIGNAL_TX, which indicates the PCC 104 operating mode that controller 220 should enable and whether controller 220 should start or stop the switching action of switch 222 to maintain V CC within a hysteresis band defined by V REF signal provided on connection 252. Modulator 246 receives FB_SIGNAL_TX and modulates the signal on winding 268 via terminals 270, 272, thereby forming an electromagnetic field in transformer 218 to provide FB_SIGNAL_TX to modulator 225 across isolation barrier 204. Controller 220 receives the communication from controller 244 and controls switch 222 accordingly. The operating mode indicated by controller 244 to controller 220 informs controller 220 of a particular way to control switch 222, as described below.

[0035] Figure 8A flowchart of a method 700 for operating a low-inrush current power converter circuit according to various examples. The method 700 can be performed by the controller 220. Alternatively, the method 700 can be performed by multiple components within the PCC 104, in which case the PCC 104 can be said to perform the method 700. Some operations of the method 700 can be performed by other components or entities external to the PCC 104. Figure 7 A timing diagram 800 indicating behavior of signals generated by a low-inrush current power converter circuit according to various examples. The timing diagram 800 is described concurrently with Figure 2 and 8 schematic diagrams of Figure 1

[0036] Before describing the operations of the method 700, the layout of the timing diagram 800 is described. The timing diagram 800 depicts the behavior of various signals in the PCC 104. At the bottom of the timing diagram 800, multiple operating modes of the PCC 104 are shown. In particular, the timing diagram 800 depicts a monitoring mode 802, a capped duty cycle mode 804, an uncapped duty cycle mode 806, and a regulation mode 808. During the monitoring mode 802, the controller 220 receives and evaluates a PING signal received from the controller 244 in the FB_SIGNAL_RX. The PING signal is based on the state of the V CC . For example, based on the frequency of the PING signal, the controller 220 enables the mode 804, the mode 806, or the mode 808. When the PING signal frequency is zero, the controller 220 enables the mode 804, which is an indication that the V CC is low or the state of the V CC is unknown. In the mode 804, the controller 220 begins switching actions of the switch 222 with a gradually increasing duty cycle, but the duty cycle is limited to a maximum value that does not exceed when in the mode 804. When the PING signal frequency is above zero but below a threshold frequency, the controller 220 enables the mode 806, which is an indication that the V CC has reached a voltage threshold and thus there is no short circuit in the PCC 104. In the mode 806, the controller 220 continues switching actions of the switch 222 with a gradually increasing duty cycle, but the duty cycle is no longer limited to a maximum value because the controller 220 has confirmed that there is no short circuit in the PCC 104. When the PING signal frequency is above the threshold frequency, the controller 220 enables the mode 808, which is an indication that the V CC has reached a target hysteresis band. In the mode 808, the controller 220 turns on and off switching actions of the switch 222 according to instructions received from the controller 244 to bring the V CC ​Maintained within the target hysteresis band. Controller 244 sends these instructions to controller 220 along with the PING signal, both of which are encoded on FB_SIGNAL_TX and FB_SIGNAL_RX. The operational modes 802, 804, 806, and 808 are described in detail below.

[0037] Timing diagram 800 also includes: signal 810, which is the output voltage V CC of PCC 104; ENABLE signal 812, which indicates whether PCC 104 is enabled, and which can be generated by a component external to PCC 104 (e.g., coupled to the same PCB 102 Figure 1 ) as PCC 104, to turn on or off a switch (not explicitly shown) between power supply 206 and positive terminal 207; COMM_ENABLE signal 814, which indicates whether communication between primary side 200 and secondary side 202 is enabled; ON / OFF-SEC signal 816, which is the ON / OFF-SEC signal on connection 256 of PCC 104, and which indicates whether V CC is within the target hysteresis band, and thus whether switch 222 should be toggled; PING signal 818, which is a signal generated by controller 244 to indicate an operational mode in which PCC 104 should operate based at least on the state of V CC ; signal 820, which is the FB_SIGNAL_TX signal (provided by controller 244 to modulator 246 and from modulator 246 to demodulator 225), and which is the same as the FB_SIGNAL_RX signal (provided from demodulator 225 to controller 220), and which is a logical OR combination of ON / OFF-SEC signal 816 and PING signal 818; ON / OFF-PRIM signal 822, which is provided by controller 220 to gate driver 224 to operate switch 222; and PRIM_DUTY_CYCLE signal 824, which indicates a change in duty cycle in ON / OFF-PRIM signal 822. Of the signals depicted in timing diagram 800, PRIM_DUTY_CYCLE signal 824 is provided to facilitate reader understanding, and can not necessarily be a signal implemented in PCC 104. The various signals shown in timing diagram 800 are described in detail below.

[0038] Method 700 begins with enabling PCC 104 (702). Any suitable entity, such as another component coupled to PCB 102 Figure 8 ), can provide an ENABLE signal (e.g., signal 812) to activate power supply 206 and / or turn on a switch that can be placed on an electrical path between power supply 206 and PCC 104. In Figure 1In the embodiment of the present invention, the ENABLE signal 812 rises from low to high to enable the PCC 104, as indicated by reference numeral 856. For example, the ENABLE signal 812 may be generated by the PCB 102 ( Figure 8 ) and can be provided to the gate terminal of the switch positioned on the positive terminal 207, and thus when the ENABLE signal 812 goes high, the power supply 206 is electrically coupled to the PCC 104 and provides power to the PCC 104.

[0039] The method 700 further includes detecting a PING signal provided by the secondary side 202 to the primary side 200 (704). Step 704 corresponds to Figure 9 During monitoring mode 802, controller 220 receives signal FB_SIGNAL_RX (signal 820) from controller 244 and separates the FB_SIGNAL_RX signal into its constituent components, namely ON / OFF-SEC signal 816 and PING signal 818. The frequency of PING signal 818 indicates to controller 220 that the secondary side 202 should be monitored based on its status (e.g., V CC The generation and transmission of the PING signal 818 will now be described, after which the description of the method 700 will be resumed.

[0040] To generate the PING signal 818, the controller 244 uses the ON / OFF-SEC and COMM_ENABLE signals from the voltage comparator circuit 250 and the SEC_SW_DET signal from the transformer switching detection circuit 254. The ON / OFF-SEC signal indicates when the switching action of the switch 222 should be started or stopped to reduce V CC Maintained within the target hysteresis band of the PCC 104. The COMM_ENABLE signal indicates when the PING signal 818 may be provided to the controller 220. The SEC_SW_DET signal indicates when the switch 222 is actively switching.

[0041] To generate ON / OFF-SEC, the voltage comparison circuit 250 converts V CC and V received on connector 252 REF The reference voltage is compared and a signal ON / OFF-SEC is generated on the connection 256, which indicates when the switching action of the switch 222 should be started and stopped to change V CC Maintained by V REF The reference voltage is within the hysteresis band defined by the reference voltage. Figure 2A schematic diagram of an example voltage comparison circuit 250. The example voltage comparison circuit 250 includes comparators 900, 902, and SR flip-flop 904. Comparator 900 includes inputs coupled to connections 252a and 908, and an output coupled to connection 910. Comparator 902 includes inputs coupled to connections 912 and 252b, and an output coupled to connection 916. Flip-flop 904 includes S and R inputs, and a Q output coupled to connection 256. The input coupled to connection 252a is a non-inverting input and receives V REFLOW , which represents the lower boundary of the hysteresis band, and the input coupled to connection 252b is an inverting input and receives V REFHIGH , which represents the upper boundary of the hysteresis band. The inputs coupled to connections 908 and 912 both receive V CC from positive terminal 212 Figure 8 . When V CC falls just below V REFLOW , output 910 goes from low to high. At the same time, V CC is below V REFHIGH , so output 916 remains low. Since the S input receives a high signal and the R input receives a low signal, connection 256 (the ON / OFF-SEC signal) is latched high. As described below, the ON / OFF-SEC going high causes switch 222 to start switching, which in turn causes V CC to rise. When V CC enters the hysteresis band, both outputs 910 and 916 are low, but ON / OFF-SEC remains high because connection 256 is latched high. When V CC rises just above V REFHIGH , output 916 will be high and output 910 will be low. Thus, flip-flop 904 will be reset, causing connection 256 (the ON / OFF-SEC signal) to be latched low. This causes switch 222 to stop switching, which in turn causes V CC to fall. When V CC re-enters the hysteresis band, both outputs 910 and 916 are low, but ON / OFF-SEC remains low because flip-flop 904 is latched low.

[0042] In an example, voltage comparison circuit 250 also includes comparator 907, which has an inverting input coupled to connection 252c and a non-inverting input coupled to connection 911, and an output coupled to connection 913. Connection 911 provides V CC , and connection 252c provides V UVLO , which is a threshold voltage, as described below. Figure 8The label 828 in FIG. 8 indicates that above the threshold voltage it is safe to assume that the PCC 104 is free of short circuits, and the connection 913 receives COMM_ENABLE (which is Figure 10 the signal 814 in FIG. 8). When V CC rises above the threshold voltage V UVLO , the COMM_ENABLE signal 814 goes high, as indicated by the label 858, indicating that there is no short circuit and that the PING signal can be sent to the controller 220.

[0043] Figure 2 A schematic of the transformer switching detection circuit 254 to generate SEC_SW_DET. The transformer switching detection circuit 254 includes a comparator 1000, a comparator 1002, and a logic OR gate 1004. The comparator 1000 includes a non-inverting input coupled to a connection 1006, an inverting input coupled to a connection 1008, and an output coupled to a connection 1010. The comparator 1002 includes a non-inverting input coupled to a connection 1012, an inverting input coupled to a connection 1014, and an output coupled to a connection 1016. The OR gate 1004 has inputs coupled to the connections 1010 and 1016, and has an output coupled to a connection 1018, which is coupled to Figure 2 the connection 258 of FIG. 8. A voltage bias 1020 is coupled to the connection 1008, and a voltage bias 1022 is coupled to the connection 1014. The connection 1006 is coupled to the terminal 264, and the connection 1008 is coupled to the terminal 266. The connection 1012 is coupled to the terminal 266, and the connection 1014 is coupled to the terminal 264. When the signal provided to the connection 1006 is higher than the signal provided to the connection 1008, the comparator 1000 provides a high signal on the connection 1010. Otherwise, the comparator 1000 provides a low signal on the connection 1010. Similarly, when the signal provided to the connection 1012 is higher than the signal provided to the connection 1014, the comparator 1002 provides a high signal on the connection 1016. When the signals on the connections 1010, 1016 are both high, the OR gate 1004 provides a high signal on the connection 1018.

[0044] In operation, the transformer switching detection circuit 254 detects switching activity of the transformer 216 (and more particularly, switching activity of the switch 222) by providing a first output when the transformer 216 is actively switching current direction due to switching activity of the switch 222, and providing a second output when the transformer 216 is not actively switching current direction due to switching activity of the switch 222. The voltage received on the connection 1008 is biased by the voltage bias 1020, and the voltage received on the connection 1014 is biased by the voltage bias 1022. When the voltage induced in the terminals 264, 266 Figure 2), the voltage SW_POS on connection 1006 will exceed the voltage of SW_NEG plus the voltage bias 1020 on connection 1008, thereby causing connection 1010 to carry a high signal. Similarly, when current is sensed in the opposite direction at terminals 264, 266 ( Figure 2 ), the voltage SW_NEG on connection 1012 will exceed the voltage of SW_POS plus the voltage bias 1022 on connection 1014, thereby causing connection 1016 to carry a high signal. In either case, the output of OR gate 1004 will be high on connection 1018 (SEC_SW_DET). Conversely, when the current between terminals 264, 266 is not switching direction due to the inactivity of switch 222, voltages SW_POS and SW_NEG will be approximately equal, and therefore the outputs of connections 1010, 1016 will both be low, causing the output of OR gate 1004 to be low on connection 1018. Therefore, a high state of SEC_SW_DET on connection 1018 is interpreted as indicating switching activity of switch 222 and transformer 216, and a low state of SEC_SW_DET on connection 1018 is interpreted as indicating a lack of switching activity of switch 222 and transformer 216.

[0045] Reference again Figure 11 、 7 and 8 and now also refer to Figure 6 , the controller 244 receives ON / OFF-SEC, COMM_ENABLE, and SEC_SW_DET on connections 256, 257, and 258, respectively, as described, and uses these signals to generate a PING signal. For example, the controller 244 ( Figure 11 ) can use the ON / OFF-SEC, COMM_ENABLE and SEC_SW_DET signals to generate a PING signal. Figure 8 1 is a schematic diagram of encoding circuit 606. Encoding circuit 606 may include a D flip-flop 1100. D flip-flop 1100 may include a D input, a clock input, a RESET input, and a Q output. The D input may be coupled to voltage source 1102. The clock input may be coupled to connection 1106, which is coupled to connection 256 and receives the ON / OFF-SEC signal via the connection. The Q output is coupled to connection 1104, on which D flip-flop 1100 provides a signal SEC_CTRL. Signal SEC_CTRL indicates whether PCC 104 is to be in regulation mode (as indicated by Figure 2 The RESET input receives the inverse of the ENABLE signal described above.

[0046] The encoding circuit 606 can include a logic NOR gate 1110 having a plurality of inputs. A first input to the NOR gate 1110 can be coupled to a connection 1105 that is coupled to the connection 258( Figure 8 ) and provides the signal SEC SW DET. A second input to the NOR gate 1110 can be coupled to the connection 1106 that provides ON / OFF-SEC. A third input to the NOR gate 1110 can be coupled to the connection 1104 that provides the signal SEC CTRL. The third input can be an inverting input. The NOR gate 1110 has an output coupled to a connection 1111.

[0047] The encoding circuit 606 includes a logic AND gate 1112 having a first input coupled to the connection 1111 and a second inverting input coupled to a connection 1119. The AND gate 1112 has an output coupled to a connection 1113. The encoding circuit 606 includes a delay block 1114, such as a 12.5 microsecond delay block, having an input coupled to the connection 1113 and an inverting reset input coupled to the connection 1113. The delay block 1114 has an output coupled to a connection 1115.

[0048] The encoding circuit 606 includes a pulse generator 1116, such as a 25 nanosecond (ns) pulse generator, having a clock input coupled to the connection 1115 and an output coupled to a connection 1117. A feedback delay block 1118 has an input coupled to the connection 1117 and an output coupled to the connection 1119.

[0049] The encoding circuit 606 includes a logic OR gate 1120 having a first input coupled to the connection 1117 and a second input coupled to a connection 1129. The OR gate 1120 provides an output coupled to a connection 1121.

[0050] The encoding circuit 606 includes a NOR gate 1123 having a first input coupled to the connection 1104 that receives SEC CTRL, a second input coupled to the connection 1106 that receives ON / OFF-SEC, and a third inverting input coupled to the connection 1109 that receives COMM ENABLE. The NOR gate 1123 includes an output coupled to a connection 1124. The encoding circuit 606 includes a logic AND gate 1125 having a first input coupled to the connection 1124 and a second inverting input coupled to a connection 1131. The AND gate 1125 has an output coupled to a connection 1126.

[0051] The encode circuit 606 includes a delay block 1127, e.g., a 25 microsecond delay block, having an input coupled to the connection 1126, an inverted reset input coupled to the connection 1126, and an output coupled to the connection 1103. The encode circuit 606 includes a pulse generator 1128, e.g., a 25 ns pulse generator, having a clock input coupled to the connection 1103 and an output coupled to the connection 1129. The encode circuit 606 can include a delay block 1130, e.g., a 50 ns delay block, having an input coupled to the connection 1129 and an output coupled to the connection 1131.

[0052] The encode circuit 606 can include a pulse generator 1132, e.g., a 25 ns pulse generator, having a clock input coupled to the connection 1106 to receive ON / OFF-SEC and an output coupled to the connection 1133. The encode circuit 606 includes a pulse generator 1137, e.g., a 30 ns pulse generator, having a clock input coupled to the connection 1133 and an output coupled to the connection 1139. The encode circuit 606 includes an inverter 1138 having an input coupled to the connection 1139 and an output coupled to the connection 1140. A logic AND gate has a first input coupled to the connection 1140 and a second input coupled to the connection 1106, and an output coupled to the connection 1143. A pulse generator 1142, e.g., a 1 microsecond pulse generator, has a clock input coupled to the connection 1143, a reset input coupled to the connection 1105, e.g., to receive SEC_SW_DET, and an output coupled to the connection 1148. The encode circuit 606 also includes a pulse generator 1144, e.g., a 1 microsecond pulse generator, having a clock input coupled to the connection 1106, e.g., to receive ON / OFF-SEC, a reset input coupled to the output of an inverter 1145, and an output coupled to the connection 1146. The input to the inverter 1145 is coupled to the connection 1105, e.g., to receive SEC_SW_DET.

[0053] The encode circuit 606 can include a logic OR gate 1134 having a first input coupled to the connection 1133, a second input coupled to the connection 1148, and an output coupled to the connection 1149. A logic OR gate has a first input coupled to the connection 1149, a second input coupled to the connection 1146, and an output coupled to the connection 1136. The logic OR gate 1122 includes a first input coupled to the connection 1121, a second input coupled to the connection 1136, and an output coupled to the connection 1147.

[0054] The operation of the encoding circuit 606, and thus the generation of the PING signal, is now described. The encoding circuit 606 uses the signals ON / OFF-SEC, SEC_SW_DET, COMM_ENABLE, and SEC_CTRL to generate the PING signal. While ON / OFF-SEC, SEC_SW_DET, and COMM_ENABLE are already available to the encoding circuit 606, as provided by other components in the PCC 104, the encoding circuit 606 should generate SEC_CTRL. Thus, reference is made to Figure 11 and 11 The D flip-flop 1100 uses ON / OFF-SEC to generate the signal SEC_CTRL, which indicates that the PCC 104 is in a hysteresis operation (e.g., the regulation mode 808). Upon receiving a rising edge of ON / OFF-SEC, the D flip-flop 1100 is triggered. Since ON / OFF-SEC only contains a pulse during the regulation mode 808, the presence of a rising edge of ON / OFF-SEC indicates that the regulation mode 808 has started. The receipt of the rising edge triggers the D flip-flop 1100 to capture the high signal provided by the voltage source 1102 at the D input. The Q output provides the latched high signal on the connection 1104 as SEC_CTRL. After SEC_CTRL goes high, SEC_CTRL should remain high until the PCC 104 is turned off and turned on again, at which point SEC_CTRL should go low until the controller 220 has an opportunity to evaluate the PING signal received from the controller 244. Thus, the inverse of the ENABLE signal 812 is provided to the RESET input of the D flip-flop 1100.

[0055] The components 1110, 1112, 1114, 1116, and 1118 together use SEC_SW_DET, ON / OFF-SEC, and SEC_CTRL to generate a high-frequency PING signal that will cause the controller 220 to enable the regulation mode 808, as described above. Such a high-frequency PING signal can be referred to herein as a fast PING signal. The components 1123, 1125, 1127, 1128, and 1130 together use SEC_CTRL, COMM_ENABLE, and ON / OFF-SEC to generate a low-frequency PING signal that will cause the controller 220 to enable the no upper limit duty cycle mode 806, as described above. Such a low-frequency PING signal (which is greater than zero frequency but less than the frequency threshold to qualify as a fast PING signal) can be referred to herein as a slow PING signal. A zero-frequency PING signal is simply the absence of a fast PING signal and a slow PING signal.

[0056] The pulse generator 1116 produces each pulse of the fast PING signal. Similarly, the pulse generator 1128 produces each pulse of the slow PING signal. The delay between successive pulses of the fast PING signal is provided by the delay block 1114. Likewise, the delay between successive pulses of the slow PING signal is provided by the delay block 1127. Since the slow PING signal has a lower frequency than the fast PING signal, the delay provided by the delay block 1127 (e.g., 25 microseconds) can be greater than the delay provided by the delay block 1114 (e.g., 12.5 microseconds). The AND gates 1112 and 1125 determine whether the fast PING signal or the slow PING signal is to be produced at a given time. For the fast PING signal to be produced, the output of the AND gate 1112 on the connection 1113 must be high, and likewise for the slow PING signal to be produced, the output of the AND gate 1125 on the connection 1126 must be high. Since the fast PING signal and the slow PING signal cannot be transmitted simultaneously, no more than one of the connections 1113, 1126 will be high at a given time. In the case of the zero frequency PING signal, neither of the connections 1113, 1126 will be high.

[0057] Whether the output of the AND gate 1112 is high depends on whether both of the inputs to the AND gate 1112 are satisfied. The second input to the AND gate 1112 is an inverting input, so for this to be satisfied, the connection 1119 should be low. To satisfy the first input to the AND gate 1112, the connection 1111 should be high. To have the connection 1111 be high, neither of the inputs to the NOR gate 1110 can be satisfied. In other words, the SEC_SW_DET signal must be low (i.e., the switch 222 must not be actively switched), the SEC_CTRL signal must be high (i.e., the PCC 104 must be in the regulation mode 808), and the ON / OFF-SEC signal must be low (i.e., the V CC must be within the target hysteresis band). If neither of the inputs to the NOR gate 1110 is satisfied, the connection 1111 will carry a high signal, and the AND gate 1112 will provide a high signal on the connection 1113 when the connection 1119 is low between the pulses produced by the pulse generator 1116. The change from low to high on the connection 1113 will cause the delay block 1114 to stop resetting and begin counting to 12.5 microseconds, after which the high signal on 1113 is provided to the connection 1115 and the clock input on the pulse generator 1116. The rising edge of the clock input provided to the pulse generator 1116 triggers the production of a 25 ns pulse. The pulse is delayed by the delay block 1118 for a short amount of time (e.g., 50 ns), and then provided to the connection 1119, at which point the process repeats. In this way, the V CCThe encode circuit 606 produces the fast PING signal with respect to the state of the target hysteresis band (e.g., ON / OFF-SEC and SEC_CTRL) and the switching state of the switch 222 (e.g., SEC_SW_DET). The delay block 1118 ensures that the pulse generator 1116 is not reset too quickly. In the absence of the delay block 1118, as soon as the fast PING signal goes high, the fast PING signal would reset the connection 1113 to low, and the connection 1115 would also go low. In other words, the delay block 1118 supports the setup and hold time requirements of the clock logic of the pulse generator 1116.

[0058] The slow PING signal is produced by the components 1125, 1127, 1128, and 1130 the same way as the fast PING signal, except for the increased delay provided by the delay block 1127 with respect to the delay provided by the delay block 1114. The inputs to the NAND gate 1123 are also different than the inputs to the NAND gate 1110. The NAND gate 1123 receives SEC_CTRL, COMM_ENABLE, and ON / OFF-SEC. When SEC_CTRL is low, it means that the PCC 104 is not in the regulation mode 808, and further when COMM_ENABLE is high, it means that the V CC exceeds the voltage threshold V UVLO , and further when ON / OFF-SEC is low, it means that the V CC Within the boundaries of the target hysteresis band, the NAND gate 1123 provides a high signal on 1124. Since the rest of the production of the slow PING signal is virtually the same as the production of the fast PING signal, the specific operation of the components 1125, 1127, 1128, and 1130 is not provided here.

[0059] The OR gate 1120 combines the fast PING signal and the slow PING signal to produce a single PING signal on the connection 1121. Since the fast PING signal and the slow PING signal do not occur at the same time, the PING signal on the connection 1121 contains pulses of the same width but different frequencies, depending on whether a fast PING pulse or a slow PING pulse is being produced.

[0060] The timing diagram 800 depicts the PING signal 818 produced by the encode circuit 606. When the PCC 104 should be in the regulation mode 808 (e.g., because the V CCWhen the PCC 104 has reached the hysteresis band), the controller 244 (e.g., the encoding circuit 606) generates a fast PING signal, as indicated by reference numeral 876. As shown in the timing diagram 800 and as described above with reference to the encoding circuit 606, the fast PING pulse 876 is generated only when the ON / OFF-SEC is low (i.e., between the ON / OFF-SEC pulses 860, 862, 864, and 866), when the PCC 104 is in the regulation mode 808 (i.e., SEC_CTRL is high), and when the switching action of the switch 222 is to be turned off (i.e., is not in agreement with the ON / OFF-PRIM pulses 890, 892, and 894). The fast PING pulse 876 is generated when the PCC 104 should be operated in the no upper duty cycle mode 806 (e.g., because V CC When the voltage is greater than the voltage threshold 828 but has not yet reached the hysteresis band), the controller 244 generates a slow PING signal pulse 874. A PING signal frequency of zero corresponds to the upper duty cycle mode 804, as shown.

[0061] In addition to generating the PING signal, the encoding circuit 606 also generates a pulse (referred to herein as an "on pulse") that signals to the controller 220 when the switching action of the switch 222 should be turned on, and a pulse (referred to herein as an "off pulse") that signals to the controller 220 when the switching action of the switch 222 should be turned off. In the embodiment shown in FIG. 8, the components 1132, 1137, 1138, 1141, 1142, and 1134 generate the on pulse, and the components 1144 and 1145 generate the off pulse. Figure 2 In the embodiment shown in FIG. 8, the components 1132, 1137, 1138, 1141, 1142, and 1134 generate the on pulse, and the components 1144 and 1145 generate the off pulse. The on pulse is a pair of pulses, the first pulse having a shorter pulse width and the second pulse having a longer pulse width. The first pulse and the second pulse are separated by a defined delay. When the controller 220 receives a pair of pulses having this particular pattern, the controller 220 recognizes the pulses as an instruction to begin the switching action of the switch 222 (e.g., because V CC is falling too low with respect to the lower boundary of the target hysteresis band). The off pulse is a single pulse of a predetermined pulse width, and when received after a pair of on pulses, the controller 220 recognizes the off pulse as an instruction to cease the switching action of the switch 222 (e.g., because V CC is rising too high with respect to the upper boundary of the target hysteresis band). When a rising edge of the ON / OFF-SEC is received, the components of the encoding circuit 606 that generate the on pulses are triggered to generate a pair of on pulses, and when a falling edge of the ON / OFF-SEC is received, the components of the encoding circuit 606 that generate the off pulse are triggered to generate the off pulse.

[0062] In particular, the rising edge of the ON / OFF-SEC pulse triggers the clock input of the pulse generator 1132 (e.g., a 25 ns pulse generator) causing the pulse generator 1132 to provide a pulse on connection 1133 with a relatively short pulse width (e.g., 25 ns). The pulse is also provided to the inverted clock input of the pulse generator 1137 (e.g., a 30 ns pulse generator). The clock input of the pulse generator 1137 receives the pulse and, when the falling edge of the pulse is received, the pulse generator 1137 generates a pulse on connection 1139. The pulse on connection 1139 is inverted by inverter 1138 resulting in an inverted pulse on connection 1140. This inverted pulse is received by AND gate 1141 and, since the inverted pulse is low, the output of the AND gate on connection 1143 will remain low for the duration of the inverted pulse. In this manner, the inverted pulse creates a delay or gap between the shorter pulse and the longer pulse in the pair of turn-on pulses described above and is shown in timing diagram 800 by reference number 884. When the inverted pulse on connection 1140 passes and both inputs to AND gate 1141 go high, connection 1143 provides a rising edge to the clock input of pulse generator 1142 (e.g., a 1 microsecond pulse generator) which triggers the pulse generator 1142 to generate a pulse with a relatively wide pulse width with respect to the pulse generated by pulse generator 1132. Pulse generator 1142 is reset when SEC_SW_DET on connection 1105 goes high.

[0063] When the ON / OFF-SEC has a falling edge, the clock input of pulse generator 1144 (e.g., a 1 microsecond pulse generator) is triggered causing the pulse generator 1144 to generate an off pulse on connection 1146 as described above. The pulse generator 1144 is reset by the inversion of SEC_SW_DET generated by inverter 1145.

[0064] The OR gate 1135 combines the turn-on and off pulses on connections 1149 and 1146 and provides the resulting signal on connection 1136, and the OR gate 1122 combines the PING signal received on connections 1121 and 1136 with the turn-on and off pulses to generate the FB_SIGNAL_TX on connection 1147 (which can be coupled to connection 260 Figure 2 )) as described above.

[0065] The controller 244 provides the FB_SIGNAL_TX on connection 260 Figure 11) provides FB_SIGNAL_TX on a 100-bit CMOS chip. Modulator 246 receives FB_SIGNAL_TX and modulates the alternating current flowing through winding 268 based on FB_SIGNAL_TX. The alternating current in winding 268 generates an electromagnetic field, which induces a current in winding 232. The current in winding 232 contains the information provided by FB_SIGNAL_TX. Demodulator 225 demodulates the current flowing through winding 232 to generate FB_SIGNAL_RX, which is identical or substantially identical to FB_SIGNAL_TX. Demodulator 225 provides FB_SIGNAL_RX to controller 220 via connector 226.

[0066] Figure 6 The circuitry shown in FIG may not necessarily represent all of the circuitry included in controller 244. Other operations attributed herein to controller 244 may be performed by other circuitry and logic, such as Figure 6 6 and memory 602 shown in FIG. 6. Some or all of the actions herein attributed to the encoding circuit 606 may be performed by the processor 600 by executing the executable instructions 604 ( Figure 4 ) to execute.

[0067] like Figure 12 , controller 220 may include decoding circuitry 406 to decode FB_SIGNAL_RX. In some examples, processor 400, by executing executable instructions 404, may perform some or all of the actions attributed herein to controller 220 and / or decoding circuitry 406.

[0068] The decoding circuit 406 is configured to separate the FB_SIGNAL_RX into its constituent components, such as the PING signal and the on and off pulses. Figure 12 and 13 An example portion of decoding circuitry 406 is included. Figure 13 The circuit system shown in is configured to isolate the on-pulses and the off-pulses and generate an ON / OFF-PRIM based on those on-pulses and off-pulses. Figure 12 The circuitry shown in is configured to isolate the PING signal and use the PING signal to determine which operating mode of the PCC 104 should be enabled and how the switch 222 is to be operated.

[0069] exist Figure 12In this embodiment, the decode circuit 406 includes a 2-bit counter 1200 having a clock input coupled to the connection 226 by way of a delay block 1201, an ENABLE input coupled to the connection 1214, and an output coupled to the connection 1209. The circuit 406 also includes a pulse generator 1202 (e.g., a 150 ns pulse generator) having a clock input coupled to the connection 226 and an output coupled to the connection 1214. The circuit 406 also includes a filter / delay block 1204 (e.g., a 50 ns filter / delay block, such as a resistance-capacitance (RC) delay) having an input coupled to the connection 226 and an output coupled to the connection 1216. In addition, the decode circuit 406 includes an AND gate 1206 having a first input coupled to the connection 1209 and a second input coupled to the connection 1216. The decode circuit 406 also includes an AND gate 1208 having an inverted input coupled to the connection 1209 and another input coupled to the connection 1216. The output of the AND gate 1206 is coupled to the connection 1218, and the output of the AND gate 1208 is coupled to the connection 1220. The decode circuit 406 includes an SR flip-flop 1210 having an S input coupled to the connection 1218, an R input coupled to the connection 1220, and a Q output coupled to the connection 1222. When the FB SIGNAL RX goes from low to high on the connection 226 (a rising edge), the clock input of the pulse generator 1202 is triggered. As a result, the pulse generator 1202 provides a pulse of defined width (e.g., 150 ns) on the connection 1214 that enables the 2-bit counter 1200 for 150 ns. During this time that the 2-bit counter 1200 is enabled, the 2-bit counter 1200 monitors its clock input for two rising edges. The first of the two rising edges is the rising edge that triggered the pulse generator 1202, and after the 2-bit counter 1200 has been enabled, the delay block 1201 enables the 2-bit counter 1200 to count this rising edge. The receipt of two rising edges (e.g., from two individual pulses) within 150 ns indicates that the received pulses are likely a pair of turn-on pulses as described above, and the possibility that the pulses are PING signal pulses (which are significantly narrower than the turn-on and turn-off pulses) is eliminated when the output of the filter / delay block 1204 (which functions to filter out pulses of threshold duration less than, e.g., 50 ns) is high on the connection 1216. As a result, both inputs to the AND gate 1206 are high, and thus, the output of the AND gate 1206 on the connection 1218 is high, while the output of the AND gate 1208 on the connection 1220 is low. Since the SR flip-flop 1210 receives a high S input and a low R input, the SR flip-flop 1210 latches high and provides a high Q output on the connection 1222.Conversely, when a single OFF pulse is received, the output of the 2-bit counter 1200 will be low, but the output of the filter / delay block 1204 on connection 1216 will be high, thereby causing connection 1218 to go low and connection 1220 to go high. Thus, the reset SR flip-flop 1210 is caused to provide a low signal on the Q output on connection 1222. In this manner, Figure 13 The circuitry in FIG. 12 produces ON / OFF-PRIM on connection 1222, which goes high when a pair of ON pulses is received and goes low when an OFF pulse is received. The timing diagram 800 shows this behavior. The ON / OFF-PRIM signal 822 includes pulses 890, 892, and 894. The pulse 890 goes high upon completion of receiving a pair of ON pulses 884 in FB_SIGNAL_RX. Conversely, the pulse 890 goes low upon completion of receiving an OFF pulse 886 in FB_SIGNAL_RX. The pulses 892 and 894 exhibit the same behavior as the pulse 890.

[0070] As mentioned, Figure 8Another example portion of the decode circuit 406 is depicted, which is configured to determine the frequency of the PING signal contained in the FB_SIGNAL_RX. The example circuitry of the decode circuit 406 includes a connection 226 on which the FB_SIGNAL_RX is received, a 2-bit counter 1300 having a clock input coupled to the connection 226 by way of a delay block 1301 and an ENABLE input coupled to a connection 1322, and an output coupled to a connection 1330. The connection 1330 is coupled to an input of a logical AND gate 1318. The circuitry includes a 13 microsecond pulse generator 1308 having a clock input coupled to the connection 226 and an output coupled to the connection 1322. The circuitry includes a 2-bit counter 1302 having a clock input coupled to the connection 226 by way of a delay block 1303 and an ENABLE input coupled to a connection 1324, and an output coupled to a connection 1348. The circuitry also includes a 10 microsecond pulse generator 1310 having a clock input coupled to the connection 226 and an output coupled to the connection 1324. An inverter 1332 has an input coupled to the connection 1348 and an output coupled to a connection 1333, which is coupled to an input of the logical AND gate 1318. The circuitry includes a 20 nanosecond filter / delay block 1312 (e.g., a pulse width filter) having an input coupled to the connection 226 and an output coupled to a connection 1334, which is coupled to an input of the AND gate 1318. The circuitry also includes a 2-bit counter 1304 having a clock input coupled to the connection 226 by way of a delay block 1305 and an ENABLE input coupled to a connection 1326, and an output coupled to a connection 1336. The connections 1334 and 1336 are coupled to inputs of a logical AND gate 1320. A 30 microsecond pulse generator 1314 has a clock input coupled to the connection 226 and an output coupled to the connection 1326. The circuitry further includes a 2-bit counter 1306 having a clock input coupled to the connection 226 by way of a delay block 1307 and an ENABLE input coupled to a connection 1328, and an output coupled to a connection 1340. The circuitry also includes a 20 microsecond pulse generator 1316 having a clock input coupled to the connection 226 and an output coupled to the connection 1328. An inverter 1338 includes an input coupled to the connection 1340 and an output coupled to a connection 1342, which is coupled to an input of the AND gate 1320. The AND gate 1318 has an output coupled to a connection 1344, and the AND gate 1320 has an output coupled to a connection 1346.

[0071] The connection 226 provides the FB_SIGNAL_RX. Referring to Figure 13 the circuitry of the Figure 4 , the rising edge of each pulse in the FB_SIGNAL_RX triggers the pulse generator 1308 which generates a 13 microsecond pulse on the connection 1322. Thus, from the rising edge of each pulse in the FB_SIGNAL_RX, the 2-bit counter 1300 is enabled for 13 microseconds. During the time that the 2-bit counter 1300 is enabled, if two rising edges are received at the clock input of the 2-bit counter 1300, then the 2-bit counter 1300 provides a high signal on the connection 1330. The delay block 1301 enables the 2-bit counter 1300 to count the rising edges that trigger the pulse generator 1308. Thus, the pulse generator 1308 and the 2-bit counter 1300 operate together to determine if two consecutive pulses occur within 13 microseconds of each other. If such pulses are received in the FB_SIGNAL_RX, then those pulses can be a fast PING pulse. The rising edge of each pulse in the FB_SIGNAL_RX also triggers the pulse generator 1310 which generates a 10 microsecond pulse on the connection 1324. Thus, the 2-bit counter 1302 is enabled for 10 microseconds. If, during that 10 microseconds, the 2-bit counter 1302 receives two rising edges at the clock input, then the 2-bit counter 1302 generates a high signal on the connection 1348 which is inverted by the inverter 1332 to generate a low signal on the connection 1333 and vice versa. Thus, the pulse generator 1310, the 2-bit counter 1302, and the inverter 1332 operate together to determine if two consecutive pulses are separated by at least 10 microseconds and, if so, the inverter 1332 provides a high signal on the connection 1333. The delay block 1303 enables the 2-bit counter 1302 to count the rising edges that trigger the pulse generator 1310. If such pulses are received in the FB_SIGNAL_RX, then those pulses can be a fast PING pulse. The 20 nanosecond filter / delay block 1312 receives the FB_SIGNAL_RX and provides on the connection 1334 only those signals that have a pulse width of at least 20 nanoseconds, which means that the filter / delay block 1312 filters out possible noise in the FB_SIGNAL_RX. If the connections 1330, 1333, and 1334 each carry a high signal, then the AND gate 1318 provides a high signal on the connection 1344 which indicates that there is a pair of pulses in the FB_SIGNAL_RX, each pulse being at least 20 nanoseconds wide and separated by at least 10 microseconds but no more than 13 microseconds. Such a pair of pulses would be accurately characterized as a fast PING pulse, and thus the high signal on the connection 1344 to the controller 220 (e.g., to the processor 400 Figure 4) indicates that controller 244 is instructing controller 220 to enable the operating mode of PCC 104 corresponding to a fast PING signal.

[0072] The rising edge of a pulse received in FB_SIGNAL_RX by 30 microsecond pulse generator 1314 produces a high signal on connection 1326, which enables 2-bit counter 1304 for 30 microseconds. If at least two rising edges are received at the clock input of 2-bit counter 1304 during that 30 microseconds, 2-bit counter 1304 provides a high signal on connection 1336. Delay block 1305 enables 2-bit counter 1304 to count the rising edges of the trigger pulse generator 1314. Similarly, the rising edge of a pulse received in FB_SIGNAL_RX by 20 microsecond pulse generator 1316 produces a high signal on connection 1328, which enables 2-bit counter 1306 for 20 microseconds. If at least two rising edges are received at the clock input of 2-bit counter 1306 during that 20 microseconds, 2-bit counter 1306 provides a high signal on connection 1340, which is inverted by inverter 1338 to produce a high signal on connection 1342, and vice versa. Delay block 1307 enables 2-bit counter 1306 to count the rising edges of the trigger pulse generator 1316. Thus, pulse generator 1316, 2-bit counter 1306, and inverter 1338 operate together to identify pairs of pulses that are not received within 20 microseconds of each other, while pulse generator 1314 and 2-bit counter 1304 operate together to identify pairs of pulses that are received within 30 microseconds of each other. When connections 1334, 1336, and 1342 all provide a high signal to AND gate 1320, AND gate 1320 provides a high signal to connection 1346. In other words, components 1304, 1314, 1316, 1306, 1338, 1312, and 1320 operate together to recognize a slow PING pulse having a width of at least 20 nanoseconds, where successive pulses are spaced between 20 microseconds and 30 microseconds. A high signal on connection 1346 indicates to controller 220 (e.g., to processor 400 Figure 13 ) that controller 244 is instructing controller 220 to enable the operating mode of PCC 104 corresponding to a slow PING signal. A low signal on both connections 1344 and 1346 indicates a no PING signal on FB_SIGNAL_RX, and controller 220 is configured to enable the operating mode of PCC 104 corresponding to a no PING signal.

[0073] Figure 13 The particular parameters of the various components shown in FIG. 13B are selected based on the properties of the pulses contained in FB_SIGNAL_RX. The parameters can be changed Figure 2The parameters of the components shown in FIG. 8 are adapted to different frequencies and pulse widths of the pulses in FB_SIGNAL_RX.

[0074] Referring again to Figure 13 , 7 and 8, as described above, the method 700 includes the controller 220 detecting the PING signal received in FB_SIGNAL_RX during the monitoring mode 802 immediately after the PCC 104 is enabled by the ENABLE signal 812, e.g., by the rising edge 856 of the ENABLE signal 812. If Figure 13 the portion of the decode circuit 406 shown in FIG. 8 indicates that FB_SIGNAL_RX does not contain a PING signal, then the controller 220 takes the branch 706 of the method 700 to enable the upper duty cycle mode 804. During the upper duty cycle mode 804, the controller 220 gradually increases the duty cycle for switching the switch 222 (712). More particularly, when the PING signal 818 is a zero frequency PING signal as in the upper duty cycle mode 804, the controller 220 gradually increases the duty cycle of the ON / OFF-PRIM signal 822, as indicated by the change in duty cycle reflected in the signal 824. As the duty cycle increases, the V CC 810 begins to rise and continues to rise. However, when the PCC 104 is operating in the upper duty cycle mode 804, the duty cycle is limited (e.g., the controller 220 can be preprogrammed not to exceed a particular duty cycle when in the upper duty cycle mode 804).

[0075] If Figure 8 the decode circuit 406 shown in FIG. 8 indicates that FB_SIGNAL_RX contains a slow PING signal Figure 13 , then the controller 220 takes the branch 708 of the method 700 to enter the no upper duty cycle mode 806. More particularly, when the PING signal 818 is a slow PING signal as indicated by the label 874 in FIG. 8, the controller 220 gradually increases the duty cycle for switching the switch 222, but there is no upper limit on how high the duty cycle can rise (716). Notably, the controller 220 can enter the no upper duty cycle mode 806 directly upon detecting a slow PING signal in FB_SIGNAL_RX without having to first enter the upper duty cycle mode 804 or any other operating mode. During the no upper duty cycle mode 806, the duty cycle of the ON / OFF-PRIM continues to rise as indicated by the signal 822, and during the mode 806, the V CC continues to rise as indicated by the V CC signal 810.

[0076] If Figure 14The decode circuit 406 shown in the middle indicates that the FB_SIGNAL_RX contains a fast PING signal, then the controller 220 takes branch 710 and enables a regulation mode with hysteresis control (720), which is depicted in timing diagram 800 as regulation mode 808. During regulation mode 808, the controller 220 operates the switching action of the switch 222 (e.g., by controlling ON / OFF-PRIM) to turn V CC V CC When the signal 810 reaches the lower boundary 832 of the hysteresis band, the ON / OFF-SEC rises (e.g., pulses 860, 862, 864, 866), which causes the controller 244 to provide a pair of on pulses (e.g., label 884) to the controller 220 along with the fast PING signal (e.g., labels 882, 888), as indicated by the FB_SIGNAL_TX and FB_SIGNAL_RX 820. Upon receiving and decoding the FB_SIGNAL_RX, the controller 220 provides rising edges of pulses (e.g., pulses 890, 892, 894) in the ON / OFF-PRIM signal 822, causing the switching action of the switch 222 to begin. When V CC When the signal 810 reaches the upper boundary 830 of the hysteresis band, the ON / OFF-SEC falls, which causes the controller 244 to provide an off pulse (e.g., label 886) to the controller 220 along with the fast PING signal, as indicated by the FB_SIGNAL_TX and FB_SIGNAL_RX 820. Upon receiving and decoding the FB_SIGNAL_RX, the controller 220 provides falling edges of pulses in the ON / OFF-PRIM signal 822, causing the switching action of the switch 222 to stop. Notably, the controller 220 is configured to enter the regulation mode 808 directly upon detecting the fast PING signal, without having to enter the modes 804 and / or 806 before entering the mode 808. Moreover, since there is a delay between the time the primary side switch is controlled to begin or stop switching and the time the signal 810 crosses the hysteresis band 830, 832, V CC V CC The band 830, 832 will be extended slightly beyond, as shown.

[0077] While controller 220 can enable any mode of operation of PCC 104 without first having to enable another mode of operation of PCC 104, in an example, controller 220 can progress from one mode of operation to another. For example, while operating in the upper-bound duty cycle mode 804 (712), controller 220 can monitor FB_SIGNAL_RX for a slow PING signal (714). In response to receiving such a slow PING signal, controller 220 can enable the no upper-bound duty cycle mode 806 (716). Similarly, while operating in the no upper-bound duty cycle mode 806 (716), controller 220 can monitor FB_SIGNAL_RX for a fast PING signal (718), which can be identified as described in detail above, or alternatively, by a pulse (referred to herein as a "flag pulse") indicating a predetermined length (generated by, for example, controller 244) for which controller 220 is to enable the regulation mode 808. In response to receiving the fast PING signal, controller 220 can enable the regulation mode 808 (720).

[0078] Figure 14 and 15 are graphs illustrating operation of a low-inrush-current power converter circuit in accordance with various examples. In particular, Figure 14 A pair of graphs 1400 is shown, where the x-axis is time and the y-axis is magnitude (the upper graph is voltage in volts; the lower graph is current in milliamps). As graph 1402 shows, V CC ramps up smoothly from the time that PCC 104 is enabled until the time that the regulation mode 808 is reached, and after the regulation mode 808 is reached. Similarly, as graph 1404 shows, the inrush current to PCC 104 ramps up smoothly, without large spikes that cause the various technical challenges described above. Figure 2 and 15 Assume that capacitor 210 Figure 15 is fully or nearly fully discharged prior to PCC 104 being enabled.

[0079] Figure 15 A pair of graphs 1500 is shown, depicting curves 1502, 1504, 1506, and 1508. Curve 1502 is the ENABLE signal, curve 1504 is the SEC_CTRL signal, curve 1506 is V CC , and curve 1508 is FB_SIGNAL_RX. Figure 14 Unlike Figure 2 , PCC 104 is operating, then disabled, and then enabled again, where the second enablement is prior to capacitor 210 ​) has been discharged. Thus, as shown, the ENABLE signal 1502 is high, the SEC CTRL signal 1504 is low, and no PING signal is received on the FB SIGNAL RX 1508, meaning that the PCC 104 is in the upper bound duty cycle mode 804. When a slow PING signal is received on the FB SIGNAL RX 1508, the V CC signal 1506 continues to rise smoothly, causing the controller 220 to enable the no upper bound duty cycle mode 806 of the PCC 104. The V CC signal 1506 plateaus after reaching the regulation mode 808, during which the FB SIGNAL RX 1508 provides a fast PING signal. The SEC CTRL signal 1504 also goes high to indicate that the regulation mode 808 has begun. At this point, the ENABLE signal 1502 goes low, meaning that power to the PCC 104 is disconnected, and the V CC signal 1506 begins to fall. At time 1512, the ENABLE signal 1502 goes high again, meaning that power is again supplied to the PCC 104, but at time 1512, the V CC is not zero or near zero, and is still near the hysteresis steady state. However, upon the PCC 104 starting at time 1512, the controller 220 immediately determines that a fast PING signal is received on the FB SIGNAL RX signal 1508, and thus, instead of stepping through a series of unnecessary modes, the controller 220 goes directly to enabling the regulation mode 808, meaning that the controller 220 provides hysteresis control to maintain the V CC within the target hysteresis band. As shown, the V CC signal 1506 shows that the V CC modestly rises to return to the hysteresis steady state, and does not suffer from overshoot as is the case with other solutions described above.

[0080] In this specification, the term "coupled" can encompass a connection, communication, or signal path that enables a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, device A is coupled to device B through intermediate component C, provided that intermediate component C does not alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.

[0081] An apparatus described herein as being configured to perform a task or function can be configured (e.g., programmed and / or hardwired) at a manufacturer to perform the function upon which it is manufactured, and / or can be configured (or reconfigured) by a user after manufacturing to perform the function and / or other additional or alternative functions. The configuration can be through firmware and / or software programming of the apparatus, through the construction and / or layout of hardware components and interconnects of the apparatus, or a combination thereof.

[0082] Circuits or apparatuses described herein as including certain components can actually be coupled to those components to form the described circuitry or apparatus. For example, structures described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) can actually include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and can be coupled to at least some of the passive elements and / or sources to form the described structures at the time of manufacture or after manufacture, e.g., by an end user and / or a third party.

[0083] The use of the term“ground” in the foregoing description includes chassis ground, line ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of grounding appropriate for or suitable to the teachings of the present specification. In the present specification, unless otherwise stated, “about,”“approximately,” or“substantially” before a parameter means within + / - 10% of the stated parameter. Modifications in the described examples are possible and other examples are possible within the scope of the claims.

[0084] As used herein, the terms“terminal,”“node,”“interconnect,”“pin,” and“lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnect or end thereof between device elements, circuit elements, integrated circuits, devices, or semiconductor components.

Claims

1. A circuit comprising: a transformer including a first winding and a second winding forming an isolation barrier; a first controller coupled to the second winding, a rectifier, and an output of the circuit, the first controller configured to generate a signal indicative of a voltage on the output; and a second controller coupled to the first winding and a switch and separated from the first controller by the isolation barrier, the second controller configured to operate the switch to have a variable duty cycle with an upper limit, to have a variable duty cycle without an upper limit, or to maintain the voltage within a hysteresis band in response to the signal.

2. The circuit of claim 1, wherein the second controller is configured to determine a mode of operating the switch based on a frequency of a first component of the signal after an enablement of the circuit.

3. The circuit of claim 2, wherein the second controller is configured to operate the switch in a first mode to have the variable duty cycle with the upper limit in response to the frequency being at a first level.

4. The circuit of claim 3, wherein the second controller is configured to operate the switch in a second mode to have the variable duty cycle without the upper limit in response to the frequency being at a second level greater than the first level.

5. The circuit of claim 4, wherein the first controller is configured to set the frequency at the second level in response to the voltage on the output exceeding a threshold.

6. The circuit of claim 4, wherein the second controller is configured to operate the switch in a third mode to maintain the voltage within the hysteresis band in response to the frequency being at a third level greater than the first level and the second level.

7. The circuit of claim 6, wherein the first controller is configured to set the frequency at the third level in response to the voltage on the output reaching a target level.

8. The circuit of claim 6, wherein the second controller is configured to turn on the switch when operating the switch in the third mode in response to a second component of the signal including a first pulse and a second pulse longer than the first pulse occurring within a target time window, and to turn off the switch in response to the second component of the signal including a third pulse longer than the first pulse occurring after the first pulse and the second pulse.

9. The circuit of claim 6, wherein the second controller is configured to skip the first mode, the second mode, or a combination thereof in response to the determination.

10. A circuit comprising: a switch coupled to a rectifier and a transformer, the rectifier coupled to an output of the circuit; a voltage comparison circuit coupled to the output and configured to provide a first signal indicative of a voltage on the output relative to a hysteresis band; a first controller coupled to the voltage comparison circuit and configured to provide a second signal combining the first signal with a third signal indicative of a state of the circuit; and a second controller configured to: determining a frequency of a first component of the second signal, and operating the switch in one of a plurality of operating modes based on the frequency of the first component; and when in a first mode of the plurality of operating modes, operating the switch based on a frequency and a pulse width of a second component of the second signal.

11. The circuit of claim 10, wherein the plurality of operating modes includes the first operating mode, a second operating mode, and a third operating mode, and wherein the second controller is configured to respond to the determining by: operating the switch in the first operating mode without first operating the switch in the second operating mode or the third operating mode, operating the switch in the second operating mode without first operating the switch in the first operating mode or the third operating mode, and operating the switch in the third operating mode without first operating the switch in the first operating mode and the second operating mode.

12. The circuit of claim 10, wherein, To indicate the state of the circuit, the third signal indicates that the voltage on the output is within the hysteresis band.

13. The circuit of claim 10, wherein the first controller includes circuitry configured to generate the first signal, the circuitry including: a first pulse generator having a first pulse generator input and a first pulse generator output, the first pulse generator input configured to be triggered by a rising pulse edge; a second pulse generator having a second pulse generator input and a second pulse generator output, the second pulse generator input coupled to the first pulse generator output and configured to be triggered by a falling pulse edge, the second pulse generator output coupled to an input of an inverter; a third pulse generator having a third pulse generator input and a third pulse generator output, the third pulse generator input configured to be triggered by a rising pulse edge; an AND logic gate having an AND logic gate output and first and second AND logic gate inputs, the first AND logic gate input coupled to an output of the inverter, the second AND logic gate input coupled to the first pulse generator input, and the AND logic gate output coupled to the third pulse generator input; a first OR logic gate having a first OR logic gate output and first and second OR logic gate inputs, the first OR logic gate input coupled to the first pulse generator output, the second OR logic gate input coupled to the third pulse generator output; a fourth pulse generator having a fourth pulse generator input and a fourth pulse generator output, the fourth pulse generator input configured to be triggered by a falling pulse edge and coupled to the first pulse generator input; and a second OR logic gate having a second OR logic gate output and third and fourth OR logic gate inputs, the third OR logic gate input coupled to the first OR logic gate output, the fourth OR logic gate input coupled to the fourth pulse generator output. ​ 14. The circuit of claim 10, wherein the first controller includes circuitry to generate the third signal, the circuitry comprising: a first AND logic gate having a first AND logic gate output and a first AND logic gate input and a second AND logic gate input, the second AND logic gate input being an inverting input; a first delay circuit having a first delay circuit output, a first delay circuit input, and a first delay circuit reset input, the first delay circuit reset input being an inverting input and coupled to the first delay circuit input and the first AND logic gate output; and a first pulse generator having a first pulse generator output and a first pulse generator input, the first pulse generator input coupled to the first delay circuit output and triggered by a rising pulse edge, the first pulse generator output coupled to the second AND logic gate input.

15. The circuit of claim 10, wherein the second controller comprises: a two-bit counter having a counter output and a first counter input and a second counter input, the first counter input triggered by a rising pulse edge, the second counter input being an enable input; a pulse generator having a pulse generator output and a pulse generator input, the pulse generator input triggered by a rising pulse edge and coupled to the first counter input, the pulse generator output coupled to the enable input; a pulse width filter having a pulse width filter output and a pulse width filter input, the pulse width filter input coupled to the pulse generator input; a first AND gate having a first AND gate output and a first AND gate input and a second AND gate input, the first AND gate input coupled to the counter output, the second AND gate input coupled to the pulse width filter output; a second AND gate having a second AND gate output and a third AND gate input and a fourth AND gate input, the third AND gate input being an inverting input coupled to the counter output, the fourth AND gate input coupled to the pulse width filter output; and a latch having a latch output and a first latch input and a second latch input, the first latch input coupled to the first AND gate output and the second latch input coupled to the second AND gate output.

16. A computer-readable medium storing instructions which, when executed by a controller, cause the controller to: determine a frequency of a first component of a signal in a power converter circuit, the first component being indicative of a state of a portion of the power converter circuit; in response to the frequency of the first component being at a first level, operate a switch of the power converter circuit with an increased duty cycle that does not exceed an upper limit; in response to the frequency of the first component being at a second level, operate the switch with an increased duty cycle that is not subject to an upper limit; and in response to the frequency of the first component being at a third level, and based on a frequency and a pulse width of a second component of the signal, operate the switch to maintain a voltage output of the power converter circuit within a hysteresis band.

17. The computer-readable medium of claim 16, wherein the instructions cause the controller to turn on the switch in response to receiving a first pulse and a second pulse wider than the first pulse in the second component of the signal within a target time window.

18. The computer-readable medium of claim 17, wherein the instructions cause the controller to turn off the switch in response to receiving a third pulse wider than the first pulse in the second component of the signal after the first and second pulses.

19. The computer-readable medium of claim 16, wherein the frequency of the first component at the second level indicates an absence of a short in the power converter circuit.

20. The computer-readable medium of claim 16, wherein the instructions cause the controller to generate the first component of the signal to have the frequency at the second level in response to the voltage output exceeding a threshold.

Images