Low-power-consumption feed-forward equalizer circuit

Abstract

The invention provides a low-power-consumption feed-forward equalizer circuit which comprises a grouping processing module which divides tap values of tap coefficients of the feed-forward equalizer circuit into a plurality of groups, each group comprises a plurality of tap values, and a tap combination value needing to be processed by each lookup table module is calculated; the lookup table module is used for storing the tap combination value which is calculated in advance and performing lookup operation according to the bit combination of the input data to generate an intermediate result; the clock gating trigger module is used for enabling a signal tapdata to be equal to 1 when a tap value is updated, completing updating of the tap value output by a register DFF, and closing an input clock of the DFF when the tap value is kept unchanged and the tapdata is equal to 0; the shift accumulation module performs weight shift operation on the intermediate results output by the lookup table module and then accumulates the intermediate results to generate a plurality of groups of tap value processing results; and the result output module outputs a final equalization signal of the feed-forward equalizer circuit. The FFE circuit is realized by converting the multiplier into the LUT table and the adder, and the power consumption of the FFE circuit is greatly reduced while the signal processing performance of the FFE circuit is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of signal processing in high-speed communication systems, and particularly relates to a low-power feed-forward equalizer circuit, which can be widely applied to 5G communication, optical fiber communication and other high-speed communication scenarios with strict requirements on signal quality and power consumption. BACKGROUND

[0002] With the rapid development of communication technology, the bandwidth of communication data is continuously increasing, and the requirements for signal processing are also becoming higher and higher. In high-speed communication systems, inter-symbol interference (ISI) in the channel can seriously affect the transmission quality of signals, leading to an increase in the bit error rate.

[0003] Feed-forward equalizer (FFE) is a widely used signal processing technology in high-speed communication systems, mainly used to overcome inter-symbol interference (ISI) in the channel. The core idea is to use a FIR (Finite Impulse Response) filter to preprocess the received signal to offset channel distortion. With the continuous increase in the bandwidth of communication data, FFE needs to support wider bandwidth and lower power consumption.

[0004] FFE is essentially a FIR digital filter, and existing technical solutions mainly use D-flip-flops, multipliers and adders to implement it, as shown in Figure 1 . The FFE output signal can be represented as:

[0005] As can be seen from the above formula, the area and power consumption of the FFE circuit mainly depend on the number of multipliers and the bit width of the multiplied data.

[0006] The existing technology has obvious power consumption problems, especially in the application scenario of large bandwidth high-speed communication. Because FFE has many tap coefficients, a large number of multipliers and adders are needed to implement it. In actual application scenarios, the tap coefficient value of FFE is a slowly varying value, which can be regarded as a constant value after normal operation, except that it will change in the adaptive stage. For a large number of multipliers tap(k) x (n - k) , tap(k) regarded as a constant, x(n - k) is the input data is a variable, so the gate circuit of the multiplier will produce a lot of dynamic power consumption. At the same time, the adder as a calculation unit will also produce a certain amount of dynamic power consumption, and for the multiplier and adder with the same data bit width operation, the number of multiplier gate circuits is usually several times to dozens of times the number of adders, so the power consumption of the entire FFE circuit is mainly determined by the number of multipliers. SUMMARY

[0007] In view of various problems existing in the prior art, the low-power feedforward equalizer circuit is provided to solve the problem of large power consumption in the prior art, and the multiplication is converted into a lookup table and an adder, so that the power consumption of the feedforward equalizer circuit is greatly reduced while the signal processing performance is ensured.

[0008] The application achieves the above-mentioned purpose through the following technical solutions: The low-power feedforward equalizer circuit comprises: The grouping processing module divides tap values of the feedforward equalizer circuit into multiple groups, each group containing multiple tap values, and calculates tap combination values to be processed by each lookup table module; wherein, input data corresponding to each group of tap values is subjected to equivalent transformation, a common factor is extracted to generate an address suitable for lookup table query; and each group of tap values after grouping is combined to form a combination value of the corresponding lookup table; The lookup table module is used for storing pre-calculated tap combination values and performing lookup operation according to input data bit combination to generate an intermediate result; wherein, the lookup table module is configured to convert multiplication calculation into lookup table calculation, and static tap combination values are stored to replace real-time multiplication operation, so as to reduce dynamic power consumption; The clock-gated flip-flop module is integrated in the lookup table module and is a flip-flop circuit with clock gating function, which is used for enabling signal tap_update_en=1 when the tap value is updated, and the tap value output by the register DFF is updated; when the tap value remains unchanged, tap_update_en=0, the input clock of the register DFF is closed to save power consumption, and the tap value output by the register DFF remains stable at this time; The shift and accumulation module accumulates the intermediate result output by the lookup table module after weight shift operation to generate processing results of multiple groups of tap values; The result output module adds multiple processing results through an adder tree structure to output a final equalization signal of the feedforward equalizer circuit, which is used for inter-symbol interference compensation in a high-speed communication system.

[0009] According to the low-power feedforward equalizer circuit, the tap_update_en enabling signal of the clock-gated flip-flop module is invalid during the normal working stage of the feedforward equalizer circuit, that is, tap_update_en=0, and is activated only during the adaptive stage or when the tap value needs to be updated, that is, tap_update_en=1, so that dynamic power consumption caused by flip-flop clock rollover is reduced.

[0010] According to the low-power feedforward equalizer circuit, the clock-gated flip-flop module comprises: Latch circuit, used to temporarily store tap_update_en enable signal, to ensure signal stability; AND gate circuit, receiving system clock clock and tap_update_en enable signal, only when tap_update_en enable signal = 1, clock signal is allowed to pass through; Register DFF, updating LUT content when clock is valid, otherwise keeping static to reduce power consumption; Wherein, when tap_update_en enable signal = 0, the current feedforward equalizer circuit is in normal working stage, AND gate circuit output closes clock, clock input of register DFF is 0, register DFF has no signal flip, dynamic power consumption is approximately zero.

[0011] According to the low power feedforward equalizer circuit provided by the application, the grouping processing module performs the following operations: Defining input signal x ( n ), wherein the value of input signal at relative time n-k is x(n-k), defining coefficient sequence tap ( k ), the number of coefficients is N , and the N coefficients are divided into M groups, each group containing L coefficient values, i.e. N = M × L ; Output signal y ( n ) is obtained by sum operation of input signal sequence and coefficient sequence, and the calculation formula is:

[0012] After grouping the coefficient sequence by grouping operation strategy, the output signal y ( n ) can be represented as the sum of each grouping operation result, i.e.

[0013] Wherein, i represents group number, j represents group number; Because the circuit structure of each group is the same after grouping, the output signal of one group is processed by equivalent transformation, which is represented by the following formula:

[0014] Wherein, the grouping processing module includes input interface, used to receive input signal sequence x(n - k)and tap value; a computing unit for performing group calculation and computing operations after equivalent transformation; an output interface for outputting result signals after group processing and calculation.

[0015] According to a low power feedforward equalizer circuit provided by the present invention, the input signal x ( n ) is converted to binary form and expressed as the following formula:

[0016] in, W is the data bit width, x ( n ) b represent x ( n ) b bits; With N coefficients, divided into M Group, each group L coefficients ( N = M × L ) as an example, combined with the input signal after binary conversion, the operation of one set of output signals is expressed as the following formula:

[0017] in, i is the group number ( i =0,1,..., M -1), j It is the sequence number within the group.

[0018] According to a low-power feedforward equalizer circuit provided by the present invention, the operation after extracting the common factor is combined with the binary bit operation in combination with the binary representation of the input signal: the input signal x ( n ) is broken down into its individual binary bits x ( n ) b With corresponding weight 2 b The product and sum of , in the expression after extracting the common factors, further integrate the operation into the weighted summation form of the results of different binary bit operations:

[0019] in, for The output value of , calculate all sum b Combine these calculations and The combined values ​​are stored in the lookup table module; wherein, .

[0020] According to the low-power feedforward equalizer circuit provided by the application, the lookup table module performs the following operations: The set of tap combination values is stored in a static random access memory or a register array in the index order of the input bit combination, forming a lookup table, which adopts a block storage structure and is divided into multiple sub-tables according to the grouping of high bits of the input data, and the content of each sub-table is the same; The input data bit stream is received, the bit height of the data stream bit is analyzed, and the bits of the same bit height in the group form an address of the lookup table; The multiple tap combination values matched with the bit combination are read from the corresponding sub-tables simultaneously through a multi-port parallel access mechanism; The tap combination values output by the lookup table according to different bit heights are subjected to a weighted shift operation to generate an intermediate result candidate set; The lookup table operation based on the address formed by the same bit combination is completed through a multiplexer MUX.

[0021] According to the low-power feedforward equalizer circuit provided by the application, when the input signal is B bits, the lookup table module is a parallel lookup table array composed of B full-parallel lookup tables, each lookup table is configured as a 4-input port, and pre-computed weight data matched with the bit width of the tap value is stored; 4 groups of B-bit-width data are input, and are split into ⌈B⌉ groups through a grouping strategy, each group of 4-bit parallel input is input to the corresponding lookup table, and the synchronous output of B weight values in a single cycle is realized.

[0022] According to the low-power feedforward equalizer circuit provided by the application, the shift and accumulation module includes a configurable shift register array, each register unit is one-to-one corresponding to the output end of the lookup table, and a dynamic right shift operation is performed on the weight value output by the lookup table according to a preset shift control word; the shift bit number is determined by the bit height of the current lookup table address data, and is represented by the following formula:

[0023] wherein, S k The shift bit number of the data output by the kth lookup table, so as to ensure that the low weight value is aligned in bit before accumulation.

[0024] According to the low-power feedforward equalizer circuit provided by the application, the result output module performs the following operations: The input data is subjected to bit width adjustment and alignment processing, so that the processing results of each group are synchronized in time to reach the adder tree structure; The adder tree structure is used to perform addition operation according to a preset structure, each layer of adder is driven by a clock signal to add input data and pass the result to the next layer of adder; for a large number of groups, a multi-layer adder is used in cascade, and the number of each layer of adder is optimized according to the number of results of the previous layer; The operation process and result of the adder tree structure are monitored in real time, and once an error is detected, the final equalization signal is corrected according to a compensation algorithm, The corrected final equalization signal is output to a high-speed communication system after power amplification, level conversion and buffering by an output driving unit, for inter-symbol interference compensation.

[0025] Therefore, compared with the prior art, the low-power feedforward equalizer circuit has the following beneficial effects: 1、The multiplier is converted into a lookup table (LUT) table and an adder to realize the present application. The value of the LUT is composed of tap values, and the combination is used as a static variable, which remains stable during the operation of the circuit. Based on this characteristic, the cell of this part of the circuit does not flip every clock, and its dynamic power consumption is approximately 0.

[0026] 2、The combination of LUT and adder used in the present application avoids the frequent flipping of the cell of the multiplier circuit, reduces the interference caused by power consumption fluctuations. The static LUT value combination makes the operation state of the circuit more stable at different times, reduces the thermal noise and electromagnetic interference caused by dynamic power consumption, and improves the stability and reliability of the entire feedforward equalizer circuit (FFE circuit). In long-term operation or complex environment, the circuit of the present application can more stably perform signal processing tasks, reduce signal distortion and errors, and ensure the normal operation of the communication system.

[0027] 3、The present application converts the multiplier into LUT and adder, simplifying the circuit structure. LUT is a programmable logic unit with high flexibility and integration, which can realize complex logic functions in a small chip area, and the structure of the adder is relatively simple and occupies a small area. Therefore, the low-power feedforward equalizer circuit of the present application effectively reduces the circuit area, reduces the design complexity, is more convenient for integration in integrated circuits, improves the integration and performance-price ratio of the chip under the premise of ensuring performance.

[0028] 4、The circuit structure has better system adaptability and expansibility. Since the values of the LUT can be flexibly configured according to different tap value combinations, when the current feedforward equalizer circuit needs to adapt to different communication scenarios or adjust signal processing parameters, only the values in the LUT need to be modified, without the need to make large-scale changes to the hardware structure of the circuit, so that the circuit can easily cope with various communication demands, such as different bandwidths and different code rate signal processing. At the same time, it also provides convenience for subsequent function expansion and performance improvement of the feedforward equalizer circuit. Developers can further improve the performance of the circuit by optimizing the configuration of the LUT and the operation mode of the adder on the basis of the existing circuit, to meet the ever-developing communication technology demand.

[0029] The application will be described in further detail below with reference to the drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a schematic diagram of a prior art feedforward equalizer (FFE) circuit.

[0031] Figure 2 is a schematic diagram of an embodiment of a low-power feedforward equalizer circuit of the application.

[0032] Figure 3 is a schematic diagram of a circuit related to the lookup table module in an embodiment of a low-power feedforward equalizer circuit of the application.

[0033] Figure 4 is a schematic diagram of a circuit related to the clock-gated flip-flop module in an embodiment of a low-power feedforward equalizer circuit of the application. DETAILED DESCRIPTION

[0034] To make the objectives, technical solutions, and advantages of the application clearer, the technical solutions in the application will be described below in detail with reference to the drawings in the application. Obviously, the described embodiments are only some of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the application.

[0035] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearance of the phrase in various places in the specification indicates that the described feature, structure, or characteristic can be included in at least one embodiment of the application. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0036] Reference is made to Figures 2 to 4The embodiment provides a low-power feedforward equalizer circuit, comprising: A packet processing module divides tap values of the feedforward equalizer circuit into multiple groups, each group containing multiple tap values, and calculates tap combination values to be processed by each lookup table module; wherein, input data corresponding to each group of tap values is subjected to equivalent transformation, common factors are extracted to generate addresses suitable for lookup table query; meanwhile, each group of tap values after grouping is combined to form combination values of the corresponding lookup table, for example, each group corresponds to 7 parallel LUTs (corresponding to 7-bit data width), and each LUT selects a pre-stored tap value combination to output according to one bit of input data; A lookup table module is used for storing pre-calculated tap combination values and performing lookup operation according to input data bit combination to generate intermediate results; wherein, the lookup table module is configured to convert multiplier calculation into lookup table calculation, and replace real-time multiplication operation by storing static tap combination values, so as to reduce dynamic power consumption; A clock gating flip-flop module is integrated in the lookup table module and is a flip-flop circuit with clock gating function, which is used for enabling signal tap_update_en=1 when the tap value is updated, and the tap value output by the register DFF is updated; when the tap value remains unchanged, tap_update_en=0, the input clock of the register DFF is closed to save power consumption, and the tap value output by the register DFF remains stable at this time; A shift and accumulation module is used for performing weight shift operation on the intermediate results output by the lookup table module and then accumulating to generate processing results of multiple groups of tap values; A result output module is used for adding multiple processing results through an adder tree structure and outputting a final equalization signal of the feedforward equalizer circuit, which is used for inter-symbol interference compensation in a high-speed communication system.

[0037] Wherein, the tap_update_en enabling signal of the clock gating flip-flop module remains invalid in the normal working stage of the feedforward equalizer circuit, that is, tap_update_en=0, and is activated only when the adaptive stage or the tap value needs to be updated, that is, tap_update_en=1, so as to reduce dynamic power consumption caused by flip-flop clock rollover.

[0038] In the embodiment, as shown in Figure 4 The clock gating flip-flop module comprises: A latch circuit is used for temporarily storing the tap_update_en enabling signal to ensure signal stability; An AND gate circuit receives a system clock clock and the tap_update_en enabling signal, and allows the clock signal to pass only when the tap_update_en enabling signal=1. Register DFF, update LUT content when clock is active, otherwise keep static to reduce power consumption; When the current feed equalizer circuit is in normal working stage, tap_update_en enable signal = 0, the AND gate circuit output closes the clock, the clock input of the register DFF is 0, the register DFF has no signal flip, and the dynamic power consumption is approximately zero.

[0039] Specifically, where tap_update_en is a tap value update enable signal, tap_update_en = 0 most of the time, so the 16 contents of the LUT table (16 combinations of 4 tap values) are not updated, the clock input of the DFF flip-flop is 0, and the dynamic power consumption of the DFF during this period is very small and can be ignored. When tap_update_en = 1, the 16 contents of the LUT table are updated, and the clock input of the DFF divider is the clock signal. During this period, the DFF has dynamic power consumption.

[0040] As can be seen, through the clock gating mechanism, the FFE circuit closes the flip-flop clock in more than 95% of the working time, and is activated only at the necessary moment, significantly reducing the overall dynamic power consumption of the multiplier and flip-flop working together, and is suitable for large bandwidth high-speed communication scenarios.

[0041] Specifically, the embodiment divides the 16 FFE tap coefficients (tap values) into 4 groups, each containing 4 tap values; performs equivalent transformation operation on the input data corresponding to each group of taps, extracts the common factor, and generates the address of the corresponding lookup table (LUT) module to adapt to the subsequent lookup table-based calculation logic.

[0042] The lookup table (LUT) module stores the values related to the combination of FFE tap coefficients (tap values) calculated in advance; according to the bit combination of the input data and the input instruction generated by the grouping processing step, a lookup operation is performed to generate an intermediate result; wherein, by converting the traditional multiplier calculation into a lookup table calculation, the stored static tap value combination is used to replace the real-time multiplication operation, thereby reducing the dynamic power consumption; and when the tap value update enable signal (tap_update_en) is invalid, the clock input is closed through the clock gating trigger module integrated in the LUT module, so that the related trigger remains static, further reducing the dynamic power consumption; only when tap_update_en is valid, the clock input is activated, allowing the LUT content to be updated.

[0043] The binary weight shift operation is performed on the intermediate result output by the look-up table (LUT) module, and then the accumulation operation is performed, so as to generate the processing result of each group of tap values; the specific shift operation is determined according to the bit weight of the input data, for example, the output result of the bth LUT is left shifted by b bits and then participates in the accumulation, so as to realize the weighted sum calculation equivalent to the original multiplier.

[0044] The results of the four grouped processing modules processed through the shift and accumulation steps are added through the adder tree structure, and the final equalization signal of the 16-tap feed-forward equalizer (FFE) is output, which is used for compensating the inter-symbol interference (ISI) in the high-speed communication system.

[0045] In the embodiment, the grouped processing module performs the following operations: The input signal is defined as x ( n ), wherein the value of the input signal at the relative time n-k is x(n-k), the signal has a specific data bit width, and in the actual application scenario, the data bit width can be set according to the requirement, for example, in the embodiment, it is 7 bits, and the most significant bit (MSB) and the least significant bit (LSB) are determined according to the specific data range.

[0046] The coefficient sequence is defined as tap ( k ), the number of coefficients is N , and the N coefficients are divided into M groups, each group containing L coefficient values, that is, N = M × L , for example, in the present patent, they are divided into 4 groups, each group containing 4 tap values The output signal y ( n ) is obtained through the product sum operation of the input signal sequence and the coefficient sequence, and the calculation formula is:

[0047] In order to improve the calculation efficiency or adapt to the hardware implementation and other requirements, the grouped operation strategy is adopted to group the coefficient sequence, and the output signal y ( n ) can be represented as the sum of the operation results of each group, that is:

[0048] Among them, i represents the group number, j represents the sequence number in the group; Taking the grouping mode in the embodiment as an example, the following calculation form can be obtained:

[0049] Since the circuit structure of each group is the same after grouping, an equivalent transformation is performed on the output signal of one group, which is expressed as the following formula:

[0050] It can be seen that through this equivalent transformation, the redundant parts in the calculation are reduced and the calculation process is further optimized.

[0051] The packet processing module includes an input interface for receiving an input signal sequence. x(n - k) and tap value; a computing unit for performing group calculation and computing operations after equivalent transformation; an output interface for outputting result signals after group processing and calculation.

[0052] Furthermore, the input signal x ( n ) is converted to binary form and expressed as the following formula:

[0053] in, W is the data bit width, x ( n ) b represent x ( n ) b bits; With N coefficients, divided into M Group, each group L coefficients ( N = M × L ) as an example, combined with the input signal after binary conversion, the operation of one set of output signals is expressed as the following formula:

[0054] in, i is the group number ( i =0,1,..., M -1), j It is the sequence number within the group.

[0055] Combine the binary representation of the input signal and the operation after extracting the common factor with the binary bit operation: Input signal x ( n ) is broken down into its individual binary bits x ( n ) b With corresponding weight 2 bthe product of the tap combination values and, after factoring out the common factor, further integrates the operation into a weighted sum form of the operation results of different binary bits:

[0056] wherein, is the output value of the tap combination value, all sum b combinations are calculated, and the calculated combination values are stored in the lookup table module; wherein, .

[0057] In this embodiment, the lookup table module performs the following operations: The set of tap combination values is stored in a static random access memory or a register array in the order of the index of the input bit combination, forming a lookup table, which adopts a block storage structure and is divided into multiple sub-tables according to the grouping of the high bits of the input data, and the content of each sub-table is the same; The input data bit stream is received, and the bit height of the data stream bits is analyzed, and the bits of the same bit height in the group form an address of the lookup table; Through a multi-port parallel access mechanism, multiple tap combination values matching the bit combination are read from the corresponding sub-tables at the same time; The tap combination values output by the lookup table according to different bit height bits are subjected to a weighted shift operation to generate an intermediate result candidate set; The lookup table operation based on the address formed by the same bit height bit combination is completed through a multiplexer MUX.

[0058] Among them, the lookup table access clock gating: only when the input data is valid, the lookup table clock signal is enabled, reducing the power consumption of invalid access; data bit width dynamic truncation: according to the sparsity of the multiplier coefficient, the tap combination values corresponding to the all-zero coefficients are shielded from storage and access; differential encoding compression: the tap combination values of adjacent input bit combinations are stored in a differential manner, reducing the flip frequency of the storage unit.

[0059] Preferably, when the input signal is B bits, the lookup table module is a parallel lookup table array composed of B full-parallel lookup tables, each lookup table is configured with 4 input ports, and pre-calculated weight data matching the tap value bit width is stored; 4 groups of B-bit-width data are input, and are split into ⌈B⌉ groups through a grouping strategy, each group of 4-bit parallel input is input to the corresponding lookup table, and the synchronous output of B weight values in a single cycle is realized.

[0060] In this embodiment, the shift accumulation module includes a configurable shift register array, each register unit corresponds to a lookup table output one by one, and performs a dynamic right shift operation on the weight value output by the lookup table according to a preset shift control word; the shift bit number is determined by the bit height of the current lookup table address data, which is expressed as the following formula:

[0061] Among them, S k The shift bit number of the kth lookup table output data is to ensure that the low weight value is aligned before accumulation.

[0062] In this embodiment, a state machine controller module is also included, which divides the working period into T0-T5, a total of 6 stages. In the T0 period, the parallel loading of lookup table input data function is realized, and the input signal is transmitted to the lookup table module through multiple data channels at the same time, ensuring that the data is quickly and accurately loaded to provide initial data support for subsequent calculation. In the T1-T4 period, the pipeline adder tree is driven to operate step by step. Each level of adder completes the corresponding addition operation in the corresponding period, and the data is transmitted and calculated in the pipeline structure in turn, realizing an efficient accumulation operation process. In the T5 period, the sign bit detection and subtraction compensation operation is performed. The result obtained after the previous operation is analyzed for the sign bit, and subtraction compensation is performed according to the preset rules to ensure the accuracy and sign correctness of the final output result.

[0063] To solve the data hazard problem that may occur when processing high-order taps, the state machine controller inserts a 2-clock cycle holding state. In these two holding periods, the transmission and operation of data are suspended, and the relevant data is prepared, to ensure that the operation on the critical path can be stable and correct, while ensuring that the critical path delay does not exceed 80% of the system clock period, maintaining the efficient and stable operation of the circuit.

[0064] In this embodiment, a dynamic reconfiguration interface module is also included, which provides an 8-bit configuration register group as the core control unit for dynamic reconfiguration. This register group has flexible configuration capability and can be parameterized and functionally adjusted according to different application requirements.

[0065] Lookup table data update: users can modify the pre-computed weight data stored in the lookup table at any time according to actual needs, so that the circuit can adapt to different calculation scenarios and data characteristics, improving the flexibility and adaptability of the circuit.

[0066] Shift control word reload: the shift control word parameters can be modified in real time S k by adjusting S kThe shift number of the weight value can be changed to adapt to the processing requirements of taps of different orders, thereby supporting different FIR filter structures.

[0067] The adder tree depth configuration: the adder tree depth can be adjusted in the range of 3-5 levels. According to different calculation accuracy and speed requirements, the user can flexibly configure the depth of the adder tree to optimize the circuit performance, so that it can adapt to FIR filter applications of various data bit widths (8 / 12 / 16 bits) and different orders (4≤N≤256).

[0068] The control circuit realizes efficient management of the shift and accumulation operation and the ability to adapt to various application scenarios through the precise timing control of the state machine controller and the flexible configuration function of the dynamic reconfiguration interface. Under the premise of ensuring the accuracy and stability of the operation, the universality and scalability of the circuit are significantly improved, the switching cost and development difficulty of the circuit in different application scenarios are reduced, and the circuit is suitable for scenarios that require FIR filters in communication, signal processing and other fields.

[0069] In the embodiment, the result output module performs the following operations: The input data is subjected to bit width adjustment and alignment processing, so that the processing results of each group are synchronized in time to reach the adder tree structure; The adder tree structure performs addition operation according to the preset structure, each layer of adder adds the input data under the drive of the clock signal, and passes the result to the next layer of adder; for a large number of groups, a multi-layer adder cascade mode is adopted, and the number of each layer of adder is optimized according to the number of results of the previous layer; The operation process and result of the adder tree structure are monitored in real time, and once an error is detected, the final equalization signal is corrected according to the compensation algorithm, The corrected final equalization signal is output to the high-speed communication system after power amplification, level conversion and buffering processing by the output driving unit for inter-symbol interference compensation.

[0070] In actual application, for the input signal sequence with a data bit width of 7 bits, i.e. the most significant bit MSB is 6 and the least significant bit LSB is 0 , and the number of taps is 16 and is divided into 4 groups, each group containing 4 tap values; The input signal is processed according to the calculation formula (FFE) of the finite word effect:

[0071] Since the circuit structure of each group after grouping is the same, one group is subjected to equivalent transformation processing, which is represented by the following formula:

[0072] Further, the can be written in binary form as:

[0073] wherein, is the bth bit of , thus we have:

[0074] The can be factored out as a common factor, and we have:

[0075]

[0076]

[0077]

[0078]

[0079]

[0080]

[0081]

[0082]

[0083] wherein . Herein , , , takes the value of 0 or 1. Thus takes the value according to the following lookup table 1: Table 1: Combination lookup table

[0084] Thus, as long as all the combinations of are pre-calculated and stored in a lookup table (LUT), and then the LUT operation is performed with , , , as the address, the value of can be calculated, and then the value of ( ) is calculated according to The results of the feed forward equalizer circuit are calculated by performing accumulation after shifting.

[0085] As Figure 3 shown, is a circuit diagram of a single group of look-up table module (LUT), each group has 7 such LUTs (corresponding to 7-bit wide data), and the content of each LUT table is the same, only the input selection data , , , will be different. The look-up table is actually a case selection circuit, according to different input values, select different tap value combination value output.

[0086] For example, for the group 1 input data , , , = {1010001, 0101101, 1100101, 0011001}, then for the input data and output data of 7 LUTs as shown in Table 2: Table 2: Input data and output data table of LUT

[0087] From the above formula derivation, for one group of circuits in the FFE function as Figure 2 shown. Because the FFE tap value is a slowly changing parameter, the FFE tap value update enable signal tap_update_en is used as the clock gating circuit. In most of the time in actual work, the FFE tap value is not updated, and the tap_update_en signal will make the clock of the DFF in the closed state, so the DFF circuit signal has no flip, and the overall FFE circuit dynamic power consumption is on the adder in the back end, thereby reducing the overall power consumption.

[0088] From the above formula derivation:

[0089] Figure 2 The circuit in is the specific implementation of the formula, where is the output value of .

[0090] The final result of the FFE function is the sum of the results of the 4 groups, represented as:

[0091] The technical scheme of the present application can obtain obvious power consumption reduction benefits. The following Table 3 is the measured data: Table 3: Comparison effect table of the present application and the traditional scheme

[0092] In summary, in the traditional FFE circuit, a large number of multipliers are used for signal processing. Since the number of multiplier gate circuits is usually several to tens of times the number of adders, and in actual application scenarios, the tap coefficient values of the FFE are mostly constant values except in the adaptive phase, while the input data is constantly changing, which makes the cells of the multiplier circuit flip every clock cycle, resulting in a large amount of dynamic power consumption. The present application converts the multiplier into a lookup table (LUT) and an adder through transformation. The LUT value is composed of tap values, and this combination remains stable during circuit operation as a static variable. Based on this characteristic, the cells of this part of the circuit do not flip every clock cycle, and its dynamic power consumption is approximately 0. Through actual test comparison, in the case of 16 FFE taps, 7-bit FFE tap data width, and 7-bit input data width, the power consumption of the traditional scheme is 59.6 mw, while the power consumption of the present application is only 38.9 mw, which is reduced by 34.74%, greatly reducing the energy consumption of the circuit and improving the energy utilization efficiency.

[0093] Due to the large use of multipliers in traditional FFE circuits and their dynamic power consumption characteristics, the circuit is easily affected by power consumption fluctuations during operation, which may cause instability in signal processing, and even cause circuit failure. The LUT and adder combination implementation method used in the present application avoids the frequent flipping of the multiplier circuit cells, reducing the interference caused by power consumption fluctuations. The static LUT value combination makes the operation state of the circuit at different times more stable, reducing the thermal noise and electromagnetic interference caused by dynamic power consumption, thereby improving the stability and reliability of the entire FFE circuit. In long-term operation or complex environments, the circuit proposed in the present application can more stably perform signal processing tasks, reduce signal distortion and errors, and ensure the normal operation of the communication system.

[0094] The use of a large number of multipliers in the traditional FFE circuit makes the circuit area large and the design complexity high, which is not conducive to the integration and optimization of the circuit. The complex structure of the multiplier occupies a large chip area, increases the manufacturing cost and power consumption of the chip. The present application simplifies the circuit structure by converting the multiplier into LUT and adder. LUT is a programmable logic unit with high flexibility and integration, which can realize complex logic functions in a small chip area. The structure of the adder is relatively simple and occupies a small area. Therefore, the low-power feedforward equalizer circuit proposed in the present application effectively reduces the circuit area and design complexity under the premise of ensuring performance, and is more convenient for integration in integrated circuits, improving the integration and performance-price ratio of the chip.

[0095] The circuit structure proposed in the present application has better system adaptability and expandability. Since the value of LUT can be flexibly configured according to different tap value combinations, when the feedforward equalizer circuit needs to adapt to different communication scenarios or adjust signal processing parameters, only the value in LUT needs to be modified, without the need for large-scale modification of the hardware structure of the circuit, so that the circuit can easily cope with various communication demands, such as different bandwidths and different code rate signal processing. At the same time, it also provides convenience for subsequent function expansion and performance improvement of the feedforward equalizer circuit. Developers can further improve the performance of the circuit by optimizing the configuration of LUT and the operation mode of the adder based on the existing circuit, to meet the ever-developing communication technology demand.

[0096] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present application.

[0097] The above-described embodiments are only preferred embodiments of the present application, and cannot be used to limit the scope of protection of the present application. Any non-essential changes and replacements made by those skilled in the art based on the present application shall fall within the scope of protection of the present application.

Claims

1. A low power feed forward equalizer circuit, characterized by, comprises: a group processing module, which divides tap values of a feedforward equalizer circuit into multiple groups, each group containing multiple tap values, and calculates tap combination values to be processed by each lookup table module; a lookup table module, which is used to store pre-calculated tap combination values and performs lookup operations according to input data bit combinations to generate intermediate results; a clock-gated flip-flop module, which is integrated in the lookup table module and is a flip-flop circuit with a clock gating function, used to enable a signal tap_update_en=1 when tap values are updated, and to complete tap value update of a register DFF output, and to close the input clock of the register DFF when the tap values remain unchanged, i.e. tap_update_en=0; a shift and accumulation module, which performs weight shift operations on the intermediate results output by the lookup table module and then accumulates the intermediate results to generate processing results of multiple tap values; a result output module, which adds multiple processing results through a tree structure of adders and outputs a final equalization signal of the feedforward equalizer circuit for inter-symbol interference compensation in a high-speed communication system.

2. The circuit of claim 1, wherein: the tap_update_en enable signal of the clock-gated flip-flop module is invalid during a normal working stage of the feedforward equalizer circuit, i.e. tap_update_en=0, and is activated only during an adaptive stage or when tap values need to be updated, i.e. tap_update_en=1, thereby reducing dynamic power consumption caused by flip-flop clock toggling.

3. The circuit of claim 2, wherein, the clock-gated flip-flop module comprises: a Latch circuit, which is used to temporarily store the tap_update_en enable signal; an AND gate circuit, which receives a system clock clock and the tap_update_en enable signal and allows the clock signal to pass through only when the tap_update_en enable signal=1; a register DFF, which updates LUT content when the clock is valid, and remains static to reduce power consumption otherwise; wherein, during the normal working stage of the feedforward equalizer circuit, the tap_update_en enable signal=0, the AND gate circuit outputs a closed clock, the clock input of the register DFF is 0, the register DFF has no signal toggling, and the dynamic power consumption is approximately zero.

4. The circuit of claim 1, wherein, The group processing module performs the following operations: defining an input signal x ( n ), wherein the value of the input signal at a relative time instant n-k is x(n-k), defining a sequence of coefficients tap ( k ), the number of coefficients being N , and dividing the N coefficients into M groups, each group comprising L coefficient values, i.e. N = M × L ; Output signal y ( n ) is obtained by summing the products of the input signal sequence and the coefficient sequence, and the calculation formula is: The output signal can be expressed as the sum of the results of the group operations after grouping the coefficient sequence using a group operation strategy y ( n ) wherein i represents a group number, j represents an intra-group serial number; Since the circuit structure of each group is the same after grouping, the output signal of one group is processed by equivalent transformation, which is represented by the following formula: The grouping processing module comprises an input interface, an input signal sequence is received x(n-k) and tap values; a calculation unit for performing grouping calculation and equivalent transformation calculation operation; and an output interface for outputting the result signal after grouping processing and calculation.

5. The circuit of claim 4, wherein: The input signal x ( n ) is converted into binary form, represented as the following equation: wherein, W is a data bit width, x ( n ) b represents x ( n ) the first b bit; with N coefficients, divided into M groups, with L coefficients in each group, the operation of the output signal of one group is expressed as the following formula in combination with the input signal converted in binary form: wherein i is a group number, j is an intra-group serial number.

6. The circuit of claim 5, wherein: In combination with the binary representation of the input signal, the operation after factoring out the common factor is combined with the binary bit operation: the input signal x ( n ) is decomposed into individual binary bits x ( n ) b and the product with the corresponding weight 2 b The operation after factoring out the common factor is further integrated into the form of weighted summation of the operation results of different binary bits in the expression: wherein, is the output value, all sum b combinations are calculated and these calculated combination values are stored in a look-up table module; wherein .

7. The circuit of claim 1, wherein, The lookup table module performs the following operations: a set of tap combination values is stored in a static random access memory or a register array in the order of the index of the input bit combination, forming a lookup table, which adopts a block storage structure and is divided into multiple sub-tables according to the grouping of high bits of input data, and each sub-table has the same content; an input data bit stream is received, and the bit height of the data stream bits is analyzed, and bits of the same bit height within a group form an address of a lookup table; Through a multi-port parallel access mechanism, simultaneously read multiple tap combination values matching the bit combination from the corresponding sub-tables; According to the tap combination values output by the look-up table according to different bit-high bits, perform a weighted shift operation to generate an intermediate result candidate set; Through a multiplexer MUX, complete the look-up table operation based on the address composed of the same bit-high bit combination.

8. The circuit of claim 1, wherein: When the input signal is B bits, the look-up table module is a parallel look-up table array composed of B full-parallel look-up tables, each look-up table being configured as a 4-input port and storing pre-computed weight data matching the tap value bit width; Input 4 groups of B-bit-wide data, split into ⌈B⌉ groups through a grouping strategy, each group being 4 bits and input to the corresponding look-up table in parallel to realize the synchronous output of B weight values in a single cycle.

9. The circuit of claim 7 or 8, wherein: The shift and accumulation module includes a configurable shift register array, each register unit corresponding to the output of a look-up table, and performing a dynamic right shift operation on the weight value output by the look-up table according to a preset shift control word; the shift bit number is determined by the bit height of the current look-up table address data, and is represented by the following formula: wherein, S k The number of shift bits for the output data of the kth lookup table is determined to ensure that the low bit weight values are bit weight aligned before accumulation.

10. The circuit according to any one of claims 1 to 8, characterized in that The result output module performs the following operations: Adjust and align the bit width of the input data to make the processing results of each group arrive at the adder tree structure synchronously in time; Through the adder tree structure, perform addition according to the preset structure, each layer of adder adding the input data under the drive of the clock signal and passing the result to the next layer of adder; for a large number of groups, use a multi-layer adder cascade mode, and the number of each layer of adder is optimized according to the number of results of the previous layer; Monitor the operation process and result of the adder tree structure in real time, and once an error is detected, immediately correct the final equalization signal according to the compensation algorithm, The corrected final equalization signal is output to the high-speed communication system after power amplification, level conversion and buffering by the output drive unit, and is used for inter-symbol interference compensation.

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