Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention discloses a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises a first semiconductor structure, and the first semiconductor structure comprises a transistor which comprises a semiconductor layer which at least extends along a first direction, and a gate layer which extends along a second direction; the semiconductor layer is provided with a first end and a second end which are oppositely arranged along a first direction, and a middle area is arranged between the first end and the second end; the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are adjacently arranged in the third direction, and the gate layer comprises a first gate layer and a second gate layer which are adjacently arranged in the third direction; the first gate layer and the second gate layer are located between the first semiconductor layer and the second semiconductor layer; a first distance is formed between the first end of the first semiconductor layer and the first end of the second semiconductor layer in the third direction, and a second distance is formed between the middle area of the first semiconductor layer and the middle area of the second semiconductor layer in the third direction; the first distance is greater than the second distance.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Some semiconductor devices, such as Dynamic Random Access Memory (DRAM), can include a memory array and a peripheral circuit, which can control the memory array, and operate the memory array to perform read, write or refresh operations. To improve the performance of the memory device, there is much room for improvement in the memory device and the manufacturing method thereof. SUMMARY

[0003] According to some aspects of embodiments of the present disclosure, a semiconductor device is provided, including a first semiconductor structure, the first semiconductor structure including: a transistor including a semiconductor layer extending at least along a first direction, and a gate layer extending along a second direction; the semiconductor layer having a first end and a second end oppositely arranged along the first direction, and an intermediate region between the first end and the second end; the semiconductor layer including a first semiconductor layer and a second semiconductor layer adjacently arranged along a third direction, and the gate layer including a first gate layer and a second gate layer adjacently arranged along the third direction; the first gate layer and the second gate layer being between the first semiconductor layer and the second semiconductor layer; the third direction intersecting the second direction, and a plane formed by the third direction and the second direction intersecting the first direction; wherein a first distance between the first end of the first semiconductor layer and the first end of the second semiconductor layer along the third direction is greater than a second distance between the intermediate region of the first semiconductor layer and the intermediate region of the second semiconductor layer along the third direction.

[0004] In some embodiments, the first semiconductor structure further includes: a wall structure extending along the second direction; and the semiconductor layer is located on two sides of the wall structure oppositely arranged along the third direction.

[0005] In some embodiments, the first semiconductor structure further includes: a first dielectric layer between the wall structure and the semiconductor layer; and the wall structure includes: a second dielectric layer, a conductive layer and a third dielectric layer stacked along the first direction, the second dielectric layer being located on a side of the conductive layer close to the first end along the first direction; wherein a size of the second dielectric layer along the third direction is less than a size of the conductive layer along the third direction.

[0006] In some embodiments, the second end of the first semiconductor layer and the second end of the second semiconductor layer have a third distance in the third direction, the third distance being greater than the second distance.

[0007] In some embodiments, the third dielectric layer has a dimension in the third direction that is less than a dimension of the conductive layer in the third direction.

[0008] In some embodiments, the semiconductor layer is disposed around two side surfaces of the wall structure opposite in the third direction, around one side surface of the wall structure in the first direction; the semiconductor layer includes two first ends, the first ends exposing another side surface of the wall structure in the first direction; the semiconductor layer provides a channel for two transistors adjacent in the third direction.

[0009] In some embodiments, the first end includes a protrusion, the protrusion extending in a direction away from the wall structure.

[0010] In some embodiments, a composition material of the semiconductor layer includes indium gallium zinc oxide (IGZO).

[0011] In some embodiments, the first semiconductor structure further includes a gate dielectric layer between the semiconductor layer and the gate layer.

[0012] In some embodiments, the first semiconductor structure further includes a capacitor structure on a side of the semiconductor layer close to the first end and coupled with the first end.

[0013] In some embodiments, the capacitor structure includes a first electrode, a fourth dielectric layer, and a second electrode, the fourth dielectric layer between the first electrode and the second electrode; the first electrode is coupled with the first end; a plurality of the capacitor structures are coupled through the second electrode.

[0014] In some embodiments, the first electrode extends in the first direction, the first electrode including an air gap.

[0015] In some embodiments, the first semiconductor structure further includes a bit line on a side of the semiconductor layer close to the second end and coupled with the second end.

[0016] In some embodiments, the semiconductor device further includes a second semiconductor structure on a side of the bit line away from the semiconductor layer; the second semiconductor structure includes a peripheral circuit, the second semiconductor structure bonded with the first semiconductor structure.

[0017] According to some aspects of some embodiments of the present disclosure, a semiconductor device is provided, comprising: a semiconductor layer extending along a first direction; the semiconductor layer having a first end and a second end oppositely arranged along the first direction; a wall structure extending along a second direction; the semiconductor layer being located on two sides of the wall structure oppositely arranged along a third direction; the third direction intersecting the second direction, and the third direction and the second direction forming a plane intersecting the first direction; a first dielectric layer located between the wall structure and the semiconductor layer; wherein the wall structure comprises a second dielectric layer, a conductive layer, and a third dielectric layer stacked along the first direction, the second dielectric layer being located on a side of the conductive layer close to the first end along the first direction; a dimension of the second dielectric layer in the third direction being smaller than a dimension of the conductive layer in the third direction.

[0018] In some embodiments, a dimension of the third dielectric layer in the third direction is smaller than a dimension of the conductive layer in the third direction.

[0019] In some embodiments, the semiconductor layer surrounds two sides of the wall structure oppositely arranged along the third direction, and surrounds a side surface of the wall structure along the first direction; the semiconductor layer comprises two first ends, and the first ends expose another side surface of the wall structure along the first direction.

[0020] In some embodiments, the first end comprises a protrusion extending away from the wall structure.

[0021] In some embodiments, the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer arranged adjacently along the third direction, and the semiconductor device further comprises: a gate layer extending along the second direction and located on two sides of the wall structure oppositely arranged along the third direction; the gate layer comprises a first gate layer and a second gate layer arranged adjacently along the third direction; the first gate layer and the second gate layer are located between the first semiconductor layer and the second semiconductor layer; and a gate dielectric layer is located between the semiconductor layer and the gate layer.

[0022] In some embodiments, the semiconductor device further comprises: a capacitor structure located on a side of the semiconductor layer close to the first end and coupled with the first end.

[0023] In some embodiments, the capacitor structure comprises: a first electrode, a fourth dielectric layer, and a second electrode, the fourth dielectric layer being located between the first electrode and the second electrode; wherein the first electrode is coupled with the first end; and a plurality of capacitor structures are coupled through the second electrode.

[0024] In some embodiments, the first electrode extends along the first direction, and the first electrode comprises an air gap.

[0025] In some embodiments, the semiconductor device further comprises a bit line located on a side of the semiconductor layer close to the second end and coupled with the second end.

[0026] In some embodiments, the wall structure, the semiconductor layer, and the bit line are located in a first semiconductor structure; the semiconductor device further comprises a second semiconductor structure located on a side of the bit line away from the semiconductor layer; the second semiconductor structure comprises a peripheral circuit, and the second semiconductor structure is bonded with the first semiconductor structure.

[0027] According to some aspects of embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided. A first semiconductor structure is formed. The method for forming the first semiconductor structure comprises: forming a first dielectric material layer, a first conductive material layer, and a second dielectric material layer stacked along a first direction; forming a first trench penetrating through the second dielectric material layer, the first conductive material layer, and at least part of the thickness of the first dielectric material layer, the first trench extending along a second direction; removing part of the first dielectric material layer at the bottom of the first trench to form a first opening with an opening direction towards a third direction to form a wall structure; wherein the dimension of the remaining first dielectric material layer in the third direction is smaller than the dimension of the first conductive material layer in the third direction; the third direction intersects the second direction, and the plane formed by the third direction and the second direction intersects the first direction; forming a first dielectric layer and a semiconductor layer on both sides of the wall structure along the third direction, the first dielectric layer being located between the wall structure and the semiconductor layer; wherein the semiconductor layer has a first end and a second end oppositely arranged along the third direction, part of the first dielectric layer is located on the inner wall of the first opening, and part of the first end is located on the inner wall of the first opening.

[0028] In some embodiments, the method for forming the wall structure further comprises: removing part of the second dielectric material layer at the opening end of the first trench to form a second opening with an opening direction towards the third direction; wherein the dimension of the remaining second dielectric material layer in the third direction is smaller than the dimension of the first conductive material layer in the third direction; part of the first dielectric layer is located on the inner wall of the second opening, and part of the second end is located on the inner wall of the second opening.

[0029] In some embodiments, the method of forming the semiconductor layer includes: forming a first dielectric layer on two sides of the first trench along the third direction; forming a semiconductor material layer covering the first dielectric layer along the third direction and covering the first trench bottom along the first direction; penetrating the semiconductor material layer along the first direction through the first trench bottom to form the semiconductor layer, the first end being located at the first trench bottom.

[0030] In some embodiments, the semiconductor material layer also covers the remaining second dielectric material layer along the first direction.

[0031] In some embodiments, the method of forming the semiconductor layer further includes: when penetrating the semiconductor material layer, a remaining part of the semiconductor material layer forms a protrusion; wherein the protrusion extends in a direction away from the wall structure.

[0032] In some embodiments, the method of forming the semiconductor layer further includes: forming a second trench along the first direction penetrating the semiconductor material layer, the second trench extending along the third direction.

[0033] In some embodiments, the method of forming the first semiconductor structure further includes: forming a gate dielectric layer and a second conductive material layer covering at least the semiconductor layer along the third direction and covering the first trench bottom along the first direction; penetrating at least the second conductive material layer along the first direction to form a gate layer.

[0034] In some embodiments, the method of forming the first semiconductor structure further includes: forming a capacitor structure on a side of the semiconductor layer close to the first end, an electrode close to the first end in the capacitor structure being coupled to the first end.

[0035] In some embodiments, the method of forming the first semiconductor structure further includes: forming a bit line on a side of the semiconductor layer close to the second end, the bit line being coupled to the second end.

[0036] In some embodiments, the method of manufacturing the semiconductor device further includes: bonding a second semiconductor structure on a side of the bit line away from the semiconductor layer, the second semiconductor structure including a peripheral circuit.

[0037] An embodiment of the present disclosure provides a semiconductor device, including a first semiconductor structure, wherein the first semiconductor structure includes a transistor, the transistor includes a semiconductor layer extending at least along a first direction and a gate layer extending along a second direction, the semiconductor layer has a first end and a second end arranged opposite to each other along the first direction, and the area between the first end and the second end is the middle area of ​​the semiconductor layer; the semiconductor layer includes a first semiconductor layer and a second semiconductor layer adjacent to each other in a third direction, the first end of the first semiconductor layer and the first end of the second semiconductor layer have a first distance in the third direction, and the middle area of ​​the first semiconductor layer and the middle area of ​​the second semiconductor layer have a second distance in the third direction; wherein the first distance is greater than the second distance, which can increase the distance between the first ends of the two semiconductor layers, reduce the electrical interference between the first semiconductor layer and the second semiconductor layer, and help expand the manufacturing process window of the semiconductor layer while further reducing the size and improving the integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a schematic diagram of a storage array according to an exemplary embodiment;

[0039] Figure 2 is a schematic diagram of a semiconductor device according to an exemplary embodiment;

[0040] Figures 3 to 7 is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure;

[0041] Figure 8 This is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0042] Figures 9 to 23 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0043] Figure 24 and Figure 25 FIG. 1 is a schematic diagram of an exemplary system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0045] In the following description, numerous specific details are given to provide a thorough understanding of the disclosure. However, it will be apparent that the disclosure can be practiced without one or more of the specific details. In other instances, well-known features are not described in order to avoid obscuring the disclosure. Unless otherwise specifically defined herein, all terms are to be given their broadest possible interpretation including modifi cations and variants thereof. Unless otherwise indicated herein, the terms "comprising", "including", "containing", "characterized by", "comprised of", "containing", "characterized by", "having", "including", and "comprised of" as used herein are used in their broadest sense and are intended to be open-ended terms.

[0046] It should be understood that although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0047] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0049] It should be understood that the specific features, structures, or characteristics described in some embodiments or one embodiment are included in at least one embodiment of the present disclosure. Therefore, the "in some embodiments" or "in one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the size of the sequence numbers of the above processes in various embodiments of the present disclosure does not mean the order of execution, and the execution order of the processes should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0050] The semiconductor device in the embodiments of the present disclosure can be a DRAM, or at least a part of the memory device in the DRAM, which can be applicable to a double data rate synchronous dynamic random access memory adopting a DDR4 memory specification, a DDR5 memory specification, a low power double data rate synchronous dynamic random access memory adopting a LPDDR5 memory specification. It should be noted that the embodiments of the present disclosure are not limited to DRAM, but in the following description, only DRAM is taken as an example for description.

[0051] In the DRAM, the storage array can be arranged in rows and columns, so that the storage unit can be addressed by specifying the row and column of its array. The storage array includes a plurality of word lines, and a plurality of bit lines, the word lines and the bit lines cross, and the storage unit at the intersection of the selected word line and the selected bit line is selected, and the read, write or refresh operation is performed. As Figure 1 As shown in the example, the storage array can include a plurality of word lines WLn, WLn+1, WLn-1 and WLn-2, a plurality of bit lines BLn, BLn+1, BLn-1 and BLn-2, and the word lines and the bit lines cross; the storage unit in the storage array can include a capacitor and a transistor, and one storage unit can include one transistor and one capacitor. The word line can also be a conductive structure such as a gate layer, which serves as the gate of the transistor, one controlled end (source) of the transistor is coupled with one electrode of the capacitor, the other controlled end (drain) of the transistor is coupled with the bit line, and the other electrode of the capacitor can be grounded or applied with other voltage (such as vdd / 2). Figure 1As shown, the memory cell array is arranged in x rows and y columns, the rows and columns can be perpendicular or not perpendicular, the x direction can be the third direction mentioned in the embodiments of the present disclosure, and the y direction can be the second direction mentioned in the embodiments of the present disclosure. The extension direction of the bit line can be parallel to the x direction or have an angle with the x direction, the extension direction of the word line can be parallel to the y direction or have an angle with the y direction, the orthogonal projection of the word line on the xoy plane is perpendicular to the orthogonal projection of the bit line on the xoy plane, or has an angle, and the embodiments of the present disclosure do not limit this. The z direction shown in the following examples can be the first direction, and the z direction can be perpendicular to the xoy plane or cross the xoy plane and not be perpendicular.

[0052] In the read or write operation, the corresponding word line can be selected by using the word line selection signal, the corresponding bit line can be selected according to the column selection signal, and the selected memory cell can be positioned when the word line and the bit line are selected at the same time. At this time, the transistor of the selected memory cell is turned on due to the operation voltage applied by the word line, so that the read, write or refresh operation of the selected memory cell can be performed. In some embodiments, the capacitor can be replaced by other storage structures, including but not limited to: phase change storage structure, resistance change storage structure or magnetic change storage structure, etc.

[0053] In some embodiments, the capacitor represents logical 1 and 0 by more and less of the charge stored therein, or the high and low of the voltage difference between the two ends of the capacitor. The voltage signal on the word line is applied to the gate to control the conduction or closing of the transistor, to realize the selection and non-selection of the capacitor, and then the data information stored in the capacitor is read through the bit line, or the data is written into the capacitor through the bit line to store.

[0054] According to some aspects of the embodiments of the present disclosure, Figure 2A semiconductor device is provided, including a first semiconductor structure. The first semiconductor structure 101 includes: a transistor 110, including a semiconductor layer 111 extending at least along the z-direction, and a gate layer 112 extending along the y-direction; the semiconductor layer 111 has a first end and a second end oppositely arranged along the z-direction, and an intermediate region between the first end and the second end; the semiconductor layer 111 includes a first semiconductor layer 1111 and a second semiconductor layer 1112 adjacently arranged in the x-direction, and the gate layer 112 includes a first gate layer 1121 and a second gate layer 1122 adjacently arranged in the x-direction. 22; the first gate layer 1121 and the second gate layer 1122 are located between the first semiconductor layer 1111 and the second semiconductor layer 1112; the x-direction intersects with the y-direction, and the plane formed by the x-direction and the y-direction intersects with the z-direction; wherein, the first end of the first semiconductor layer 1111 and the first end of the second semiconductor layer 1112 have a first distance in the x-direction, and the first distance is denoted as D1; ​​the middle region of the first semiconductor layer 1111 and the middle region of the second semiconductor layer 1112 have a second distance in the x-direction, and the second distance is denoted as D2; the first distance is less than or equal to the second distance.

[0055] Transistor 110 may include a semiconductor layer 111, a gate dielectric layer 113 located on semiconductor layer 111, and a gate layer 112. Gate layer 112 serves as a control gate or word line for transistor 110, while semiconductor layer 111 serves as the channel of transistor 110. A voltage applied through gate layer 112 can control the on / off state of transistor 110, specifically controlling the on / off state of the corresponding semiconductor layer 111. At least a portion of semiconductor layer 111 may extend in the yoz plane. Opposite ends of semiconductor layer 111 in the z-direction are designated as a first end and a second end, respectively. The region between the first and second ends is designated as an intermediate region. The first and second ends may have the same doping type and serve as the active region (drain or source, with the source and drain being interchangeable) of transistor 110. The intermediate region between the first and second ends may have a doping type opposite to that of the first end, serving as the channel of transistor 110. Gate layer 112 covers the intermediate region between the first and second ends in the x-direction. The first end, the second end, and the middle area of ​​the embodiment of the present disclosure are different areas of the semiconductor layer 111. They are only for the purpose of explaining the embodiment. In the actual physical structure, there may not be a clear dividing line. The first end can be the end in the negative z direction in the figure, which can be the lower end of the semiconductor layer 111 and can be used to couple with the capacitor structure 140; the second end can be the end in the positive z direction in the figure, which can be the upper end of the semiconductor layer 111 and can be used to couple with the bit line 114 (which can be described later). Figure 6 shown) coupling.

[0056] Exemplarily, the semiconductor layer 111 can include any semiconductor material in the art, including but not limited to: elemental semiconductor material (e.g. silicon, germanium), Group III-V compound semiconductor material, Group II-VI compound semiconductor material, organic semiconductor material, or other semiconductor material known in the art; for example, monocrystalline silicon, polycrystalline silicon, germanium, silicon carbide, indium gallium zinc oxide (IGZO), etc. The gate layer 112 can include but not limited to: tungsten, gold, silver, copper, chromium, nickel, titanium, or aluminum, etc. The gate dielectric layer 113 can include but not limited to: silicon oxide, silicon nitride, silicon oxynitride, silicon nitride, or aluminum oxide, etc.

[0057] Figure 2 Exemplarily, the semiconductor layer 111 can be located on two sides of the wall structure 120 opposite to each other in the x direction, the wall structure 120 extends along the y direction, the semiconductor layer 111 and the gate layer 112 are located between two adjacent wall structures 120, and the wall structure 120 provides an adhesion surface for the semiconductor layer 111; the first semiconductor layer 1111 can be located on the right side of the wall structure 120, and the second semiconductor layer 1112 can be located on the left side of the wall structure 120; the first gate layer 1121 can be located on the right side of the wall structure 120, and the second gate layer 1122 can be located on the left side of the wall structure 120. The second end of the first semiconductor layer 1111 and the second end of the second semiconductor layer 1112 can be a continuous structure, one semiconductor layer 111 can cover one side surface of the wall structure 120 in the z direction and two surfaces opposite to each other in the x direction; one semiconductor layer 111 can include a first semiconductor layer 1111 and a second semiconductor layer 1112, and the second ends of the first semiconductor layer 1111 and the second semiconductor layer 1112 are connected by the semiconductor layer 111 extending along the x direction, and the first semiconductor layer 1111 and the second semiconductor layer 1112 correspond to two transistors 110 respectively. Alternatively, the cross-sectional view of the semiconductor layer 111 in the xoz plane can be U-shaped (or inverted U-shaped), including two first ends and one second end covering the top surface of the wall structure 120, the two first ends enclosing an opening to expose the wall structure 120, and one semiconductor layer 111 corresponding to two transistors 110, and extending along the z direction as the first semiconductor layer 1111 and the second semiconductor layer 1112 respectively. For example, the first transistor 110 can include the first semiconductor layer 1111 located on the right side of a wall structure 120, the first gate layer 1121 located on the first semiconductor layer 1111, specifically the part of the first gate layer 1121 overlapping the first semiconductor layer 1111 in the x direction, and the gate dielectric layer 113 located between the first semiconductor layer 1111 and the first gate layer 1121.

[0058] In some embodiments, Figure 2The U-shaped semiconductor layer 111 shown in the middle is broken or removed along the z direction to cover the film layer of the wall structure 120, and the second end of the first semiconductor layer 1111 and the second end of the second semiconductor layer 1112 are not connected by the semiconductor layer 111. Figure 2 The U-shaped semiconductor layer 111 shown in the middle covers part of the wall structure 120 along the z direction, provides a larger and flatter contact surface for the bit line 114 to reduce the contact gap between the bit line 114 and the semiconductor layer 111, improve the stability of the device, and save the process step of removing the semiconductor layer 111 to expose the wall structure 120 to reduce the manufacturing cost.

[0059] In the manufacturing of the semiconductor device, based on the trench penetrating the wall structure 120, the semiconductor material layer covering the bottom and sidewall of the trench can also cover the top surface of the wall structure 120; the semiconductor material layer is etched to form the first semiconductor layer 1111 and the second semiconductor layer 1112 penetrating the bottom of the trench, and the first end is exposed at the bottom of the trench; the first distance D1 of the first end at the bottom of the trench in the x direction is less than or equal to the second distance D2 of the middle region of the first semiconductor layer 1111 and the middle region of the second semiconductor layer 1112 in the x direction. In some other embodiments, the bottom of the trench can be etched to form an opening extending along the x direction, so that the formed semiconductor material layer extends along the x direction towards the wall structure 120, which is convenient for the process window of film layer deposition and etching, and makes the first distance D1 of the formed semiconductor layer 111 greater than the second distance D2, reducing the electrical interference between the first semiconductor layer 1111 and the second semiconductor layer 1112.

[0060] According to some aspects of embodiments of the present disclosure, Figure 3A semiconductor device is provided, comprising a first semiconductor structure 101, the first semiconductor structure 101 comprising: a transistor 110 comprising a semiconductor layer 111 extending at least along a first direction (z direction) and a gate layer 112 extending along a second direction (y direction); the semiconductor layer 111 has a first end and a second end oppositely arranged along the first direction (z direction), and an intermediate region between the first end and the second end; the semiconductor layer 111 comprises a first semiconductor layer 1111 and a second semiconductor layer 1112 adjacently arranged along a third direction (x direction), and the gate layer 112 comprises a first gate layer 1121 and a second gate layer 1122 adjacently arranged along the third direction; the first gate layer 1121 and the second gate layer 1122 are located between the first semiconductor layer 1111 and the second semiconductor layer 1112; the third direction intersects the second direction, and a plane formed by the third direction and the second direction intersects the first direction; wherein the first end of the first semiconductor layer 1111 and the first end of the second semiconductor layer 1112 have a first distance D1 in the x direction, and the intermediate region of the first semiconductor layer 1111 and the intermediate region of the second semiconductor layer 1112 have a second distance D2 in the x direction; the first distance D1 is greater than the second distance D2.

[0061] Unlike Figure 2 the semiconductor layer 111, Figure 3 the first semiconductor layer 1111 has a portion extending towards the wall structure 120, and the first distance D1 of the first end of the first semiconductor layer 1111 and the first end of the second semiconductor layer 1112 in the x direction is greater than the second distance D2 of the intermediate region of the first semiconductor layer 1111 and the intermediate region of the second semiconductor layer 1112 in the x direction, which is beneficial to increase the spacing distance between the two first ends and reduce the electrical interference between the first semiconductor layer 1111 and the second semiconductor layer 1112.

[0062] In some embodiments, with reference to Figure 3As shown, the first semiconductor structure 101 further comprises: a wall structure 120 extending along the y direction; the semiconductor layer 111 is located on two sides of the wall structure 120 arranged oppositely along the x direction, the semiconductor layer 111 is located between two adjacent wall structures 120, and the gate layer 112 is located between two adjacent wall structures 120. The wall structure 120 extending along the y direction provides an attachment plane for the semiconductor layer 111 and provides support for the semiconductor layer 111. The semiconductor layer 111 covers two sides of the wall structure 120 arranged oppositely along the x direction, and the semiconductor layer 111 can cover one surface of the wall structure 120 along the z direction. The cross-sectional shape of the semiconductor layer 111 in the xoz plane is U-shaped. The second end of the first semiconductor layer 1111 and the second end of the second semiconductor layer 1112 located on the same wall structure 120 are connected. The semiconductor layer 111 can only cover two sides of the wall structure 120, and the second end of the first semiconductor layer 1111 and the second end of the second semiconductor layer 1112 are spaced apart and not connected.

[0063] In some embodiments, with reference to Figure 3 As shown, the first semiconductor structure 101 further comprises: a first dielectric layer 131 located between the wall structure 120 and the semiconductor layer 111; the wall structure 120 comprises: a second dielectric layer 121, a conductive layer 122, and a third dielectric layer 123 stacked along the z direction, the second dielectric layer 121 is located on the side of the conductive layer 122 close to the first end along the z direction; wherein the size of the second dielectric layer 121 in the x direction is smaller than the size of the conductive layer 122 in the x direction.

[0064] The wall structure 120 can comprise an insulating material, which provides an attachment surface for the semiconductor layer 111 and mechanical support, or the wall structure 120 can comprise a conductive material, which acts as a back gate connected to a low potential, such as ground or negative voltage, to improve the coupling effect between adjacent transistors 110, reduce the parasitic capacitance between adjacent first semiconductor layer 1111 and second semiconductor layer 1112, and improve device stability. For example, the wall structure 120 comprises a second dielectric layer 121, a conductive layer 122, and a third dielectric layer 123 stacked in sequence, and the conductive layer 122 is grounded or connected to a negative voltage as a back gate; a first dielectric layer 131 is further provided between the side of the wall structure 120 and the semiconductor layer 111 to electrically isolate the conductive layer 122 from the semiconductor layer 111; the third dielectric layer 123 is used to electrically isolate the semiconductor layer 111 and the conductive layer 122 on both sides of the z direction; the second dielectric layer 121 is used to electrically isolate the conductive layer 122 and other conductive devices on both sides of the z direction, such as the electrode of the capacitor structure 140. The materials of the first dielectric layer 131, the second dielectric layer 121, and the third dielectric layer 123 can include but are not limited to: silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, etc. Figure 3The second dielectric layer 121 in the structure shown in FIG. 1 has a dimension in the x direction smaller than the conductive layer 122, and the second dielectric layer 121 has a dimension in the x direction smaller than the third dielectric layer 123. The second dielectric layer 121 and the third dielectric layer 123 are made of different materials so as to have different etching selectivity. In the manufacturing process, the dimension of the second dielectric layer 121 in the x direction can be reduced by etching without etching the third dielectric layer 123. Figure 2 The second dielectric layer 121, the conductive layer 122 and the third dielectric layer 123 in the structure shown in FIG. 1 can have equal dimensions in the x direction or substantially equal dimensions in the x direction within a certain error. The second dielectric layer 121 and the third dielectric layer 123 can be made of the same material.

[0065] For example, the conductive layer 122 can include, but is not limited to, tungsten, gold, silver, copper, chromium, nickel, titanium, aluminum, titanium nitride, and other conductive materials.

[0066] In some embodiments, referring to Figure 4 As shown in FIG. 1, the second end of the first semiconductor layer 1111 and the second end of the second semiconductor layer 1112 have a third distance (denoted as D3) in the x direction. The third distance D3 is greater than the second distance D2. The second end of the first semiconductor layer 1111 extends in the x direction towards the wall structure 120, so that the third distance is greater than the second distance, the distance between the adjacent first semiconductor layer 1111 and the second semiconductor layer 1112 is increased, and the interference between the adjacent semiconductor layers 111 is reduced.

[0067] In some embodiments, referring to Figure 4 As shown in FIG. 1, the third dielectric layer 123 has a dimension in the x direction smaller than the dimension of the conductive layer 122 in the x direction. The dimension of the third dielectric layer 123 in the x direction can be equal to or different from the dimension of the second dielectric layer 121 in the x direction. The third dielectric layer 123 can be made of the same material as the second dielectric layer 121 so as to have the same etching selectivity. In the manufacturing process, the dimensions of the third dielectric layer 123 and the second dielectric layer 121 in the x direction can be reduced by the same etching, and the manufacturing cost is reduced.

[0068] In some embodiments, referring to Figure 3 and Figure 4 As shown in FIG. 1, the first end and / or the second end of the semiconductor layer 111 extend in the x direction towards the wall structure 120. The gap between at least a part of the semiconductor layer 111 and the conductive layer 122 as the back gate can be reduced. The control ability of the back gate is increased, and the interference between the semiconductor layers 111 on both sides of the conductive layer 122 is reduced.

[0069] In some embodiments, referring to Figure 3 and Figure 4As shown, taking the first gate layer 1121 and the second gate layer 1122 adjacent to each other as an example, the first gate layer 1121 is located on the right side of the wall structure 120 and corresponds to the first semiconductor layer 1111, and the second gate layer 1122 is located on the left side of the wall structure 120 and corresponds to the second semiconductor layer 1112; the first end and / or the second end of the first gate layer 1121 extends towards the corresponding first semiconductor layer 1111, and the first end and / or the second end of the second gate layer 1122 extends towards the corresponding second semiconductor layer 1112.

[0070] In some embodiments, referring to Figure 3 and Figure 4 As shown, the semiconductor layer 111 is arranged on two sides of the wall structure 120 in the x direction and covers one side surface of the wall structure 120 in the z direction; the semiconductor layer 111 includes two first ends, and the first ends expose another side surface of the wall structure 120 in the z direction; the semiconductor layer 111 provides a channel for two transistors 110 adjacent in the x direction.

[0071] The second end of the first semiconductor layer 1111 and the second end of the second semiconductor layer 1112 can be a continuous structure, one semiconductor layer 111 can cover one side surface of the wall structure 120 in the z direction and two oppositely arranged surfaces in the x direction; one semiconductor layer 111 can include one first semiconductor layer 1111 and one second semiconductor layer 1112, and the second ends of the first semiconductor layer 1111 and the second semiconductor layer 1112 are connected by the semiconductor layer 111 extending in the x direction, and the first semiconductor layer 1111 and the second semiconductor layer 1112 correspond to two transistors 110 respectively. Alternatively, the cross-sectional pattern of the semiconductor layer 111 in the xoz plane can be U-shaped (or inverted U-shaped), including two first ends and one second end covering the top surface of the wall structure 120, the two first ends form an opening to expose the wall structure 120, one semiconductor layer 111 corresponds to two transistors 110, and the first semiconductor layer 1111 and the second semiconductor layer 1112 extend in the z direction respectively. The semiconductor layer 111 covers part of the wall structure 120 in the z direction, provides a larger and flatter contact surface for the bit line 114 to reduce the contact gap between the bit line 114 and the semiconductor layer 111, improve the stability of the device, and can save the process step of removing the semiconductor layer 111 to expose the wall structure 120 to reduce the manufacturing cost.

[0072] In some embodiments, referring to Figure 3 and Figure 4As shown, the first end includes a protrusion 1113 extending away from the wall structure 120. The end of the first end farthest from the second end has the protrusion 1113, which can extend away from the wall structure 120 in the x-direction, which can couple with the capacitor structure 140, increasing the coupling area of the first end with the capacitor structure 140 and providing a flat contact surface, improving the coupling stability. In some embodiments, the protrusion 1113 is a residue when the semiconductor layer 111 is formed by etching the semiconductor material between the adjacent wall structures 120 in the z-direction, which can not exist in some embodiments, or the protrusion 1113 can be small in the x-direction and not obviously visible.

[0073] In some embodiments, the semiconductor layer 111 includes indium-gallium-zinc oxide (IGZO) as the material. The IGZO material can include oxides of indium, gallium, and zinc, etc., which has excellent semiconductor properties. The addition of indium and gallium can improve the electron mobility of the semiconductor material, which can achieve lower operating voltage and lower power consumption compared to traditional semiconductor materials such as silicon; the introduction of zinc helps to improve the stability of the semiconductor material. The IGZO material can be used to deposit the semiconductor layer 111, which can control the film thickness, crystal type, and film morphology of the semiconductor layer 111 by controlling the deposition process parameters, which is beneficial to improve the yield of the semiconductor layer 111 and simplify the manufacturing process. The IGZO material can allow the semiconductor layer 111 to be directly in contact with the metal components such as the first electrode 141, which can reduce the contact resistance.

[0074] In some embodiments, referring to Figure 3 and Figure 4 As shown, the first semiconductor structure 101 further includes a gate dielectric layer 113 between the semiconductor layer 111 and the gate layer 112. The gate layer 112 can include a single-layer structure, for example, which can include tungsten; the gate layer 112 can also include a multi-layer structure, for example, which can include a first sub-gate layer and a second sub-gate layer, the first sub-gate layer being between the gate dielectric layer and the second sub-gate layer, the first sub-gate layer having a thickness smaller than the second sub-gate layer in the x-direction, and the first sub-gate layer being used to increase the adhesion of the gate dielectric layer and the second sub-gate layer. For example, the first sub-gate layer can include titanium nitride, and the second sub-gate layer can include tungsten. In some embodiments, the adjacent wall structures 120 have a filling layer therebetween to electrically isolate the adjacent gate and the semiconductor layer 111, and the filling layer and the gate dielectric layer 113 can include the same material, which can not have a clear physical boundary.

[0075] In some embodiments, referring to Figure 5As shown, the first semiconductor structure 101 further comprises: a capacitor structure 140 located at a side of the semiconductor layer 111 close to the first end and coupled with the first end. The capacitor structure 140 comprises two conductive electrodes and a dielectric layer electrically isolated between the two conductive electrodes. One electrode of the capacitor structure 140 is directly in contact with the first end of the semiconductor layer 111 or coupled through a conductive structure, and the specific structure of the capacitor structure 140 is not limited in the embodiments of the present disclosure. At least one electrode of the capacitor structure 140 can extend in the z direction.

[0076] In some embodiments, referring to Figure 5 As shown, the capacitor structure 140 comprises: a first electrode 141, a fourth dielectric layer 142, and a second electrode 143, the fourth dielectric layer 142 being located between the first electrode 141 and the second electrode 143; wherein the first electrode 141 is coupled with the first end; and a plurality of capacitor structures 140 are coupled through the second electrode 143. In some embodiments, referring to Figure 5 As shown, the first electrode 141 extends in the z direction, and the first electrode 141 comprises an air gap 144.

[0077] The first electrode 141 extends in the z direction and is directly in contact with the first end of the semiconductor layer 111 or coupled through a connecting portion (or a contact portion); the first electrode 141 can comprise an air gap 144 to reduce stress concentration and reduce deformation of the device. The fourth dielectric layer 142 can surround the sidewall of the first electrode 141 and the end of the first electrode 141 not coupled with the first end, and the second electrode 143 can surround the fourth dielectric layer 142; a part of the fourth dielectric layer 142 can extend in the z direction, a part of the second electrode 143 extends in the z direction and is located between two adjacent first electrodes 141, and another part of the second electrode 143 extends in the x direction and covers the fourth dielectric layer 142 in the z direction. The plurality of capacitor structures 140 can be coupled through the part of the second electrode 143 extending in the x direction, the part of the second electrode 143 extending in the x direction connects the plurality of capacitor structures 140, and the part of the second electrode 143 extending in the x direction can be used for grounding or applied with other voltages (such as vdd / 2).

[0078] In some embodiments, referring to Figure 5The first electrode 141 can include a first connecting layer and a conductive pillar, the first connecting layer surrounds the conductive pillar, the first connecting layer is between the conductive pillar and the fourth dielectric layer 142, and the first connecting layer is used to increase the adhesion between the fourth dielectric layer 142 and the conductive pillar. A second connecting layer is arranged between the fourth dielectric layer 142 and the second electrode 143, and the second connecting layer can increase the adhesion between the fourth dielectric layer 142 and the second electrode 143. For example, the first electrode 141 and the second electrode 143 can include conductive materials such as tungsten, gold, silver, copper, chromium, nickel, titanium, or aluminum; and the first connecting layer and the second connecting layer can include, but are not limited to, titanium nitride.

[0079] In some embodiments, referring to Figure 6 As shown, the first semiconductor structure 101 further includes a bit line 114 located on one side of the semiconductor layer 111 close to the second end and coupled with the second end.

[0080] For example, the second electrode 143 is connected to a common voltage, a voltage is applied to the bit line 114 through one bit line 114 and one gate layer 112 to select the semiconductor layer 111 at the intersection of the bit line 114 and the gate layer 112, a voltage is applied to one gate layer 112 to turn on the semiconductor layer 111 and provide a voltage to one first electrode 141, at this time, one capacitor structure 140 is selected, and a read, write or update operation is performed. An interconnection layer is arranged on the side of the bit line 114 away from the capacitor structure 140 to supply power to the bit line 114, or to supply power to the gate layer 112 and other structures, so as to supply power to the first semiconductor structure 101 or to lead out electrical signals.

[0081] In some embodiments, referring to Figure 7 As shown, the semiconductor device 100 further includes a second semiconductor structure 102 located on the side of the bit line 114 away from the semiconductor layer 111; the second semiconductor structure 102 includes a peripheral circuit 150, and the second semiconductor structure 102 is bonded with the first semiconductor structure 101; the bonding can include hybrid bonding.

[0082] Before the bonding, the to-be-bonded surfaces of the first semiconductor structure 101 and the second semiconductor structure 102 have first bonding contacts and second bonding contacts respectively, which respectively lead electrical signals of the semiconductor structures out to the to-be-bonded surfaces. The bonding contacts 115 can include: a pad, a conductive plug, or the like. The to-be-bonded surfaces of the first semiconductor structure 101 and the second semiconductor structure 102 are bonded, and the interface where the two to-be-bonded surfaces contact is a bonding interface. The first bonding contacts and the second bonding contacts contact and bond at the bonding interface, realizing electrical signal interconnection between the first semiconductor structure 101 and the second semiconductor structure 102. The first bonding contacts and the second bonding contacts can not have a physical boundary after bonding, and can be regarded as the bonding contacts 115 in the figure, which penetrate the bonding interface. The part of the bonding contacts 115 located in the first semiconductor structure 102 is the first bonding contact before bonding, and the part of the bonding contacts 115 located in the second semiconductor structure 102 is the second bonding contact before bonding. Taking the gate layer 112, the bit line 114, and the second electrode 143 as examples, the gate layer 112, the bit line 114, and the second electrode 143 can be coupled with the peripheral circuit 150 by contact structures to lead electrical signals out to the bonding contacts 115.

[0083] For example, the peripheral circuit 150 can include but is not limited to: a sense amplification circuit, a row decoding circuit, a column decoding circuit, a voltage generation circuit, and the like. The sense amplification circuit is coupled with the bit line 114, and can be configured to capture weak voltage fluctuations on the bit line 114, and restore the capacitance voltage of the storage unit locally according to the situation of the voltage fluctuations. The sense amplification circuit can include a latch, and the restored capacitance voltage value can be latched to make the information stored in the storage unit transferred from the capacitor to the amplification circuit. The sense amplification circuit can include a differential sense amplification circuit, which is coupled with two bit lines 114, and works with a selected bit line 114 and a complementary bit line 114 serving as a reference line to detect and amplify the voltage difference on the pair of bit lines 114. The row decoding circuit is configured to address the storage array and apply an operating voltage to the word line. The column decoding circuit is configured to column-address the storage array and apply or receive a bit line voltage. The voltage generation circuit generates the required high and low voltages for various devices.

[0084] In some embodiments, the second semiconductor structure 102 is not fixed with the first semiconductor structure 101 by bonding, and the bonding contacts 115 can not be arranged between the first semiconductor structure 101 and the second semiconductor structure 102.

[0085] According to some aspects of embodiments of the present disclosure, Figure 3A semiconductor device is provided, comprising: a semiconductor layer 111 extending at least along a first direction (z direction); the semiconductor layer 111 has a first end and a second end oppositely arranged along the first direction; a wall structure 120 extending along a second direction (y direction); the semiconductor layer 111 is located on two sides of the wall structure 120 oppositely arranged along a third direction (x direction); the third direction intersects the second direction, and a plane formed by the third direction and the second direction intersects the first direction; a first dielectric layer 131 is located between the wall structure 120 and the semiconductor layer 111; wherein the wall structure 120 comprises a second dielectric layer 121, a conductive layer 122 and a third dielectric layer 123 stacked along the first direction, and the second dielectric layer 121 is located on a side of the conductive layer 122 close to the first end along the first direction; the size of the second dielectric layer 121 in the third direction is smaller than the size of the conductive layer 122 in the third direction.

[0086] In some embodiments, as shown in Figure 4 , the size of the third dielectric layer 123 in the x direction is smaller than the size of the conductive layer 122 in the x direction.

[0087] In some embodiments, as shown in Figure 3 and Figure 4 , the semiconductor layer 111 surrounds two sides of the wall structure 120 oppositely arranged along the x direction, and surrounds a side surface of the wall structure 120 along the z direction; the semiconductor layer 111 comprises two first ends, and the first end exposes another side surface of the wall structure 120 along the z direction.

[0088] In some embodiments, as shown in Figure 3 and Figure 4 , the first end comprises a protrusion 1113 extending away from the wall structure 120.

[0089] In some embodiments, as shown in Figure 3 and Figure 4 , the semiconductor layer 111 comprises a first semiconductor layer 1111 and a second semiconductor layer 1112 arranged adjacent to each other in the x direction, and the semiconductor device further comprises: a gate layer 112 extending along the y direction and located on two sides of the wall structure 120 oppositely arranged along the x direction; the gate layer 112 comprises a first gate layer 1121 and a second gate layer 1122 arranged adjacent to each other in the x direction; the first gate layer 1121 and the second gate layer 1122 are located between the first semiconductor layer 1111 and the second semiconductor layer 1112; and a gate dielectric layer 113 is located between the semiconductor layer 111 and the gate layer 112.

[0090] In some embodiments, as shown in Figure 5 and Figure 6As shown, the semiconductor device further includes: a capacitor structure 140 located at a side of the semiconductor layer 111 close to the first end and coupled with the first end.

[0091] In some embodiments, referring to Figure 5 and Figure 6 As shown, the capacitor structure 140 includes: a first electrode 141, a fourth dielectric layer 142, and a second electrode 143, the fourth dielectric layer 142 being located between the first electrode 141 and the second electrode 143; wherein the first electrode 141 is coupled with the first end; a plurality of capacitor structures 140 are coupled through the second electrode 143.

[0092] In some embodiments, referring to Figure 5 and Figure 6 As shown, the first electrode 141 extends along a first direction, and the first electrode 141 includes an air gap 144.

[0093] In some embodiments, referring to Figure 6 As shown, the semiconductor device further includes: a bit line 114 located at a side of the semiconductor layer 111 close to the second end and coupled with the second end.

[0094] In some embodiments, referring to Figure 7 As shown, the wall structure 120, the semiconductor layer 111, and the bit line 114 are located in a first semiconductor structure 101; the semiconductor device 100 further includes: a second semiconductor structure 102 located at a side of the bit line 114 away from the semiconductor layer 111; the second semiconductor structure 102 includes a peripheral circuit 150, and the second semiconductor structure 102 is bonded with the first semiconductor structure 101.

[0095] According to some aspects of embodiments of the present disclosure, a method for manufacturing a semiconductor device 100 is provided, a first semiconductor structure 101 is formed, referring to Figure 8 As shown, the method for forming the first semiconductor structure 101 includes:

[0096] forming a first dielectric material layer, a first conductive material layer, and a second dielectric material layer stacked along a first direction;

[0097] forming a first trench penetrating through the second dielectric material layer, the first conductive material layer, and at least part of the thickness of the first dielectric material layer, the first trench extending along a second direction;

[0098] removing part of the first dielectric material layer at the bottom of the first trench to form a first opening with an opening direction towards a third direction to form a wall structure; wherein the size of the remaining first dielectric material layer in the third direction is smaller than the size of the first conductive material layer in the third direction; the third direction intersects the second direction, and the plane formed by the third direction and the second direction intersects the first direction.

[0099] A first dielectric layer and a semiconductor layer are formed on both sides of the wall structure along the third direction, the first dielectric layer is located between the wall structure and the semiconductor layer; wherein the semiconductor layer has a first end and a second end oppositely arranged along the third direction, a part of the first dielectric layer is located on the inner wall of the first opening, and a part of the first end is located on the inner wall of the first opening.

[0100] Specifically, referring to FIG. 1, a first dielectric material layer 1201, a first conductive material layer 1202, and a second dielectric material layer 1203 are sequentially formed in the z direction. The material layers can be formed on a structure such as a substrate, a base, or the like. For example, the formation process of the material layers can include, but is not limited to, a deposition process, which can include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). Figure 9 As shown in FIG. 1, a first trench 12 extending along the y direction is etched to pass through the second dielectric material layer 1203, the first conductive material layer 1202, and the first dielectric material layer 1201 in the z direction. The first trench 12 can only pass through part of the thickness of the first dielectric material layer 1201, and the remaining first dielectric material layer 1201 can be removed by subsequent etching.

[0101] As shown in FIG. 1, a first trench 12 extending along the y direction is etched to pass through the second dielectric material layer 1203, the first conductive material layer 1202, and the first dielectric material layer 1201 in the z direction. The first trench 12 can only pass through part of the thickness of the first dielectric material layer 1201, and the remaining first dielectric material layer 1201 can be removed by subsequent etching. Figure 10 As shown in FIG. 1, a first trench 12 extending along the y direction is etched to pass through the second dielectric material layer 1203, the first conductive material layer 1202, and the first dielectric material layer 1201 in the z direction. The first trench 12 can only pass through part of the thickness of the first dielectric material layer 1201, and the remaining first dielectric material layer 1201 can be removed by subsequent etching.

[0102] As shown in FIG. 1, a first trench 12 extending along the y direction is etched to pass through the second dielectric material layer 1203, the first conductive material layer 1202, and the first dielectric material layer 1201 in the z direction. The first trench 12 can only pass through part of the thickness of the first dielectric material layer 1201, and the remaining first dielectric material layer 1201 can be removed by subsequent etching. Figure 11 As shown in FIG. 1, a first trench 12 extending along the y direction is etched to pass through the second dielectric material layer 1203, the first conductive material layer 1202, and the first dielectric material layer 1201 in the z direction. The first trench 12 can only pass through part of the thickness of the first dielectric material layer 1201, and the remaining first dielectric material layer 1201 can be removed by subsequent etching. Figures 3 to 7 As shown in FIG. 1, a first trench 12 extending along the y direction is etched to pass through the second dielectric material layer 1203, the first conductive material layer 1202, and the first dielectric material layer 1201 in the z direction. The first trench 12 can only pass through part of the thickness of the first dielectric material layer 1201, and the remaining first dielectric material layer 1201 can be removed by subsequent etching. Figure 11In the etching process, the first dielectric material layer 1201 and the second dielectric material layer 1203 are different in material, and the second dielectric material layer 1203 is not etched or is substantially not etched in etching the first dielectric material layer 1201. The remaining first dielectric material layer 1201 is smaller in size in the x direction than the remaining first conductive material layer 1202 in the x direction. The etching process can include, but is not limited to, dry etching, wet etching, or any combination thereof.

[0103] Referring to Figure 12 Based on Figure 11 Referring to Figure 13 Referring to Figure 13 In some embodiments, the method of forming the semiconductor layer 111 further includes: etching the semiconductor material layer 1101 through the first dielectric layer 131 in the x direction to form the semiconductor layer 111, wherein the first end of the semiconductor layer 111 is located at the bottom of the first trench 12, and at least a portion of the first end is located in the first opening 13.

[0104] In some embodiments, the method of forming the semiconductor layer 111 includes: referring to Figure 13 Referring to Figure 14 Referring to Figure 15 Referring to

[0105] In some embodiments, referring to Figure 14 In some embodiments, referring to Figure 15 In some embodiments, the method of forming the semiconductor layer 111 further includes: when etching the semiconductor material layer 1101, a remaining portion of the semiconductor material layer 1101 forms a protrusion 1113; wherein the protrusion 1113 extends away from the wall structure 120.

[0106] Referring to Figure 14 As shown, when the semiconductor material layer 1101 is deposited, the semiconductor material layer 1101 covers the first dielectric layer 131 along the x direction, and covers the second dielectric material layer 1203 along the z direction. The semiconductor material layer 1101 is etched along the z direction through the bottom of the first trench 12 to form independent semiconductor layers 111 to be independently controlled by the gate layer 112. The part of the semiconductor layer 111 covering the second dielectric material layer 1203 along the z direction can be reserved to provide a larger and flatter contact surface for the subsequent bit line 114, reduce the contact gap between the bit line 114 and the semiconductor layer 111, improve the stability of the device, and save the process step of removing the semiconductor layer 111 to expose the wall structure 120 to reduce the manufacturing cost. When the semiconductor material layer 1101 is etched along the z direction through the bottom of the first trench 12, the residual semiconductor material layer 1101 forms a protrusion 1113 extending away from the first dielectric layer 131 along the x direction. The protrusion 1113 can be coupled with the capacitor structure 140 to increase the contact area of the first end with the capacitor structure 140 and provide a flat contact surface to improve the coupling stability.

[0107] In some embodiments, the part of the semiconductor layer 111 covering the second dielectric material layer 1203 along the z direction can be removed. The electronic migration phenomenon of the first semiconductor layer 1111 and the second semiconductor layer 1112 located on the same wall structure 120 on the opposite sides in the x direction is reduced to improve the stability of the device. For example, the removal process can include but is not limited to etching process, chemical mechanical polishing process or any combination thereof.

[0108] In some embodiments, as shown in Figure 16 The method of forming the semiconductor layer 111 further includes forming a second trench 14 extending through the semiconductor material layer 1101 along the z direction. The second trench 14 extends along the x direction. The cross-sectional view of the second trench 14 in the xoz plane can be an inverted U shape. The second trench 14 includes a part extending along the z direction and a part extending along the x direction. The second trench 14 exposes the first dielectric layer 131 along the z direction. The second trench 14 exposes the first dielectric layer 131 along the x direction. The second trench 14 divides the semiconductor material layer 1101 to form Figure 16 As shown, the semiconductor layers 111 are arranged in the y direction. The area between the adjacent semiconductor layers 111 in the y direction exposes the first dielectric layer 131.

[0109] In some embodiments, the method of forming the first semiconductor structure 101 further includes forming a gate dielectric layer 113 and a second conductive material layer 1102 covering the semiconductor layer 111 along the x direction and covering the bottom of the first trench 12 along the z direction; and etching along the z direction at least through the second conductive material layer 1102 to form the gate layer 112.

[0110] Reference Figure 17 and Figure 18 As shown, based on Figure 15 The first trench 12 shown in FIG. 1 is formed in sequence to form a gate dielectric layer 113, a second conductive material layer 1102 and a protective layer 1103 covering the semiconductor layer 111 along the x-direction and the z-direction; Figure 19 As shown, the protective layer 1103 and the second conductive material layer 1102 at least penetrate the bottom of the first trench 12 along the z direction, and the remaining second conductive material layer 1102 forms the gate layer 112. The protective layer 1103 is used to block the etchant to adjust the remaining size of the gate layer 112 in the z direction. The protective layer 1103 may include silicon nitride, silicon oxide, or silicon oxynitride. Figure 17 In the embodiment, the second conductive material layer 1102 may include a first sub-conductive material layer and a second sub-conductive material layer. The first sub-conductive material layer increases adhesion between the gate dielectric layer 113 and the second sub-conductive material layer. For example, the first sub-conductive material layer may include titanium nitride, and the second sub-conductive material layer may include tungsten. Figure 19 In the embodiment, the gate dielectric layer 113 located at the bottom of the first trench 12 may not be penetrated.

[0111] Reference Figure 20 As shown, the remaining space in the first trench 12 is filled with an insulating material, and the gate dielectric layer 113 on the surface of the second end side of the semiconductor layer 111 is planarized to expose the semiconductor layer 111. The filling process may include a spin coating process, and the planarization process may include chemical mechanical polishing. The insulating material and the protective layer 1103 may include the same material, such as silicon oxide, and there may be no obvious physical boundary between the same film layer materials.

[0112] In some embodiments, reference Figure 21 As shown, the method for forming the wall structure 120 also includes: removing a portion of the second dielectric material layer 1203 at the open end of the first groove 12 to form a second opening 15 with the opening direction facing the x-direction; wherein the size of the remaining second dielectric material layer 1203 in the x-direction is smaller than the size of the first conductive material layer 1202 in the x-direction; a portion of the first dielectric layer 131 is located on the inner wall of the second opening 15, and a portion of the second end is located on the inner wall of the second opening 15. Figure 21 The second dielectric material layer 1203 and the first dielectric material layer 1201 may be made of the same material. The sizes of the second dielectric material layer 1203 and the first dielectric material layer 1201 may be reduced by etching in the x-direction at the same time, forming a first opening 13 at the bottom of the first trench 12 and a second opening 15 at the open end of the first trench 12. A portion of the first dielectric layer 131 formed subsequently is located on the inner wall of the second opening 15, and a portion of the second end is located on the first dielectric layer 131 in the second opening 15. The formed first dielectric layer 131 and the semiconductor layer 111 may be as shown in FIG.Figure 4 shown.

[0113] In some embodiments, reference Figure 22 As shown, the method for forming the first semiconductor structure 101 further includes: forming a capacitor structure 140 on a side of the semiconductor layer 111 close to the first end, wherein the electrode close to the first end in the capacitor structure 140 is coupled to the first end. The capacitor structure 140 may include a first electrode 141, a fourth dielectric layer 142, and a second electrode 143, wherein the fourth dielectric layer 142 is located between the first electrode 141 and the second electrode 143; wherein the first electrode 141 is coupled to the first end; and a plurality of capacitor structures 140 are coupled through the second electrode 143. The first electrode 141 extends along the z-direction, and the first electrode 141 is directly contacted and coupled to the first end of the semiconductor layer 111 or coupled through a connecting portion (or, contact portion); the first electrode 141 may include an air gap 144 to reduce stress concentration to reduce deformation of the device. The fourth dielectric layer 142 may surround the first electrode 141, and the second electrode 143 may surround the fourth dielectric layer 142. A portion of the fourth dielectric layer 142 may extend along the z-direction, a portion of the second electrode 143 extends along the z-direction and is located between two adjacent first electrodes 141, and another portion of the second electrode 143 extends along the x-direction and covers the fourth dielectric layer 142 along the z-direction. Multiple capacitor structures 140 can be coupled via the portion of the second electrode 143 extending along the x-direction. The portion of the second electrode 143 extending along the x-direction connects multiple capacitor structures 140 in series, and the portion of the second electrode 143 extending along the x-direction can be used to be grounded or applied with other voltages (such as vdd / 2). The first electrode 141 may include a first connection layer and a conductive pillar. The first connection layer surrounds the conductive pillar and is located between the conductive pillar and the fourth dielectric layer 142. The first connection layer is used to increase the adhesion between the fourth dielectric layer 142 and the conductive pillar.

[0114] The capacitor structure 140 may be preceded by Figure 20 The structure shown in FIG. 1 may also be formed before the semiconductor layer 111 is formed, or a portion of the capacitor structure 140 such as the first electrode 141 is formed first, and a capacitor 140 is formed at one end of the first electrode 141. Figures 3 to 5 ,or Figure 20 The transistor 110 structure shown in FIG is further formed into a second electrode 143 .

[0115] In some embodiments, reference Figure 6 and Figure 23 As shown, the method for forming the first semiconductor structure 101 further includes: forming a bit line 114 on a side of the semiconductor layer 111 close to the second end, wherein the bit line 114 is coupled to the second end.

[0116] In some embodiments, reference Figure 7 and Figure 23As shown, the method of manufacturing the semiconductor device 100 further includes bonding the second semiconductor structure 102 to the bit line 114 away from the semiconductor layer 111. The second semiconductor structure 102 includes the peripheral circuit 150.

[0117] Before the bonding, the to-be-bonded surfaces of the first semiconductor structure 101 and the second semiconductor structure 102 have first bonding contacts and second bonding contacts, respectively, for leading electrical signals of the semiconductor structures to the to-be-bonded surfaces. The bonding contacts 115 can include pads, conductive plugs, or the like. The to-be-bonded surfaces of the first semiconductor structure 101 and the second semiconductor structure 102 are bonded, and the interface where the two to-be-bonded surfaces contact is a bonding interface. The first bonding contacts and the second bonding contacts contact and bond at the bonding interface, achieving electrical signal interconnection between the first semiconductor structure 101 and the second semiconductor structure 102. After the bonding, the first bonding contacts and the second bonding contacts can have no physical boundary and can be regarded as the bonding contacts 115 in the figure, which penetrate the bonding interface. Taking the gate layer 112, the bit line 114, and the second electrode 143 as examples, the gate layer 112, the bit line 114, and the second electrode 143 can be coupled to the peripheral circuit 150 through contact structures for leading electrical signals to the bonding contacts 115.

[0118] According to some aspects of embodiments of the present disclosure, a memory system is provided, including a memory device including a semiconductor device; and a memory controller coupled with the memory device and controlling the memory device.

[0119] The semiconductor device of embodiments of the present disclosure can be as shown in Figures 3 to 7 、 Figure 20 、 Figure 22 and Figure 23 As shown, the semiconductor device can be used as a DRAM, or at least as part of a DRAM. Alternatively, referring to Figure 24 As shown, the semiconductor device can be used as a DRAM, or at least as part of a DRAM. Alternatively, referring to

[0120] As shown, the semiconductor device can be used as a DRAM, or at least as part of a DRAM. Alternatively, referring to Figure 24 As shown, the semiconductor device can be used as a DRAM, or at least as part of a DRAM. Alternatively, referring to Figure 24As shown in FIG. 1, the system 200 can include a host 208 and a memory system 202 having one or more memory devices 204 and a memory controller 206. The host 208 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 208 can be configured to send or receive data to or from the memory device 204.

[0121] According to some embodiments, the memory controller 206 is coupled to the memory device 204 and the host 208, and is configured to control the memory device 204 to perform a read, a write, or a refresh. The memory controller 206 can manage data stored in the memory device 204 and communicate with the host 208. The memory device 204 includes a DRAM, or a package structure of multiple DRAM stacks, such as an HBM or an HMC package structure. The memory system 202 can serve as a memory of the host 208 in the system 200 or a buffer of the system 200. In some specific examples, the memory system 202 can be used in a solid state disk, which can improve the read / write performance of the solid state disk. Currently, high-end solid state disk products often select embedded DRAM to improve the performance of the products and improve the random read / write speed. For example, when writing a file, especially a small file, the small file is processed by the DRAM before being stored in the Flash, so that the solid state disk has higher storage efficiency and faster speed. The Flash includes a non-volatile memory, including but not limited to a 2D NAND memory or a 3D NAND memory.

[0122] In some other embodiments, referring to FIG. 2, Figure 25 As shown in FIG. 2, the system 200 can include only the host 208 and the memory device 204 coupled thereto, and a controller for controlling the memory device 204 can be located inside the host 208, such as a memory controller integrated in a central processing unit (CPU) or a south bridge or north bridge chip of a mainboard of the system 200. The memory device 204 can include, but is not limited to, a double data rate synchronous dynamic random access memory of a DDR4 memory specification, a DDR5 memory specification, a low power double data rate synchronous dynamic random access memory of an LPDDR5 memory specification.

[0123] In some embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-targeted manner. The device embodiments described above are merely illustrative, for example, the division of the units is merely a logical functional division, and actual implementation can have another division manner, for example, multiple units or components can be combined, or can be integrated into another system, or some features can be omitted or not executed. In addition, the direct coupling or indirect coupling between the various components shown or discussed. The disclosed methods in several method embodiments provided in the present disclosure can be combined arbitrarily to obtain new method embodiments without conflict.

[0124] The above merely illustrates the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized by, The first semiconductor structure comprises: A transistor comprises a semiconductor layer extending along a first direction and a gate layer extending along a second direction; the semiconductor layer has a first end and a second end oppositely arranged along the first direction, and an intermediate region between the first end and the second end; The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer arranged adjacently along a third direction, and the gate layer comprises a first gate layer and a second gate layer arranged adjacently along the third direction; the first gate layer and the second gate layer are located between the first semiconductor layer and the second semiconductor layer; the third direction intersects the second direction, and a plane formed by the third direction and the second direction intersects the first direction; The first end of the first semiconductor layer and the first end of the second semiconductor layer have a first distance along the third direction, and the intermediate region of the first semiconductor layer and the intermediate region of the second semiconductor layer have a second distance along the third direction; the first distance is greater than the second distance.

2. The semiconductor device according to claim 1, wherein The first semiconductor structure further comprises: A wall structure extending along the second direction; the semiconductor layer is located on two sides of the wall structure oppositely arranged along the third direction.

3. The semiconductor device of claim 2, wherein, The first semiconductor structure further comprises: A first dielectric layer located between the wall structure and the semiconductor layer; The wall structure comprises: A second dielectric layer, a conductive layer and a third dielectric layer stacked along the first direction, the second dielectric layer is located on a side of the conductive layer close to the first end along the first direction; wherein the size of the second dielectric layer in the third direction is smaller than the size of the conductive layer in the third direction.

4. The semiconductor device according to claim 3, wherein The second end of the first semiconductor layer and the second end of the second semiconductor layer have a third distance along the third direction, and the third distance is greater than the second distance.

5. The semiconductor device of claim 4, wherein, The size of the third dielectric layer in the third direction is smaller than the size of the conductive layer in the third direction.

6. The semiconductor device of claim 2, wherein The semiconductor layer surrounds two sides of the wall structure oppositely arranged along the third direction, and surrounds a side surface of the wall structure along the first direction; the semiconductor layer comprises two first ends, the first ends expose another side surface of the wall structure along the first direction; the semiconductor layer provides a channel for two transistors arranged adjacently along the third direction.

7. The semiconductor device of claim 6, wherein The first end comprises a protrusion extending away from the wall structure.

8. The semiconductor device of claim 1, wherein The composition of the semiconductor layer comprises indium gallium zinc oxide (IGZO).

9. The semiconductor device of claim 1, wherein, The first semiconductor structure further comprises: A gate dielectric layer located between the semiconductor layer and the gate layer.

10. The semiconductor device of claim 1, wherein The first semiconductor structure further comprises: A capacitor structure located on a side of the semiconductor layer close to the first end and coupled with the first end.

11. The semiconductor device of claim 10, wherein, The capacitor structure comprises: A first electrode, a fourth dielectric layer and a second electrode, the fourth dielectric layer is located between the first electrode and the second electrode; wherein the first electrode is coupled with the first end; a plurality of capacitor structures are coupled through the second electrode.

12. The semiconductor device of claim 11, wherein, The first electrode extends along the first direction, and the first electrode comprises an air gap.

13. The semiconductor device of claim 1, wherein The first semiconductor structure further comprises: a bit line located on a side of the semiconductor layer close to the second end and coupled with the second end.

14. The semiconductor device of claim 13, wherein, The semiconductor device further comprises a second semiconductor structure located on a side of the bit line away from the semiconductor layer; the second semiconductor structure comprises a peripheral circuit, and the second semiconductor structure is bonded with the first semiconductor structure.

15. A semiconductor device, characterized by comprising: Comprise: a semiconductor layer extending at least along a first direction; the semiconductor layer has a first end and a second end oppositely arranged along the first direction; a wall structure extending along a second direction; the semiconductor layer is located on two sides of the wall structure oppositely arranged along a third direction; the third direction intersects the second direction, and a plane formed by the third direction and the second direction intersects the first direction; a first dielectric layer located between the wall structure and the semiconductor layer; wherein the wall structure comprises a second dielectric layer, a conductive layer and a third dielectric layer stacked along the first direction, the second dielectric layer is located on a side of the conductive layer close to the first end along the first direction; the size of the second dielectric layer in the third direction is smaller than the size of the conductive layer in the third direction.

16. The semiconductor device of claim 15, wherein, The size of the third dielectric layer in the third direction is smaller than the size of the conductive layer in the third direction.

17. The semiconductor device of claim 15, wherein, The semiconductor layer surrounds two sides of the wall structure oppositely arranged along the third direction, and surrounds a side surface of the wall structure along the first direction; the semiconductor layer comprises two first ends, and the first ends expose another side surface of the wall structure along the first direction.

18. The semiconductor device of claim 17, wherein, The first end comprises a protrusion extending away from the wall structure.

19. The semiconductor device of claim 15, wherein, The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer arranged adjacent in the third direction, and the semiconductor device further comprises: a gate layer extending along the second direction and located on two sides of the wall structure oppositely arranged along the third direction; the gate layer comprises a first gate layer and a second gate layer arranged adjacent in the third direction; the first gate layer and the second gate layer are located between the first semiconductor layer and the second semiconductor layer; and a gate dielectric layer located between the semiconductor layer and the gate layer.

20. The semiconductor device of claim 14, wherein, The semiconductor device further comprises: a capacitor structure located on a side of the semiconductor layer close to the first end and coupled with the first end.

21. The semiconductor device of claim 20, wherein, The capacitor structure comprises: a first electrode, a fourth dielectric layer and a second electrode, the fourth dielectric layer is located between the first electrode and the second electrode; wherein the first electrode is coupled with the first end; a plurality of capacitor structures are coupled through the second electrode.

22. The semiconductor device of claim 21, wherein, The first electrode extends along the first direction, and the first electrode comprises an air gap.

23. The semiconductor device of claim 15, wherein, The semiconductor device further comprises: a bit line located on a side of the semiconductor layer close to the second end and coupled with the second end.

24. The semiconductor device of claim 23, wherein, The wall structure, the semiconductor layer and the bit line are located in a first semiconductor structure; the semiconductor device further comprises: A second semiconductor structure is located on a side of the bit line away from the semiconductor layer; the second semiconductor structure comprises a peripheral circuit, and the second semiconductor structure is bonded to the first semiconductor structure.

25. A method of fabricating a semiconductor device, comprising: The first semiconductor structure is formed, and a method for forming the first semiconductor structure comprises: A first dielectric material layer, a first conductive material layer, and a second dielectric material layer are formed in a stacked manner along a first direction; A first trench is formed through the second dielectric material layer, the first conductive material layer, and at least part of the thickness of the first dielectric material layer, and the first trench extends along a second direction; Part of the first dielectric material layer at the bottom of the first trench is removed to form a first opening with an opening direction towards a third direction, so as to form a wall structure; wherein the size of the remaining first dielectric material layer in the third direction is smaller than the size of the first conductive material layer in the third direction; the third direction intersects the second direction, and the plane formed by the third direction and the second direction intersects the first direction; A first dielectric layer and a semiconductor layer are formed on both sides of the wall structure along the third direction, and the first dielectric layer is located between the wall structure and the semiconductor layer; wherein the semiconductor layer has a first end and a second end oppositely arranged along the third direction, part of the first dielectric layer is located on the inner wall of the first opening, and part of the first end is located on the inner wall of the first opening.

26. The method of manufacturing according to claim 25, wherein, The method for forming the wall structure further comprises: Part of the second dielectric material layer at the opening end of the first trench is removed to form a second opening with an opening direction towards the third direction; wherein the size of the remaining second dielectric material layer in the third direction is smaller than the size of the first conductive material layer in the third direction; part of the first dielectric layer is located on the inner wall of the second opening, and part of the second end is located on the inner wall of the second opening.

27. The method of manufacturing according to claim 25, wherein, The method for forming the semiconductor layer comprises: A first dielectric layer is formed on both sides of the first trench along the third direction; A semiconductor material layer is formed to cover the first dielectric layer along the third direction and cover the bottom of the first trench along the first direction; The semiconductor material layer is etched through the bottom of the first trench along the first direction to form the semiconductor layer, and the first end is located at the bottom of the first trench.

28. The method of manufacturing according to claim 27, wherein, The semiconductor material layer also covers the remaining second dielectric material layer along the first direction.

29. The method of manufacturing according to claim 27, wherein, The method for forming the semiconductor layer further comprises: When etching through the semiconductor material layer, a remaining part of the semiconductor material layer forms a protrusion; wherein the protrusion extends in a direction away from the wall structure.

30. The method of manufacturing of claim 27, wherein, The method for forming the semiconductor layer further comprises: A second trench is formed through the semiconductor material layer along the first direction, and the second trench extends along the third direction.

31. The method of manufacturing according to claim 27, wherein, The method for forming the first semiconductor structure further comprises: A gate dielectric layer and a second conductive material layer are formed to cover at least the semiconductor layer along the third direction and cover the bottom of the first trench along the first direction; The first conductive material layer is formed along the first direction at least through the second conductive material layer to form a gate layer.

32. The method of manufacturing of claim 25, wherein, The method of forming the first semiconductor structure further comprises: forming a capacitor structure on a side of the semiconductor layer close to the first end, an electrode of the capacitor structure close to the first end being coupled to the first end.

33. The method of manufacturing of claim 25, wherein, The method of forming the first semiconductor structure further comprises: forming a bit line on a side of the semiconductor layer close to the second end, the bit line being coupled to the second end.

34. The method of manufacturing according to claim 33, wherein, The method of forming the semiconductor device further comprises: bonding a second semiconductor structure on a side of the bit line away from the semiconductor layer, the second semiconductor structure comprising a peripheral circuit.

Images