Semiconductor device, manufacturing method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof, and a memory system, and the method comprises the steps: forming a semiconductor body which extends in a first direction; forming a conductive structure; the conductive structure is located on one side of the semiconductor body along the first direction; the semiconductor body and the conductive structure are used for forming a semiconductor structure; wherein the conductive structure comprises a first part and a second part which are arranged along the second direction, the first part is in contact with one end of the semiconductor main body, and the size of the part, close to the second part, of the first part in the third direction is different from the size of the part, close to the first part, of the second part in the third direction; the second direction intersects with the third direction, and the first direction is perpendicular to a plane formed by the second direction and the third direction.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof, and a storage system. BACKGROUND

[0002] Semiconductor devices, such as dynamic random access memory (DRAM), are one of the most important access components in electronic systems, and usually adopt a transistor (T) and a capacitor (C) to form a 1T1C structure as a memory cell. Such a 1T1C structure makes the dynamic random access memory have a high integration degree and a low cost, and has an irreplaceable position in computer access devices. With the rapid development of semiconductor technology, dynamic random access memory is rapidly developing towards high density and high quality. SUMMARY

[0003] According to an aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor structure; the semiconductor structure comprising a semiconductor body extending along a first direction; and a conductive structure located at one side of the semiconductor body along the first direction; wherein the conductive structure comprises a first part and a second part arranged along a second direction, the first part being in contact with one end of the semiconductor body, and a part of the first part close to the second part has a different dimension in a third direction from a part of the second part close to the first part; the second direction intersects the third direction, and the first direction is perpendicular to a plane formed by the second direction and the third direction.

[0004] In some embodiments, the part of the first part close to the second part has a first dimension in the third direction; the part of the second part close to the first part has a second dimension in the third direction; and the second dimension is greater than the first dimension.

[0005] In some embodiments, a cross-sectional shape of the first part on the plane comprises a square; and a cross-sectional shape of the second part on the plane comprises an axisymmetric figure containing an arc edge.

[0006] In some embodiments, a distance between a surface of the first part away from the second part in the second direction and a surface of the semiconductor body away from the second part in the second direction is less than a preset value.

[0007] In some embodiments, the semiconductor structure further comprises: a gate structure located on a side of the semiconductor body close to the second portion in the second direction; wherein the gate structure is spaced apart from a surface of the second portion close to the gate structure in the first direction.

[0008] In some embodiments, the semiconductor structure further comprises: a first isolation structure located on a side of the semiconductor body away from the second portion in the second direction; and a second isolation structure located on a side of the gate structure away from the semiconductor body in the second direction, and the second isolation structure contacts a surface of the second portion away from the first portion, a surface of the second portion close to the gate structure in the first direction, and a surface of the gate structure close to the second portion in the first direction.

[0009] In some embodiments, the second isolation structure comprises a first sub-structure and a second sub-structure arranged in the first direction; wherein the first sub-structure is located on a side of the gate structure away from the semiconductor body in the second direction; and the second sub-structure is located on a side of the second portion away from the first portion, and between a surface of the gate structure close to the second portion in the first direction and a surface of the second portion close to the gate structure in the first direction.

[0010] In some embodiments, the second isolation structure comprises a first sub-structure, a third sub-structure, and a fourth sub-structure arranged in the first direction; wherein the first sub-structure is located on a side of the gate structure away from the semiconductor body in the second direction; the third sub-structure is located between a surface of the gate structure close to the second portion in the first direction and a surface of the second portion close to the gate structure in the first direction; and the fourth sub-structure is located on a side of the second portion away from the first portion.

[0011] In some embodiments, a material of the third sub-structure is different from a material of the fourth sub-structure.

[0012] In some embodiments, a dimension of the second portion in the second direction is smaller than a dimension of the third sub-structure in the second direction.

[0013] In some embodiments, a side of the second portion away from the first portion in the second direction is a straight line extending in the third direction.

[0014] In some embodiments, the conductive structure is located between the first isolation structure and the fourth sub-structure, and the conductive structure contacts a side of the third sub-structure away from the gate structure in the first direction.

[0015] In some embodiments, the first isolation structure includes a first end surface and a second end surface opposite to each other along the first direction, and the second isolation structure includes a third end surface and a fourth end surface opposite to each other along the first direction; the first end surface, the third end surface, the surface of the semiconductor body away from the first portion along the first direction, and the surface of the semiconductor body away from the second portion along the first direction are aligned along the second direction.

[0016] In some embodiments, the conductive structure includes a polysilicon layer, a metal silicide layer and a conductive metal layer stacked along the first direction; or, the conductive structure includes a polysilicon layer and a metal silicide layer stacked along the first direction; or, the conductive structure includes a metal silicide layer in contact with the semiconductor body.

[0017] In some embodiments, the semiconductor body includes a channel region, and a source and a drain respectively located on two sides of the channel region along the first direction.

[0018] In some embodiments, the semiconductor structure further includes a capacitor structure; the capacitor structure is connected to one end of the conductive structure away from the semiconductor body along the first direction.

[0019] In some embodiments, the capacitor structure includes a fifth end surface and a sixth end surface opposite to each other along the first direction; at least part of the surface of the first portion away from the semiconductor body along the first direction and the surface of the second portion away from the semiconductor body along the first direction are in contact with the fifth end surface.

[0020] In some embodiments, the semiconductor device includes a plurality of semiconductor structures arranged in an array along the second direction and the third direction; wherein the plurality of semiconductor structures arranged along the second direction includes first semiconductor structures and second semiconductor structures arranged alternately; the first semiconductor structure and the second semiconductor structure arranged adjacently constitute a semiconductor structure group.

[0021] In some embodiments, the first semiconductor structure includes a first semiconductor body, a first gate structure and a first conductive structure; the second semiconductor structure includes a second semiconductor body, a second gate structure and a second conductive structure; the first gate structure is located at a side of the first semiconductor body close to the second semiconductor body, the second gate structure is located at a side of the second semiconductor body close to the first gate structure; a second part of the first conductive structure is located at a side of a first part of the first conductive structure close to the second conductive structure, a second part of the second conductive structure is located at a side of a first part of the second conductive structure close to the first conductive structure.

[0022] In some embodiments, the semiconductor device further includes: a plurality of bit lines extending along the second direction and spaced apart along the third direction, each of the bit lines is connected to an end of a row of the semiconductor bodies away from the conductive structure along the first direction.

[0023] Embodiments of the present disclosure further provide a semiconductor device, including: a plurality of semiconductor structures, each of the semiconductor structures includes a semiconductor body extending along a first direction, a conductive structure located at a side of the semiconductor body along the first direction, the semiconductor body and the conductive structure are used to form a semiconductor structure; wherein the conductive structure includes a first part and a second part arranged along a second direction, the first part is in contact with an end of the semiconductor body, a part of the first part close to the second part has a different size in a third direction from a part of the second part close to the first part; the second direction intersects the third direction, and the first direction is perpendicular to a plane formed by the second direction and the third direction.

[0024] Embodiments of the present disclosure further provide a manufacturing method of a semiconductor device, the method includes: forming a semiconductor body extending along a first direction; forming a conductive structure; the conductive structure is located at a side of the semiconductor body along the first direction; the semiconductor body and the conductive structure are used to form a semiconductor structure; wherein the conductive structure includes a first part and a second part arranged along a second direction, the first part is in contact with an end of the semiconductor body, a part of the first part close to the second part has a different size in a third direction from a part of the second part close to the first part; the second direction intersects the third direction, and the first direction is perpendicular to a plane formed by the second direction and the third direction.

[0025] In some embodiments, the forming the semiconductor body extending along the first direction comprises: forming a plurality of first recesses extending along a second direction and spaced along a third direction, and a plurality of second recesses and a plurality of third recesses extending along the third direction and alternately spaced along the second direction in the semiconductor layer to form a plurality of semiconductor pillars extending along the first direction; the semiconductor pillars are used to form the semiconductor body; forming a first isolation structure in the second recesses; forming a gate material layer in the third recesses, the gate material layer covers part of surfaces of the semiconductor pillars and covers exposed bottom surfaces of the semiconductor layer; and forming a first sub-structure on a side of the gate material layer away from the semiconductor pillars along the second direction. In some embodiments, the method further comprises: filling a first dielectric layer in the third recesses; the first dielectric layer covers remaining surfaces of the semiconductor pillars and covers surfaces of the gate material layer and the first sub-structure away from the bottom surfaces of the semiconductor layer along the first direction.

[0026] In some embodiments, the method further comprises: removing part of the semiconductor pillars to form fourth recesses; remaining semiconductor pillars have a dimension along the first direction greater than a dimension of the gate material layer along the first direction.

[0027] In some embodiments, the method further comprises: removing part of the first dielectric layer to form fifth recesses having arc-shaped edges; wherein the remaining first dielectric layer constitutes a second sub-structure; the first sub-structure and the second sub-structure constitute a second isolation structure.

[0028] In some embodiments, the forming the conductive structure comprises: forming a first part of the conductive structure in the fourth recesses, and forming a second part of the conductive structure in the fifth recesses; the first part is in contact with one end of the remaining semiconductor pillars.

[0029] In some embodiments, the forming the conductive structure in the fourth recesses and the fifth recesses comprises: forming a polysilicon layer in the fourth recesses and the fifth recesses; the polysilicon layer is in contact with one end of the remaining semiconductor pillars; forming a metal silicide layer on a side of the polysilicon layer away from the remaining semiconductor pillars; forming a conductive metal layer on a side of the metal silicide layer away from the polysilicon layer.

[0030] In some embodiments, the forming the conductive structure in the fourth recesses and the fifth recesses comprises: forming a polysilicon layer in the fourth recesses and the fifth recesses; the polysilicon layer is in contact with one end of the remaining semiconductor pillars; forming a metal silicide layer on a side of the polysilicon layer away from the remaining semiconductor pillars.

[0031] In some embodiments, the forming the conductive structure in the fourth recess and the fifth recess comprises: forming a polysilicon layer in the fourth recess and the fifth recess; and performing a metallization process on the polysilicon layer to obtain a metal silicide to form the conductive structure. In some embodiments, the method further comprises: forming a second dielectric layer in the third recess; the second dielectric layer covers a remaining surface of the semiconductor pillar, and covers surfaces of the gate material layer and the first sub-structure away from the bottom surface of the semiconductor layer along the first direction; and forming a fourth sub-structure on a side of the second dielectric layer away from the semiconductor pillar along the second direction.

[0032] In some embodiments, the method further comprises: removing part of the semiconductor pillar to form a sixth recess; a remaining portion of the semiconductor pillar has a dimension along the first direction greater than a dimension of the gate material layer along the first direction.

[0033] In some embodiments, the method further comprises: removing part of the second dielectric layer to form a seventh recess having an arc-shaped side; wherein a remaining portion of the second dielectric layer constitutes a third sub-structure; the first sub-structure, the third sub-structure, and the fourth sub-structure constitute a second isolation structure. In some embodiments, a material constituting the third sub-structure is different from a material constituting the fourth sub-structure.

[0034] In some embodiments, a dimension of the second portion along the second direction is less than a dimension of the third sub-structure along the second direction.

[0035] In some embodiments, a side of the second portion away from the first portion along the second direction is a straight line extending along the third direction.

[0036] In some embodiments, the forming the conductive structure comprises: forming a first portion of the conductive structure in the sixth recess, and forming a second portion of the conductive structure in the seventh recess; the first portion is in contact with an end of the remaining semiconductor pillar.

[0037] In some embodiments, the removing process comprises a wet etching process.

[0038] In some embodiments, the first isolation structure comprises a first end surface and a second end surface opposite to each other along the first direction, and the second isolation structure comprises a third end surface and a fourth end surface opposite to each other along the first direction; the first end surface, the third end surface, a surface of the first portion away from the semiconductor body along the first direction, and a surface of the second portion away from the gate structure along the first direction are aligned along the second direction.

[0039] In some embodiments, a dimension of a portion of the first portion proximate to the second portion in the third direction is a first dimension; a dimension of a portion of the second portion proximate to the first portion in the third direction is a second dimension; the second dimension is greater than the first dimension.

[0040] In some embodiments, the method further comprises: removing the gate material layer covering the bottom surface of the semiconductor layer to form a gate structure.

[0041] In some embodiments, the method further comprises: forming a capacitor structure connected to the conductive structure along the first direction away from one end of the semiconductor body.

[0042] In some embodiments, the method further comprises: doping a first end portion of the remaining semiconductor pillar along the first direction away from the bottom surface of the semiconductor layer to form one of a source or a drain before forming the capacitor structure; thinning the semiconductor layer to expose a second end portion of the remaining semiconductor pillar along the first direction opposite to the first end portion after forming the capacitor structure; and doping the second end portion to form the other of the source or the drain; wherein a region of the remaining semiconductor pillar between the source and the drain constitutes a channel region; the channel region, the source, and the drain constitute the semiconductor body.

[0043] In some embodiments, the capacitor structure comprises a fifth end surface and a sixth end surface opposite along the first direction; at least part of a surface of the first portion away from the semiconductor body along the first direction and a surface of the second portion away from the semiconductor body along the first direction are in contact with the fifth end surface.

[0044] In some embodiments, the method further comprises: forming a plurality of the semiconductor structures arranged in an array along the second direction and the third direction; wherein a plurality of the semiconductor structures arranged along the second direction comprises first semiconductor structures and second semiconductor structures arranged alternately; the first semiconductor structure and the second semiconductor structure arranged adjacently constitute a semiconductor structure group.

[0045] In some embodiments, the forming a plurality of the semiconductor structures arranged in an array along the second direction and the third direction comprises: forming a first gate structure on a side of a first semiconductor body proximate to a second semiconductor body, and forming a first conductive structure on a side of the first semiconductor body along the first direction to form the first semiconductor structure; and forming a second gate structure on a side of the second semiconductor body proximate to the first gate structure, and forming a second conductive structure on a side of the second semiconductor body along the first direction to form the second semiconductor structure.

[0046] In some embodiments, the method further comprises forming a plurality of bit lines extending along the second direction and spaced apart along the third direction, each of the bit lines being connected to one end of a row of the semiconductor bodies along the first direction away from the conductive structure.

[0047] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and a storage system. The manufacturing method of the semiconductor device comprises forming a semiconductor body extending along a first direction; forming a conductive structure; the conductive structure is located on one side of the semiconductor body along the first direction; the semiconductor body and the conductive structure are used to form a semiconductor structure; wherein the conductive structure comprises a first part and a second part arranged along a second direction, the first part is in contact with one end of the semiconductor body, and the size of the part of the first part close to the second part in a third direction is different from the size of the part of the second part close to the first part in the third direction; the second direction intersects the third direction, and the first direction is perpendicular to the plane formed by the second direction and the third direction. In the embodiments of the present disclosure, by forming the conductive structure connected with the semiconductor body on one side of the semiconductor body along the first direction, the self-alignment of the conductive structure and the semiconductor body can be realized, so that the alignment accuracy of the first part of the conductive structure and the semiconductor body can be increased, the alignment difficulty of the two is reduced, the reliability of the semiconductor device is improved, the manufacturing time and cost are saved, and the process speed and efficiency are improved. On the other hand, the conductive structure comprises the first part connected with the semiconductor body and the second part arranged in parallel with the first part along the second direction, so that the volume / surface area of the conductive structure can be increased, and then the contact area of the conductive structure and other external structures (such as a capacitor structure) can be increased, and the reliability of the semiconductor device is improved. On the other hand, the size of the part of the first part close to the second part in the third direction is different from the size of the part of the second part close to the first part in the third direction, so that the structure layout of the conductive structure and the semiconductor body can be more matched and reasonable. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 A structure schematic diagram of a dynamic random access memory provided by the embodiments of the present disclosure;

[0049] Figures 2a-2d A manufacturing process schematic diagram of a conductive structure provided by the embodiments of the present disclosure;

[0050] Figure 3 A manufacturing method flowchart of a semiconductor device provided by the embodiments of the present disclosure;

[0051] Figures 4a-4b A structure schematic diagram of forming a first groove provided by the embodiments of the present disclosure;

[0052] Figures 5a-5b A structure diagram for forming a first isolation structure is provided for an embodiment of the present disclosure.

[0053] Figure 6 A structure diagram for forming an insulating material layer is provided for an embodiment of the present disclosure.

[0054] Figure 7 A structure diagram for forming a gate material layer is provided for an embodiment of the present disclosure.

[0055] Figure 8 A structure diagram for forming a first dielectric layer is provided for an embodiment of the present disclosure.

[0056] Figures 9a-9b A structure diagram for forming a fourth recess is provided for an embodiment of the present disclosure.

[0057] Figures 10a-10b A structure diagram for forming a fifth recess is provided for an embodiment of the present disclosure.

[0058] Figures 11a-11b A structure diagram for forming a conductive structure is provided for an embodiment of the present disclosure.

[0059] Figures 12a-12b A structure diagram for forming a fourth sub-structure is provided for an embodiment of the present disclosure.

[0060] Figures 13a-13b A structure diagram for forming a sixth recess is provided for an embodiment of the present disclosure.

[0061] Figures 14a-14b A structure diagram for forming a seventh recess is provided for an embodiment of the present disclosure.

[0062] Figures 15a-15b Another structure diagram for forming a conductive structure is provided for an embodiment of the present disclosure.

[0063] Figure 16 A structure diagram for forming a semiconductor body is provided for an embodiment of the present disclosure.

[0064] Figure 17 A structure diagram for a semiconductor structure group is shown for an embodiment of the present disclosure.

[0065] Figure 18 A structure diagram for forming a capacitor structure is provided for an embodiment of the present disclosure.

[0066] Figure 19 A structure diagram for a semiconductor device is provided for an embodiment of the present disclosure.

[0067] In the drawings, which are not necessarily drawn to scale, like numerals describe similar components throughout the several views. Like numerals having different letter suffixes can represent different instances of the components. The drawings illustrate generally, by way of example, various embodiments discussed herein. DETAILED DESCRIPTION

[0068] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. While example embodiments of the present disclosure are described herein, the present disclosure can be embodied in various forms without being limited to specific described embodiments. Rather, these embodiments are provided as examples of implementing the present disclosure, with the understanding that the scope of the disclosure is to be given the broadest interpretation in accordance with the appended claims.

[0069] In the following description, numerous specific details are given to provide a thorough understanding of the present disclosure. However, it will be apparent that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known structures and techniques have not been described in order to avoid obscuring the understanding of this description. In the following description, numerous specific details are presented to provide a thorough understanding of the present disclosure. One skilled in the relevant art, however, will recognize that the present disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. Some features have not been described in detail because they can be apparent to one skilled in the art, or can not be necessary for an understanding of the present disclosure.

[0070] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0071] It is to be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described herein is turned over, then a relative prefi x term such as "below" can be interpreted as "above" or "up". The spatially relative terms can be interpreted differently depending on the particular orientation of the device. Thus, the examples described herein should be understood not to be limited to the following described orientations, but are to be interpreted as a broader description of the application, in suitable form. The application or devices shown in the figures can be manufactured, used, or shipped in a number of positions and orientations. For example, the device can be inverted or rotated about 90-degrees (or another suitable angle). Accordingly, the spatially relative terms can, as appropriate, mean both the absolute directions as well as the reverse directions.

[0072] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of associated items.

[0073] In order to enable a person skilled in the art to more fully understand the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present disclosure.

[0074] The semiconductor device related to the embodiments of the present disclosure is at least a part of a subsequent process to form a final device structure. Here, the final device can include a memory, which includes but is not limited to a dynamic random access memory, which will be described below only as an example. However, it should be noted that the description of the dynamic random access memory in the following embodiments is only used to illustrate the present disclosure and does not limit the scope of the present disclosure.

[0075] With the development of dynamic random access memory technology, the size of the storage unit is getting smaller and smaller, and its array architecture is from 8F 2 to 6F 2 to 4F 2 ; in addition, based on the requirements of dynamic random access memory for ion and leakage current, the architecture of the memory is from planar array transistor to recess gate array transistor, from recess gate array transistor to buried channel array transistor, and from buried channel array transistor to vertical channel array transistor.

[0076] In some embodiments of the present disclosure, whether it is a planar transistor or a buried transistor, the dynamic random access memory is composed of a plurality of storage units, each of which is composed of a transistor and a capacitor controlled by the transistor, that is, the dynamic random access memory includes a 1 transistor and 1 capacitor (1T1C) architecture; its main principle of action is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0077] The following detailed description Figure 1 One architecture of dynamic random access memory is described in detail. Before introducing Figure 1 The semiconductor device is shown before defining the directions that can be used in the following description. The extension direction of the semiconductor body is defined as the first direction (i.e., the Z direction). The intersecting second direction (i.e., the X direction) and the third direction (i.e., the Y direction) are defined in the plane perpendicular to the Z direction. In some embodiments, the X direction, the Y direction, and the Z direction can be perpendicular to each other in pairs.

[0078] Reference is made to Figure 1 , Figure 1 A cross-sectional view of a three-dimensional (3D) dynamic random access memory 100 including vertical transistors is provided in embodiments of the present disclosure; as shown in Figure 1 The dynamic random access memory 100 includes a first device 102 and a second device 104 stacked on the first device 102 along the Z-axis direction, and the first device 102 and the second device 104 are connected through a bonding interface 106; the first device 102 and the second device 104 can be connected through hybrid bonding or the like. In some embodiments, the second device 104 can be bonded on the top of the first device 102 in a face-to-face manner at the bonding interface 106.

[0079] The first device 102 can include a first substrate 1010, a peripheral circuit 1012 located on one side of the first substrate 1010, and a first interconnection layer 1016 located on the side of the peripheral circuit 1012 away from the first substrate 1010, the first interconnection layer 1016 being used to transmit electrical signals of the peripheral circuit 1012. The peripheral circuit 1012 can include a plurality of transistors 1014. In some embodiments, trench isolation (such as shallow trench isolation STI) and doped regions (such as the well, source, and drain of the transistors 1014) can also be formed on or in the first substrate 1010.

[0080] The first device 102 can also include a first bonding layer 1018 at the bonding interface 106 and on a side of the first interconnect layer 1016 away from the peripheral circuit 1012. The first bonding layer 1018 can include a plurality of first bonding contacts 1019 and a dielectric that electrically isolates the first bonding contacts 1019. The first bonding contacts 1019 and the surrounding dielectric in the first bonding layer 1018 can be used for hybrid bonding. Conversely, the second device 104 can also include a second bonding layer 1020 at the bonding interface 106 and on a side of the first bonding layer 1018 away from the first interconnect layer 1016. The second bonding layer 1020 can include a plurality of second bonding contacts 1021 and a dielectric that electrically isolates the second bonding contacts 1021. The second bonding contacts 1021 and the surrounding dielectric in the second bonding layer 1020 can be used for hybrid bonding. Here, the second bonding contacts 1021 contact the first bonding contacts 1019 at the bonding interface 106.

[0081] In some embodiments, the peripheral circuit 1012 can also include word lines (WL) and word line drivers / row decoders in the second interconnect layer 1022 coupled to the first bonding contacts 1019 in the first bonding layer 1018 and the second bonding contacts 1021 in the second bonding layer 1020 and the first interconnect layer 1016. In other embodiments, the peripheral circuit 1012 can also include bit lines 1023 (BL) and bit line drivers / column decoders in the second interconnect layer 1022 coupled to the first bonding contacts 1019 in the first bonding layer 1018 and the second bonding contacts 1021 in the second bonding layer 1020 and the first interconnect layer 1016, where the second interconnect layer 1022 includes the bit lines 1023 above the second bonding layer 1020, the bit lines 1023 used to transmit electrical signals.

[0082] In other embodiments, the first device 102 and the second device 104 can be stacked and connected without bonding, but instead integrated on the same substrate (only the first substrate, not the second substrate) and connected directly through one or more interconnect layers between the first device 102 and the second device 104. In this case, the first bonding layer 1018 and the first bonding contacts 1019 are not present in the first device 102; the second bonding layer 1020 and the second bonding contacts 1019 are not present in the second device 104; and the bonding interface 106 between the first device 102 and the second device 104 is also not present.

[0083] References Figure 1The second device 104 also includes an array of memory cells 1024 on the second interconnect layer 1022, which can include a plurality of memory cells 1024, a second substrate 1048 on the memory cells 1024, and a third interconnect layer 1050 on the second substrate 1048. Figure 1 A cross-section of the dynamic random access memory 100 in the second interconnect layer 1022 extending laterally in the bit line direction (X-axis direction) can be taken, and a bit line 1023 in the second interconnect layer 1022 extending laterally in the X-axis direction can be coupled to a column of memory cells 1024.

[0084] Here, each memory cell 1024 can include a vertical transistor 1026 and a capacitor structure 1028 coupled to the vertical transistor 1026; the vertical transistor 1026 includes a semiconductor body 1030 extending vertically (in the Z-axis direction) and a gate structure 1036 in contact with one side of the semiconductor body 1030 in the bit line direction (X-axis direction); in other embodiments, the gate structure can also fully surround the semiconductor body, half-surround the semiconductor body, be located at two opposite sides of the semiconductor body, etc., which are not elaborated here. Here, the gate structure 1036 includes a gate electrode 1034 and a gate dielectric 1032 between the gate electrode 1034 and the semiconductor body 1030 in the bit line direction (X-axis direction). In some embodiments, the gate dielectric 1032 is adjacent to one side of the semiconductor body 1030, and the gate electrode 1034 is adjacent to the gate dielectric 1032.

[0085] In some embodiments, the semiconductor body 1030 has two ends (an upper end and a lower end) in the vertical direction (Z-axis direction), and one end (e.g., the lower end in the second interconnect layer 1022) extends beyond the gate dielectric 1032 into an interlayer dielectric (ILD) layer in the vertical direction (Z-axis direction), and the other end (e.g., the upper end in the second interconnect layer 1022) is flush with a corresponding end of the gate dielectric 1032. Figure 1 In some embodiments, the semiconductor body 1030 has two ends (an upper end and a lower end) in the vertical direction (Z-axis direction), and one end (e.g., the lower end in the second interconnect layer 1022) extends beyond the gate dielectric 1032 into an interlayer dielectric (ILD) layer in the vertical direction (Z-axis direction), and the other end (e.g., the upper end in the second interconnect layer 1022) is flush with a corresponding end of the gate dielectric 1032. Figure 1 In other embodiments, both ends (the upper end and the lower end) of the semiconductor body 1030 extend beyond the gate electrode 1034 into the ILD layer in the vertical direction (Z-axis direction). In other words, the semiconductor body 1030 can have a vertical dimension (e.g., a depth in the Z-axis direction) greater than a vertical dimension of the gate electrode 1034, and neither the upper end nor the lower end of the semiconductor body 1030 is flush with a corresponding end of the gate electrode 1034. In this way, short circuits between the bit line 1023 and the gate electrode 1034 or between the gate electrode 1034 and the capacitor structure 1028 can be avoided.

[0086] The vertical transistor 1026 can also include a source 1038 and a drain 1040 disposed at two end portions (upper end portion and lower end portion) of the semiconductor body 1030 in the vertical direction (Z-axis direction), respectively (the positions of the source and the drain can be exchanged, and hereinafter, the upper end portion is taken as the source 1038 and the lower end portion is taken as the drain 1040 as an example). In some embodiments, the source 1038 is coupled to the capacitive structure 1028, and the drain 1040 is coupled to the bit line 1023.

[0087] Since the gate electrode 1034 can be part of or extend in the word line direction as a word line, the second device 104 of the dynamic random access memory 100 can also include a plurality of word lines each extending in the word line direction (Y-axis direction). Here, each word line can be coupled to a row of the memory cells 1024.

[0088] The vertical transistor 1026 extends vertically through and contacts the word line, and the drain 1040 of the vertical transistor 1026 at its lower end portion contacts the bit line 1023. Thus, due to the vertical arrangement of the vertical transistor 1026, the word line and the bit line 1023 can be disposed in different planes in the vertical direction, which simplifies the wiring of the word line and the bit line 1023. Here, the vertical transistors 1026 can be arranged in a mirror-symmetrical manner to increase the density of the memory cells 1024 in the bit line direction (X-axis direction). Two adjacent vertical transistors 1026 in the bit line direction are mirror-symmetrical to each other with respect to the trench isolation 1060, that is, the second device 104 can include a plurality of trench isolations 1060 each extending in the word line direction (Y-axis direction) parallel to the word line and disposed between the semiconductor bodies 1030 of two adjacent rows of the vertical transistors 1026. In some embodiments, the rows of the vertical transistors 1026 separated by the trench isolation 1060 are mirror-symmetrical to each other with respect to the trench isolation 1060. It should be understood that the trench isolation 1060 can include air gaps each disposed laterally between adjacent semiconductor bodies 1030. The second device 104 also includes a plurality of gate isolations 1062 each extending in the word line direction (Y-axis direction) parallel to the word line and disposed between two adjacent rows of the word lines of the vertical transistors 1026. It should be understood that the dimensions of the gate isolation 1062 and the word line in the bit line direction (X-axis direction) can be the same as or different from the dimensions of the trench isolation 1060 in the bit line direction (X-axis direction); when the dimensions of the gate isolation 1062 and the word line in the bit line direction (X-axis direction) are different, the spacing between the plurality of semiconductor bodies 1030 arranged in the bit line direction (X-axis direction) is different, that is, the plurality of semiconductor bodies 1030 arranged in the bit line direction (X-axis direction) are non-uniformly arranged.

[0089] As Figure 1As shown, the capacitor structure 1028 can be a vertical capacitor. In some embodiments, a conductive structure 1064 is formed between the vertical transistor 1026 (further example, the source 1038) and the capacitor structure 1028 to reduce contact resistance.

[0090] like Figure 1 As shown, the second device 104 may further include a capacitor contact 1047 in contact with the common plate of the capacitor structure 1028 for coupling the capacitor structure 1028 to the peripheral circuit 1012 or directly to ground. In some embodiments, the ILD layer forming the capacitor structure 1028 has the same dielectric material as the two ILD layers into which the semiconductor body 1030 extends, such as silicon oxide. The configuration of the capacitor structure 1028 may include any suitable structure and configuration, such as a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor.

[0091] like Figure 1 As shown, vertical transistor 1026 extends vertically through and contacts the word line, a drain 1040 at a lower end of vertical transistor 1026 contacts bit line 1023, and a source 1038 at an upper end of vertical transistor 1026 contacts capacitor structure 1028. That is, due to the vertical arrangement of vertical transistor 1026, bit line 1023 and capacitor structure 1028 can be arranged in different planes in the vertical direction and vertically coupled to opposite ends of vertical transistor 1026 of memory cell 1024. In some embodiments, bit line 1023 and capacitor structure 1028 are arranged on opposite sides of vertical transistor 1026 in the vertical direction, simplifying the routing of bit line 1023 and reducing the coupling capacitance between bit line 1023 and capacitor structure 1028 compared to conventional memory cells in which the bit line and capacitor structure are arranged on the same side of a planar transistor.

[0092] In some embodiments, the vertical transistor 1026 is vertically disposed between the capacitor structure 1028 and the bonding interface 106. That is, the vertical transistor 1026 can be arranged closer to the peripheral circuit 1012 / bonding interface 106 of the first device 102 than the capacitor structure 1028. Since the bit line 1023 and the capacitor structure 1028 are coupled to opposite ends of the vertical transistor 1026, the bit line 1023 (as part of the second interconnect layer 1022) is vertically disposed between the vertical transistor 1026 and the bonding interface 106 to reduce interconnect routing distance and complexity.

[0093] In some embodiments, the second device 104 further includes a second substrate 1048 disposed above the memory cell 1024, and a pad-out third interconnect layer 1050 above the memory cell 1024. The pad-out third interconnect layer 1050 may include interconnects in one or more ILD layers, such as contact pads 1054.

[0094] In some embodiments, the second device 104 further includes one or more contacts 1052, which extend through the pads to lead out of the third interconnect layer 1050 and the second substrate 1048, so as to lead out of the third interconnect layer 1050 through the pads and couple to the memory cell 1024 and the second interconnect layer 1022. In this way, the peripheral circuit 1012 can be coupled to the memory cell 1024 through the first interconnect layer 1016 and the second interconnect layer 1022 and the second bonding layer 1020 and the first bonding layer 1018, and the peripheral circuit 1012 and the memory cell 1024 can be led out to the third interconnect layer 1050 through the contacts 1052 and the pads and coupled to the external circuit.

[0095] As mentioned above, in order to reduce the contact resistance between the source 1038 and the capacitor structure 1028, a conductive structure 1064 is provided between the source 1038 and the capacitor structure 1028. The present disclosure provides a method for manufacturing the conductive structure 1064. Figure 2a-2d .

[0096] like Figure 2a As shown, a mask layer 2020 is formed on the semiconductor pillar 2010 .

[0097] like Figure 2b As shown, a conductive hole 2030 is formed in the mask layer 2020 using a self-alignment technique to expose the upper end of the semiconductor pillar 2010 .

[0098] like Figure 2c As shown, a polysilicon layer 2040 is deposited in the conductive hole 2030, and the polysilicon is etched back (EB), and a metal silicide layer 2050, such as cobalt silicide (CoSi), is formed on the remaining polysilicon layer. The polysilicon layer 2040 is connected to the upper end of the semiconductor pillar 2010.

[0099] like Figure 2d As shown, a conductive layer 2060 (such as titanium nitride TiN, tungsten W, etc.) is formed in the conductive hole 2030 and on the metal silicide layer 2050 , and chemical mechanical polishing (CMP) is performed to form a conductive structure 1064 .

[0100] However, as the size of semiconductor devices gradually decreases, there are many problems to be overcome when using the self-alignment technology, such as non-uniform arrangement of semiconductor bodies, depth difference between semiconductor bodies and word lines in the Z-axis direction, complexity of the self-alignment technology, technical defects in the process of forming the metal silicide layer, etc., which increase the difficulty of alignment between the conductive structure and the upper end of the semiconductor body, and between the conductive structure and the capacitor structure, and easily cause leakage current (Leakage) problems between the conductive structure and the word line, and possibly increase manufacturing costs.

[0101] Based on this, to solve one or more of the above problems, the embodiments of the present disclosure also provide a manufacturing method of a semiconductor device. Referring to Figure 3 , Figure 3 A flowchart of a manufacturing method of a semiconductor device provided by the embodiments of the present disclosure; the method comprises:

[0102] Step S301: forming a semiconductor body extending along a first direction;

[0103] Step S302: forming a conductive structure; the conductive structure is located on one side of the semiconductor body along the first direction; the semiconductor body and the conductive structure are used to form a semiconductor structure; wherein the conductive structure comprises a first part and a second part arranged along a second direction, the first part is in contact with one end of the semiconductor body, and the size of the part of the first part close to the second part in a third direction is different from the size of the part of the second part close to the first part in the third direction; the second direction intersects the third direction, and the first direction is perpendicular to the plane formed by the second direction and the third direction.

[0104] It should be understood that Figure 3 The steps shown in the above description are not exclusive and other steps can be performed before, after or between any of the steps shown in the description; Figure 3 The steps shown in the above description can be adjusted in sequence according to actual needs. It should be noted that the semiconductor device can include one or more semiconductor structures, and here and below, the semiconductor device is taken as an example including multiple semiconductor structures.

[0105] It should be understood that when the relative positions of the gate structure and the semiconductor body in the semiconductor structure are different, the way of forming the semiconductor structure is different. In the embodiment of the present disclosure, the gate structures of two adjacent semiconductor structures are arranged face to face as an example; however, it should be understood that the following description of the relative positions of the gate structure and the semiconductor body is only used to illustrate the present disclosure and is not used to limit the scope of the present disclosure. Based on this, the semiconductor device described in the embodiment of the present disclosure may include a plurality of semiconductor structures arranged in an array along the X-axis direction and the Y-axis direction, and the plurality of semiconductor structures arranged along the X-axis direction include a first semiconductor structure and a second semiconductor structure arranged alternately; the adjacent first semiconductor structure and the second semiconductor structure constitute a semiconductor structure group.

[0106] The formation process of multiple semiconductor structures is described in detail below with reference to the accompanying drawings.

[0107] In some embodiments, step S301 is performed, and the method specifically includes: providing a semiconductor layer, forming a plurality of first grooves extending along the second direction and arranged at intervals along the third direction in the semiconductor layer, and a plurality of second grooves and a plurality of third grooves extending along the third direction and arranged alternately at intervals along the second direction, so as to form a plurality of semiconductor pillars arranged in an array along the first direction and the second direction; forming a first isolation structure in the second groove; forming a gate material layer in the third groove, the gate material layer covering a portion of the surface of the semiconductor pillar and covering the exposed bottom surface of the semiconductor layer; and forming a first substructure on a side of the gate material layer away from the semiconductor pillar along the second direction.

[0108] refer to Figure 4a 、 Figure 4b , Figure 4b for Figure 4a A schematic cross-sectional view along the AA' direction in FIG. 4 is provided; a semiconductor layer 401 is provided, and a plurality of first grooves 402 extending along the X-axis direction and arranged at intervals along the Y-axis direction are formed in the semiconductor layer 401; and a plurality of second grooves 403 and a plurality of third grooves 404 extending along the Y-axis direction and arranged alternately at intervals along the X-axis direction are formed. The plurality of first grooves 402, the plurality of second grooves 403, and the plurality of third grooves 404 divide a portion of the semiconductor layer 401 into a plurality of semiconductor pillars 405 arranged in an array (e.g., Figure 4a At this time, the bottom surface 406 of the semiconductor layer is exposed. The component material of the semiconductor layer 401 includes but is not limited to silicon (Si).

[0109] The size of the second groove 403 along the X-axis direction can be the same as or different from the size of the third groove 404 along the X-axis direction. In consideration of the different structures formed in the second groove 403 and the third groove 404 in subsequent processes and effective utilization of the area of the semiconductor layer, the size of the third groove 404 along the X-axis direction is set to be greater than the size of the second groove 403 along the X-axis direction. For example, referring to Figure 4b , the size of the second groove 403 along the X-axis direction is L1, and the size of the third groove 404 along the X-axis direction is L2, where L2>L1; in other words, the plurality of semiconductor pillars are arranged non-uniformly.

[0110] In some embodiments, the first groove 402, the second groove 403, and the third groove 404 can be formed by a photolithography process (hereinafter and below, which can be understood as lithography-etch (LE, Lithography-Etch)). The order of forming the first groove 402, the second groove 403, and the third groove 404 can be selected and set according to actual conditions. For example, the first groove 402 is formed first, and then the second groove 403 and the third groove 404 are formed. The method can specifically include: forming a first mask layer on the surface of the semiconductor layer 401, performing developing and exposure on the first mask layer to form a first preset pattern corresponding to the first groove, forming the first groove 402 by using the first mask layer and the first preset pattern, and then filling the first groove 402 with an insulating material (marked 40a in Figure 9b 、 Figure 13b , such as silicon oxide (SiO2), and removing the first mask layer. Next, a second mask layer is formed on the surface of the semiconductor layer 401, and the second mask layer is also used to cover the top surface of the insulating material; developing and exposure are performed on the second mask layer to form a second preset pattern corresponding to the second groove and the third groove; the second groove 403 and the third groove 404 are formed based on the second mask layer and the second preset pattern, and the second mask layer is removed. The method of forming the first groove, the second groove, and the third groove can also include other methods, which will not be described herein. The method of filling the insulating material in the first groove includes but is not limited to a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, and an atomic layer deposition (ALD) process.

[0111] The first isolation structure 407 is formed in the second groove 403, and the first isolation structure 407 can be used to reduce the coupling capacitance between two adjacent semiconductor devices. The first isolation structure 407 can include an air gap 4071 and a cap layer 4072 (refer to Figure 5a ), and can also include a conductive material layer 4073 and a protective layer 4074 (refer toFigure 5b It should be noted that when the first isolation structure comprises a conductive material layer, the protective layer needs to surround the conductive material layer to avoid the conductive material layer from contacting the semiconductor pillar. The air gap 4071 can comprise air; the cap layer 4072 can comprise, but is not limited to, silicon oxide; the conductive material layer 4073 can comprise, but is not limited to, tungsten W; and the protective layer 4074 can comprise, but is not limited to, silicon oxide. The method for forming the first isolation structure 407 can comprise, but is not limited to, PVD, CVD, ALD, and the like.

[0112] Referring back to Figure 6 A dielectric material layer 4081 covering the sidewall of the third recess 404 (i.e. the surface of the semiconductor pillar 405) and the bottom of the third recess 404 (i.e. the bottom surface 406 of the semiconductor layer) is formed in the third recess 404, and a gate layer 4082 covering part of the surface of the dielectric material layer 4081 is formed. The dielectric material layer 4081 can comprise, but is not limited to, silicon oxide, and the gate layer 4082 can comprise, but is not limited to, metal (e.g. tungsten W). The method for forming the dielectric material layer 4081 and the gate layer 4082 can comprise, but is not limited to, PVD, CVD, ALD, and the like.

[0113] Continuing to refer back to Figure 6 An insulating material layer 409 is filled in the third recess 404. The insulating material layer 409 can comprise, but is not limited to, silicon oxide. The method for forming the insulating material layer 409 can comprise, but is not limited to, PVD, CVD, ALD, and the like.

[0114] Referring back to Figure 7 Part of the dielectric material layer 4081 and part of the insulating material layer 409 are removed to form a first trench 410. It should be understood that the first trench 410 is a part of the third recess 404. The remaining dielectric material layer 4081 and the gate layer 4082 form a gate material layer 408, and the remaining insulating material layer 409 forms a first sub-structure 411. The removal process can comprise, but is not limited to, dry etching, and the like. It should be understood that the first sub-structure 411 is located on the side of the gate material layer 408 away from the semiconductor pillar 405 along the X-axis direction. Here, the top surface of the remaining dielectric material layer 4081 and the top surface of the gate layer 4082 can be aligned or not aligned along the X-axis direction, Figure 7 The case shown in FIG. 4G is that the top surface 4081a of the remaining dielectric material layer 4081 and the top surface 4082a of the gate layer 4082 are aligned along the X-axis direction.

[0115] Step S302 is performed to form a conductive structure (including forming a conductive hole and forming a conductive structure in the conductive hole). It should be noted that there are multiple methods for forming the conductive hole and the conductive structure, and two exemplary methods are shown in the embodiments of the present disclosure, which are described in detail below with reference to the drawings.

[0116] Method 1:

[0117] Referring to Figure 8 , the method comprises: filling the first dielectric layer 412 in the first trench 410; at this time, the first dielectric layer 412 is located on the side of the semiconductor column 405 away from the first isolation structure 407, and the first dielectric layer 412 covers the remaining surface of the semiconductor column 405; it should be understood that the first dielectric layer 412 is located on the side of the gate material layer 408 and the first sub-structure 411 away from the semiconductor layer bottom surface 406 along the Z-axis direction, and covers the surface of the gate material layer 408 and the first sub-structure 411 away from the semiconductor layer bottom surface 406 along the Z-axis direction. The composition material of the first dielectric layer 412 includes but is not limited to silicon nitride (SiN). The method of forming the first dielectric layer 412 includes but is not limited to processes such as PVD, CVD and ALD.

[0118] In some embodiments, based on a certain etchant, such as hot phosphoric acid, the etching rate of the first dielectric layer 412 is greater than the etching rate of the insulating material 40a, the etching rate of the first dielectric layer 412 is greater than the etching rate of the first isolation structure 407, and the etching rate of the first dielectric layer 412 is greater than the etching rate of the semiconductor column 405. In other words, based on a certain etchant, such as hot phosphoric acid, the first dielectric layer 412 is more easily removed than the insulating material 40a (refer to Figure 9b 40a shown in FIG. 1), the first isolation structure 407, and the semiconductor column 405.

[0119] Referring to Figure 9a , Figure 9b , Figure 9b for Figure 9a , a cross-sectional view along the direction of BB' is shown; the method further comprises: removing part of the semiconductor column to form a fourth recess 413; the removal process includes but is not limited to dry etching. Among them, the size of the remaining semiconductor column 405a along the Z-axis direction is greater than the size of the gate material layer 408 along the Z-axis direction. As Figure 9a shown in FIG. 1, the size of the remaining semiconductor column 405a along the Z-axis direction is R1, and the size of the gate material layer 408 along the Z-axis direction is R2, where R1>R2.

[0120] In some embodiments, referring to Figure 9a , the fourth recess 413 is aligned along the Z-axis direction with the surface of the remaining semiconductor column 405a away from the gate material layer 408 in the X-axis direction, that is, the surface of the first dielectric layer 412 away from the first isolation structure 407 in the X-axis direction.

[0121] Referring to Figure 9bOne surface of the fourth groove 413 along the X-axis direction is adjacent to the first isolation structure 407, and the other surface along the X-axis direction is adjacent to the first dielectric layer 412; the opposite two sides of the fourth groove 413 along the Y-axis direction are adjacent to the insulating material 40a filled in the first groove.

[0122] In some embodiments, reference Figure 10a , part of the first dielectric layer 412 is removed to form a fifth groove 414 with an arc edge; the fourth groove 413 and the fifth groove 414 together constitute a conductive hole; the remaining first dielectric layer 412 constitutes a second substructure 415, where the first substructure 411 and the second substructure 415 together constitute a second isolation structure 416.

[0123] The method used to remove a portion of the first dielectric layer 412 includes, but is not limited to, wet etching. Specifically, an etchant, such as hot phosphoric acid, is filled into the fourth recess 413, and the etchant etches the first dielectric layer 412 to remove a portion of the first dielectric layer 412. It should be understood that the amount of first dielectric layer removed is related to the composition, concentration, and etching temperature of the etchant, and is not specifically limited in this disclosure. However, it should be understood that, due to the isotropic etching characteristics of wet etching, the fifth recess 414 formed has curved edges. In other words, the cross-sectional shape of the fifth recess 414 in the XY plane is an axisymmetric figure containing curved edges.

[0124] In some embodiments, reference Figure 10b , Figure 10b for Figure 10a the cross-sectional shape of the fourth groove 413 on the XY plane is a rectangle, such as a square, a rectangle, etc.; the cross-sectional shape of the fifth groove 414 on the XY plane is an irregular semicircle.

[0125] Since the etchant can etch a small amount of the structures (e.g., the first isolation structure 407, the insulating material 40a, the remaining semiconductor pillar 405a) around the fourth recess, in other words, after the fifth recess is formed by wet etching, the boundary of the fourth recess can exist an outward expansion, so that the interface shape of the fourth recess in the XY plane presents an irregular rectangular shape. However, since the etchant etches a small amount of the structures (e.g., the first isolation structure 407, the insulating material 40a) around the fourth recess, the size of the outward expansion of the boundary of the fourth recess is small. For example, the etchant removes a small amount of the first isolation structure, at this time, the fourth recess 413 is non-aligned with the side wall of the first isolation structure 407 in the X-axis direction, and the side surface of the remaining semiconductor pillar 405a away from the gate material layer 408 in the Z-axis direction. For example, the surface of the fourth recess 413 is close to the surface of the first isolation structure 407 in the X-axis direction, and the distance between the surface of the remaining semiconductor pillar 405 away from the gate material layer 408 in the X-axis direction is less than a preset value. For example, the preset value is less than 3 nm. However, it should be understood that the etchant etches a small amount of the structures around the fourth recess, so that the outward expansion size of the boundary of the fourth recess is relatively small, which does not affect the formation of the conductive structure in the subsequent process, and does not affect the performance of the conductive structure, so the disclosure ignores the outward expansion size of the boundary of the fourth recess.

[0126] In some embodiments, with reference to Figure 11a , the method further comprises: forming a first part 417a of the conductive structure in the fourth recess, and forming a second part 417b of the conductive structure in the fifth recess; the first part 417a of the conductive structure is in contact with one end of the remaining semiconductor pillar 405a.

[0127] In some embodiments, the size of the part of the first part 417a of the conductive structure close to the second part 417b of the conductive structure in the Y-axis direction is different from the size of the part of the second part 417b of the conductive structure close to the first part 417a of the conductive structure in the Y-axis direction.

[0128] For example, with reference to Figure 11b , Figure 11b is a schematic view of the cross section along the DD' direction in FIG. 11; the size of the part of the first part 417a of the conductive structure close to the second part 417b of the conductive structure in the Y-axis direction is a first size M1, and the size of the part of the second part 417b of the conductive structure close to the first part 417a of the conductive structure in the Y-axis direction is a second size M2, the second size M2 is greater than the first size M1, that is, M2>M1.

[0129] In some embodiments, the first isolation structure includes a first end surface and a second end surface opposite to each other along the first direction, and the second isolation structure includes a third end surface and a fourth end surface opposite to each other along the first direction; the first end surface, the third end surface, the first part of the conductive structure away from the surface of the semiconductor body along the first direction, and the second part of the conductive structure away from the surface of the gate structure along the first direction are aligned along the second direction.

[0130] For example, referring to Figure 11a , the first isolation structure 407, the second isolation structure 416, the first part 417a of the conductive structure, and the second part 417b of the conductive structure are aligned along the X-axis direction.

[0131] Since the size of the remaining semiconductor pillar 405a along the Z-axis direction is greater than the size of the gate material layer 408 along the Z-axis direction, the conductive structure 417 is spaced apart from the gate material layer 408, as Figure 11a shown, the conductive structure 417 and the gate material layer 408 are separated by the second sub-structure 415, so that the leakage current between the gate material layer 408 (subsequently formed into a gate structure) and the conductive structure 417 can be avoided, and the reliability of the semiconductor device is improved.

[0132] In some embodiments, the conductive structure can include a polysilicon layer, a metal silicide layer, and a conductive metal layer stacked along the Z-axis direction, and the polysilicon layer is in contact with the semiconductor body; or the conductive structure can include a polysilicon layer and a metal silicide layer stacked along the Z-axis direction, and the polysilicon layer is in contact with the semiconductor body; or the conductive structure can include a metal silicide layer in contact with the semiconductor body.

[0133] In other words, in some specific embodiments, the method of forming the conductive structure can include: forming a polysilicon layer (such as Poly) in the fourth recess and the fifth recess; the polysilicon layer is in contact with one end of the remaining semiconductor pillar; forming a metal silicide layer (such as CoSi) on the side of the polysilicon layer away from the remaining semiconductor pillar; and forming a conductive metal layer (such as TiN, W) on the side of the metal silicide layer away from the polysilicon layer.

[0134] In some embodiments, the method of forming the conductive structure can include: forming a polysilicon layer in the fourth recess and the fifth recess; the polysilicon layer being in contact with one end of the remaining semiconductor pillars; and forming a metal silicide layer on a side of the polysilicon layer away from the remaining semiconductor pillars.

[0135] In some embodiments, the method of forming the conductive structure can include: forming a polysilicon layer in the fourth recess and the fifth recess; and performing a metalization process on the polysilicon layer to obtain a metal silicide to form the conductive structure.

[0136] The method of forming the metal silicide layer in the above embodiments can be to perform a metalization process on part of the polysilicon layer, or can be to deposit a metal silicide layer on the polysilicon layer, and the present disclosure is not limited in this regard. The method of forming the polysilicon layer and the conductive metal layer can include, but is not limited to, processes such as PVD, CVD, and ALD.

[0137] In the embodiments of the present disclosure, the fourth recess is formed by removing part of the semiconductor pillars, and the first part of the conductive structure is formed in the fourth recess and is in direct contact with the remaining semiconductor pillars. In this way, the alignment accuracy of the first part of the conductive structure and the remaining semiconductor pillars can be increased, and the alignment difficulty of the two can be reduced, and the reliability of the semiconductor device can be improved. In addition, by expanding the fourth recess, i.e., forming the fifth recess, the size of the conductive hole can be increased, and the top surface of the conductive structure can be increased. In this way, the contact area between the conductive structure and other device structures (such as a capacitor structure) is increased, and the process difficulty of realizing the contact between the conductive structure and other device structures (such as a capacitor structure) is reduced. Furthermore, by forming the fifth recess on one side of the gate material layer along the Z-axis direction, and forming the second part of the conductive structure in the fifth recess, the space on one side of the gate material layer along the Z-axis direction is effectively utilized, and the structure layout is more matched and reasonable with the non-uniform arrangement layout of the semiconductor pillars.

[0138] Method two:

[0139] Reference Figure 12a , Figure 12b , Figure 12b For Figure 12aFIG. 6 is a schematic view of a cross section along the direction of EE' of the semiconductor structure. The method includes forming a second dielectric layer 501 in the first trench 410, and forming a fourth sub-structure 502 on a side of the second dielectric layer 501 away from the semiconductor pillar 405 along the direction of the X axis. The second dielectric layer 501 covers the remaining surface of the semiconductor pillar on the side away from the first isolation structure 407 along the direction of the X axis, and the second dielectric layer 501 covers the surface of the gate material layer 408 and the first sub-structure 411 away from the bottom surface 406 of the semiconductor layer along the direction of the Z axis. The material of the second dielectric layer 501 includes but is not limited to silicon nitride (SiN), and the material of the fourth sub-structure 502 includes but is not limited to silicon oxide (SiO2). The method of forming the second dielectric layer 501 and the fourth sub-structure 502 includes but is not limited to PVD, CVD, ALD, and the like.

[0140] Referring to Figure 13a , Figure 13b , Figure 13b To Figure 13a FIG. 7 is a schematic view of a cross section along the direction of FF' of the semiconductor structure. The method includes removing part of the semiconductor pillar 405 to form a sixth recess 503; the removing process includes but is not limited to dry etching. Here, the size of the remaining semiconductor pillar 405a along the direction of the Z axis is greater than the size of the gate material layer 408 along the direction of the Z axis.

[0141] In some embodiments, referring to Figure 13a , the sixth recess 503 is aligned with the surface of the remaining semiconductor pillar 405a away from the gate material layer 408 along the direction of the Z axis on the side of the first isolation structure 407 along the direction of the X axis.

[0142] Referring to Figure 13b , the sixth recess 503 is adjacent to the first isolation structure 407 on one side along the direction of the X axis, and is adjacent to the second dielectric layer 501 on the other side along the direction of the X axis; the opposite sides of the sixth recess 503 along the direction of the Y axis are adjacent to the insulating material 40a filled in the first recess.

[0143] In some embodiments, referring to Figure 14a , Figure 14b , Figure 14b To Figure 14aA schematic view of a cross section along the direction of GG'. The method comprises: removing part of the second dielectric layer 501 to form the seventh groove 504 with an arc-shaped side; the sixth groove 503 and the seventh groove 504 together form the conductive hole, and the remaining second dielectric layer forms the third sub-structure 505. The first sub-structure 411, the third sub-structure 505, and the fourth sub-structure 502 together form the second isolation structure 506. It should be noted that the method for removing part of the second dielectric layer 501 includes but is not limited to wet etching. Specifically: fill the etchant such as hot phosphoric acid into the sixth groove 503, and etch the second dielectric layer 501 by the etchant to remove part of the second dielectric layer 501, and the remaining second dielectric layer forms the third sub-structure 505. It should be understood that the amount of removed second dielectric layer is related to the composition of the etchant, the concentration of the etchant, and the etching temperature, etc., which will not be limited herein.

[0144] Based on a certain etchant, for example, hot phosphoric acid, the etching rate of the second dielectric layer 501 is greater than the etching rate of the insulating material 40a, the etching rate of the second dielectric layer 501 is greater than the etching rate of the first isolation structure 407, the etching rate of the second dielectric layer 501 is greater than the etching rate of the remaining semiconductor column 405a, and the etching rate of the second dielectric layer 501 is greater than the etching rate of the fourth sub-structure 502. In other words, based on a certain etchant, such as hot phosphoric acid, the second dielectric layer 501 is more easily removed than the insulating material 40a, the first isolation structure 407, the remaining semiconductor column 405a, and the fourth sub-structure 502. However, it should be understood that based on the isotropic etching characteristics of wet etching, the seventh groove 504 formed has an arc-shaped side, in other words, the cross-sectional shape of the seventh groove 504 in the XY plane is an axisymmetric figure containing an arc-shaped side.

[0145] The fourth sub-structure 502 can act as an etching stop layer for wet etching. Specifically: when the etchant removes the first dielectric layer between the sixth groove 503 and the fourth sub-structure 502, the fourth sub-structure 502 is used to block the etchant from continuing to etch. Based on this, the straight side of the seventh groove 504 formed away from one side of the sixth groove 503 along the X-axis direction is a straight line.

[0146] Since the etchant can etch a small amount of structure around the sixth groove, in other words, after the seventh groove is formed, the boundary of the sixth groove can have an outward expansion, so that the interface shape of the sixth groove in the XY plane is an irregular rectangular shape. However, it should be understood that the etching amount of the etchant on the structure around the sixth groove is small, which does not affect the formation of the conductive structure in the subsequent process, nor does it affect the performance of the conductive structure, therefore, the outward expansion size of the boundary of the sixth groove is ignored in the present disclosure.

[0147] In some embodiments, reference is made to Figure 15a , Figure 15b , Figure 15bFor Figure 15a FIG. 6 is a schematic view of a cross section along the direction of HH' of the semiconductor device shown in FIG. 5. The method comprises forming a first portion 507a of the conductive structure 507 in the sixth recess 503 and forming a second portion 507b of the conductive structure in the seventh recess 504; the first portion 507a of the conductive structure is in contact with one end of the remaining semiconductor pillar 405a.

[0148] In some embodiments, the dimension of the portion of the first portion 507a of the conductive structure close to the second portion 507b of the conductive structure in the Y-axis direction is different from the dimension of the portion of the second portion 507b of the conductive structure close to the first portion 507a of the conductive structure in the Y-axis direction.

[0149] For example, referring to Figure 15b , the dimension of the portion of the first portion 507a of the conductive structure close to the second portion 507b of the conductive structure in the Y-axis direction is a first dimension N1, and the dimension of the portion of the second portion 507b of the conductive structure close to the first portion 507a of the conductive structure in the Y-axis direction is a second dimension N2, the second dimension N2 is greater than the first dimension N1, i.e. N2>N1.

[0150] In some embodiments, as Figure 15a shown, the surface of the semiconductor layer bottom surface 406 away from which the first isolation structure 407 extends in the Z-axis direction (the top surface of the first isolation structure 407), the surface of the semiconductor layer bottom surface 406 away from which the second isolation structure 506 extends in the Z-axis direction (the top surface of the second isolation structure 506), the surface of the semiconductor layer bottom surface 406 away from which the first portion 507a of the conductive structure extends in the Z-axis direction (i.e. the top surface of the first portion 507a of the conductive structure), and the surface of the gate material layer away from which the second portion 507b of the conductive structure extends in the Z-axis direction (i.e. the top surface of the second portion 507b of the conductive structure) are aligned in the X-axis direction.

[0151] Based on the dimension of the remaining semiconductor pillar 405a in the Z-axis direction being greater than the dimension of the gate material layer 408 in the Z-axis direction, the conductive structure 507 and the gate material layer 408 are spaced apart, as Figure 15a shown, the conductive structure 507 and the gate material layer 408 are separated by the third sub-structure 505, so that the occurrence of leakage current between the gate material layer 408 (subsequently formed into a gate structure) and the conductive structure 507 can be avoided, and the reliability of the semiconductor device is improved.

[0152] In some embodiments, the dimension of the second portion 507b of the conductive structure in the X-axis direction is less than the dimension of the third sub-structure 505 in the X-axis direction. In this way, the third sub-structure 505 is more easily isolated from the conductive structure 507 and the gate material layer 408, further improving the reliability of the semiconductor device.

[0153] In some embodiments, referring to Figure 15a The third substructure 505 between two adjacent semiconductor pillars 405a along the X-axis direction has a "concave" shape in the cross-sectional shape in the XZ plane; in other embodiments, the third substructure 505 can also have a "straight" shape, a "convex" shape, etc. in the cross-sectional shape in the XZ plane, which is not limited in the present disclosure.

[0154] In some embodiments, the conductive structure can include a polysilicon layer, a metal silicide layer, and a conductive metal layer stacked along the Z-axis direction, wherein the polysilicon layer is in contact with the semiconductor body; or the conductive structure can include a polysilicon layer and a metal silicide layer stacked along the Z-axis direction, wherein the polysilicon layer is in contact with the semiconductor body; or the conductive structure can include a metal silicide layer in contact with the semiconductor body. The method of forming the conductive structure has been described above and will not be repeated here.

[0155] In the embodiments of the present disclosure, the sixth groove is formed by removing part of the semiconductor pillars, and the first part of the conductive structure in direct contact with the remaining semiconductor pillars is formed in the sixth groove. In this way, the alignment accuracy of the first part of the conductive structure and the remaining semiconductor pillars can be increased, thereby reducing the alignment difficulty and improving the reliability of the semiconductor device. In addition, by expanding the sixth groove, i.e., forming the seventh groove, the size of the conductive hole can be increased, thereby increasing the top surface of the conductive structure. In this way, the contact area between the conductive structure and other device structures (such as a capacitor structure) is increased, and the process difficulty of realizing the contact between the conductive structure and other device structures (such as a capacitor structure) is reduced. Furthermore, by forming the seventh groove on one side of the gate material layer along the Z-axis direction, and forming the second part of the conductive structure in the seventh groove, the space on one side of the gate material layer along the Z-axis direction is effectively utilized, and the structure layout is more matched and reasonable with the non-uniform arrangement of the semiconductor pillars. Moreover, during the formation of the seventh groove, the fourth substructure acts as an etching stop layer for wet etching, so that the expansion size of the seventh groove is limited, the size of the seventh groove can be better controlled, and the controllability of the process is improved.

[0156] Referring to Figure 16 The method further includes: flipping the semiconductor layer and performing a thinning process on the semiconductor layer to expose the lower end 601 of the remaining semiconductor pillar 405a.

[0157] In some embodiments, the method further includes: forming a source or a drain on the upper end and the lower end of the remaining semiconductor pillar 405, respectively. The process sequence of forming the source and the drain can be selected according to the requirements, and the present disclosure shows a process sequence of forming the source and the drain.

[0158] For example, the method specifically includes: doping the remaining semiconductor pillar 405a away from the upper end of the semiconductor layer bottom surface 406 in the Z-axis direction before forming the conductive structure to form one of the source 603 or the drain 604; thinning the semiconductor layer after forming the conductive structure to expose the lower end of the remaining semiconductor pillar opposite to the upper end in the Z-axis direction; and doping the lower end of the remaining semiconductor pillar 405a to form the other of the source 603 or the drain 604. Wherein, the region of the remaining semiconductor pillar 405a between the source 603 and the drain 604 constitutes the channel region 605; the channel region 605, the source 603 and the drain 604 together constitute the semiconductor body 606.

[0159] The positions of the source 603 and the drain 604 can be interchanged, Figure 16 For example, the source 603 is located at the upper end of the remaining semiconductor pillar 405a, and the drain 604 is located at the lower end of the remaining semiconductor pillar 405a.

[0160] Reference Figure 16 The method further includes: removing the gate material layer covering the semiconductor layer bottom surface; wherein the remaining gate material layer constitutes the gate structure 602.

[0161] Based on the above method and steps, a plurality of semiconductor structures arranged in an array along the X-axis direction and the Y-axis direction are formed. As described above, the plurality of semiconductor structures arranged along the X-axis direction include first semiconductor structures and second semiconductor structures arranged alternately; the first semiconductor structure and the second semiconductor structure arranged adjacently constitute a semiconductor structure group.

[0162] For example, referring to Figure 17 , Figure 17 For Figure 16An enlarged schematic view of the semiconductor structure group 701 is shown in the dotted box. The semiconductor structure group 701 includes a first semiconductor structure 702 and a second semiconductor structure 703. The first semiconductor structure 702 includes a first semiconductor body 704, a first gate structure 705, and a first conductive structure 706. The second semiconductor structure 703 includes a second semiconductor body 707, a second gate structure 708, and a second conductive structure 709. The first gate structure 705 is located on a side of the first semiconductor body 704 close to the second semiconductor body 707. The second gate structure 708 is located on a side of the second semiconductor body 707 close to the first gate structure 705. The first conductive structure 706 is located on a side of the first semiconductor body 704 along the Z-axis direction. The second conductive structure 709 is located on a side of the second semiconductor body 707 along the Z-axis direction. A second part 507b of the first conductive structure 706 is located on a side of a first part 507a of the first conductive structure 706 close to the second conductive structure 709. A second part 507b of the second conductive structure 709 is located on a side of a first part 507a of the second conductive structure 709 close to the first conductive structure 706.

[0163] Reference is made to Figure 18 The method further includes forming a capacitor structure 607 connected to an end of the conductive structure 507 away from the semiconductor body 606 along the Z-axis direction. It is to be noted that the capacitor structure 607 can include a first electrode layer, a dielectric layer covering a surface of the first electrode layer, and a second electrode layer covering a surface of the dielectric layer. The first electrode layer is used as a lower electrode of the capacitor structure. The dielectric layer is used as a dielectric of the capacitor. The second electrode layer is used as an upper electrode of the capacitor structure. Exemplarily, the first electrode layer and the second electrode layer can each include, but are not limited to, titanium nitride. The dielectric layer can include a high-k material, which generally refers to a material with a dielectric constant higher than 3.9, and is usually significantly higher than this value. In some specific examples, the dielectric layer can include, but is not limited to, aluminum oxide (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc. The methods for forming the first electrode layer, the dielectric layer, and the second electrode layer can each include, but are not limited to, PVD, CVD, ALD, etc.

[0164] In some embodiments, the capacitor structure can also present a plurality of different shapes, such as a cylindrical or pillar-shaped capacitor. That is, the capacitor structure can include a cup-shaped capacitor CUP, a cylindrical capacitor CYL, and a pillar-shaped capacitor PIL. The shape of the capacitor structure can be selected according to actual requirements, and the present disclosure is not limited in this regard.

[0165] In some embodiments, at least a portion of a surface of the first portion 507a of the conductive structure that is away from the semiconductor body 606 along the Z-axis direction (i.e., the top surface of the first portion 507a of the conductive structure) and a portion of a surface of the second portion 507b of the conductive structure that is away from the semiconductor body 606 along the Z-axis direction (i.e., the top surface of the second portion 507b of the conductive structure) are in contact with the capacitor structure 607. In other words, the capacitor structure 607 may only be in contact with all or part of the top surface of the first portion 507a of the conductive structure, or only be in contact with all or part of the top surface of the second portion 507b of the conductive structure, or may be in contact with all or part of the top surface of both the first portion 507a of the conductive structure, 507b of the conductive structure. In this way, the process window for contact between the conductive structure 507 and the capacitor structure 607 can be expanded, the process difficulty can be reduced, and the reliability of the semiconductor device can be improved.

[0166] Figure 18 The second isolation structure shown in the figure is a second isolation structure formed by method 2 (including the first substructure 411, the third substructure 505 and the fourth substructure 502), but it should be understood that the above exemplary diagram is only used to illustrate the present disclosure and is not used to limit the scope of the present disclosure.

[0167] Continue to refer Figure 18 The method further includes forming a plurality of bit lines 608 extending along the X-axis and spaced apart along the Y-axis, each bit line 608 being connected to an end of a row of semiconductor bodies 606 that is distal from the conductive structure 507 along the Z-axis. Exemplarily, each bit line 608 is connected to the drain 604 of each semiconductor body 606 in the row of semiconductor bodies 606 arranged along the X-axis. The material comprising the bit lines 608 includes, but is not limited to, tungsten W. Methods for forming the bit lines include, but are not limited to, processes such as PVD, CVD, and ALD.

[0168] In the embodiment of the present disclosure, a conductive structure connected to the semiconductor body is formed on one side of the semiconductor body along the first direction, so that self-alignment of the conductive structure and the semiconductor body can be achieved, thereby increasing the alignment accuracy of the first part of the conductive structure and the semiconductor body, reducing the difficulty of alignment between the two, improving the reliability of the semiconductor device, saving manufacturing time and cost, and improving process speed and efficiency; on the other hand, the conductive structure includes a first part connected to the semiconductor body, and a second part arranged parallel to the first part along the second direction, so that the purpose of increasing the volume / surface area of ​​the conductive structure can be achieved, and then the contact area between the conductive structure and other external structures (such as a capacitor structure) can be increased, thereby improving the reliability of the semiconductor device; on the other hand, the size of the part of the first part close to the second part in the third direction is different from the size of the part of the second part close to the first part in the third direction, so that the structural layout of the conductive structure and the semiconductor body can be more matched and more reasonable.

[0169] Based on the above semiconductor device manufacturing method, the embodiments of the present disclosure further provide a semiconductor device, which refers to Figure 19 The semiconductor device 1900 includes a semiconductor structure 1901, the semiconductor structure 1901 includes a semiconductor body 606 extending along a first direction, and a conductive structure 507 located on one side of the semiconductor body along the first direction; wherein the conductive structure 507 includes a first part 507a and a second part 507b arranged along a second direction, the first part 507a is in contact with one end of the semiconductor body 606, and the size of the part of the first part close to the second part in a third direction is different from the size of the part of the second part close to the first part in the third direction; the second direction intersects the third direction, and the first direction is perpendicular to the plane formed by the second direction and the third direction.

[0170] In some embodiments, the size of the part of the first part close to the second part in the third direction is a first size; the size of the part of the second part close to the first part in the third direction is a second size; and the second size is greater than the first size.

[0171] In some embodiments, the cross-sectional shape of the first part on the plane includes a square; and the cross-sectional shape of the second part on the plane includes an axisymmetric figure containing an arc edge.

[0172] In some embodiments, the interval distance between the surface of the first part away from the second part in the second direction and the surface of the semiconductor body away from the second part in the second direction in the second direction is less than a preset value.

[0173] In some embodiments, referring to Figure 19 The semiconductor structure further includes a gate structure 602 located on one side of the semiconductor body 606 close to the second part in the second direction; wherein the gate structure 602 is arranged at an interval between the surface of the second part close to the gate structure along the first direction and the surface of the first part close to the second part 507b along the first direction.

[0174] In some embodiments, referring to Figure 19, the semiconductor structure further comprises: a first isolation structure 407 located at a side of the semiconductor body away from the second portion in the second direction; and a second isolation structure 506 located at a side of the gate structure away from the semiconductor body in the second direction, and the second isolation structure contacts the surface of the second portion away from the first portion, the surface of the second portion close to the gate structure in the first direction, and the surface of the gate structure close to the second portion in the first direction.

[0175] In some embodiments, the second isolation structure comprises a first sub-structure and a second sub-structure arranged in the first direction; wherein the first sub-structure is located at a side of the gate structure away from the semiconductor body in the second direction; and the second sub-structure is located at a side of the second portion away from the first portion, and between the surface of the second portion close to the gate structure in the first direction and the surface of the gate structure close to the second portion in the first direction.

[0176] In some embodiments, referring to Figure 19 , the second isolation structure 506 comprises a first sub-structure 411, a third sub-structure 505, and a fourth sub-structure 502 arranged in the first direction; wherein the first sub-structure 411 is located at a side of the gate structure 602 away from the semiconductor body 606 in the second direction; the third sub-structure 505 is located between the surface of the gate structure 602 close to the second portion 507b in the first direction and the surface of the second portion 507b close to the gate structure 602 in the first direction; and the fourth sub-structure 502 is located at a side of the second portion 507b away from the first portion 507a.

[0177] In some embodiments, the third sub-structure and the fourth sub-structure are made of different materials.

[0178] In some embodiments, the second portion has a dimension in the second direction smaller than a dimension of the third sub-structure in the second direction.

[0179] In some embodiments, the side of the second portion away from the first portion in the second direction is a straight line extending in the third direction.

[0180] In some embodiments, the conductive structure is located between the first isolation structure and the fourth sub-structure, and the conductive structure contacts a side of the third sub-structure away from the gate structure in the first direction.

[0181] In some embodiments, the first isolation structure includes a first end surface and a second end surface opposite to each other along the first direction, and the second isolation structure includes a third end surface and a fourth end surface opposite to each other along the first direction; the first end surface, the third end surface, the surface of the semiconductor body away from the first portion along the first direction, and the surface of the semiconductor body away from the second portion along the first direction are aligned along the second direction.

[0182] In some embodiments, the conductive structure includes a polysilicon layer, a metal silicide layer and a conductive metal layer stacked along the first direction; or, the conductive structure includes a polysilicon layer and a metal silicide layer stacked along the first direction; or, the conductive structure includes a metal silicide layer in contact with the semiconductor body.

[0183] In some embodiments, referring to Figure 19 , the semiconductor body 606 includes a channel region 605, and a source 603 and a drain 604 located on two sides of the channel region 605 along the first direction respectively.

[0184] In some embodiments, referring to Figure 19 , the semiconductor structure further includes a capacitor structure 607; the capacitor structure 607 is connected to one end of the conductive structure 507 away from the semiconductor body 606 along the first direction.

[0185] In some embodiments, the capacitor structure includes a fifth end surface and a sixth end surface opposite to each other along the first direction; at least part of the surface of the semiconductor body away from the first portion along the first direction and the surface of the semiconductor body away from the second portion along the first direction is in contact with the fifth end surface.

[0186] In some embodiments, the semiconductor device includes a plurality of semiconductor structures arranged in an array along the second direction and the third direction; wherein the plurality of semiconductor structures arranged along the second direction includes first semiconductor structures and second semiconductor structures arranged alternately; the first semiconductor structure and the second semiconductor structure arranged adjacently constitute a semiconductor structure group.

[0187] In some embodiments, the first semiconductor structure includes a first semiconductor body, a first gate structure and a first conductive structure; the second semiconductor structure includes a second semiconductor body, a second gate structure and a second conductive structure; the first gate structure is located on a side of the first semiconductor body close to the second semiconductor body, the second gate structure is located on a side of the second semiconductor body close to the first gate structure; a second part of the first conductive structure is located on a side of a first part of the first conductive structure close to the second conductive structure, a second part of the second conductive structure is located on a side of a first part of the second conductive structure close to the first conductive structure.

[0188] In some embodiments, referring to Figure 19 , the semiconductor device further includes: a plurality of bit lines 608 extending along the second direction and spaced apart along the third direction, each of the bit lines 608 is connected to an end of a row of the semiconductor bodies 606 away from the conductive structure 507 along the first direction.

[0189] According to an aspect of the present disclosure, there is provided a storage system, including: a semiconductor device as described in the above embodiments of the present disclosure; and a memory controller connected to the semiconductor device and configured to control the semiconductor device.

[0190] It should be noted that, Figure 19 The conductive structure 507 shown in FIG. 6 is formed by the method two described in the above embodiments of the present disclosure. In other semiconductor devices, the conductive structure can also be formed by the method one described in the above embodiments, which is not described in the present disclosure.

[0191] The specific embodiments of the present disclosure have been described above, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present disclosure, which should be covered within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be subject to the scope of protection of the claims.

Claims

1. A semiconductor device, characterized by, Comprising: a semiconductor structure; the semiconductor structure comprises a semiconductor body extending along a first direction; and a conductive structure located on one side of the semiconductor body along the first direction; wherein the conductive structure comprises a first portion and a second portion arranged along a second direction, the first portion is in contact with one end of the semiconductor body, and the portion of the first portion close to the second portion has a dimension in a third direction different from the dimension of the portion of the second portion close to the first portion in the third direction; the second direction intersects the third direction, and the first direction is perpendicular to the plane formed by the second direction and the third direction.

2. The semiconductor device of claim 1, wherein: the dimension of the portion of the first portion close to the second portion in the third direction is a first dimension; the dimension of the portion of the second portion close to the first portion in the third direction is a second dimension; the second dimension is greater than the first dimension.

3. The semiconductor device of claim 1, wherein: the cross-sectional shape of the first portion on the plane comprises a square shape; the cross-sectional shape of the second portion on the plane comprises an axisymmetric figure comprising an arc edge.

4. The semiconductor device of claim 1, wherein the interval distance in the second direction between the surface of the first portion away from the second portion and the surface of the semiconductor body away from the second portion in the second direction is less than a preset value.

5. The semiconductor device of claim 4, wherein, The semiconductor structure further comprises: a gate structure located on one side of the semiconductor body close to the second portion in the second direction; wherein the gate structure is spaced apart between the surface of the second portion close to the gate structure in the first direction and the surface of the second portion close to the gate structure in the first direction.

6. The semiconductor device of claim 5, wherein, The semiconductor structure further comprises: a first isolation structure located on one side of the semiconductor body away from the second portion in the second direction; a second isolation structure located on one side of the gate structure away from the semiconductor body in the second direction, and the second isolation structure is in contact with the surface of the second portion away from the first portion, the surface of the second portion close to the gate structure in the first direction, and the surface of the gate structure close to the second portion in the first direction.

7. The semiconductor device of claim 6, wherein, The second isolation structure comprises a first sub-structure and a second sub-structure arranged along the first direction; wherein the first sub-structure is located on one side of the gate structure away from the semiconductor body in the second direction; the second sub-structure is located on one side of the second portion away from the first portion, and between the surface of the gate structure close to the second portion in the first direction and the surface of the second portion close to the gate structure in the first direction.

8. The semiconductor device of claim 6, wherein, The second isolation structure comprises a first sub-structure, a third sub-structure, and a fourth sub-structure arranged along the first direction; wherein the first sub-structure is located on one side of the gate structure away from the semiconductor body in the second direction; The third sub-structure is located between a surface of the gate structure close to the second portion along the first direction and a surface of the second portion close to the gate structure along the first direction. The fourth sub-structure is located on a side of the second portion away from the first portion.

9. The semiconductor device of claim 8, wherein, The third sub-structure is composed of a material different from that of the fourth sub-structure.

10. The semiconductor device according to claim 8, wherein The second portion has a dimension along the second direction smaller than that of the third sub-structure along the second direction.

11. The semiconductor device of claim 8, wherein, A side of the second portion away from the first portion along the second direction is a straight line extending along the third direction.

12. The semiconductor device of claim 8, wherein, The conductive structure is located between the first isolation structure and the fourth sub-structure, and contacts a side of the third sub-structure away from the gate structure along the first direction.

13. The semiconductor device of claim 12, wherein, The first isolation structure includes first and second end faces opposite along the first direction, and the second isolation structure includes third and fourth end faces opposite along the first direction. The first end face, the third end face, a surface of the first portion away from the semiconductor body along the first direction, and a surface of the second portion away from the gate structure along the first direction are aligned along the second direction.

14. The semiconductor device according to claim 7 or 8, wherein The conductive structure includes a polysilicon layer, a metal silicide layer, and a conductive metal layer stacked along the first direction. Alternatively, The conductive structure includes a polysilicon layer and a metal silicide layer stacked along the first direction. Alternatively, The conductive structure includes a metal silicide layer in contact with the semiconductor body.

15. The semiconductor device of claim 1, wherein, The semiconductor body includes a channel region, and a source and a drain located on both sides of the channel region along the first direction, respectively.

16. The semiconductor device of claim 1, wherein The semiconductor structure further includes: A capacitor structure connected to an end of the conductive structure away from the semiconductor body along the first direction.

17. The semiconductor device of claim 16, wherein, The capacitor structure includes fifth and sixth end faces opposite along the first direction. At least part of a surface of the first portion away from the semiconductor body along the first direction and a surface of the second portion away from the semiconductor body along the first direction is in contact with the fifth end face.

18. The semiconductor device of claim 1, wherein, The semiconductor device includes a plurality of semiconductor structures arranged in an array along the second and third directions. Among the semiconductor structures arranged along the second direction, first and second semiconductor structures are arranged alternately; the first and second semiconductor structures arranged adjacently constitute a semiconductor structure group.

19. The semiconductor device of claim 18, wherein, The first semiconductor structure includes a first semiconductor body, a first gate structure, and a first conductive structure; the second semiconductor structure includes a second semiconductor body, a second gate structure, and a second conductive structure. The first gate structure is located on a side of the first semiconductor body close to the second semiconductor body, and the second gate structure is located on a side of the second semiconductor body close to the first gate structure. The second part of the first conductive structure is located on a side of the first part of the first conductive structure close to the second conductive structure, and the second part of the second conductive structure is located on a side of the first part of the second conductive structure close to the first conductive structure.

20. The semiconductor device of claim 1, wherein, The semiconductor device further comprises: a plurality of bit lines extending along the second direction and spaced apart along the third direction, each of the bit lines being connected to an end of a row of the semiconductor bodies away from the conductive structure along the first direction.

21. A storage system, comprising: comprising: the semiconductor device as claimed in claims 1-20; and, a memory controller connected to the semiconductor device and configured to control the semiconductor device.

22. A method of manufacturing a semiconductor device, characterized by The method comprises: forming a semiconductor body extending along a first direction; forming a conductive structure; the conductive structure is located on a side of the semiconductor body along the first direction; the semiconductor body and the conductive structure are used to form a semiconductor structure; wherein the conductive structure comprises a first part and a second part arranged along a second direction, the first part is in contact with an end of the semiconductor body, and the size of the part of the first part close to the second part in a third direction is different from the size of the part of the second part close to the first part in the third direction; the second direction intersects the third direction, and the first direction is perpendicular to the plane formed by the second direction and the third direction.

23. The manufacturing method according to claim 22, wherein The method of forming a semiconductor body extending along a first direction comprises: forming a plurality of first grooves extending along a second direction and spaced apart along a third direction in a semiconductor layer, and a plurality of second grooves and a plurality of third grooves extending along the third direction and alternately spaced apart along the second direction, to form a plurality of semiconductor columns extending along a first direction; the semiconductor columns are used to form the semiconductor body; forming a first isolation structure in the second grooves; forming a gate material layer in the third grooves, the gate material layer covers part of the surface of the semiconductor column, and covers the exposed bottom surface of the semiconductor layer; and forming a first sub-structure on a side of the gate material layer away from the semiconductor column along the second direction.

24. The manufacturing method according to claim 23, wherein, The method further comprises: filling a first dielectric layer in the third grooves; the first dielectric layer covers the remaining surface of the semiconductor column, and covers the surface of the gate material layer and the first sub-structure away from the bottom surface of the semiconductor layer along the first direction.

25. The manufacturing method according to claim 24, characterized in that The method further comprises: removing part of the semiconductor column to form a fourth groove; the remaining semiconductor column has a size along the first direction greater than the size of the gate material layer along the first direction.

26. The manufacturing method according to claim 25, wherein The method further comprises: removing part of the first dielectric layer to form a fifth groove with an arc-shaped side; wherein the remaining first dielectric layer constitutes a second sub-structure; the first sub-structure and the second sub-structure constitute a second isolation structure.

27. The manufacturing method according to claim 26, wherein The method of forming a conductive structure comprises: forming a first part of the conductive structure in the fourth groove, and a second part of the conductive structure in the fifth groove; the first part is in contact with an end of the remaining semiconductor column.

28. The manufacturing method according to claim 27, wherein, forming a conductive structure in the fourth recess and the fifth recess, the forming comprising: forming a polysilicon layer in the fourth recess and the fifth recess; the polysilicon layer being in contact with one end of the remaining semiconductor pillar; forming a metal silicide layer on a side of the polysilicon layer away from the remaining semiconductor pillar; forming a conductive metal layer on a side of the metal silicide layer away from the polysilicon layer.

29. The manufacturing method according to claim 27, wherein forming a conductive structure in the fourth recess and the fifth recess, the forming comprising: forming a polysilicon layer in the fourth recess and the fifth recess; the polysilicon layer being in contact with one end of the remaining semiconductor pillar; forming a metal silicide layer on a side of the polysilicon layer away from the remaining semiconductor pillar.

30. The manufacturing method according to claim 27, wherein forming a conductive structure in the fourth recess and the fifth recess, the forming comprising: forming a polysilicon layer in the fourth recess and the fifth recess; forming a metal silicide layer on a side of the polysilicon layer away from the remaining semiconductor pillar.

31. The manufacturing method of claim 23, wherein, The method further comprises: forming a second dielectric layer in the third recess; the second dielectric layer covering a remaining surface of the semiconductor pillar, and covering a surface of the gate material layer and the first sub-structure away from the bottom surface of the semiconductor layer along the first direction; and forming a fourth sub-structure on a side of the second dielectric layer away from the semiconductor pillar along the second direction.

32. The manufacturing method of claim 31, wherein, The method further comprises: removing part of the semiconductor pillar to form a sixth recess; a remaining portion of the semiconductor pillar along the first direction being larger than a size of the gate material layer along the first direction.

33. The manufacturing method of claim 32, wherein, The method further comprises: removing part of the second dielectric layer to form a seventh recess having an arc-shaped side; wherein a remaining portion of the second dielectric layer constitutes a third sub-structure; the first sub-structure, the third sub-structure, and the fourth sub-structure constitute a second isolation structure.

34. The manufacturing method of claim 33, wherein, A material of the third sub-structure is different from a material of the fourth sub-structure.

35. The manufacturing method of claim 33, wherein, A size of the second portion along the second direction is smaller than a size of the third sub-structure along the second direction.

36. The manufacturing method of claim 33, wherein, A side of the second portion away from the first portion along the second direction is a straight side extending along the third direction.

37. The manufacturing method of claim 33, wherein, The forming of the conductive structure comprises: forming a first portion of the conductive structure in the sixth recess, and forming a second portion of the conductive structure in the seventh recess; the first portion being in contact with one end of the remaining semiconductor pillar.

38. The manufacturing method according to claim 27 or 37, wherein The removing process comprises a wet etching process.

39. The manufacturing method according to claim 27 or 37, wherein The first isolation structure comprises a first end surface and a second end surface opposite to each other along the first direction, and the second isolation structure comprises a third end surface and a fourth end surface opposite to each other along the first direction; The first end surface, the third end surface, a surface of the first portion away from the semiconductor body along the first direction, and a surface of the second portion away from the gate structure along the first direction are aligned along the second direction.

40. The manufacturing method of claim 27 or 37, wherein: a size of a portion of the first portion close to the second portion along the third direction is a first size; The second portion has a second dimension in the third direction, which is close to the first portion; The second dimension is greater than the first dimension.

41. The manufacturing method according to claim 27 or 37, wherein The method further comprises: Removing the gate material layer covering the bottom surface of the semiconductor layer to form a gate structure.

42. The method of manufacturing according to claim 41, wherein, The method further comprises: Forming a capacitor structure connected to the conductive structure along the first direction away from one end of the semiconductor body.

43. The method of manufacturing according to claim 42, wherein, The method further comprises: Doping a first end portion of the remaining semiconductor pillar away from the bottom surface of the semiconductor layer along the first direction to form one of a source or a drain before forming the capacitor structure; Thinning the semiconductor layer to expose a second end portion of the remaining semiconductor pillar opposite to the first end portion along the first direction after forming the capacitor structure; and Doping the second end portion to form the other of the source or the drain; The region between the source and the drain in the remaining semiconductor pillar constitutes a channel region; the channel region, the source, and the drain constitute the semiconductor body.

44. The manufacturing method of claim 42, wherein, The capacitor structure comprises a fifth end surface and a sixth end surface opposite along the first direction; At least part of the surface of the first portion away from the surface of the semiconductor body along the first direction and the surface of the second portion away from the surface of the semiconductor body along the first direction is in contact with the fifth end surface.

45. The manufacturing method of claim 22, wherein, The method further comprises: Forming a plurality of semiconductor structures arranged in an array along the second direction and the third direction; The plurality of semiconductor structures arranged along the second direction comprises first semiconductor structures and second semiconductor structures arranged alternately; the first semiconductor structure and the second semiconductor structure arranged adjacently constitute a semiconductor structure group.

46. The method of manufacturing according to claim 45, wherein, The forming of the plurality of semiconductor structures arranged in an array along the second direction and the third direction comprises: Forming a first gate structure on the side of a first semiconductor body close to a second semiconductor body and forming a first conductive structure on the side of the first semiconductor body along the first direction to form the first semiconductor structure; and Forming a second gate structure on the side of the second semiconductor body close to the first gate structure and forming a second conductive structure on the side of the second semiconductor body along the first direction to form the second semiconductor structure.

47. The manufacturing method of claim 22, wherein, The method further comprises: Forming a plurality of bit lines extending along the second direction and arranged at intervals along the third direction, each of the bit lines being connected to one end of a row of semiconductor bodies away from the conductive structure along the first direction.

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