Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises an active column which comprises a first doped region, a channel region and a second doped region which are sequentially arranged along a first direction; wherein the first direction is the height direction of the active column; the gate structure covers the first side wall of the channel region; the first barrier layer at least covers the second side wall of the first doped region; wherein the first side wall is continuous with the second side wall.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and relate to, but are not limited to, a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] In recent years, the semiconductor integrated circuit industry has experienced rapid growth, and the feature size of semiconductor devices has been continuously reduced, and the integration density of memories has been increasingly high, and the performance has been increasingly powerful. For example, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM) and NAND memory are commonly used semiconductor memory devices in computers.

[0003] Through improving the circuit design and manufacturing process, the planar storage unit is scaled to a smaller size. However, as the feature size of the storage unit approaches the lower limit, the planar process and manufacturing technology become challenging and costly. Therefore, how to further improve the electrical performance and manufacturing yield of the semiconductor structure has become a problem to be solved in the industry. SUMMARY

[0004] The present disclosure provides a semiconductor structure and a manufacturing method thereof.

[0005] In a first aspect, the present disclosure provides a semiconductor structure, comprising:

[0006] an active pillar, comprising: a first doped region, a channel region and a second doped region arranged in sequence along a first direction; wherein the first direction is a height direction of the active pillar;

[0007] a gate structure covering a first sidewall of the channel region;

[0008] a first barrier layer covering at least a second sidewall of the first doped region; wherein the first sidewall and the second sidewall are continuous.

[0009] In some embodiments, the semiconductor structure further comprises:

[0010] a first isolation structure covering the gate structure and at least part of the first barrier layer; wherein the gate structure is located between the first isolation structure and the channel region; and at least part of the first barrier layer is located between the first isolation structure and the first doped region.

[0011] In some embodiments, the semiconductor structure comprises:

[0012] a plurality of active pillars arranged at intervals along a second direction; wherein the second direction is perpendicular to the first direction.

[0013] Two of the first sidewalls opposite to each other of two adjacent active pillars are respectively covered with the gate structure; the first isolation structure is located between the gate structures on the two of the first sidewalls opposite to each other of the two adjacent active pillars;

[0014] Two of the second sidewalls opposite to each other of two adjacent active pillars are respectively covered with the first barrier layer.

[0015] In some embodiments, the first barrier layer comprises:

[0016] A first sub-barrier layer covering the second sidewall;

[0017] A second sub-barrier layer covering a surface of the first isolation structure close to the first doped region in the first direction; wherein the first sub-barrier layer is connected with the second sub-barrier layer.

[0018] In some embodiments, a size of the first sub-barrier layer in the second direction is substantially equal to a size of the gate structure in the second direction.

[0019] In some embodiments, the first isolation structure comprises:

[0020] A recess located at a surface of the first isolation structure close to the first doped region in the first direction; wherein at least part of the second sub-barrier layer is located in the recess.

[0021] In some embodiments, the semiconductor structure further comprises:

[0022] A second barrier layer covering at least a third sidewall of the second doped region; wherein the first sidewall and the third sidewall are continuous.

[0023] In some embodiments, the semiconductor structure comprises:

[0024] A plurality of active pillars; wherein two of the third sidewalls opposite to each other of two adjacent active pillars are respectively covered with the second barrier layer.

[0025] In some embodiments, the second barrier layer is used to block impurity ions in the gate structure from entering the second doped region.

[0026] In some embodiments, the first barrier layer is used to block impurity ions in the gate structure from entering the first doped region.

[0027] In some embodiments, a material of the first barrier layer comprises silicon nitride.

[0028] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0029] forming an active pillar; wherein the active pillar comprises a first doped region, a channel region and a second doped region arranged in sequence along a first direction, the first direction being a height direction of the active pillar;

[0030] forming a gate structure covering a first sidewall of the channel region;

[0031] forming a first blocking layer covering at least a second sidewall of the first doped region; wherein the first sidewall and the second sidewall are continuous.

[0032] In some embodiments, the method further comprises:

[0033] forming a first isolation structure covering the gate structure and at least part of the first blocking layer; wherein the gate structure is between the first isolation structure and the channel region; at least part of the first blocking layer is between the first isolation structure and the first doped region.

[0034] In some embodiments, the method further comprises:

[0035] providing a substrate;

[0036] etching the substrate to form trenches and the active pillars arranged alternately along a second direction; wherein the trenches expose two opposite first sidewalls and two opposite second sidewalls of two adjacent active pillars;

[0037] the forming of the gate structure covering the first sidewall of the channel region comprises:

[0038] forming the gate structure on the two opposite first sidewalls exposed by the trenches respectively;

[0039] the forming of the first isolation structure covering the gate structure and at least part of the first blocking layer comprises:

[0040] forming the first isolation structure between the gate structures on at least the two opposite first sidewalls exposed by the trenches.

[0041] In some embodiments, the forming of the first blocking layer covering at least the second sidewall of the first doped region comprises:

[0042] forming an initial blocking layer covering a top surface of the active pillar, the two opposite second sidewalls exposed by the trenches and the first isolation structure;

[0043] forming a sacrificial layer covering the initial blocking layer and filling the trenches;

[0044] etching back the sacrificial layer until the initial barrier layer covering the second sidewall is exposed; wherein the initial barrier layer remaining and covering the second sidewall constitutes a first sub-barrier layer, the initial barrier layer remaining and covering the first isolation structure constitutes a second sub-barrier layer, and the first sub-barrier layer and the second sub-barrier layer are connected and constitute the first barrier layer.

[0045] In some embodiments, the manufacturing method further comprises:

[0046] forming a gate material layer covering the trench sidewall and bottom wall;

[0047] the forming the first isolation structure covering the gate structure and at least part of the first barrier layer comprises:

[0048] forming an initial first isolation structure in the trench with the gate material layer; wherein a height of the initial first isolation structure is greater than or equal to a height of the active pillar;

[0049] etching the initial first isolation structure and the gate material layer to form the first isolation structure and an initial gate structure; wherein the initial gate structure covers the first sidewall, a third sidewall of the second doped region, and a bottom wall of the trench;

[0050] the forming the gate structure on each of the two opposite first sidewalls exposed by the trench respectively comprises:

[0051] removing the initial gate structure covering the third sidewall and the bottom wall of the trench to form the gate structure on each of the two opposite first sidewalls respectively.

[0052] In some embodiments, the etching the initial first isolation structure comprises:

[0053] etching the initial first isolation structure to form the first isolation structure with a recess; wherein the recess is located on a surface of the first isolation structure close to the first doped region in the first direction;

[0054] the forming the initial barrier layer covering the first isolation structure comprises:

[0055] forming the initial barrier layer filling the recess; wherein at least part of the second sub-barrier layer is located in the recess.

[0056] In some embodiments, the manufacturing method further comprises:

[0057] forming a second barrier layer covering at least a third sidewall of the second doped region; wherein the first sidewall and the third sidewall are continuous.

[0058] In the embodiments of the present disclosure, the first side wall of the gate structure covers the channel region, the first blocking layer covers at least the second side wall of the first doped region, and the first side wall and the second side wall are continuous. In this way, the first blocking layer can reduce the mutual diffusion of impurity ions in the gate structure and the first doped region, and reduce the problem of leakage between the gate structure and the conductive structure connected to the first doped region, thereby improving the electrical performance of the semiconductor structure and improving the manufacturing yield. BRIEF DESCRIPTION OF DRAWINGS

[0059] Figures la to Id A process flow diagram of a semiconductor structure provided by the embodiments of the present disclosure is provided.

[0060] Figure 2 A schematic diagram of a semiconductor structure provided by the embodiments of the present disclosure is provided.

[0061] Figure 3 A schematic diagram of a first isolation structure in a semiconductor structure provided by the embodiments of the present disclosure is provided.

[0062] Figure 4 A schematic diagram of another semiconductor structure provided by the embodiments of the present disclosure is provided.

[0063] Figure 5 A step flow diagram of a manufacturing method of a semiconductor structure provided by the embodiments of the present disclosure is provided.

[0064] Figures 6a to 6h A schematic diagram of the structure of each step in a manufacturing method of a semiconductor structure provided by the embodiments of the present disclosure is provided. DETAILED DESCRIPTION

[0065] In order to facilitate the understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms, and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood, and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0066] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present disclosure. However, it should be apparent to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid obscuring the present disclosure, some technical features that are well known in the art are not described; that is, all features of the actual embodiments can not be described here, and well-known functions and structures are not described in detail.

[0067] Generally, the terminology can be understood at least in part from usage in context. For example, terms, such as "one or more" as used herein, can be taken to describe any feature, structure, or characteristic in the singular or can be taken to describe a combination of features, structures or characteristics in the plural, depending in part on the context in which such terms are used. Similarly, terms, such as "a," "an," or "the," again, can be taken to convey a singular usage or a plural usage, depending at least in part on the context in which such terms are used. Additionally, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and instead can allow for existence of additional factors not necessarily expressly described, again, at least in part, depending on the context in which the term is used.

[0068] Unless otherwise defined, the terms used in this disclosure are intended to be descriptive only and not to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0069] For a thorough understanding of the present disclosure, reference will be made to the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0070] In some embodiments, the memory can include a memory cell array, and the memory cell array can include a plurality of arrayed memory cells, each of which can be formed by one memory node and one transistor. The memory in the present disclosure includes, but is not limited to, dynamic random access memory, static random access memory, ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), and the like. Hereinafter, a dynamic random access memory is taken as an example for illustration, and the memory node in the dynamic random access memory can be a capacitor, so that one transistor and one capacitor in the memory cell form a 1T1C (1 Transistor 1 Capacitor) structure.

[0071] Here and hereinafter, the first direction can be a direction perpendicular to the substrate surface (e.g., the height direction of the active pillar in the following), and the second direction can be a direction parallel to the substrate surface, and the included angle between the second direction and the first direction can be 90 degrees. In order to clearly describe the present disclosure, the first direction is taken as the Z direction in the drawing and the second direction is taken as the X direction in the drawing in the following embodiments for illustration. It should be noted that the description of the direction in the following embodiments is only used to illustrate the present disclosure and does not limit the scope of the present disclosure.

[0072] As shown in FIG. 1, a semiconductor structure 10 provided by the present disclosure includes a substrate 1, a plurality of active pillars 2, and a plurality of memory cells 3. Figures la to Id As shown in FIG. 2, a manufacturing method of the semiconductor structure 10 provided by the present disclosure includes the following steps. Figures la to Id The manufacturing method includes at least the following steps:

[0073] As shown in FIG. 2, a manufacturing method of the semiconductor structure 10 provided by the present disclosure includes the following steps. Figure laAs shown, a plurality of trenches T spaced apart along the X direction (second direction) can be formed in the substrate 100 using processes such as photolithography and etching. The plurality of trenches T divide the substrate 100 into a plurality of active pillars 101 spaced apart along the X direction. The active pillars 101 can be used to form transistors in the memory cell. The material of the substrate 100 may include a single element semiconductor material, such as silicon (Si) or germanium (Ge), or a compound semiconductor material, such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP). The substrate 100 may also be doped, or include doped and undoped regions. In some embodiments, two doped regions may be formed at both ends of the active pillar 101 along the Z direction (first direction). The doped regions may be formed by processes such as diffusion and ion implantation. For example, a first doped region 102 and a second doped region 103 may be formed at both ends of the active pillar 101 along the Z direction, respectively.

[0074] like Figure lb As shown, deposition and other processes can be used to form second isolation structures 150 at intervals in multiple trenches T. Then, a gate material layer 110 covering the inner wall of the trench T is formed in the trench T that is not filled with the second isolation structure 150. The gate material layer 110 includes but is not limited to conductive materials such as tungsten (W), copper (Cu), and titanium nitride (TiN). An initial first isolation structure 120 is then formed in the trench T in which the gate material layer 110 is formed. It can be understood that the gate material layer 110 can be used to form two gate structures respectively located on two opposite sidewalls of the trench T. In some embodiments, before forming the gate material layer 110, a gate dielectric layer ( Figure lb not shown).

[0075] like Figure lc As shown, a portion of the gate material layer 110 and the initial first isolation structure 120 are etched away to form a first isolation structure 121 and an initial gate structure 111. It should be noted that the purpose of this step is to etch the gate material layer 110 to a predetermined height, thereby forming a gate structure at a designated location on the active pillar 101. However, due to the different etching rates of the gate material layer 110 and the initial first isolation structure 120, the top surface of the first isolation structure 121 is higher than the top surface of the initial gate structure 111. In other words, a narrow groove 160 is formed in the space between the first isolation structure 121 and the sidewalls of the trench T and above the initial gate structure 111. In addition, due to the unevenness of the etching process, a concave portion 122 is formed on the top surface of the first isolation structure 121, i.e., the top surface of the first isolation structure 121 has a low center and high sides. This further increases the depth of the groove 160, making it more difficult to fill the groove 160 with isolation material.

[0076] like Figure Id As shown, an isolation material 170 is filled in the trench T in which the first isolation structure 121 and the initial gate structure 111 are formed, thereby preventing leakage problems from occurring between the gate structure and the conductive structure (such as capacitor contact) subsequently formed on the upper surface of the substrate 100, and preventing leakage problems from occurring between the gate structure and the first doped region 102 of the active pillar 101 close to one end of the upper surface of the substrate 100. However, due to the narrow width of the groove 160, gaps 161 are easily generated in the groove 160 when filling the isolation material 170, which increases the risk of leakage problems between the gate structure and the conductive structure subsequently formed on the upper surface of the substrate 100. In addition, in the above process steps, after the gate material layer 110 is deposited, the impurity ions in the gate material layer 110 easily diffuse into the first doped region 102, resulting in poor electrical performance of the transistor and reduced manufacturing yield. For example, the material of the gate material layer 110 is tungsten, and after tungsten is deposited in the trench T, some boron ions (B 3+ ) will diffuse into the first doped region 102, affecting the electrical performance of the transistor. In some embodiments, the silicon oxide layer formed on the sidewall of the trench T can be nitrided to block the boron ions (B 3+ ) diffuses into the first doped region 102.

[0077] like Figure 2 As shown, the present disclosure provides a semiconductor structure 20, including: an active pillar 201, including: a first doped region 202, a channel region 204 and a second doped region 203 arranged in sequence along a first direction; wherein the first direction is the height direction of the active pillar 201; a gate structure 212, covering the first sidewall 201a of the channel region 204; a first barrier layer 230, covering at least the second sidewall 201b of the first doped region 202; wherein the first sidewall 201a and the second sidewall 201b are continuous.

[0078] In the embodiments of the present disclosure, the semiconductor structure 20 includes at least one active pillar 201, which can be used to form a transistor in a 1T1C structure of a memory cell. The material of the active pillar 201 can include a single-element semiconductor material, such as silicon (Si), germanium (Ge), etc., or a compound semiconductor material, such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc. The active pillar 201 includes, in sequence along a first direction (i.e., the Z direction), a first doped region 202, a channel region 204, and a second doped region 203. The first doped region 202 and the second doped region 203 are located at two ends of the active pillar 201 and can be formed by diffusion, ion implantation, etc. It can be understood that, for a PMOS transistor, the first doped region 202 and the second doped region 203 are P-type doped, and the channel region 204 is N-type doped; for an NMOS transistor, the first doped region 202 and the second doped region 203 are N-type doped, and the channel region 204 is P-type doped.

[0079] In some embodiments, one of the first doped region 202 and the second doped region 203 can be connected to a bit line structure, and the other is connected to a capacitor structure. For example, the first doped region 202 is connected to the capacitor structure through a capacitor contact, and the second doped region 203 is connected to the bit line structure through a bit line contact. It should be noted that the capacitor structure in the present disclosure can also be replaced by any other form of storage node (Storage Node), such as a magnetic tunnel junction (MTJ), a GST (Ge x Sb y Te z ) cell, etc., and the capacitor contact can be a storage node contact (SNC) corresponding to the storage node.

[0080] The gate structure 212 can cover a first sidewall 201a of the channel region 204. The gate structure 212 can include a gate dielectric layer and a gate electrode, which can be a word line. The gate dielectric layer includes, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k material, etc., and the gate electrode includes, but is not limited to, a conductive material such as copper (Cu), tungsten (W), titanium nitride (TiN), etc.

[0081] The first barrier layer 230 covers at least the second sidewall 201b of the first doped region 202, and the first sidewall 201a and the second sidewall 201b are continuous. Exemplarily, the first barrier layer 230 can also be disposed around the first doped region 202 of the active pillar 201. The material of the first barrier layer 230 includes, but is not limited to, silicon nitride (Si3N4), silicon oxynitride (SiON), etc. The first barrier layer 230 can be used to reduce the diffusion of impurity ions in the gate structure 212 into the first doped region 202, and the diffusion of impurity ions generated in the process of forming the gate structure 212 into the first doped region 202. The first barrier layer 230 can also be used to reduce the diffusion of impurity ions in the first doped region 202 into the gate structure 212. In addition, the first barrier layer 230 can be a dense insulating material, and there is no gap or void in the first barrier layer 230, so the first barrier layer 230 can also effectively isolate the gate structure 212 from the storage node contact formed on the top surface of the first doped region 202, thereby reducing the occurrence of the leakage problem.

[0082] That is, the first barrier layer 230 can reduce the mutual diffusion of impurity ions in the gate structure 212 and impurity ions in the first doped region 202, and reduce the leakage problem between the gate structure 212 and the conductive structure connected to the first doped region 202, thereby improving the electrical performance of the semiconductor structure 20 and improving the manufacturing yield.

[0083] In some embodiments, the first barrier layer 230 is configured to block impurity ions in the gate structure 212 from entering the first doped region 202.

[0084] In some embodiments, the material of the first barrier layer 230 includes silicon nitride.

[0085] In the embodiments of the present disclosure, the first barrier layer 230 can block impurity ions in the gate structure 212 from entering the first doped region 202. Here, the impurity ions in the gate structure 212 can refer to the impurity ions existing in the material of the gate structure 212 itself, or the impurity ions generated by the precursors, reactants, etc. used in the process of forming the gate structure 212. Exemplarily, the gate of the gate structure 212 is a metal material tungsten, and the first barrier layer 230 can be a linear silicon nitride (Liner Si3N4), so the first barrier layer 230 can block the diffusion of boron ions (B 3+ ) into the first doped region 202, thereby improving the electrical performance of the semiconductor structure 20 and the manufacturing yield. It should be noted that the material of the first barrier layer 230 can be any silicon nitride or a mixture including a silicon nitride component.

[0086] In some embodiments, as Figure 3As shown, the semiconductor structure 20 also includes: a first isolation structure 221, covering the gate structure 212 and at least part of the first barrier layer 230; wherein the gate structure 212 is located between the first isolation structure 221 and the channel region 204; at least part of the first barrier layer 230 is located between the first isolation structure 221 and the first doped region 202.

[0087] In the disclosed embodiment, the semiconductor structure 20 further includes a first isolation structure 221. A gate structure 212 is located between the first isolation structure 221 and the channel region 204. In the Z direction, the top surface of the gate structure 212 is lower than the top surface of the first isolation structure 221. In other words, the space between the first isolation structure 221 and the active pillar 201 and above the gate structure 212 forms a narrow groove 260. At least a portion of the first barrier layer 230 is located between the first isolation structure 221 and the first doped region 202, and the first barrier layer 230 can fill the groove 260. The first barrier layer 230 does not contain gaps or voids, thereby reducing leakage between the gate structure 212 and the storage node contact formed on the top surface of the first doped region 202. For example, the first barrier layer 230 can be formed by depositing linear silicon nitride, so that the first barrier layer 230 densely fills the groove 260, preventing the formation of gaps when filling the groove 260.

[0088] In some embodiments, as Figure 4 As shown, the semiconductor structure 20 includes: a plurality of active pillars 201, arranged at intervals along a second direction; wherein the second direction is perpendicular to the first direction; the two first side walls 201a opposite to two adjacent active pillars 201 are respectively covered with the gate structure 212; the first isolation structure 221 is located between the gate structures 212 on the two first side walls 201a opposite to two adjacent active pillars 201; and the two second side walls 201b opposite to two adjacent active pillars 201 are respectively covered with the first blocking layer 230.

[0089] In the embodiments of the present disclosure, reference Figure 4 The semiconductor structure 20 may include a plurality of active pillars 201 spaced apart along the X direction (second direction). Two opposing first sidewalls 201a of two adjacent active pillars 201 are respectively covered with a gate structure 212. For example, in a mirror single gate (MSG) vertical transistor structure, the gate structures of two adjacent vertical transistors are arranged in a mirror-symmetrical manner.

[0090] The first isolation structure 221 is located between the gate structures 212 on the two opposite first sidewalls 201a of the two adjacent active pillars 201, that is, the first isolation structure 221 can be used to isolate the two opposite gate structures 212 of the two adjacent transistors. The material of the first isolation structure 221 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, spin-on dielectric, etc. Exemplarily, the first isolation structure 221 can also have an air gap.

[0091] The two second sidewalls 201b of the two adjacent active pillars 201 can be respectively covered with a first blocking layer 230. In this way, the two grooves 260 formed between the first isolation structure 221 and the two adjacent active pillars 201 can be filled with the two first blocking layers 230, and there is no gap or hole in the first blocking layer 230 to reduce the problem of leakage occurring between the gate structure 212 and the storage node contact formed on the top surface of the first doped region 202. In addition, the first blocking layer 230 can also reduce the mutual diffusion of impurity ions in the gate structure 212 and the impurity ions in the first doped region 202.

[0092] In some embodiments, as shown in Figure 4 the first blocking layer 230 includes a first sub-blocking layer 231 covering the second sidewall 201b, and a second sub-blocking layer 232 covering the surface of the first isolation structure 221 close to the first doped region 202 in the first direction, and the first sub-blocking layer 231 is connected to the second sub-blocking layer 232.

[0093] In the embodiments of the present disclosure, the first blocking layer 230 includes a first sub-blocking layer 231 and a second sub-blocking layer 232. The first sub-blocking layer 231 covers the second sidewall 201b, and the second sub-blocking layer 232 can cover the top surface of the first isolation structure 221 in the Z direction, thereby further reducing the problem of leakage occurring between the gate structure 212 and the storage node contact formed on the top surface of the first doped region 202. Exemplarily, as shown in Figure 4 , the first sub-blocking layer 231 and the second sub-blocking layer 232 on the two second sidewalls 201b of the two adjacent active pillars 201 can present an "H" shaped topography. It can be understood that, since the first sub-blocking layer 231 and the second sub-blocking layer 232 can be formed synchronously by using a deposition process, the first sub-blocking layer 231 is connected to the second sub-blocking layer 232. Further, the first sub-blocking layer 231 and the second sub-blocking layer 232 are of the same material and form an integral whole.

[0094] In some embodiments, as shown in Figure 4As shown, the size of the first sub-blocking layer 231 in the second direction is substantially equal to the size of the gate structure 212 in the second direction.

[0095] In the embodiments of the present disclosure, the size of the first sub-blocking layer 231 in the X direction is substantially equal to the size of the gate structure 212 in the X direction, that is, the first sub-blocking layer 231 can densely fill the groove 260, and there is no gap or hole in the groove 260, that is, there is no leakage path between the gate structure 212 and the storage node contact formed on the top surface of the first doped region 202.

[0096] In some embodiments, as shown in FIG. 2B, the semiconductor structure 20 further includes a first sub-blocking layer 231, which is located in the groove 260 and covers at least part of the top surface of the gate structure 212. Figure 4 As shown, the first isolation structure 221 includes a recess 222 located on the surface of the first isolation structure 221 close to the first doped region 202 in the first direction; and at least part of the second sub-blocking layer 232 is located in the recess 222.

[0097] In the embodiments of the present disclosure, due to the non-uniformity of the etching process, the top surface of the first isolation structure 221 formed will have a recess 222, that is, the top surface of the first isolation structure 221 has a morphology of being low in the middle and high on both sides. In this case, at least part of the second sub-blocking layer 232 is located in the recess 222, that is, the second sub-blocking layer 232 can fill the recess 222, thereby improving the top surface morphology of the first isolation structure 221 and being beneficial to improving the yield of subsequent processes.

[0098] In some embodiments, as shown in FIG. 2B, the semiconductor structure 20 further includes a first sub-blocking layer 231, which is located in the groove 260 and covers at least part of the top surface of the gate structure 212. Figure 2 As shown, the semiconductor structure 20 further includes a second blocking layer 240 covering at least the third side wall 201c of the second doped region 203; and the first side wall 201a and the third side wall 201c are continuous.

[0099] In the embodiments of the present disclosure, the second barrier layer 240 covers at least the third sidewall 201c of the second doped region 203, and the first sidewall 201a and the third sidewall 201c are continuous. For example, the second barrier layer 240 can also be arranged around the second doped region 203 of the active pillar 201. The material of the second barrier layer 240 includes, but is not limited to, silicon nitride (Si3N4), silicon oxynitride (SiON), etc. The second barrier layer 240 can be used to reduce the diffusion of impurity ions in the gate structure 212 into the second doped region 203, and the diffusion of impurity ions generated in the process of forming the gate structure 212 into the second doped region 203. The second barrier layer 240 can also be used to reduce the diffusion of impurity ions in the second doped region 203 into the gate structure 212. In addition, the second barrier layer 240 can be a dense insulating material, and there is no gap or hole in the second barrier layer 240, so the second barrier layer 240 can also effectively isolate the gate structure 212 from the conductive structure (such as a bit line contact) formed on the bottom surface of the second doped region 203, thereby reducing the occurrence of the leakage problem.

[0100] In some embodiments, the second barrier layer 240 is used to block impurity ions in the gate structure 212 from entering the second doped region 203.

[0101] In the embodiments of the present disclosure, the second barrier layer 240 can block impurity ions in the gate structure 212 from entering the second doped region 203. Here, the impurity ions in the gate structure 212 can refer to the impurity ions existing in the material of the gate structure 212 itself, or the impurity ions generated by the precursors, reactants, etc. used in the process of forming the gate structure 212. For example, the gate of the gate structure 212 is a metal material tungsten, and the second barrier layer 240 can be a linear silicon nitride (Liner Si3N4), so the second barrier layer 240 can block the diffusion of boron ions (B 3+ ) into the second doped region 203, thereby improving the electrical performance and manufacturing yield of the semiconductor structure 20. It should be noted that the material of the second barrier layer 240 can be any silicon nitride or a mixture including a silicon nitride component. The materials of the second barrier layer 240 and the first barrier layer 230 can be the same or different.

[0102] In some embodiments, as shown in Figure 4 , the semiconductor structure 20 includes: a plurality of active pillars 201; wherein the second barrier layer 240 is arranged on the two opposite third sidewalls 201c of each two adjacent active pillars 201, respectively.

[0103] In the embodiments of the present disclosure, the two opposite third side walls 201c of the two adjacent active pillars 201 can be respectively covered with a second blocking layer 240. In this way, the two grooves formed between the first isolation structure 221 and the two opposite third side walls 201c can be filled with the two second blocking layers 240, and there is no gap or hole in the second blocking layer 240, so as to reduce the leakage problem between the gate structure 212 and the conductive structure (such as a bit line contact) formed on the bottom surface of the second doped region 203. In addition, the second blocking layer 240 can also reduce the mutual diffusion of impurity ions in the gate structure 212 and the second doped region 203.

[0104] As shown in Figure 5 The present disclosure provides a manufacturing method of a semiconductor structure, Figures 6a to 6h which is a schematic diagram of a structure corresponding to the manufacturing method, and the manufacturing method comprises the following steps:

[0105] Step S10, forming an active pillar; wherein the active pillar comprises a first doped region, a channel region and a second doped region arranged in sequence along a first direction, and the first direction is a height direction of the active pillar;

[0106] Step S20, forming a gate structure covering a first side wall of the channel region;

[0107] Step S30, forming a first blocking layer covering at least a second side wall of the first doped region; wherein the first side wall and the second side wall are continuous.

[0108] It should be understood that Figure 5 the steps shown in the above description are not exclusive, and other steps can also be performed before, after or between any of the steps shown in the above description; Figure 5 each step shown in the above description can be adjusted in sequence according to actual needs.

[0109] In the embodiments of the present disclosure, with reference to Figure 6aThe active pillar 301 can be formed in the substrate 300 by etching or other processes, and can be used to form a transistor in a 1T1C memory cell structure. The material of the active pillar 301 can include a single-element semiconductor material, such as silicon, germanium, etc., or a compound semiconductor material, such as gallium nitride, gallium arsenide, or indium phosphide, etc. The active pillar 301 includes a first doped region 302, a channel region 304, and a second doped region 303 in sequence along a first direction (i.e., the Z direction). The first doped region 302 and the second doped region 303 are located at both ends of the active pillar 301, and can be formed by diffusion, ion implantation, or other processes. It can be understood that, for a PMOS transistor, the first doped region 302 and the second doped region 303 are P-type doped, and the channel region 304 is N-type doped; for an NMOS transistor, the first doped region 302 and the second doped region 303 are N-type doped, and the channel region 304 is P-type doped.

[0110] In some embodiments, one of the first doped region 302 and the second doped region 303 can be connected to a bit line structure, and the other can be connected to a capacitor structure. For example, the first doped region 302 is connected to the capacitor structure through a capacitor contact, and the second doped region 303 is connected to the bit line structure through a bit line contact. It should be noted that the capacitor structure in the present disclosure can also be replaced by any other form of storage node, such as a magnetic tunnel junction, a GST cell, etc., and the capacitor contact can be a storage node contact corresponding to the storage node.

[0111] Reference Figure 6c The gate structure 312 covering the first sidewall 301a of the channel region 304 can be formed by deposition, etching, or other processes. The gate structure 312 can include a gate dielectric layer and a gate electrode, the gate electrode can be a word line, and the gate dielectric layer can include but is not limited to silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant material, etc., and the gate electrode can include but is not limited to a conductive material such as copper, tungsten, titanium nitride, etc. It should be noted that Figure 6c Only the initial gate structure 311 for forming the gate structure 312 is shown in FIG. 3B, and the gate structure 312 can be formed by removing part of the initial gate structure 311 at the bottom wall of the trench T and removing part of the initial gate structure 311 on the third sidewall 301c. For example, the bottom of one of the initial gate structures 311 in the trench T is etched to be disconnected, thereby forming two separate gate structures 312.

[0112] Reference Figure 6fA first blocking layer 330 covering at least the second sidewall 301b of the first doped region 302 can be formed by deposition, etching, or the like, and the first sidewall 301a and the second sidewall 301b are continuous. Exemplarily, the first blocking layer 330 can also be formed around the first doped region 302 of the active pillar 301. The material of the first blocking layer 330 includes, but is not limited to, silicon nitride, silicon oxynitride, or the like. The first blocking layer 330 can be used to reduce the diffusion of impurity ions in the gate structure 312 into the first doped region 302, and the diffusion of impurity ions generated in the process of forming the gate structure 312 into the first doped region 302. The first blocking layer 330 can also be used to reduce the diffusion of impurity ions in the first doped region 302 into the gate structure 312. In addition, the first blocking layer 330 can be a dense insulating material, and there is no gap or void in the first blocking layer 330, so the first blocking layer 330 can also effectively isolate the gate structure 312 from the storage node contact formed on the top surface of the first doped region 302, thereby reducing the occurrence of leakage problems.

[0113] That is, the first blocking layer 330 can reduce the mutual diffusion of impurity ions in the gate structure 312 and impurity ions in the first doped region 302, and reduce the leakage problem between the gate structure 312 and the conductive structure connected to the first doped region 302, thereby improving the electrical performance of the semiconductor structure 30 and improving the manufacturing yield.

[0114] In some embodiments, referring to Figures 6b to 6h , the manufacturing method further includes: forming a first isolation structure 321 covering the gate structure 312 and at least part of the first blocking layer 330; wherein the gate structure 312 is located between the first isolation structure 321 and the channel region 304; and at least part of the first blocking layer 330 is located between the first isolation structure 321 and the first doped region 302.

[0115] In the embodiments of the present disclosure, the first isolation structure 321 can be formed by deposition, etching and the like. The finally formed gate structure 312 can be located between the first isolation structure 321 and the channel region 304, and in the Z direction, the top surface of the gate structure 312 is lower than the top surface of the first isolation structure 321, that is, the space between the first isolation structure 321 and the active pillar 301 and above the gate structure 312 forms a narrow-width groove 360. At least part of the first barrier layer 330 is located between the first isolation structure 321 and the first doped region 302, and the first barrier layer 330 can be filled in the groove 360, and there is no gap or hole in the first barrier layer 330, so as to reduce the problem of leakage between the gate structure 312 and the storage node formed on the top surface of the first doped region 302. Exemplarily, the first barrier layer 330 can be formed by depositing linear silicon nitride, so that the first barrier layer 330 densely fills the groove 360 and prevents the gap from being generated when filling the groove 360.

[0116] In some embodiments, referring to Figures 6a to 6h , the manufacturing method further comprises: providing a substrate 300; etching the substrate 300 to form trenches T and the active pillars 301 which are alternately arranged along a second direction; wherein the trenches T expose two opposite first sidewalls 301a and two opposite second sidewalls 301b of two adjacent active pillars 301; forming the gate structure 312 covering the first sidewall 301a of the channel region 304, comprising: forming the gate structure 312 on the two opposite first sidewalls 301a exposed by the trenches T, respectively; forming the first isolation structure 321 covering the gate structure 312 and at least part of the first barrier layer 330, comprising: forming the first isolation structure 321 between the gate structures 312 on the two opposite first sidewalls 301a exposed by the trenches T.

[0117] In the embodiments of the present disclosure, referring to Figure 6a , a plurality of trenches T can be formed in the substrate 300 by photolithography, etching and the like, and the plurality of trenches T divide the substrate 300 into a plurality of active pillars 301 which are spaced apart along the X direction (the second direction), and the active pillars 301 can be used to form transistors in the memory cell. The trenches T expose two opposite first sidewalls 301a and two opposite second sidewalls 301b of two adjacent active pillars 301.

[0118] Referring to Figure 6c , the gate structure 312 can be formed on the two opposite first sidewalls 301a exposed by the trenches T by deposition, etching and the like, and it should be noted that Figure 6cOnly the initial gate structure 311 for forming the gate structure 312 is shown, the gate structure 312 can be formed by removing part of the initial gate structure 311 of the bottom wall of the trench T and removing part of the initial gate structure 311 on the third side wall 301c, for example, the bottom of one initial gate structure 311 in the trench T is etched to be disconnected, thereby forming two separated gate structures 312.

[0119] Reference is made to Figure 6c The first isolation structure 321 can be formed between the gate structures 312 on the opposite two first side walls 301a exposed by the trench T by using deposition, etching and other processes. It can be understood that the first isolation structure 321 can be etched synchronously with the initial gate structure 311.

[0120] Exemplarily, reference is made to Figure 6b The second isolation structure 350 can be formed in the middle of the plurality of trenches T by using deposition and other processes, and the mask layer 380 can be formed on the top surface of the second isolation structure 350, where the mask layer 380 can be used to define the formation area of the gate material layer 310 (i.e. the trench T not filled with the second isolation structure 350), and the material of the mask layer 380 includes but is not limited to silicon nitride. Then the gate material layer 310 covering the inner wall of the trench T is formed in the trench T not filled with the second isolation structure 350. Then the initial first isolation structure 320 is formed in the trench T with the gate material layer 310. Finally, reference is made to Figure 6c The part of the gate material layer 310 and the initial first isolation structure 320 are etched to form the first isolation structure 321 and the initial gate structure 311.

[0121] In some embodiments, reference is made to Figures 6d to 6f The first barrier layer 330 covering at least the second side wall 301b of the first doped region 302 includes: forming an initial barrier layer 333 covering the top surface of the active pillar 301, the opposite two second side walls 301b exposed by the trench T and the first isolation structure 321; forming a sacrificial layer 390 covering the initial barrier layer 333 and filling the trench T; etching back the sacrificial layer 390 until the initial barrier layer 333 covering the second side wall 301b is exposed; wherein the initial barrier layer 333 covering the second side wall 301b retained constitutes a first sub-barrier layer 331, the initial barrier layer 333 covering the first isolation structure 321 retained constitutes a second sub-barrier layer 332, and the first sub-barrier layer 331 and the second sub-barrier layer 332 are connected and constitute the first barrier layer 330.

[0122] In the embodiments of the present disclosure, reference is made to Figure 6dAn initial barrier layer 333 can be formed on the mask layer 380 on the top surface of the active pillar 301, and on the top surface of the first isolation structure 321 and the opposite two second sidewalls 301b exposed by the trench T, by deposition or other processes. The material of the initial barrier layer 333 includes but is not limited to silicon nitride, and the initial barrier layer 333 can be used to form the first barrier layer 330.

[0123] Referring to Figure 6e A sacrificial layer 390 can be formed to cover the initial barrier layer 333 and fill the trench T by deposition or other processes. The material of the sacrificial layer 390 includes but is not limited to carbon, spin-on dielectric, silicon oxide, silicon nitride, silicon oxynitride, etc. Preferably, the material of the mask layer 380 is silicon nitride, the material of the sacrificial layer 390 is spin-on carbon (SOC), and the material of the initial barrier layer 333 is linear silicon nitride.

[0124] Referring to Figure 6f The sacrificial layer 390 can be etched back until the initial barrier layer 333 covering the second sidewall 301b is exposed. For example, the sacrificial layer 390 (i.e., the spin-on carbon) can be etched back first, and the etching product can be detected in real time during the etching back process. When the material of the initial barrier layer 333 (e.g., silicon nitride) appears in the etching product, the etching selectivity is changed so that the etching rate of the silicon nitride is greater than the etching rate of the spin-on carbon. In this way, after the etching stops at the surface of the substrate 300, all the silicon nitride (including the entire mask layer 380 and part of the initial barrier layer 333) above the substrate 300 is etched and removed, and part of the spin-on carbon (sacrificial layer 390) above the trench T is retained. It can be understood that, in the final retained initial barrier layer 333, the part of the initial barrier layer 333 covering the second sidewall 301b constitutes the first sub-barrier layer 331, and the part of the initial barrier layer 333 covering the top surface of the first isolation structure 321 constitutes the second sub-barrier layer 332, thereby further reducing the leakage problem between the gate structure and the storage node contact formed on the top surface of the first doped region 302. The first sub-barrier layer 331 and the second sub-barrier layer 332 can present an "H" shaped topography, the first sub-barrier layer 331 is connected with the second sub-barrier layer 332 and constitutes the first barrier layer 330, that is, the first sub-barrier layer 331 and the second sub-barrier layer 332 are the same in material and form an integral whole.

[0125] Referring to Figure 6g The remaining sacrificial layer 390 in the trench T and above the surface of the substrate 300 can be removed by ashing (Asher) or other processes.

[0126] In some embodiments, after the sacrificial layer 390 remaining in the trench T is removed by using the ashing process, a process such as deposition can be used to continue filling the silicon oxide in the "H" shaped first barrier layer 330 in the trench T, and then a chemical mechanical polishing (CMP) process is performed on the surface of the substrate 300. It can be understood that since all the silicon nitride (including the entire mask layer 380 and part of the initial barrier layer 333) above the substrate 300 is etched and removed, the difficulty of chemical mechanical polishing on the surface of the substrate 300 is reduced, and the product yield is further improved.

[0127] In some embodiments, referring to Figure 6c and Figure 6d , the etching the initial first isolation structure 320 includes: etching the initial first isolation structure 320 to form the first isolation structure 321 with a recess 322; wherein the recess 322 is located on a surface of the first isolation structure 321 close to the first doped region 302 in the first direction; and the forming the initial barrier layer 333 covering the first isolation structure 321 includes: forming the initial barrier layer 333 filling the recess 322; wherein at least part of the second sub-barrier layer 332 is located in the recess 322.

[0128] In the embodiments of the present disclosure, referring to Figure 6c , due to the non-uniformity of the etching process, the top surface of the first isolation structure 321 formed will have a recess 322, that is, the top surface of the first isolation structure 321 presents a morphology of being low in the middle and high on both sides. Referring to Figure 6d , the initial barrier layer 333 is formed on the top surface of the first isolation structure 321 with the recess 322, so that at least part of the second sub-barrier layer 332 is located in the recess 322, that is, the second sub-barrier layer 332 can fill the recess 322, thereby improving the top surface morphology of the first isolation structure 321 and being beneficial to improving the yield of subsequent processes.

[0129] In some embodiments, referring to Figure 6b , Figure 6c and Figure 6h, the manufacturing method further comprises: forming a gate material layer 310 covering the sidewalls and the bottom wall of the trench T; the forming the first isolation structure 321 covering the gate structure 312 and at least part of the first barrier layer 330 comprises: forming an initial first isolation structure 320 in the trench T with the gate material layer 310 formed; wherein the height of the initial first isolation structure 320 is greater than or equal to the height of the active pillar 301; etching the initial first isolation structure 320 and the gate material layer 310 to form the first isolation structure 321 and an initial gate structure 311; wherein the initial gate structure 311 covers the first sidewall 301a, the third sidewall 301c of the second doped region 303 and the bottom wall of the trench T; the forming the gate structure 312 on the exposed opposite two first sidewalls 301a of the trench T respectively comprises: removing the initial gate structure 311 covering the third sidewall 301c and the bottom wall of the trench T to form the gate structure 312 on the opposite two first sidewalls 301a respectively.

[0130] In the embodiments of the present disclosure, referring to Figure 6b , the gate material layer 310 covering the inner wall of the trench T is formed in the trench T which is not filled with the second isolation structure 350, where the inner wall of the trench T includes the sidewall and the bottom wall of the trench T. Then the initial first isolation structure 320 is formed in the trench T with the gate material layer 310 formed, and the height of the initial first isolation structure 320 is greater than or equal to the height of the active pillar 301.

[0131] Referring to Figure 6c , the initial first isolation structure 320 and part of the gate material layer 310 are etched to form the first isolation structure 321 and the initial gate structure 311. It can be understood that part of the gate material layer 310 covering the second sidewall 301b is removed in this step, so that the initial gate structure 311 covers the first sidewall 301a, the third sidewall 301c of the second doped region 303 and the bottom wall of the trench T.

[0132] Referring to Figure 6h , the bottom of the trench T can be etched from the other side surface of the substrate 300 (the other surface opposite to the surface on which the trench T is formed), so that the initial gate structure 311 covering the third sidewall 301c and the bottom wall of the trench T is removed. It can be understood that the bottom of one initial gate structure 311 located in the trench T is etched to be disconnected, so that two separated gate structures 312 are formed, and the two gate structures 312 are located on the opposite two first sidewalls 301a respectively.

[0133] In some embodiments, referring to Figure 6hThe manufacturing method further includes: forming a second barrier layer 340 covering at least the third sidewall 301c of the second doped region 303; and wherein the first sidewall 301a and the third sidewall 301c are continuous.

[0134] In the embodiments of the present disclosure, after removing the partial initial gate structure 311 covering the third sidewall 301c and the bottom wall of the trench T from the back of the substrate 300, the second barrier layer 340 can be formed on the two opposite third sidewalls 301c respectively by using a deposition process or the like, and the first sidewall 301a and the third sidewall 301c are continuous. Exemplarily, the second barrier layer 340 can also be arranged around the second doped region 303 of the active pillar 301. The material of the second barrier layer 340 includes but is not limited to silicon nitride, silicon oxynitride or the like. The second barrier layer 340 can be used to reduce the diffusion of impurity ions in the gate structure 312 into the second doped region 303, and the diffusion of impurity ions generated in the process of forming the gate structure 312 into the second doped region 303. The second barrier layer 340 can also be used to reduce the diffusion of impurity ions in the second doped region 303 into the gate structure 312. In addition, the second barrier layer 340 can be a dense insulating material, and there is no gap or hole in the second barrier layer 340, so the second barrier layer 340 can also effectively isolate the gate structure 312 from the conductive structure (such as a bit line contact) formed on the bottom surface of the second doped region 303, thereby reducing the occurrence of the leakage problem.

[0135] The methods disclosed in the several method embodiments provided by the present disclosure can be combined in any manner without conflict, to obtain new method embodiments.

[0136] The features disclosed in the several device embodiments provided by the present disclosure can be combined in any manner without conflict, to obtain new device embodiments.

[0137] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the size of the sequence number of each process in various embodiments of the present disclosure does not mean the order of execution. The execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence number of the above embodiments of the present disclosure is only for description, not representing the advantages and disadvantages of the embodiments.

[0138] It should be noted that, in the present document, the terms "comprising", "comprises" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0139] The above description is merely that of the embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art can easily conceive of changes or replacements within the technical scope disclosed by the present disclosure, and all such changes or replacements should be encompassed within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be subject to the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: an active pillar comprising a first doped region, a channel region, and a second doped region arranged in sequence along a first direction, wherein the first direction is a height direction of the active pillar; a gate structure covering a first sidewall of the channel region; a first barrier layer covering at least a second sidewall of the first doped region, wherein the first sidewall and the second sidewall are continuous.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a first isolation structure covering the gate structure and at least part of the first barrier layer, wherein the gate structure is located between the first isolation structure and the channel region, and at least part of the first barrier layer is located between the first isolation structure and the first doped region.

3. The semiconductor structure of claim 2, wherein, The semiconductor structure comprises: a plurality of the active pillars arranged at intervals along a second direction, wherein the second direction is perpendicular to the first direction; the gate structure is respectively covered on two opposite first sidewalls of two adjacent active pillars; and the first barrier layer is respectively covered on two opposite second sidewalls of the two adjacent active pillars.

4. The semiconductor structure of claim 3, wherein, The first barrier layer comprises: a first sub-barrier layer covering the second sidewall; a second sub-barrier layer covering a surface of the first isolation structure close to the first doped region in the first direction, wherein the first sub-barrier layer is connected with the second sub-barrier layer.

5. The semiconductor structure of claim 4, wherein, A size of the first sub-barrier layer in the second direction is substantially equal to a size of the gate structure in the second direction.

6. The semiconductor structure of claim 4, wherein, The first isolation structure comprises: a recessed portion located on a surface of the first isolation structure close to the first doped region in the first direction, wherein at least part of the second sub-barrier layer is located in the recessed portion.

7. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a second barrier layer covering at least a third sidewall of the second doped region, wherein the first sidewall and the third sidewall are continuous.

8. The semiconductor structure of claim 7, wherein, The semiconductor structure comprises: a plurality of the active pillars, wherein the second barrier layer is respectively covered on two opposite third sidewalls of two adjacent active pillars.

9. The semiconductor structure of claim 7, wherein, The second barrier layer is used to block impurity ions in the gate structure from entering the second doped region.

10. The semiconductor structure of claim 1, wherein, The first barrier layer is used to block impurity ions in the gate structure from entering the first doped region.

11. The semiconductor structure of claim 1, wherein, A material of the first barrier layer comprises silicon nitride.

12. A method of manufacturing a semiconductor structure, characterized by, The manufacturing method comprises: forming an active pillar, wherein the active pillar comprises a first doped region, a channel region, and a second doped region arranged in sequence along a first direction, and the first direction is a height direction of the active pillar; forming a gate structure covering a first sidewall of the channel region; forming a first barrier layer covering at least a second sidewall of the first doped region, wherein the first sidewall and the second sidewall are continuous.

13. The manufacturing method according to claim 12, wherein The manufacturing method further comprises: forming a first isolation structure covering the gate structure and at least part of the first blocking layer; wherein the gate structure is between the first isolation structure and the channel region; and at least part of the first blocking layer is between the first isolation structure and the first doped region.

14. The manufacturing method according to claim 13, wherein The manufacturing method further comprises: providing a substrate; etching the substrate to form trenches and the active pillars arranged alternately along a second direction; wherein the trenches expose two opposite first sidewalls and two opposite second sidewalls of each two adjacent active pillars; the forming of the gate structure covering the first sidewall of the channel region comprises: forming the gate structure on the two opposite first sidewalls exposed by the trenches respectively; the forming of the first isolation structure covering the gate structure and at least part of the first blocking layer comprises: forming the first isolation structure between the gate structures on the two opposite first sidewalls exposed by the trenches.

15. The manufacturing method according to claim 14, wherein the forming of the first blocking layer covering at least the second sidewall of the first doped region comprises: forming an initial blocking layer covering the top surface of the active pillars, the two opposite second sidewalls exposed by the trenches and the first isolation structure; forming a sacrificial layer covering the initial blocking layer and filling the trenches; etching back the sacrificial layer until the initial blocking layer covering the second sidewall is exposed; wherein the initial blocking layer remaining and covering the second sidewall constitutes a first sub-blocking layer, the initial blocking layer remaining and covering the first isolation structure constitutes a second sub-blocking layer, and the first sub-blocking layer and the second sub-blocking layer are connected and constitute the first blocking layer.

16. The manufacturing method according to claim 15, wherein The manufacturing method further comprises: forming a gate material layer covering the sidewalls and the bottom wall of the trenches; the forming of the first isolation structure covering the gate structure and at least part of the first blocking layer comprises: forming an initial first isolation structure in the trenches with the gate material layer; wherein the height of the initial first isolation structure is greater than or equal to the height of the active pillars; etching the initial first isolation structure and the gate material layer to form the first isolation structure and an initial gate structure; wherein the initial gate structure covers the first sidewall, a third sidewall of the second doped region and the bottom wall of the trenches; the forming of the gate structure on the two opposite first sidewalls exposed by the trenches respectively comprises: removing the initial gate structure covering the third sidewall and the bottom wall of the trenches to form the gate structure on the two opposite first sidewalls respectively.

17. The manufacturing method according to claim 16, wherein the etching of the initial first isolation structure comprises: etching the initial first isolation structure to form the first isolation structure with a recess; wherein the recess is on the surface of the first isolation structure close to the first doped region in the first direction; the forming of the initial blocking layer covering the first isolation structure comprises: forming the initial blocking layer filling the recess; wherein at least part of the second sub-blocking layer is in the recess.

18. The manufacturing method according to claim 12, wherein, The manufacturing method further comprises: forming a second blocking layer covering at least a third sidewall of the second doped region; wherein the first sidewall and the third sidewall are continuous.

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