Semiconductor structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, and relates to the technical field of semiconductor chips. The semiconductor structure comprises a first transistor structure layer and a connection contact. The first transistor structure layer comprises a first semiconductor layer and a first transistor arranged on one side of the first semiconductor layer. The connection contact penetrates through the first semiconductor layer and the first transistor and is connected to the first electrode of the first transistor. The semiconductor structure is applied to the dynamic random access memory so as to realize data reading and writing operation.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a semiconductor structure, a preparation method thereof, a storage system and an electronic device. BACKGROUND

[0002] With the improvement of process technology, circuit design and manufacturing process, dynamic random access memory (DRAM) is scaled to a smaller size. However, as the feature size of the memory memory cell approaches the lower limit, the planar process and manufacturing technology become challenging and costly, causing the density of the memory cell to approach the upper limit.

[0003] Therefore, how to further realize the miniaturization of DRAM becomes a technical problem difficult for current technical personnel to solve. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure, a preparation method thereof, a storage system and an electronic device.

[0005] Embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a semiconductor structure is provided. The semiconductor structure includes a first transistor structure layer and a connection contact. The first transistor structure layer includes a first semiconductor layer and a first transistor disposed on one side of the first semiconductor layer. The connection contact penetrates the first semiconductor layer and the first transistor, and is connected to a first electrode of the first transistor.

[0007] In some embodiments, the connection contact includes a first insulating layer and a conductive column, wherein the conductive column penetrates the first semiconductor layer and the first transistor, the conductive column is connected to the first electrode of the first transistor, and the first insulating layer is disposed around the conductive column.

[0008] In some embodiments, the semiconductor structure further includes an interconnection layer. The interconnection layer is disposed on a side of the first transistor away from the first semiconductor layer. The conductive column is connected to the first electrode of the first transistor through the interconnection layer.

[0009] In some embodiments, the interconnection layer includes a circuit layer and a plurality of interconnection contacts. The interconnection contacts are located between the circuit layer and the first transistor structure layer. The circuit layer is connected to the first electrode of one first transistor through one interconnection contact, and the connection contact is connected to the interconnection contact.

[0010] In some embodiments, the interconnection contact includes a first connecting portion and a second connecting portion connected to each other. The first connecting portion is located on a side of the second connecting portion close to the first transistor structure layer, the second connecting portion is connected to the circuit layer, the first connecting portion is connected to the first electrode, and the second connecting portion is connected to the connection contact.

[0011] In some embodiments, the connection contact penetrates the first electrode to which it is connected.

[0012] In some embodiments, the first semiconductor layer comprises a substrate and a doped layer, the doped layer being disposed between the substrate and the first transistor. The connection contact penetrates the doped layer and the substrate.

[0013] In some embodiments, the semiconductor structure further comprises an array structure. The array structure is stacked on a side of the interconnection layer facing away from the first transistor structure layer and is bonded to the interconnection layer.

[0014] In some embodiments, the array structure comprises a second semiconductor layer and a memory array. The memory array is disposed on a side of the second semiconductor layer, and the interconnection layer is bonded on a side of the memory array facing away from the second semiconductor layer.

[0015] In some embodiments, the memory array comprises a plurality of conductive lines, a plurality of second transistors, and a plurality of capacitors. The plurality of capacitors are located between the plurality of second transistors and the second semiconductor layer, and the plurality of conductive lines are located on a side of the plurality of second transistors facing away from the second semiconductor layer. A second electrode of each second transistor is connected to one end of one capacitor, and a third electrode of the plurality of second transistors is connected to the same conductive line, and the conductive line is connected to the interconnection layer.

[0016] In some embodiments, the semiconductor structure further comprises a conductive layer and a second insulating layer. The conductive layer is disposed on a side of the first semiconductor layer facing away from the first transistor. The second insulating layer is disposed on a side of the conductive layer facing away from the first semiconductor layer, wherein the second insulating layer comprises a first opening exposing part of the conductive layer.

[0017] In another aspect, a method for manufacturing a semiconductor structure is provided. The method comprises forming a first transistor structure layer comprising a first semiconductor layer and a first transistor disposed on a side of the first semiconductor layer. A connection contact is formed, the connection contact penetrating the first semiconductor layer and the first transistor and being connected to a first electrode of the first transistor.

[0018] In some embodiments, forming the connection contact comprises forming a first contact hole penetrating the first transistor and extending into the first semiconductor layer. A first insulating layer and a conductive pillar are sequentially formed in the first contact hole, the first insulating layer being disposed around the conductive pillar.

[0019] In some embodiments, after the connection contact is formed, the method further comprises: forming an interconnection layer on a side of the first transistor away from the first semiconductor layer, the connection contact being connected to the first electrode of the first transistor through the interconnection layer. The forming of the interconnection layer comprises: forming an interconnection contact on a side of the first transistor away from the first semiconductor layer, the interconnection contact being connected to both the first electrode of the first transistor and the connection contact. A circuit layer is formed on a side of the interconnection contact away from the first semiconductor layer, the circuit layer being connected to the interconnection contact.

[0020] In some embodiments, the forming of the interconnection contact on a side of the first transistor away from the first semiconductor layer comprises: sequentially forming a first connecting part and a second connecting part on a side of the first transistor away from the first semiconductor layer, the first connecting part being located on a side of the second connecting part close to the first semiconductor layer, the first connecting part being connected to the first electrode, and the second connecting part being connected to both the first connecting part and the connection contact.

[0021] In some embodiments, the method further comprises: forming a conductive layer on a side of the first semiconductor layer away from the first transistor. A second insulating layer is formed on a side of the conductive layer away from the first semiconductor layer, wherein the second insulating layer comprises a first opening exposing part of the conductive layer.

[0022] In another aspect, a storage system is provided, comprising: the semiconductor structure as described above and a controller. The controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

[0023] In another aspect, an electronic device is provided, comprising the storage system as described above. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0025] Figure 1 a structural block diagram of an electronic device provided by some embodiments of the present disclosure;

[0026] Figure 2 a structural block diagram of a memory provided by some embodiments of the present disclosure;

[0027] Figure 3 a structural schematic diagram of a semiconductor structure provided by some embodiments of the present disclosure;

[0028] Figure 4 A schematic structural diagram of another semiconductor structure provided in some embodiments of the present disclosure;

[0029] Figure 5 A flowchart of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0030] Figure 6 For Figure 5 A schematic structural diagram of a semiconductor structure corresponding to the preparation method;

[0031] Figure 7 For Figure 5 A schematic structural diagram of another semiconductor structure corresponding to the preparation method;

[0032] Figure 8 For Figure 5 A schematic structural diagram of another semiconductor structure corresponding to the preparation method;

[0033] Figure 9 A flow chart of a method for preparing connection contacts provided in some embodiments of the present disclosure;

[0034] Figure 10 A flow chart of a method for preparing an interconnect layer provided in some embodiments of the present disclosure;

[0035] Figure 11 For Figure 10 A schematic structural diagram of a semiconductor structure corresponding to the preparation method;

[0036] Figure 12 A flow chart of a method for preparing another semiconductor structure provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0038] Unless the context clearly requires otherwise, throughout the description and the claims, the word "comprise," and variations such as "comprises" or "comprising," will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps. In describing some embodiments, the expressions "coupled" and "connected" along with their derivatives, can be used. For example, some embodiments can be described as being "connected" to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments can be described as being "coupled" to indicate that two or more elements are in direct physical or electrical contact. However, "coupled" can also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited in scope by the embodiments set forth in the following text, examples, figures, or discussions. Further, the embodiments are not necessarily limited by the applicability of the various embodiments to the apparatus, system, method, or material described above and / or shown in the accompanying drawings.

[0039] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description and should not be construed as indicating or implying relative importance or implying the number of the indicated technical features. Thus, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0040] In describing some embodiments, the expressions "coupled" and "connected" along with their derivatives, can be used. For example, some embodiments can be described as being "connected" to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments can be described as being "coupled" to indicate that two or more elements are in direct physical or electrical contact. However, "coupled" can also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited in scope by the embodiments set forth in the following text, examples, figures, or discussions. Further, the embodiments are not necessarily limited by the applicability of the various embodiments to the apparatus, system, method, or material described above and / or shown in the accompanying drawings.

[0041] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have jagged and / or curved edges. Thus, the regions illustrated in the figures are schematic and not drawn to scale. The same should be understood with regard to the dimensions of regions relative to each other. In addition, the use of "approximately" or "substantially” in describing some embodiments is intended to mean that the described feature could deviate from the stated value by 10% or less.

[0042] Figure 1A structural block diagram of an electronic device 9000 is provided for some embodiments of the disclosure. The electronic device 9000 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic device having a storage.

[0043] As shown in Figure 1 The electronic device 9000 can include a storage system 910 and a host 920. The storage system 910 can be integrated into various types of storage devices, such as a memory card. The memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD), and a universal flash storage (UFS). That is, the storage system 910 can be applied to and packaged into different types of electronic products.

[0044] The host 920 can include a processor of the electronic device 9000, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The host 920 can be configured to send data to or receive data from the storage.

[0045] In some embodiments, the storage system 910 can have one or more memories 911 and a controller 912. For example, the controller 912 can be configured to operate in a low duty cycle environment, such as an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment, such as an SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. Yet alternatively, in some examples, the controller 912 is coupled to the memory 911 and the host 920 and configured to control data in the memory 911 while being able to communicate with an external device, such as a host.

[0046] The number of memories 911 in the storage system 910 can be one or more, Figure 1911 as an example. The controller 912 can manage the data stored in each memory 911 and communicate with the host 920. The controller 912 can be configured to control the operations of each memory 911, such as read, write and refresh operations. The controller 912 can also be configured to manage various functions related to the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the controller 912 is also configured to determine the maximum memory capacity that can be used by the computer system, the number of memory banks, memory type and speed, memory granule data depth and data width, and other important parameters. Any other suitable function can also be performed by the controller 912. The controller 912 can communicate with an external device (e.g., the host 920) according to a specific communication protocol. For example, the controller 912 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, FireWire protocol, etc.

[0047] Figure 2 This is a structural block diagram of the memory 911 provided in some embodiments of the present disclosure. Figure 2 As shown, the memory 911 includes a memory cell array 913 and a peripheral circuit 914 for controlling the memory cell array 913. The peripheral circuit 914 (also referred to as a control and sensing circuit) may include any suitable digital, analog, and / or mixed signal circuit for facilitating the operation of the memory cell array 913. For example, the peripheral circuit 914 may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a sub-circuit) of the aforementioned functional circuits, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor).

[0048] Exemplarily, the peripheral circuit 914 can use complementary metal-oxide-semiconductor (CMOS) technology, for example, it can be implemented with a logic process (e.g., a technology node of 90 nm, 65 nm, 60 nm, 45 nm, 32 nm, 28 nm, 22 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.).

[0049] The memory cell array 913 and the peripheral circuit 914 can be arranged side by side in the same plane, for example, on the same wafer, that is, the memory cell array 913 and the peripheral circuit 914 can be located in the same semiconductor structure. The memory cell array 913 and the peripheral circuit 914 can also be formed on different wafers and bonded together in a face-to-face manner. Figure 2 As shown, when the memory cell array 913 and the peripheral circuit 914 are formed on different wafers and bonded together in a face-to-face manner, the memory 911 can include a first semiconductor structure 901 and a second semiconductor structure 902, and a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902. Among them, the first semiconductor structure 901 can include the memory cell array 913, and the second semiconductor structure 902 can include the peripheral circuit 914.

[0050] Among them, the memory cell array 913 can be an array of memory cells using vertical transistors as switching and selection devices. In some embodiments, the memory cell array 913 can be a dynamic random access memory cell array. For ease of description, a DRAM cell array can be used to describe an example of the memory cell array 913 in the present disclosure. However, it should be understood that the memory cell array 913 is not limited to a DRAM cell array, for example, it can also include any other suitable type of memory cell array 913 that can use vertical transistors as switching and selection devices, such as a PCM cell array, a static random access memory (SRAM) cell array, a FRAM cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, etc.

[0051] When the memory cell array 913 is a DRAM cell array, the memory cells therein are DRAM cells. A DRAM cell includes a capacitor for storing a data bit as a positive or negative charge and one or more transistors (also known as pass transistors) for controlling (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a transistor and capacitor (1T1C) cell. According to some embodiments, the DRAM cell can be refreshed by the peripheral circuit 914 to retain data.

[0052] Currently, in the X-tacking architecture, the memory cell array 913 and peripheral circuits 914 (such as sense amplifier circuits and CMOS circuits) are fabricated on separate wafers. The two wafers are then bonded together using hybrid bonding and packaged. This process can improve the array density of the memory 911. However, when the bit lines of the memory cell array 913 are connected to the latch transistors of the sense amplifier circuits within the peripheral circuits 914, they must pass through all metal layers on both the wafers containing the memory cell array 913 and the peripheral circuits 914. This arrangement increases the wiring length from the bit lines to the sense amplifier circuits, hindering further scaling of the memory 911.

[0053] Figure 3 A schematic structural diagram of a semiconductor structure 100 provided in some embodiments of the present disclosure.

[0054] like Figure 3 As shown, in some embodiments, the semiconductor structure 100 includes: a first transistor structure layer 110 and a connection contact 120. The first transistor structure layer 110 includes a first semiconductor layer 111 and a first transistor 112 disposed on one side of the first semiconductor layer 111. The connection contact 120 passes through the first semiconductor layer 111 and the first transistor 112 and is connected to the first electrode of the first transistor 112.

[0055] In this embodiment, the semiconductor structure 100 can be used as the aforementioned Figure 2 An example of the second semiconductor structure 902 of the memory 911 in FIG. Figure 3 It is for illustrative purposes only and may not actually necessarily reflect actual device structure (eg, interconnects).

[0056] like Figure 3As shown, in the embodiments of the present disclosure, the first semiconductor layer 111 can be made of a semiconductor material. For example, the semiconductor material can include monocrystalline silicon (Si), monocrystalline germanium (Ge), etc. The material of the first semiconductor layer 111 can also include a compound semiconductor. For example, the compound semiconductor can include gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), etc. The first semiconductor layer 111 of the present disclosure can also be made of other semiconductor materials commonly used in the art.

[0057] The plurality of first transistors 112 arranged at intervals in the first transistor structure layer 110 can be, for example, COMS transistors, and the first electrodes of the first transistors 112 can be source electrodes or drain electrodes.

[0058] The connection contact 120 is arranged on the first transistor 112 and extends through the first transistor 112 to the first semiconductor layer 111. For example, the connection contact 120 can include a through silicon contact (TSC), a through silicon via, etc. The connection contact 120 can realize the connection between the first transistor 112 and other external circuits, thereby providing electrical signals for the operation of the semiconductor structure 100.

[0059] In the embodiments, by arranging the connection contact 120, the complexity of the internal layout of the semiconductor structure 100 can be reduced when the semiconductor structure 100 is bonded with the first semiconductor structure 901 to form the memory 911, thereby avoiding the mutual interference between different types of wires (for example, power lines and other signal lines), and further reducing the line loss. For example, by arranging the connection contact 120, the power lines and other signal lines in the semiconductor structure can be arranged on both sides of the first transistor structure layer 110, thereby avoiding the mutual interference between the power lines and other signal lines, and reducing the line loss.

[0060] In addition, the connection contact 120 is arranged on the first transistor 112, and no additional layout position needs to be reserved for the connection contact 120, thereby reducing the layout area of the semiconductor structure 100, and further improving the array density of the device, which is conducive to the further miniaturization of the semiconductor structure 100 formed subsequently in size.

[0061] In some embodiments, the connection contact 120 includes a first insulating layer 121 and a conductive column 122. The conductive column 122 penetrates the first semiconductor layer 111 and the first transistor 112, and is connected to the first electrode of the first transistor 112. The first insulating layer 121 is arranged around the conductive column 122.

[0062] Please continue to refer to Figure 3In the semiconductor structure 100 of the embodiment, the connection between the connection contact 120 and other circuit structures outside is achieved by the internal conductive pillar 122. For example, one end of the conductive pillar 122 can be connected to the first electrode of the first transistor 112, and the other end can be connected to other circuits outside, thereby providing electrical signals for the operation of the first transistor 112. For example, the first transistor 112 can include a source terminal, a drain terminal, and a control terminal, wherein the source terminal and the drain terminal can both serve as the first electrode.

[0063] In a possible implementation, a first insulating layer 121 can be arranged on the periphery of the conductive pillar 122, so as to isolate the entire column of the conductive pillar 122 from the first transistor 112, thereby improving the reliability of the semiconductor structure 100.

[0064] The material of the first insulating layer 121 can include one or more of an oxide material (such as silicon oxide), a nitride material (such as silicon nitride), and an oxynitride material (such as silicon oxynitride). The material of the conductive pillar 122 can include a conductive material, for example, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof.

[0065] In some embodiments, an interconnection layer 130 is arranged on the side of the first transistor 112 away from the first semiconductor layer 111. The conductive pillar 122 is connected to the first electrode 1121 of the first transistor 112 through the interconnection layer 130.

[0066] Please continue to refer to Figure 3 By arranging the interconnection layer 130, the connection between the first transistor structure layer 110 and other device structures (such as a memory array) in the semiconductor structure 100 can be achieved, thereby achieving the control of the first transistor structure layer 110 over the other device structures in the semiconductor structure 100. The connection can include electrical connection or physical connection.

[0067] For example, when the other device structure is a memory array, the embodiment can achieve the control of the first transistor structure layer 110 over the memory array through the interconnection layer 130, thereby achieving the writing, reading, and erasing of data by the memory array.

[0068] In some embodiments, the interconnection layer 130 includes a circuit layer 131 and a plurality of interconnection contacts 132, and the interconnection contacts 132 are located between the circuit layer 131 and the first transistor structure layer 110. The circuit layer 131 is connected to the first electrode 1121 of one first transistor 112 through one interconnection contact 132, and the connection contact 120 is connected to the interconnection contact 132.

[0069] Please continue to refer to Figure 3In the semiconductor structure 100 of the present embodiment, the circuit layer 131 can include at least one circuit structure, and the first transistor 112 can be connected to other devices outside the semiconductor structure 100 through the internal circuit structure (e.g., interconnection lines) and the interconnection contact 132. In addition, the circuit layer 131 can further include an interlayer dielectric to isolate the circuit structure. The interlayer dielectric can be made of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The interconnection contact 132 can include a conductive material, for example, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof.

[0070] In the present embodiment, the interconnection contact 132 can be used to connect the connection contact 120 and the first electrode of the first transistor 112, thereby simplifying the manufacturing process of the connection contact 120. In addition, the interconnection contact 132 can also be used to connect the circuit layer 131 and the first electrode of the first transistor 112, thereby enabling the signal transmitted by the connection contact 120 to be transmitted to the first electrode and the circuit layer 131 at the same time, and further transmitted to other components (e.g., DRAM cells or DRAM arrays) inside the semiconductor structure 100 via the circuit layer 131, thereby enabling the data read and write operations of the semiconductor structure 100.

[0071] In some embodiments, the interconnection contact 132 includes a first connection portion 1321 and a second connection portion 1322 connected to each other. The first connection portion 1321 is located on the side of the second connection portion 1322 close to the first transistor structure layer 110, the second connection portion 1322 is connected to the circuit layer 131, the first connection portion 1321 is connected to the first electrode, and the second connection portion 1322 is connected to the connection contact 120.

[0072] Please continue to refer to Figure 3 In the semiconductor structure 100 of the present embodiment, the first electrode can be connected to the connection contact 120 through the first connection portion 1321 and the second connection portion 1322, thereby enabling the connection between the first electrode and the connection contact 120. In addition, the second connection portion 1322 can also enable the connection between the connection contact 120, the first electrode, and the circuit layer 131. In this way, the layout can be optimized, the layout area can be saved, and the manufacturing process of the connection contact 120 and the interconnection contact 132 can be simplified, thereby enabling the further miniaturization of the semiconductor structure 100 in size.

[0073] In some embodiments, the connection contact 120 penetrates the first electrode connected thereto.

[0074] Please continue to refer to Figure 3In the semiconductor structure 100 of the embodiment, the connection contact 120 is arranged on the first electrode of the first transistor, so that in the layout, the semiconductor structure 100 does not need to reserve a position for the connection contact 120 on the layout other than the first transistor, thereby reducing the layout area of the semiconductor structure 100, improving the device density, and realizing further miniaturization of the semiconductor structure 100.

[0075] In some embodiments, the first semiconductor layer 111 includes a substrate 1111 and a doped layer 1112, and the doped layer 1112 is arranged between the substrate 1111 and the first transistor 112. The connection contact 120 penetrates the doped layer 1112 and the substrate 1111.

[0076] Please continue to refer to Figure 3 In the embodiment of the disclosure, the substrate 1111 can be made of a semiconductor material. For example, the substrate 1111 can include a monocrystalline silicon (Si) substrate or a monocrystalline germanium (Ge) substrate. The material of the substrate 1111 can also include a compound semiconductor. For example, the substrate 1111 can also include a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate. The substrate 1111 of the disclosure can also be made of other semiconductor materials commonly used in the art.

[0077] In this way, the connection contact 120 can extend into the substrate 1111 after penetrating the first transistor 112, so that the substrate 1111 can be thinned by a backside process to expose the connection contact 120, realize the lead-out of the connection contact 120, and further realize the connection between the connection contact 120 and other circuit structures or devices (such as a power supply) outside the semiconductor structure 100.

[0078] The substrate 1111 is provided with a doped layer 1112 on the side close to the first transistor 112. For example, the doped layer 1112 can include a plurality of doped regions, each of which corresponds to a first electrode of a first transistor 112 and provides carriers for the operation of the first transistor 112.

[0079] In some examples, the doped region can be doped with a p-type dopant.

[0080] In some examples, the doped region can be doped with a p-type dopant.

[0081] Figure 4 Another structure diagram of a semiconductor structure 100 provided by some embodiments of the disclosure.

[0082] As Figure 4As shown, in some embodiments, the semiconductor structure 100 further includes: an array structure 200. The array structure 200 is stacked on a side of the interconnection layer 130 facing away from the first transistor structure layer 110 and is bonded to the interconnection layer 130.

[0083] In this embodiment, the array structure 200 and the interconnection layer 130 are connected by a hybrid bonding process, in which the bonding interface is located on the surface of the side of the interconnection layer 130 facing away from the first transistor structure layer 110. Through the circuit layer 131 and the plurality of interconnection contacts 132 inside the interconnection layer 130, electrical signal transmission between the array structure 200 and the first transistor structure layer 110 can be achieved.

[0084] In some examples, hybrid bonding is a direct bonding technique, that is, a bond is formed between surfaces without the use of an intermediate layer (such as solder or adhesive), and both metal-metal bonding and dielectric-dielectric bonding can be achieved simultaneously. In some implementations, the bonding interface is the location where the interconnection layer 130 and the array structure 200 meet and bond.

[0085] In this embodiment, the array structure 200 and the first transistor structure layer 110 are bonded and connected by a bonding process, which can achieve separate preparation of the wafer on which the array structure 200 is located and the wafer on which the first transistor structure layer 110 is located, thereby reducing the process difficulty of their preparation and improving the preparation efficiency of the semiconductor structure 100. In addition, the bonding process is conducive to reducing the height of the semiconductor structure 100 in the stacking direction Z, and is also conducive to further miniaturization of the semiconductor structure 100.

[0086] Please continue to refer to Figure 4 In some embodiments, the array structure 200 includes: a second semiconductor layer 210 and a storage array 220. The storage array 220 is disposed on a side of the second semiconductor layer 210, and the interconnection layer 130 is bonded on a side of the storage array 220 facing away from the second semiconductor layer 210.

[0087] In some examples, the storage array 220 can be an array of storage cells that use vertical transistors as switching and selection devices, where the storage cells can be DRAM cells.

[0088] In other examples, the storage array 220 can also include any other suitable type of storage array 220 that can use vertical transistors as switching and selection devices, such as an array of PCM cells, an array of SRAM cells, an array of FRAM cells, an array of resistive memory cells, an array of magnetic memory cells, an array of STT memory cells, etc.

[0089] In this embodiment, the memory array 220 is fabricated based on the second semiconductor layer 210, which can provide support for the subsequently fabricated memory array 220 and improve the stability and reliability of the wafer on which the memory array 220 is fabricated.

[0090] In some embodiments, the second semiconductor layer 210 can be made of a semiconductor material. For example, the semiconductor material can include monocrystalline silicon (Si), monocrystalline germanium (Ge), etc. The material of the second semiconductor layer 210 can also include a compound semiconductor. For example, the compound semiconductor can include gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), etc. The second semiconductor layer 210 can also be made of other semiconductor materials commonly used in the art.

[0091] Please continue to refer to Figure 4 In some embodiments, the memory array 220 includes a plurality of conductive lines 221, a plurality of second transistors 222, and a plurality of capacitors 223. The plurality of capacitors 223 are located between the plurality of second transistors 222 and the second semiconductor layer 210, and the plurality of conductive lines 221 are located on the side of the plurality of second transistors 222 away from the second semiconductor layer 210. The second electrode of each second transistor 222 is connected to one end of one capacitor 223, the third electrode of the plurality of second transistors 222 is connected to the same conductive line 221, and the conductive line 221 is connected to the interconnection layer 130.

[0092] For example, when the memory array 220 is a DRAM cell array, each DRAM cell includes a capacitor 223 for storing a data bit as a positive or negative charge and a second transistor 222 (also referred to as a pass transistor) for controlling (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a 1T1C cell including one capacitor 223 and one second transistor 222. In other embodiments, the DRAM cell can also be any other configuration, such as a 2T1C cell, a 3T1C cell, etc.

[0093] For example, when the DRAM cell is a 1T1C cell, one of the source and drain of the second transistor 222 is coupled to one end of the capacitor 223, and the other is coupled to a bit line (one of the conductive lines 221). That is, the second electrode can be one of the source and drain of the second transistor 222, and the third electrode is the other. In addition, the control electrode (gate) of the second transistor 222 will be connected to a word line (another of the conductive lines 221). In this way, the second transistor 222 and thus the entire DRAM cell can be controlled by controlling the bit line and the word line, thereby enabling read, write, and erase operations of the DRAM cell.

[0094] Please continue to refer to Figure 4In some embodiments, the semiconductor structure 100 further comprises: a conductive layer 140 and a second insulating layer 150. The conductive layer 140 is disposed on a side of the first semiconductor layer 111 away from the first transistor 112. The second insulating layer 150 is disposed on a side of the conductive layer 140 away from the first semiconductor layer 111, wherein the second insulating layer 150 comprises a first opening 151 exposing part of the conductive layer 140.

[0095] In the present embodiment, by disposing the conductive layer 140 on a side of the first semiconductor layer 111, the connection contacts 120 can be led out and connected to external circuit structures or devices, wherein one conductive layer can be connected to multiple connection contacts 120, realizing the unified leading-out of the connection contacts 120. In this way, the circuit structure can be simplified, thereby reducing the circuit loss and the preparation cost.

[0096] In addition, by preparing the second insulating layer 150 on the conductive layer 140, the isolation between the conductive layer 140 and even the entire semiconductor structure 100 and other external circuit structures or devices can be realized, thereby improving the reliability of the semiconductor structure 100. By disposing the first opening 151, the connection between the semiconductor structure 100 and the external devices or circuit structures can be realized via the first opening 151. For example, a pad pin can be prepared at the first opening 151, thereby realizing the connection with the external devices or circuit structures by using the pad pin.

[0097] Based on the semiconductor structure 100 provided in some embodiments above, the present embodiment further provides a preparation method of a semiconductor structure 100, which is used to prepare the semiconductor structure 100 described above.

[0098] Figure 5 A flowchart of a preparation method of a semiconductor structure 100 provided in some embodiments of the present disclosure, Figure 6 A structure schematic diagram of a semiconductor structure 100 corresponding to the preparation method in Figure 5 A structure schematic diagram of another semiconductor structure 100 corresponding to the preparation method in Figure 7 A structure schematic diagram of still another semiconductor structure 100 corresponding to the preparation method in Figure 5 A structure schematic diagram of still another semiconductor structure 100 corresponding to the preparation method in Figure 8 A structure schematic diagram of still another semiconductor structure 100 corresponding to the preparation method in Figure 5 A structure schematic diagram of still another semiconductor structure 100 corresponding to the preparation method in

[0099] As shown in Figure 5 The preparation method of the semiconductor structure 100 comprises the following steps S1-S2.

[0100] S1, forming a first transistor structure layer 110, the first transistor structure layer 110 comprising a first semiconductor layer 111 and a first transistor 112 disposed on a side of the first semiconductor layer 111.

[0101] In this step S1 , forming the first transistor structure layer 110 may further include the following steps S11 to S13 .

[0102] S11. Form a substrate 1111.

[0103] like Figure 6 As shown, illustratively, in this step S11, the substrate 1111 can be formed by using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof thin film deposition process.

[0104] The substrate 1111 may be a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The material of the substrate 1111 may also be a compound semiconductor. For example, the substrate 1111 may be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate. The substrate 1111 of the present disclosure may also be made of other semiconductor materials commonly used in the art.

[0105] S12 , forming a doping layer 1112 on one side of the substrate 1111 .

[0106] Please continue reading Figure 6 ion implantation is performed to implant n / p impurities onto one side of substrate 1111 to form multiple doped regions. In some examples, when high-energy boron ions are implanted, localized p-type regions can be formed for subsequent fabrication of NMOS transistors. In other examples, when high-energy phosphorus ions are implanted, localized n-type regions can be formed for subsequent fabrication of PMOS transistors.

[0107] S13 , forming first transistors 112 corresponding to the plurality of doping regions of the doping layer 1112 .

[0108] Please continue reading Figure 6 For example, on the basis of the doped region, CVD, PVD, ALD or any combination thereof thin film deposition process can be used to sequentially deposit a gate oxide layer 500 and a polysilicon layer 600, and then the gate oxide layer 500 and the polysilicon layer 600 are blocked, etched, and other operations are performed using a photolithography process to obtain a gate 1121 (also known as a control electrode).

[0109] High-concentration impurities are implanted into the source 1122 and drain 1123 at corresponding locations on both sides of the gate 1121 using a high-current ion implantation device. For example, if the aforementioned doped region is a p-type region, high-energy phosphorus ions can be implanted at corresponding locations on both sides of the gate and activated by annealing to form the source and drain regions of the NMOS transistor.

[0110] In other examples, when the aforementioned doped region is an n-type region, high-energy boron ions may be implanted at corresponding positions on both sides of the gate and activated by annealing to form the source and drain regions of the PMOS tube.

[0111] S2 . Form a connection contact 120 . The connection contact 120 penetrates the first semiconductor layer 111 and the first transistor 112 , and is connected to the first electrode 1121 of the first transistor 112 .

[0112] like Figure 7 As shown, before step S2, in this embodiment, after step S13, an insulating material may be deposited on a side of the first transistor 112 away from the first semiconductor layer 111 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof to form a first dielectric layer 160, thereby isolating the plurality of first transistors 112 and facilitating the subsequent preparation of the connection contacts 120. Exemplarily, the insulating material may include one or more of an oxide material (e.g., silicon oxide), a nitride material (e.g., silicon nitride), and a nitride oxide (e.g., silicon oxynitride).

[0113] In this step S2, if Figure 8 As shown, photoresist is applied to the surface of the first dielectric layer 160 on the side away from the first transistor structure layer 110 to form a photoresist pattern, and then the photoresist pattern is used to form an etching pattern on the first dielectric layer 160. The first dielectric layer 160, the first transistor 112 and the first semiconductor layer 111 are etched using the etching pattern to obtain a first contact hole that penetrates the first dielectric layer 160, the first transistor 112 and extends to the first semiconductor layer 111.

[0114] For example, the photoresist may be applied by static spin coating or dynamic spray coating. Alternatively, the first semiconductor layer 111 and the first transistor 112 may be etched by dry etching.

[0115] A connection contact 120 is formed in the first contact hole.

[0116] In this embodiment, the connection contact 120 is formed to shorten the wire length of the connection between the first transistor structure layer 110 and other circuit structures (e.g., array structures) inside the semiconductor structure 100, reduce the complexity of the wire, and avoid the influence of the stability of the semiconductor structure 100 caused by the coupling between the wires. In addition, the connection contact 120 penetrates the first transistor 112, so that the semiconductor structure 100 does not need to reserve a layout position for the connection contact 120 in the area outside the first transistor 112, thereby reducing the layout area of the semiconductor structure 100, improving the device density of the semiconductor structure 100, and realizing the further miniaturization of the semiconductor structure 100.

[0117] Figure 9 A preparation method flowchart of the connection contact 120 is provided for some embodiments of the present disclosure.

[0118] As shown in Figure 9 The preparation method of the connection contact 120 in step S2 includes steps S21-S22.

[0119] S21, a first contact hole is formed, which penetrates the first transistor 112 and extends into the first semiconductor layer 111.

[0120] In this step S21, dry etching can be used to etch the first dielectric layer 160, the first transistor 112, and the first semiconductor layer 111 to form the first contact hole.

[0121] S22, a first insulating layer 121 and a conductive column 122 are sequentially formed in the first contact hole, and the first insulating layer 121 is arranged around the conductive column 122.

[0122] Please continue to refer to Figure 8 In this step 22, the first insulating layer 121 is formed by epitaxial growth on the hole wall of the first contact hole. The insulating material of the first insulating layer 121 can include one or more of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and oxynitride materials (e.g., silicon oxynitride). The insulating material of the first insulating layer 121 can be the same as or different from the insulating material of the first dielectric layer 160.

[0123] After the first insulating layer 121 is formed, a conductive material can be deposited in the first contact hole by using a CVD, PVD, ALD, or any combination of thin film deposition processes to form the conductive column 122. The conductive material can include but is not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof.

[0124] In this way, by forming the first insulating layer 121 between the conductive column 122 and the first transistor 112, the conductive column 122 is isolated from the first transistor 112, avoiding contact between the conductive column and the internal doped region of the first transistor 112, which affects the reliability of the semiconductor structure 100. In addition, by depositing the conductive column 122, the device connected with the connection contact 120 can be electrically connected, thereby realizing the electrical signal transmission between the devices connected with the connection contact 120.

[0125] Although not shown, in some examples, when the connection contact 120 is connected with other devices outside the semiconductor structure 100, the connection contact 120 can penetrate the first semiconductor layer 111. That is, after forming the conductive column 122, the first semiconductor layer 111 can be thinned, for example, using a planarization process and / or an etching process, to expose the connection contact 120.

[0126] After forming the connection contact 120, the preparation method further includes forming an interconnection layer 130 on the side of the first transistor 112 away from the first semiconductor layer 111, and the connection contact 120 is connected to the first electrode of the first transistor 112 through the interconnection layer 130.

[0127] Figure 10 A preparation method flow chart of an interconnection layer 130 provided for some embodiments of the present disclosure, Figure 11 A structure diagram of a semiconductor structure 100 corresponding to the preparation method in Figure 10

[0128] As shown in Figure 10 The preparation method of the interconnection layer 130 includes the following steps S31-S32.

[0129] S31, forming an interconnection contact 132 on the side of the first transistor 112 away from the first semiconductor layer 111, and the interconnection contact 132 is connected with the first electrode 1211 of the first transistor 112 and the connection contact 120.

[0130] As shown in Figure 11 The interconnection contact 132 is formed on the side of the first dielectric layer 160 away from the first semiconductor layer 111, so that the connection between the connection contact 120 and the first electrode of the first transistor 112 is realized through the interconnection contact 132. In this way, it is beneficial to reduce the layout area while simplifying the preparation process of the connection contact 120 and improving the preparation efficiency.

[0131] S32, forming a circuit layer 131 on the side of the interconnection contact 132 away from the first semiconductor layer 111, and the circuit layer 131 is connected with the interconnection contact 132.

[0132] The circuit layer 131 is formed on the side of the interconnection contact 132 to obtain a structure as shown in Figure 3 ​The structure shown is a schematic diagram. For example, the circuit layer 131 can include interconnection circuits 171, such as metal wires or pad contacts, formed in at least one second dielectric layer 170. The second dielectric layer 170 can include a dielectric material, for example, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The interconnection circuits can include a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof.

[0133] In some examples, the material of the second dielectric layer 170 can be the same as the material of the first dielectric layer 160.

[0134] In this embodiment, by forming the circuit layer 131, the connection between the connection contact 120 and other devices of the semiconductor structure 100 can be achieved, so that other devices of the semiconductor structure 100 can be connected to an external circuit structure through the connection contact 120.

[0135] The preparation process of the circuit layer 131 will be introduced below.

[0136] For example, a dielectric material is deposited on the side of the interconnection contact 132 away from the first transistor structure layer 110 to form a second dielectric layer 170. According to the circuit connection requirement, a recess (for example, a strip-shaped slot) or a via hole is etched in the second dielectric layer 170, and a conductive material is filled in the recess or via hole to form an interconnection circuit or an interconnection contact, thereby forming a circuit layer 131.

[0137] Please continue to refer to Figure 11 In some embodiments, the above step S31 can further include the following step S311.

[0138] S311, a first connection part 1321 and a second connection part 1322 are sequentially formed on the side of the first transistor 112 away from the first semiconductor layer 111, the first connection part 1321 is located on the side of the second connection part 1322 close to the first transistor structure layer 110, the first connection part 1321 is connected to the first electrode, and the second connection part 1322 is connected to the first connection part 1321 and the connection contact 120.

[0139] In this step S311, photoresist is applied on the surface of the first dielectric layer 160 away from the first semiconductor layer 111 to form a photoresist pattern, and then an etching pattern is formed on the first dielectric layer 160 by using the photoresist pattern, and the first dielectric layer 160 is etched through the etching pattern to form a via hole, wherein the via hole exposes the first electrode of the first transistor 112.

[0140] As an example, the photoresist can be applied by static spin coating or dynamic spray coating, or any other suitable method. As an option, the first dielectric layer 160 can be etched by dry etching. As an implementation, a CVD, PVD, ALD or any combination thereof thin film deposition process can be used to deposit a conductive material in the via to form the first connection 1321 in contact with the first electrode. The conductive material can include, but is not limited to, W, Co, Cu, Al, doped Si, silicide, or any combination thereof.

[0141] In this step S311, a pad is formed on the side of the first dielectric layer 160 away from the first semiconductor layer 111, so as to realize the simultaneous leading-out of the first connection 1321 and the connection contact 120. The pad is the second connection 1322.

[0142] In this way, the first connection 1321 and the connection contact 120 can be simultaneously led out by the second connection 1322, i.e., the first electrode 1121 of the first transistor 112 and the connection contact 120 can be simultaneously led out by the second connection 1322, so that the first electrode 1121 can realize electrical signal transmission with other devices outside the semiconductor structure 100 via the connection contact 120. In this embodiment, the provision of the second connection 1322 can simplify the preparation process, reduce the preparation difficulty, and improve the preparation efficiency.

[0143] Figure 12 Another semiconductor structure 100 preparation method flowchart is provided for some embodiments of the present disclosure.

[0144] As shown in Figure 12 The semiconductor structure 100 preparation method further includes the following steps S4-S5.

[0145] S4, forming a conductive layer 140, the conductive layer 140 is formed on the side of the first semiconductor layer 111 away from the first transistor 112.

[0146] In this step S4, a CVD, PVD, ALD or any combination thereof thin film deposition process can be used to deposit a conductive material on the first semiconductor layer 111 to form the conductive layer 140. The conductive material can include, but is not limited to, W, Co, Cu, Al, doped Si, silicide, or any combination thereof.

[0147] S5, forming a second insulating layer 150, the second insulating layer 150 is formed on the side of the conductive layer 140 away from the first semiconductor layer 111, wherein the second insulating layer 150 includes a first opening 151, and the first opening 151 exposes part of the conductive layer 140.

[0148] In this step S5, the insulating material can be deposited on the conductive layer 140 by CVD, PVD, ALD or any combination thereof to form the second insulating layer 150. The insulating material can include one or more of oxide material (e.g. silicon oxide), nitride material (e.g. silicon nitride), oxynitride (e.g. silicon oxynitride).

[0149] In this embodiment, the conductive layer 140 can be used to simultaneously lead out the plurality of connection contacts 120 and connect with external circuit structure or device, thereby simplifying the circuit structure, reducing the circuit loss and lowering the manufacturing cost.

[0150] In addition, the second insulating layer 150 prepared on the conductive layer 140 can isolate the conductive layer 140 and even the whole semiconductor structure 100 from other external circuit structure or device, thereby improving the reliability of the semiconductor structure 100.

[0151] By providing the first opening 151 on the second insulating layer 150, a connection position for the conductive layer 140 to connect with external device or circuit structure can be reserved. For example, a pad pin can be prepared at the first opening 151, thereby simplifying the connection structure with external device or circuit structure while ensuring the reliability of the semiconductor structure 100.

[0152] The above merely provides the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of the changes or replacements within the technical scope disclosed by the present disclosure, which shall be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a first transistor structure layer comprising a first semiconductor layer and a first transistor disposed on one side of the first semiconductor layer; a connection contact penetrating the first semiconductor layer and the first transistor and connected to a first electrode of the first transistor.

2. The semiconductor structure according to claim 1, wherein: the connection contact comprises a first insulating layer and a conductive column, wherein the conductive column penetrates the first semiconductor layer and the first transistor, the conductive column is connected to the first electrode of the first transistor, and the first insulating layer is disposed around the conductive column.

3. The semiconductor structure of claim 2, wherein, Further comprising: an interconnection layer disposed on a side of the first transistor away from the first semiconductor layer; the conductive column is connected to the first electrode of the first transistor through the interconnection layer.

4. The semiconductor structure of claim 3, wherein, The interconnection layer comprises a circuit layer and a plurality of interconnection contacts between the circuit layer and the first transistor structure layer; the circuit layer is connected to the first electrode of the first transistor through one of the interconnection contacts, and the connection contact is connected to the interconnection contact.

5. The semiconductor structure of claim 4, wherein, The interconnection contact comprises a first connecting portion and a second connecting portion connected to each other, the first connecting portion is located on a side of the second connecting portion close to the first transistor structure layer, the second connecting portion is connected to the circuit layer, the first connecting portion is connected to the first electrode, and the second connecting portion is connected to the connection contact.

6. The semiconductor structure according to any one of claims 1-5, wherein: the connection contact penetrates the first electrode connected thereto.

7. The semiconductor structure according to claim 6, wherein: the first semiconductor layer comprises a substrate and a doped layer disposed between the substrate and the first transistor; wherein the connection contact penetrates the doped layer and the substrate.

8. The semiconductor structure of claim 7, wherein, Further comprising: an array structure stacked on a side of the interconnection layer away from the first transistor structure layer and bonded to the interconnection layer.

9. The semiconductor structure of claim 8, wherein, The array structure comprises: a second semiconductor layer; a storage array disposed on a side of the second semiconductor layer, the interconnection layer being bonded on a side of the storage array away from the second semiconductor layer.

10. The semiconductor structure of claim 9, wherein, The storage array comprises a plurality of wires, a plurality of second transistors, and a plurality of capacitors, the plurality of capacitors being located between the plurality of second transistors and the second semiconductor layer, and the plurality of wires being located on a side of the plurality of second transistors away from the second semiconductor layer; a second electrode of each of the second transistors is connected to one end of one of the capacitors, third electrodes of the plurality of second transistors are connected to the same wire, and the wire is connected to the interconnection layer.

11. The semiconductor structure of claim 10, wherein, Further comprising: a conductive layer disposed on a side of the first semiconductor layer away from the first transistor; a second insulating layer disposed on a side of the conductive layer away from the first semiconductor layer, wherein the second insulating layer comprises a first opening exposing part of the conductive layer.

12. A method of fabricating a semiconductor structure, characterized by, The semiconductor structure comprises: forming a first transistor structure layer, the first transistor structure layer comprising a first semiconductor layer and a first transistor disposed on one side of the first semiconductor layer; forming a connection contact, the connection contact penetrating the first semiconductor layer and the first transistor and connected to a first electrode of the first transistor.

13. The method of claim 12, wherein the semiconductor structure is prepared by a method comprising: The forming of the connection contact comprises: forming a first contact hole, the first contact hole penetrating the first transistor and extending into the first semiconductor layer; forming a first insulating layer and a conductive column in the first contact hole in sequence, the first insulating layer being disposed around the conductive column.

14. The method of producing a semiconductor structure according to claim 12 or 13, characterized in that, The method further comprises: forming a conductive layer on a side of the first semiconductor layer away from the first transistor; forming a second insulating layer on a side of the conductive layer away from the first semiconductor layer, wherein the second insulating layer comprises a first opening exposing part of the conductive layer. The method further comprises: forming a semiconductor structure, the semiconductor structure comprising a first semiconductor layer and a first transistor disposed on one side of the first semiconductor layer; 15. The method of claim 14, wherein the semiconductor structure is prepared by a method comprising: forming a connection contact, the connection contact penetrating the first semiconductor layer and the first transistor and connected to a first electrode of the first transistor. The forming of the connection contact comprises:

16. The method of claim 15, wherein the semiconductor structure is prepared by a method comprising: forming a first contact hole, the first contact hole penetrating the first transistor and extending into the first semiconductor layer; forming a first insulating layer and a conductive column in the first contact hole in sequence, the first insulating layer being disposed around the conductive column. The method further comprises:

17. A storage system, characterized by forming a conductive layer on a side of the first semiconductor layer away from the first transistor; forming a second insulating layer on a side of the conductive layer away from the first semiconductor layer, wherein the second insulating layer comprises a first opening exposing part of the conductive layer. The method further comprises:

18. An electronic device, characterized in that: forming a semiconductor structure, the semiconductor structure comprising a first semiconductor layer and a first transistor disposed on one side of the first semiconductor layer; forming a connection contact, the connection contact penetrating the first semiconductor layer and the first transistor and connected to a first electrode of the first transistor. The forming of the connection contact comprises: forming a first contact hole, the first contact hole penetrating the first transistor and extending into the first semiconductor layer; forming a first insulating layer and a conductive column in the first contact hole in sequence, the first insulating layer being disposed around the conductive column. The method further comprises: forming a conductive layer on a side of the first semiconductor layer away from the first transistor; forming a second insulating layer on a side of the conductive layer away from the first semiconductor layer, wherein the second insulating layer comprises a first opening exposing part of the conductive layer. The method further comprises: forming a semiconductor structure, the semiconductor structure comprising a first semiconductor layer and a first transistor disposed on one side of the first semiconductor layer; forming a connection contact, the connection contact penetrating the first semiconductor layer and the first transistor and connected to a first electrode of the first transistor. The forming of the connection contact comprises: forming a first contact hole, the first contact hole penetrating the first transistor and extending into the first semiconductor layer; forming a first insulating layer and a conductive column in the first contact hole in sequence, the first insulating layer being disposed around the conductive column. The method further comprises: forming a conductive layer on a side of the first semiconductor layer away from the first transistor; forming a second insulating layer on a side of the conductive layer away from the first semiconductor layer, wherein the second insulating layer comprises a first opening exposing part of the conductive layer. The method further comprises: forming a semiconductor structure, the semiconductor structure comprising a first semiconductor layer and a first transistor disposed on one side of the first semiconductor layer; forming a connection contact, the connection contact penetrating the first semiconductor layer and the first transistor and connected to a first electrode of the first transistor. The forming of the connection contact comprises: forming a first contact hole, the first contact hole penetrating the first transistor and extending into the first semiconductor layer; forming a first insulating layer and a conductive column in the first contact hole in sequence, the first insulating layer being disposed around the conductive column. The method further comprises: forming a conductive layer on a side of the first semiconductor layer away from the first transistor; forming a second insulating layer on a side of the conductive layer away from the first semiconductor layer, wherein the second insulating layer comprises a first opening exposing part of the conductive layer. The method further comprises: forming a semiconductor structure, the semiconductor structure comprising a first semiconductor layer and a first transistor disposed on one side of the first semiconductor layer; forming a connection contact, the connection contact penetrating the first semiconductor layer and the first transistor and connected to a first electrode of the first transistor. The forming of the connection contact comprises: forming a first contact hole, the first contact hole penetrating the first transistor and extending into the first semiconductor layer; forming a first insulating layer and a conductive column in the first contact hole in sequence, the first insulating layer being disposed around the conductive column. The method further comprises: forming a conductive layer on a side of the first semiconductor layer away from the first transistor; forming a second insulating layer on a side of the conductive layer away from the first semiconductor layer, wherein the second insulating layer comprises a first opening exposing part of the conductive layer. The method further comprises: forming a semiconductor structure, the semiconductor structure comprising a first semiconductor layer and a first transistor disposed on one side of the first semiconductor layer; forming a connection contact, the connection contact penetrating the first semiconductor layer and the first transistor and connected to a first electrode of the first transistor. The forming of the connection contact comprises: forming a first contact hole, the first contact hole penetrating the first transistor and extending into the first semiconductor layer; forming a first insulating layer and a conductive column in the first contact hole in sequence, the first insulating layer being disposed around the conductive column. The method further comprises: forming a conductive layer on a side of the first semiconductor layer away from the first transistor; forming a second insulating layer on a side of the conductive layer away from the first semiconductor layer, wherein the second insulating layer comprises a first opening exposing part of the conductive layer. The method further comprises: forming a semiconductor structure, the semiconductor structure comprising a first semiconductor layer and a first transistor disposed on one side of the first semiconductor layer; forming a connection contact, the connection contact penetrating the first semiconductor layer and the first transistor and connected to a first electrode of the first transistor. The forming of the connection contact comprises: forming a first contact hole, the first contact hole penetrating the first transistor and extending into the first semiconductor layer; forming a first insulating layer and a conductive column in the first contact hole in sequence, the first insulating layer being disposed around the conductive column. The method further comprises: forming a conductive layer on a side of the first semiconductor layer away from the first transistor; forming a second insulating layer on a side of the conductive layer away from the first semiconductor layer, wherein the second insulating layer comprises a first opening exposing part of the conductive layer. The method further comprises: forming a semiconductor structure, the semiconductor structure comprising a first semiconductor layer and a first transistor disposed on one side of the first semiconductor layer; forming a connection contact, the connection contact penetrating the first semiconductor layer and the first transistor and connected to a first electrode of the first transistor. The forming of the connection contact comprises: forming a first contact hole, the first contact hole penetrating the first transistor and extending into the first semiconductor layer; forming a first insulating layer and a conductive column in the first contact hole in sequence, the first insulating layer being disposed around the conductive column. The method further comprises: forming a conductive layer on a side of the first semiconductor layer away from the first transistor; forming a second insulating layer on a side of the conductive layer away from the first semiconductor layer, wherein the second insulating layer comprises a first opening exposing part of the conductive layer. The method further comprises: forming a semiconductor structure, the semiconductor structure comprising a first semiconductor layer and a first transistor disposed on one side of the first semiconductor layer; forming a connection contact, the connection contact penetrating the first semiconductor layer and the first transistor and connected to a first electrode of the first transistor. The forming of the connection contact comprises: forming a first contact hole, the first contact hole penetrating the first transistor and extending into the first semiconductor layer; forming a first insulating layer and a conductive column in the first contact hole in sequence, the first insulating layer being disposed around the conductive column. The method further comprises: forming a conductive layer on a side of the first semiconductor layer away from the first transistor; forming a second insulating layer on a side of the conductive layer away from the first semiconductor layer, wherein the second insulating layer comprises a first opening exposing part of the conductive layer. The method further comprises: forming a semiconductor structure, the semiconductor structure comprising a first semiconductor layer and a first transistor disposed on one side of the first semiconductor layer; forming a connection contact, the connection contact penetrating the first semiconductor layer and the first transistor and connected to a first electrode of the first transistor. The forming of the connection contact comprises: forming a first contact hole, the first contact hole penetrating the first transistor and extending into the first semiconductor layer; forming a first insulating layer and a conductive column in the first contact hole in sequence, the first insulating layer being disposed around the conductive column. The method further comprises: forming a conductive layer on a side of the first semiconductor layer away from the first transistor; forming a second insulating layer on a side of the conductive layer away from the first semiconductor layer, wherein the second insulating layer comprises a first opening exposing part of the conductive layer. The method further comprises: forming a semiconductor structure, the semiconductor structure comprising

Images