Semiconductor element and forming method thereof

Abstract

The semiconductor element comprises a lower electrode layer, a barrier layer, a dielectric layer and an upper electrode layer. The barrier layer is disposed on the lower electrode layer. The dielectric layer is disposed on the barrier layer. The upper electrode layer is arranged on the dielectric layer. The barrier layer is located between the lower electrode layer and the dielectric layer. The forming method of the semiconductor element improves the electrical performance of the whole semiconductor element.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a method of forming the same. BACKGROUND

[0002] As dynamic random access memory (DRAM) capacitor size is developed, much effort has been put into finding new material stacks to overcome the size limitations of current material stacks, such as leakage and capacitance. Shrinking capacitor dielectrics more and more difficultly meet the retention time target. Therefore, it is needed to reduce the leakage current in the cell capacitance. In the thermal treatment of the subsequent layers, oxygen in the dielectric high-k layer diffuses towards the titanium nitride (TiN) electrode, and then creates some oxygen vacancies in the dielectric high-k layer. The leakage current can pass through the oxygen vacancies, which makes the capacitor leakage current more serious. In addition, the thermal treatment of the subsequent layers causes the thickness of the TiN electrode and the dielectric interface to be unstable. The unstable interface can cause the capacitor effective oxygen thickness (EOT) to have variations. The leakage and thickness stability of the interface between the TiN electrode and the dielectric are the key points of micro-DRAM. SUMMARY

[0003] Therefore, the present disclosure provides a semiconductor device and a method of forming the same to solve the above problems.

[0004] To achieve the above object, according to one embodiment of the present disclosure, a semiconductor device includes a lower electrode layer, a barrier layer, a dielectric layer, and an upper electrode layer. The barrier layer is disposed on the lower electrode layer. The dielectric layer is disposed on the barrier layer. The upper electrode layer is disposed on the dielectric layer. The barrier layer is between the lower electrode layer and the dielectric layer.

[0005] In one or more embodiments of the present disclosure, the dielectric layer is separated from the lower electrode layer by the barrier layer.

[0006] In one or more embodiments of the present disclosure, the dielectric layer includes a high-k material.

[0007] In one or more embodiments of the present disclosure, the barrier layer includes an upper portion and a lower portion. The material of the upper portion is different from the material of the lower portion.

[0008] In one or more embodiments of the present disclosure, the material of the lower portion of the barrier layer has the same electron affinity as the material of the lower electrode layer.

[0009] In one or more embodiments of the present disclosure, the thickness of the barrier layer is in a range between 5 angstroms and 35 angstroms .

[0010] To achieve the above object, according to one embodiment of the present disclosure, a semiconductor device includes a lower electrode layer, a first barrier layer, a second barrier layer, a dielectric layer, and an upper electrode layer. The first barrier layer is disposed on the lower electrode layer. The second barrier layer is disposed on the first barrier layer. The first barrier layer and the second barrier layer form a barrier layer. The dielectric layer is disposed on the second barrier layer. The upper electrode layer is disposed on the dielectric layer.

[0011] In one or more embodiments of the present disclosure, the dielectric layer is separated from the lower electrode layer by the first barrier layer and the second barrier layer.

[0012] In one or more embodiments of the present disclosure, the material of the first barrier layer is different from the material of the second barrier layer.

[0013] In one or more embodiments of the present disclosure, the material of the second barrier layer has the same electron affinity as the material of the lower electrode layer.

[0014] In one or more embodiments of the present disclosure, the thickness of the first barrier layer is in a range between 4 angstroms (A) and 20 A, and the thickness of the second barrier layer is in a range between 1 A and 20 A.

[0015] In one or more embodiments of the present disclosure, the thickness of the barrier layer is in a range between 5 angstroms (A) and 35 A.

[0016] To achieve the above object, according to one embodiment of the present disclosure, a method for forming a semiconductor device includes: forming a lower electrode layer; depositing a first barrier layer on the lower electrode layer; depositing a second barrier layer on the first barrier layer, such that the first barrier layer and the second barrier layer form a barrier layer; forming a dielectric layer on the second barrier layer; and forming an upper electrode layer on the dielectric layer.

[0017] In one or more embodiments of the present disclosure, the step of depositing the first barrier layer is performed after the step of forming the lower electrode layer.

[0018] In one or more embodiments of the present disclosure, the step of depositing the second barrier layer is performed after the step of depositing the first barrier layer.

[0019] In one or more embodiments of the present disclosure, the step of depositing the first barrier layer is performed by ozone treatment.

[0020] In one or more embodiments of the present disclosure, the process temperature for depositing the first barrier layer is in a range between 200 degrees Celsius (°C) and 400 °C. ​​​​​​

[0021] In one or more embodiments of the present disclosure, depositing the first barrier layer is performed by using ozone, and the ozone has a density in a range between 50 grams per cubic meter (g / m3) and 500 grams per cubic meter (g / m3).

[0022] In one or more embodiments of the present disclosure, the step of depositing the second barrier layer is performed by using nitrogen plasma.

[0023] In one or more embodiments of the present disclosure, a process temperature of depositing the second barrier layer is in a range between 200 degrees Celsius (°C) and 600 degrees Celsius (°C).

[0024] In summary, in the semiconductor element and the forming method thereof of the present disclosure, since the barrier layer is formed between the lower electrode layer and the dielectric layer, the barrier layer can inhibit the ions of the dielectric layer from diffusing toward the lower electrode layer, thereby stabilizing the thickness of the interface between the dielectric layer and the lower electrode layer. In the semiconductor element and the forming method thereof of the present disclosure, since the barrier layer comprises the first barrier layer and the second barrier layer, and the electron affinity of the material of the second barrier layer is the same as the electron affinity of the material of the second barrier layer, the ions generated from the dielectric layer can be captured by the second barrier layer, thereby avoiding the leakage problem of the semiconductor element. In the semiconductor element and the forming method thereof of the present disclosure, since the material of the first barrier layer is different from the material of the second barrier layer, the thickness of the barrier layer composed of multiple layers of different materials can be smaller than the thickness of the barrier layer composed of a single layer of a single type of material, thereby reducing the resistance of the semiconductor element. Overall, the forming method of the semiconductor element of the present disclosure improves the electrical performance of the entire semiconductor element.

[0025] The above merely provides the problems to be solved by the present disclosure, the technical means to solve the problems, and the effects thereof, and specific details of the present disclosure will be described in the embodiments below and the related drawings. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more obvious and easy to understand, the following describes the drawings:

[0027] Figure 1 A flowchart of a forming method of a semiconductor element according to an embodiment of the present disclosure is shown.

[0028] Figure 2 A cross-sectional view of an intermediate stage of forming a semiconductor element according to an embodiment of the present disclosure is shown.

[0029] Figure 3 A cross-sectional view of an intermediate stage of forming a semiconductor element according to an embodiment of the present disclosure is shown.

[0030] Figure 4 FIG. 1 illustrates a cross-sectional view of a semiconductor device 100 formed according to an embodiment of the present disclosure.

[0031] Figure 5 FIG. 1 illustrates a cross-sectional view of a semiconductor device 100 formed according to an embodiment of the present disclosure.

[0032] Figure 6 FIG. 1 illustrates a cross-sectional view of a semiconductor device 100 formed according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] The following detailed description is presented in terms of a number of different embodiments or implementations for implementing different features of the provided patent. The detailed description is presented for purposes of simplicity and ease of understanding. It is not intended to constrain the application to the

[0034] Also for ease of description, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for describing the orientation of one element or feature to another element or feature, as shown in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0035] As used herein, "about", "approximately", "around", or "substantially" generally means within 20% or within 10% or within 5% of a given value or range. Numerical values given herein are approximate, meaning that terms such as "about", "approximately", "around", or "substantially" can be inferred if not expressly stated.

[0036] Reference is made to Figure 1 . Figure 1 FIG. 1 illustrates a cross-sectional view of a semiconductor device 100 formed according to an embodiment of the present disclosure. Figure 6 FIG. 1 illustrates a cross-sectional view of a semiconductor device 100 formed according to an embodiment of the present disclosure. Figure 1The method M shown includes a step S101, a step S102, a step S103, a step S104, and a step S105. For a better understanding of the step S101, please refer to Figure 1 and Figure 2 . For a better understanding of the step S102, please refer to Figure 1 and Figure 3 . For a better understanding of the step S103, please refer to Figure 1 and Figure 4 . For a better understanding of the step S104, please refer to Figure 1 and Figure 5 . For a better understanding of the step S105, please refer to Figure 1 and Figure 6 .

[0037] The step S101, the step S102, the step S103, the step S104, and the step S105 are explained in detail below.

[0038] In the step S101, a lower electrode layer 110 is formed.

[0039] Please refer to Figure 1 and Figure 2 . Figure 2 is a cross-sectional view of an intermediate stage of forming a semiconductor device 100 according to an embodiment of the present disclosure. As Figure 2 shown, in the present embodiment, a lower electrode layer 110 is provided. In some embodiments, the lower electrode layer 110 is configured as a lower electrode of the semiconductor device 100 as Figure 6 shown. In some embodiments, the semiconductor device 100 is configured as a capacitor of a dynamic random access memory (DRAM).

[0040] In some embodiments, the lower electrode layer 110 can be a conductive material. In some embodiments, the lower electrode layer 110 can be a metal material. In some embodiments, the lower electrode layer 110 can include, for example, titanium nitride (TiN) or other similar materials. However, any suitable material can be used.

[0041] In some embodiments, the lower electrode layer 110 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), electroless plating, or other similar methods. The present disclosure is not intended to be limited to the method of forming the lower electrode layer 110.

[0042] In the step S102, a first barrier layer 120 is deposited.

[0043] Reference is made to Figure 1 and Figure 3 , Figure 3 is a cross-sectional view of an intermediate stage of forming a semiconductor element 100 according to an embodiment of the present disclosure. As shown in Figure 3 , in the present embodiment, a first barrier layer 120 is formed on the lower electrode layer 110. In other words, the deposition of the first barrier layer 120 is performed after the step of forming the lower electrode layer 110. As shown in Figure 3 , the first barrier layer 120 is formed by a deposition process DEP1. In some embodiments, the first barrier layer 120 has a thickness T 120 .

[0044] In some embodiments, the thickness T 120 of the first barrier layer 120 is in a range between about 4 angstroms (A) and about 20 angstroms (A) , but the present disclosure is not limited thereto. In some embodiments where the thickness T 120 of the first barrier layer 120 is less than about 4 angstroms (A), the first barrier layer 120 can not be able to suppress the diffusion of ions toward the lower electrode layer 110, thereby causing a leakage problem to occur. In some embodiments where the thickness T 120 of the first barrier layer 120 is greater than about 20 angstroms (A), the resistance of the semiconductor element 100 can not be satisfactory, thereby reducing the total capacitance of the semiconductor element 100.

[0045] In some embodiments, the first barrier layer 120 can comprise, for example, titanium oxide (TiO2) or other similar materials. However, any suitable material can be used.

[0046] In some embodiments, the first barrier layer 120 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), electroless plating, or other similar methods. The present disclosure is not intended to be limited to the method of forming the first barrier layer 120.

[0047] In some embodiments, the first barrier layer 120 can be deposited by a deposition process DEP1 using ozone treatment. The present disclosure is not intended to be limited to the method of forming the first barrier layer 120.

[0048] In some embodiments, the process temperature of the deposition process DEP1 of depositing the first barrier layer 120 is in a range between about 200 degrees Celsius (°C) and about 400 degrees Celsius (°C). However, the present disclosure is not limited thereto.

[0049] In some embodiments, the first barrier layer 120 can be deposited by a deposition process DEP1 using ozone. In some embodiments, the density of ozone is in a range between about 50 grams per cubic meter (g / m 3 ) and about 500 grams per cubic meter (g / m 3 ). However, the present disclosure is not limited to this.

[0050] In step S103, the second barrier layer 130 is deposited.

[0051] Please refer to Figure 1 and Figure 4 . Figure 4 is a cross-sectional view of an intermediate stage of forming the semiconductor element 100 according to an embodiment of the present disclosure. As shown in Figure 4 , in the present embodiment, the second barrier layer 130 is formed on the first barrier layer 120. As shown in Figure 4 , the second barrier layer 130 is formed by a deposition process DEP2. In some embodiments, the second barrier layer 130 has a thickness T 130 . As shown in Figure 4 , in some embodiments, the deposition of the second barrier layer 130 is performed after the deposition of the first barrier layer 120, so that a barrier layer BL is formed. More specifically, the barrier layer BL includes an upper portion (e.g., the second barrier layer 130) and a lower portion (e.g., the first barrier layer 120). In some embodiments, the material of the upper portion is different from the material of the lower portion. In other words, the material of the first barrier layer 120 is different from the material of the second barrier layer 130. In some embodiments, the material of the lower portion of the barrier layer BL has the same electron affinity as the material of the lower electrode layer 110. In other words, the material of the first barrier layer 120 has the same electron affinity as the material of the lower electrode layer 110. In some embodiments, the barrier layer BL has a thickness T BL . In some embodiments, the thickness T BL of the barrier layer BL is substantially the sum of the thickness T 120 of the first barrier layer 120 and the thickness T 130 of the second barrier layer 130.

[0052] In some embodiments, the thickness T 130 of the second barrier layer 130 is in a range between about 1 angstrom and about 20 angstrom , but the present disclosure is not limited to this. In some embodiments, the thickness T 130 of the second barrier layer 130 is in a range between about 1 angstrom and about 20 angstrom.In some embodiments where the thickness is less than about 1 angstrom, the second barrier layer 130 may not be able to inhibit ions from diffusing toward the first barrier layer 120 and the lower electrode layer 110, thereby causing leakage problems. 130 In some embodiments, the resistance of the semiconductor device 100 may be unsatisfactory if the resistance is greater than about 20 angstroms, thereby reducing the overall capacitance of the semiconductor device 100 .

[0053] In some embodiments, the thickness T of the second barrier layer 130 is 130 It can be smaller than the thickness T of the first barrier layer 120 120 However, the present disclosure is not limited thereto.

[0054] In some embodiments, the thickness T of the first barrier layer 120 is 120 In some embodiments, the thickness T of the second barrier layer 130 is about 8.5 angstroms. 130 Preferably, it is about 1.5 angstroms. However, the present disclosure is not limited thereto.

[0055] In some embodiments, the thickness T of the barrier layer BL is BL At about 5 angstroms to about 35 angstroms The thickness T of the barrier layer BL is within the range of , but the present disclosure is not limited thereto. BL In some embodiments where the thickness of the barrier layer BL is less than about 5 angstroms, the barrier layer BL may not be able to inhibit the diffusion of ions toward the lower electrode layer 110, thereby causing leakage problems. BL In some embodiments, the resistance of the semiconductor device 100 may be unsatisfactory if the resistance is greater than about 35 angstroms, thereby reducing the overall capacitance of the semiconductor device 100 .

[0056] In some embodiments, the second barrier layer 130 may include materials such as titanium oxynitride (TiON) or the like. However, any suitable material may be used.

[0057] In some embodiments, the second barrier layer 130 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), or other similar methods. The present disclosure is not intended to be limited to the method for forming the second barrier layer 130.

[0058] In some embodiments, the second barrier layer 130 may be deposited by a deposition process DEP2 using nitrogen plasma. The present disclosure is not intended to be limited to the method of forming the second barrier layer 130 .

[0059] In some embodiments, the process temperature of the deposition process DEP2 for depositing the second barrier layer 130 is in a range between about 200 degrees Celsius (°C) and about 600 degrees Celsius (°C). However, the present disclosure is not intended to be limited thereto.

[0060] In step S104, the dielectric layer 140 is formed.

[0061] Referring to Figure 1 and Figure 5 . Figure 5 A cross-sectional view of an intermediate stage of forming the semiconductor element 100 according to an embodiment of the present disclosure is shown. As shown in Figure 5 , in the present embodiment, the dielectric layer 140 is disposed on the barrier layer BL. In some embodiments, the dielectric layer 140 is disposed on the second barrier layer 130. As shown in Figure 5 , the barrier layer BL is located between the lower electrode layer 110 and the dielectric layer 140. In other words, the dielectric layer 140 is separated from the lower electrode layer 110 by the barrier layer BL. In some embodiments, the first barrier layer 120 and the second barrier layer 130 are located between the lower electrode layer 110 and the dielectric layer 140. In other words, the dielectric layer 140 is separated from the lower electrode layer 110 by the first barrier layer 120 and the second barrier layer 130.

[0062] In some embodiments, the dielectric layer 140 can comprise a high-k material. In some embodiments, the dielectric layer 140 can comprise an oxide material. In some embodiments, the dielectric layer 140 can comprise a material such as zirconium oxide (Zr02), hafnium oxide (Hf02), aluminum oxide (AI2O3), silicon oxide (Si02), or other similar materials. However, any suitable material can be used.

[0063] In some embodiments, the dielectric layer 140 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), electroless plating, or other similar methods. The present disclosure is not intended to be limited to the method for forming the dielectric layer 140.

[0064] As shown in Figure 4 , in some embodiments, step S104 is performed after step S103. In some embodiments, the step of forming the dielectric layer 140 is performed after the step of forming the barrier layer BL. In other words, the formation of the dielectric layer 140 is performed after the deposition of the second barrier layer 130.

[0065] In some embodiments of the dielectric layer 140 composed of high-k oxides, oxygen in the dielectric layer 140 diffuses toward the lower electrode layer 110 during subsequent processes (e.g., thermal treatment), and then creates some vacancies in the dielectric layer 140. Because of the similar (or, in some embodiments, the same) electron affinity between the barrier layer BL (particularly, the first barrier layer 120) and the lower electrode layer 110, the barrier layer BL can inhibit the diffusion of oxygen toward the lower electrode layer 110.

[0066] In step S105, the upper electrode layer 150 is formed.

[0067] Please refer to Figure 1 and Figure 6 . Figure 6 is a cross-sectional view of an intermediate stage of forming the semiconductor element 100 according to an embodiment of the present disclosure. As shown in Figure 6 , in the present embodiment, the upper electrode layer 150 is formed, so that the semiconductor element 100 is formed. More specifically, the upper electrode layer 150 is disposed on the dielectric layer 140. The dielectric layer 140 is disposed between the upper electrode layer 150 and the lower electrode layer 110, so that a capacitor is formed. In some embodiments, the upper electrode layer 150 is configured as the upper electrode of the semiconductor element 100 as shown in Figure 6 .

[0068] In some embodiments, the upper electrode layer 150 can be a conductive material. In some embodiments, the upper electrode layer 150 can be a metallic material. In some embodiments, the upper electrode layer 150 can include, for example, titanium nitride (TiN) or other similar materials. However, any suitable material can be used.

[0069] In some embodiments, the upper electrode layer 150 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), electroless plating, or other similar methods. The present disclosure is not intended to be limited to the method of forming the upper electrode layer 150.

[0070] By performing the method M shown in Figure 1 , the semiconductor element 100 with better electrical performance can be formed.

[0071] As is evident from the foregoing detailed description of the specific embodiments of the present disclosure, in the semiconductor element and the method of forming the same of the present disclosure, the barrier layer is formed between the lower electrode layer and the dielectric layer, so that the barrier layer can inhibit the diffusion of ions of the dielectric layer toward the lower electrode layer, thereby stabilizing the thickness of the interface between the dielectric layer and the lower electrode layer. In the semiconductor element and the method of forming the same of the present disclosure, since the barrier layer includes the first barrier layer and the second barrier layer, and the material of the second barrier layer has the same electron affinity as the material of the second barrier layer, the ions generated from the dielectric layer can be captured by the second barrier layer, thereby avoiding the leakage problem of the semiconductor element. In the semiconductor element and the method of forming the same of the present disclosure, since the material of the first barrier layer is different from the material of the second barrier layer, the thickness of the barrier layer composed of multiple layers of different materials can be smaller than the thickness of the barrier layer composed of a single layer of a single type of material, thereby reducing the resistance of the semiconductor element. Overall, the method of forming the semiconductor element of the present disclosure improves the electrical performance of the entire semiconductor element.

[0072] While the present disclosure has been described in detail with respect to certain embodiments thereof, other embodiments are possible. Accordingly, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0073] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the present disclosure presented herein. Those skilled in the art should appreciate that they can readily use the foregoing description and embodiments as a basis for modifying or designing other structures for carrying out the same purposes and / or achieving the same advantages of the embodiments presented herein. Those skilled in the art should accordingly see the description as illustrative only and not in a limiting sense as to the scope of the disclosure.

[0074] [Explanation of Symbols]

[0075] 100: semiconductor element

[0076] 110: lower electrode layer

[0077] 120: first barrier layer

[0078] 130: second barrier layer

[0079] 140: dielectric layer

[0080] 150: upper electrode layer

[0081] BL: barrier layer

[0082] DEP1, DEP2: deposition process

[0083] M: method

[0084] S101, S102, S103, S104, S105: step

[0085] T 120 ,T 130 ,T BL : thickness.

Claims

1. A semiconductor element, characterized by, A method for manufacturing a capacitor, comprising: forming a lower electrode layer; depositing a first barrier layer on the lower electrode layer; depositing a second barrier layer on the first barrier layer, such that the first barrier layer and the second barrier layer form a barrier layer; forming a dielectric layer on the second barrier layer; and 2. The semiconductor device according to claim 1, wherein forming an upper electrode layer on the dielectric layer.

3. The semiconductor device according to claim 1, wherein The step of depositing the first barrier layer is performed after the step of forming the lower electrode layer.

4. The semiconductor device according to claim 1, wherein The step of depositing the second barrier layer is performed after the step of depositing the first barrier layer.

5. The semiconductor device according to claim 1, wherein The step of depositing the first barrier layer is performed by ozone treatment.

6. The semiconductor device according to claim 5, wherein The barrier layer has a thickness in the range of 5 Angstroms and 35 Angstroms .

7. A semiconductor element characterized by comprising: The process temperature of the step of depositing the first barrier layer is in a range between 200 degrees Celsius (°C) and 400 degrees Celsius (°C). The step of depositing the second barrier layer is performed by using nitrogen plasma. The process temperature of the step of depositing the second barrier layer is in a range between 200 degrees Celsius (°C) and 600 degrees Celsius (°C). A method for manufacturing a capacitor, comprising: forming a lower electrode layer; depositing a first barrier layer on the lower electrode layer; depositing a second barrier layer on the first barrier layer, such that the first barrier layer and the second barrier layer form a barrier layer; 8. The semiconductor device according to claim 7, wherein forming a dielectric layer on the second barrier layer; 9. The semiconductor device according to claim 7, wherein and 10. The semiconductor device according to claim 7, wherein forming an upper electrode layer on the dielectric layer.

11. The semiconductor device according to claim 7, wherein The first barrier layer has a thickness in the range of 4 Angstroms and 20 Angstroms and the second barrier layer has a thickness in the range of 1 Angstrom and 20 Angstroms .

12. The semiconductor device according to claim 7, wherein The barrier layer has a thickness in the range of 5 Angstroms to 35 Angstroms between 5 Angstroms and 35 Angstroms.

13. A method for forming a semiconductor element, characterized by, The dielectric layer is separated from the lower electrode layer by the barrier layer. The dielectric layer comprises a high-k material. The barrier layer comprises an upper portion and a lower portion, and the material of the upper portion is different from the material of the lower portion. The material of the lower portion of the barrier layer has the same electron affinity as the material of the lower electrode layer. A method for manufacturing a capacitor, comprising: forming a lower electrode layer; depositing a first barrier layer on the lower electrode layer; 14. The method of claim 13, wherein, depositing a second barrier layer on the first barrier layer, such that the first barrier layer and the second barrier layer form a barrier layer; 15. The method of claim 13, wherein, forming a dielectric layer on the second barrier layer; 16. The method of claim 13, wherein, and 17. The method of claim 13, wherein, forming an upper electrode layer on the dielectric layer.

18. The method of claim 13, wherein, The depositing the first barrier layer is performed by using ozone, and the ozone has a density in a range between 50 grams per cubic meter (g / m 3 ) and 500 grams per cubic meter (g / m 3 ).

19. The method of claim 13, wherein, The dielectric layer is separated from the lower electrode layer by the first barrier layer and the second barrier layer.

20. The method of claim 13, wherein, The material of the first barrier layer is different from the material of the second barrier layer. The material of the second barrier layer has the same electron affinity as the material of the lower electrode layer. A method for manufacturing a capacitor, comprising: forming a lower electrode layer; depositing a first barrier layer on the lower electrode layer; depositing a second barrier layer on the first barrier layer, such that the first barrier layer and the second barrier layer form a barrier layer; forming a dielectric layer on the second barrier layer; and forming an upper electrode layer on the dielectric layer. The step of depositing the first barrier layer is performed after the step of forming the lower electrode layer. The step of depositing the second barrier layer is performed after the step of depositing the first barrier layer. The step of depositing the first barrier layer is performed by ozone treatment. The process temperature of the step of depositing the first barrier layer is in a range between 200 degrees Celsius (°C) and 400 degrees Celsius (°C). The step of depositing the second barrier layer is performed by using nitrogen plasma. The process temperature of the step of depositing the second barrier layer is in a range between 200 degrees Celsius (°C) and 600 degrees Celsius (°C).

Images