Semiconductor device and data storage system including same

Abstract

A semiconductor device and a data storage system including the same are provided. The semiconductor device includes a first semiconductor structure including a substrate, a circuit device on the substrate, and a circuit interconnect on the circuit device; and a second semiconductor structure on the first semiconductor structure and having a first region and a second region. The second semiconductor structure comprises a plate layer; gate electrodes stacked in a vertical direction on an upper surface of the plate layer and spaced apart from each other, extending a different length in a first direction intersecting the vertical direction on the second region, and including a gate contact region; interlayer insulating layers alternately stacked with the gate electrodes; a channel structure penetrating the gate electrode and the interlayer insulating layer in the first region and extending in a vertical direction; and contact plugs penetrating the gate electrode in the second region, extending in the vertical direction, and electrically connecting the gate electrode to a portion of the circuit interconnects, respectively.

Description

TECHNICAL FIELD

[0001] Various example embodiments relate to a semiconductor device and a data storage system including the same. BACKGROUND

[0002] A semiconductor device capable of storing large-capacity data in a data storage system is desirable. Therefore, methods for increasing the data storage capacity of a semiconductor device have been studied. For example, as a method for increasing the integration density of a semiconductor device, a semiconductor device including a storage cell and a peripheral circuit region disposed vertically has been proposed. SUMMARY

[0003] Various example embodiments provide a semiconductor device having improved reliability and a data storage system including the same.

[0004] According to various example embodiments, a semiconductor device includes a first semiconductor structure including a substrate, a circuit device on the substrate, and a circuit interconnect on the circuit device, and a second semiconductor structure on the first semiconductor structure and having a first region and a second region. The second semiconductor structure includes a plate layer, gate electrodes stacked in a vertical direction on an upper surface of the plate layer and spaced apart from each other, extending different lengths in a first direction intersecting the vertical direction on the second region, and including gate contact regions, interlayer insulating layers stacked alternately with the gate electrodes, channel structures penetrating the gate electrodes and the interlayer insulating layers in the first region and extending in the vertical direction, contact plugs penetrating the gate electrodes in the second region, extending in the vertical direction, and electrically connecting the gate electrodes to part of the circuit interconnects, respectively, and contact insulating layers stacked alternately with the interlayer insulating layers, surrounding the contact plugs, and including first contact insulating layers between the gate contact regions and the contact plugs. Each of the contact plugs includes a vertical extension extending in the vertical direction, a horizontal extension extending from the vertical extension in a horizontal direction and overlapping the gate contact regions and the first contact insulating layers in the vertical direction, and a conductive liner extending to a region between the horizontal extension and the first contact insulating layer and to a region between the horizontal extension and the gate contact regions.

[0005] According to various example embodiments, a semiconductor device includes a stack pattern having a memory cell array region and a staircase region, and a stack structure extending over the stack pattern from the memory cell array region to the staircase region. The stack structure includes interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, and the gate electrodes include gate contact pads arranged in a staircase form over the staircase region. The semiconductor device further includes channel structures penetrating the stack structure in the memory cell array region and extending in the vertical direction, contact plugs penetrating the gate electrodes and the interlayer insulating layers in the staircase region, and contact insulating layers alternately stacked with the interlayer insulating layers and surrounding the contact plugs. The contact insulating layers include first contact insulating layers between the gate contact pads and the contact plugs, and second contact insulating layers alternately stacked with the interlayer insulating layers at lower portions of the gate contact pads and surrounding the contact plugs. Each of the contact plugs includes a vertically extending portion extending in the vertical direction, and a horizontally extending portion extending from the vertically extending portion in a horizontal direction and contacting each of the first contact insulating layers and the gate contact pads. A height of each of the first contact insulating layers is less than a height of each of the second contact insulating layers.

[0006] According to various example embodiments, a data storage system includes: a semiconductor storage device including a first semiconductor structure, a second semiconductor structure, and an input / output pad, the first semiconductor structure including a circuit device and a circuit interconnect electrically connected to the circuit device, the second semiconductor structure located on one surface of the first semiconductor structure and including a first region and a second region, the input / output pad electrically connected to the circuit device; and a controller electrically connected to the semiconductor storage device through the input / output pad and controlling the semiconductor storage device. The second semiconductor structure includes: a plate layer; gate electrodes stacked in a vertical direction on an upper surface of the plate layer and spaced apart from each other, the gate electrodes extending different lengths in a first direction intersecting the vertical direction on the second region and respectively including gate contact regions; interlayer insulating layers alternately stacked with the gate electrodes; channel structures penetrating the gate electrodes and the interlayer insulating layers in the first region and extending in the vertical direction; contact plugs penetrating the gate contact regions of each of the gate electrodes in the second region, extending in the vertical direction, and respectively electrically connecting the gate electrodes to a portion of the circuit interconnects; a first contact insulating layer alternately stacked with the interlayer insulating layers between the gate contact regions and the contact plugs, the first contact insulating layer surrounding the contact plugs; and a second contact insulating layer alternately stacked with the interlayer insulating layers at a lower portion of the gate contact regions, and the second contact insulating layer surrounding the contact plugs. Each of the contact plugs includes: a vertical extension portion extending in the vertical direction; a horizontal extension portion extending from the vertical extension portion in a horizontal direction, the horizontal extension portion overlapping each of the first contact insulating layer and the gate contact region; and a conductive liner extending to a region between the horizontal extension portion and the first contact insulating layer, and the conductive liner further extending to a region between the horizontal extension portion and the gate contact region. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other aspects, features, and advantages of various example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1A is a plan view illustrating a semiconductor device according to various example embodiments; FIG. 1B is a cross-sectional view illustrating various example embodiments of the semiconductor device taken along line I-I' in FIG. 1A ; and FIG. 1C is a cross-sectional view showing various example embodiments of a semiconductor device taken along line II-II' in FIG. 1A FIG. 2 is a close-up view showing a region A of the semiconductor device shown in FIG. 1B FIG. 3A is a close-up view showing a region B of the semiconductor device shown in FIG. 2 FIG. 3B is a close-up view showing a region C of the semiconductor device shown in FIG. 3A FIG. 4A to FIG. 4C is a close-up view showing a region B of the semiconductor device shown in FIG. 2 FIG. 5A to FIG. 5F is a cross-sectional view showing various example embodiments of a method of manufacturing a semiconductor device in FIG. 1B FIG. 6A to FIG. 6J is a cross-sectional view showing various example embodiments of a method of manufacturing a semiconductor device in FIG. 3A FIG. 7A to FIG. 7C is a cross-sectional view showing various example embodiments of a method of manufacturing a semiconductor device in FIG. 4B FIG. 8A to FIG. 8G is a cross-sectional view showing various example embodiments of a method of manufacturing a semiconductor device in FIG. 4C FIG. 9 and FIG. 10 is a cross-sectional view showing a semiconductor device according to various example embodiments; FIG. 11 is a diagram showing a data storage system including a semiconductor device according to various example embodiments; FIG. 12 is a perspective view showing a data storage system including a semiconductor device according to various example embodiments; FIG. 13 is a cross-sectional view showing a semiconductor package according to various example embodiments. DETAILED DESCRIPTION

[0008] Hereinafter, various example embodiments will be described below with reference to the accompanying drawings.

[0009] FIG. 1A is a top view showing a semiconductor device according to various example embodiments. FIG. 1B is a cross-sectional view showing various example embodiments of a semiconductor device taken along line II-II' in​​​​​​​​​FIG. 1A FIG. 6 is a cross-sectional view of various example embodiments of a semiconductor device taken along line I-I' in FIG. 1C FIG. 7 is a cross-sectional view of various example embodiments of a semiconductor device taken along line II-II' in FIG. 1A FIG. 7 is a cross-sectional view of various example embodiments of a semiconductor device taken along line II-II' in

[0010] Referring to FIG. 1A to FIG. 1C The semiconductor device 100 can include a peripheral circuit region PERI that is a first semiconductor structure including a first substrate 201, and a memory cell region CELL that is a second semiconductor structure including a second substrate 101. The memory cell region CELL can be disposed at an upper portion of the peripheral circuit region PERI. In another example, the memory cell region CELL can be disposed at a lower portion of the peripheral circuit region PERI.

[0011] The peripheral circuit region PERI can include the first substrate 201, a source / drain region 205 located in the first substrate 201, a source isolation layer 210, circuit devices 220 disposed on the first substrate 201, circuit contact plugs 270, circuit interconnection lines 280, and a peripheral region insulating layer 290.

[0012] The first substrate 201 can have an upper surface extending in a first direction (X direction) and a second direction (Y direction). In the first substrate 201, an active region can be defined by the source isolation layer 210. A source / drain region 205 including impurities can be disposed in a portion of the active region. The first substrate 201 can include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. The first substrate 201 can be provided as a bulk wafer or an epitaxial layer.

[0013] The circuit devices 220 can include planar transistors. Each of the circuit devices 220 can include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. The source / drain region 205 can be disposed in the first substrate 201 on both sides of the circuit gate electrode 225.

[0014] The peripheral region insulating layer 290 can be disposed on the circuit devices 220 located on the first substrate 201. The circuit contact plugs 270 can penetrate the peripheral region insulating layer 290 and can be connected to the source / drain region 205. In a region not shown, the circuit contact plugs 270 can also be connected to the circuit gate electrode 225. The circuit interconnection lines 280 can be connected to the circuit contact plugs 270 and can be disposed in multiple layers.

[0015] The memory cell region CELL can include a first region R1, a second region R2, and a third region R3, a source structure SS including a second substrate 101, a gate electrode 130 stacked on the source structure SS, an interlayer insulating layer 120 stacked alternately with the gate electrode 130, a channel structure CH provided to penetrate the stacked structure of the gate electrode 130 in the first region R1, a first isolation region MS1 and a second isolation region MS2 extending through the stacked structure of the gate electrode 130, a contact plug 170 extending through the gate electrode 130 in the second region R2, and a through plug 175 provided in the third region R3 outside the second substrate 101. The memory cell region CELL can further include a contact insulating layer 160 surrounding the contact plug 170.

[0016] The memory cell region CELL can include a first horizontal conductive layer 102 on the first region R1, a horizontal insulating layer 110 provided side by side with the first horizontal conductive layer 102 on the second region R2 of the second substrate 101, a second horizontal conductive layer 104 on the first horizontal conductive layer 102 and the horizontal insulating layer 110, a substrate insulating layer 121 penetrating the second substrate 101, an upper isolation region US penetrating a portion of the stacked structure of the gate electrode 130, a dummy channel structure DCH provided to penetrate the stacked structure of the gate electrode 130 in the second region R2, a cell region insulating layer 190, and a cell interconnection line 195.

[0017] The source structure SS can include the second substrate 101, the first horizontal conductive layer 102, and the second horizontal conductive layer 104 stacked in order. The second substrate 101 can have a shape of a plate and can serve as at least a portion of a common source line of the semiconductor device 100. The second substrate 101 can include a conductive material, for example, a semiconductor material. The second substrate 101 can further include impurities. The second substrate 101 can be provided as a polycrystalline semiconductor layer such as a polysilicon layer or an epitaxial layer. In various example embodiments, the source structure SS can be referred to as a plate structure, and the second substrate 101 can be referred to as a plate layer.

[0018] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can be stacked in order on an upper surface of the first region R1 of the second substrate 101. The first horizontal conductive layer 102 can not extend to an upper surface of the second region R2, and the second horizontal conductive layer 104 can extend into the second region R2.

[0019] The first horizontal conductive layer 102 can serve as a portion of a common source line of the semiconductor device 100, for example, together with the second substrate 101 as the common source line. The first horizontal conductive layer 102 can be directly connected to a channel layer 140 in the channel structure CH.

[0020] The second horizontal conductive layer 104 can be in contact with the second substrate 101 in a partial region where the first horizontal conductive layer 102 and the horizontal insulating layer 110 are not disposed. The second horizontal conductive layer 104 can cover an end portion of the first horizontal conductive layer 102 or the horizontal insulating layer 110 in a partial region, and can be bent to extend to the second substrate 101.

[0021] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can include a semiconductor material. For example, the first horizontal conductive layer 102 and the second horizontal conductive layer 104 can each include polysilicon. In this case, at least the first horizontal conductive layer 102 can be a doped layer, and the second horizontal conductive layer 104 can be a doped layer or a layer including impurities diffused from the first horizontal conductive layer 102. However, in various example embodiments, the second horizontal conductive layer 104 can be replaced with an insulating layer.

[0022] The horizontal insulating layer 110 can be disposed on the second substrate 101 at the same horizontal level as the first horizontal conductive layer 102. The horizontal insulating layer 110 can include a first horizontal insulating layer 111 and a second horizontal insulating layer 112. The horizontal insulating layer 110 can be a layer left after a portion thereof is replaced with the first horizontal conductive layer 102 in a process of manufacturing the semiconductor device 100. The horizontal insulating layer 110 can include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. However, example embodiments are not limited thereto. In various example embodiments, the first horizontal insulating layer 111 and the second horizontal insulating layer 112 can include different insulating materials.

[0023] The substrate insulating layer 121 can extend from the second region R2 in a third direction (Z direction), and can penetrate the second substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104. The substrate insulating layer 121 can be disposed to surround each contact plug 170. Accordingly, the contact plugs 170 connected to different gate electrodes 130 can be electrically isolated from each other. The substrate insulating layer 121 can also be disposed in the third region R3 to surround each through plug 175.

[0024] The substrate insulating layer 121 can include an insulating material, such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. However, example embodiments are not limited thereto.

[0025] The gate electrodes 130 can be vertically stacked on the second substrate 101 and spaced apart from each other on the second substrate 101, and can form a stacked structure. The gate electrodes 130 can include a lower gate electrode 130L included in a gate of a ground select transistor, a plurality of storage gate electrodes 130M included in a storage gate electrode, and an upper gate electrode 130U included in a gate of a string select transistor. The number of the storage gate electrodes 130M included in the storage gate electrode can be determined according to the capacity of the semiconductor device 100. In various example embodiments, the number of the upper gate electrodes 130U and the number of the lower gate electrodes 130L can be 1 to 4 or more, respectively, and can have the same or different structures from those of the storage gate electrodes 130M. In various example embodiments, the gate electrodes 130 can further include a gate electrode 130 included in an erase transistor disposed at a lower portion of the upper gate electrode 130U and / or the lower gate electrode 130L and used in an erase operation using a gate induced drain leakage (GIDL) phenomenon. In addition, a portion of the gate electrodes 130 (e.g., the storage gate electrodes 130M adjacent to the upper gate electrodes 130U or the lower gate electrodes 130L) can be dummy gate electrodes.

[0026] The gate electrodes 130 can be vertically stacked on the first region R1 and spaced apart from each other on the first region R1, can extend to different lengths from the first region R1 to the second region R2, and can form a stepped structure having a stair form. The gate electrodes 130 can form the stepped structure between the gate electrodes 130 in the first direction (X direction), and can be disposed to have the stepped structure in the second direction (Y direction). Due to the stepped structure, the lower gate electrodes 130 can be extended longer than the upper gate electrodes 130, can be exposed upward from the interlayer insulation layer 120, and can have regions respectively in contact with the contact plugs 170, and these regions can be referred to as gate contact regions 130P. In each of the gate electrodes 130, the gate contact regions 130P can include end portions in the first direction (X direction). The gate contact regions 130P can correspond to portions of the gate electrodes 130 included in the stacked structure in the second region R2 of the second substrate 101. The gate electrodes 130 can be connected to the contact plugs 170 in the gate contact regions 130P.

[0027] The gate electrodes 130 can be isolated from each other in the second direction (Y direction) by the first isolation regions MS1 extending in the first direction (X direction). The gate electrodes 130 located between pairs of the first isolation regions MS1 can form a storage block, but example embodiments of the storage block are not limited thereto. The gate electrodes 130 can include a metal material such as tungsten (W). In various example embodiments, the gate electrodes 130 can include a polysilicon or a metal silicide material.

[0028] The interlayer insulating layer 120 can be disposed between the gate electrodes 130. Like the gate electrodes 130, the interlayer insulating layer 120 can be spaced apart from each other in a direction perpendicular to the upper surface of the second substrate 101 and can extend in the first direction (X direction). The interlayer insulating layer 120 can include an insulating material such as silicon oxide or silicon nitride.

[0029] The first isolation region MS1 and the second isolation region MS2 can penetrate the gate electrodes 130 and can extend in the first direction (X direction). The first isolation region MS1 and the second isolation region MS2 can be disposed in parallel to each other. The first isolation region MS1 and the second isolation region MS2 can penetrate the entire gate electrodes 130 stacked on the second substrate 101 and can be connected to the second substrate 101. The first isolation region MS1 can extend as an integral region in the first direction (X direction), and the second isolation region MS2 can extend intermittently between the pairs of the first isolation region MS1 or can be disposed only in a partial region. However, in various example embodiments, the arrangement order of the first isolation region MS1 and the second isolation region MS2 and the number of the first isolation region MS1 and the second isolation region MS2 are not limited to the example shown in FIG. 10. FIG. 1A As shown in FIG. 11, the isolation insulating layer 105 can be disposed in the first isolation region MS1 and the second isolation region MS2. FIG. 1C As shown in FIG. 11, the isolation insulating layer 105 can be disposed in the first isolation region MS1 and the second isolation region MS2.

[0030] As shown in FIG. 11, the isolation insulating layer 105 can be disposed in the first isolation region MS1 and the second isolation region MS2. FIG. 1A and FIG. 1C The upper isolation region US can extend in the first direction (X direction) between the first isolation region MS1 and the second isolation region MS2 in the first region R1. For example, the upper isolation region US can isolate three gate electrodes 130 including the upper gate electrode 130U from each other in the second direction (Y direction). However, in various example embodiments, the number of gate electrodes 130 isolated by the upper isolation region US can vary. The upper gate electrode 130U isolated by the upper isolation region US can form different string selection lines. The upper isolation insulating layer 103 can be disposed in the upper isolation region US. The upper isolation insulating layer 103 can include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0031] As shown in FIG. 11, the isolation insulating layer 105 can be disposed in the first isolation region MS1 and the second isolation region MS2. FIG. 1A The channel structure CH can form a memory cell string and can be spaced apart from each other while forming rows and columns on the first region R1. The channel structure CH can be disposed to form a grid pattern or can be disposed in a zigzag pattern in one direction. The channel structure CH can have a columnar shape and can have an inclined side surface whose width decreases toward the second substrate 101 according to an aspect ratio.

[0032] As shown in FIG. 11, the isolation insulating layer 105 can be disposed in the first isolation region MS1 and the second isolation region MS2. FIG. 1BAs illustrated, the channel structure CH can include a first channel portion CH1 and a second channel portion CH2 stacked vertically. Each channel structure CH can have a form in which the first channel portion CH1 of the lower stack structure in which the gate electrode 130 penetrates and the second channel portion CH2 of the upper stack structure in which the gate electrode 130 penetrates are connected to each other, and can include a curved portion due to a difference in width in the connection region. However, in various example embodiments, the number of channel structures stacked in the third direction (Z direction) can vary.

[0033] As illustrated in an enlarged view in FIG. 1B, the channel layer 140 can be disposed in the channel structure CH. In the channel structure CH, the channel layer 140 can be formed in an annular shape surrounding the channel fill insulating layer 147. The channel layer 140 can be connected to the first horizontal conductive layer 102 at a lower portion. The channel layer 140 can include a semiconductor material such as polysilicon or single crystal silicon. FIG. 1C

[0034] The gate dielectric layer 145 can be disposed between the gate electrode 130 and the channel layer 140. Although not specifically illustrated, the gate dielectric layer 145 can include a tunneling layer, a charge storage layer, and a blocking layer stacked in order from the channel layer 140. The tunneling layer can tunnel charges into the charge storage layer, and can include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. However, example embodiments are not limited thereto. The charge storage layer can be a charge trapping layer or a floating gate conductive layer. The blocking layer can include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k material, or a combination thereof. However, example embodiments are not limited thereto. In various example embodiments, at least a portion of the gate dielectric layer 145 can extend in a horizontal direction along the gate electrode 130. The channel pad 149 can be disposed only on an upper end of the upper second channel portion CH2. The channel pad 149 can include, for example, doped polysilicon.

[0035] The channel layer 140, the gate dielectric layer 145, and the channel fill insulating layer 147 can be connected to each other between the first channel portion CH1 and the second channel portion CH2. The upper interlayer insulating layer 125, which is relatively thick, can be disposed between the first channel portion CH1 and the second channel portion CH2, i.e., between the lower stack structure and the upper stack structure. However, in various example embodiments, the shapes of the interlayer insulating layer 120 and the upper interlayer insulating layer 125 can vary.

[0036] ​The dummy channel structures DCH can be spaced apart from each other in rows and columns in the second region R2. In a top view, the dummy channel structures DCH can have a size greater than a size of the channel structures CH, although example embodiments are not limited thereto. The dummy channel structures DCH can be further provided in a portion of the first region R1 adjacent to the second region R2. Unlike the channel structures CH, the dummy channel structures DCH can not be electrically connected to the upper interconnection structures, and can not form a memory cell string in the semiconductor device 100.

[0037] The dummy channel structures DCH can have a structure identical to or different from a structure of the channel structures CH. When the dummy channel structures DCH are formed together with the channel structures CH, the dummy channel structures DCH can have a structure identical to a structure of the channel structures CH. When the dummy channel structures DCH are formed using a portion of a process of forming the contact plug 170, the dummy channel structures DCH can have a structure different from a structure of the channel structures CH. In this case, for example, the dummy channel structures DCH can have a structure filled with an insulating material such as an oxide.

[0038] The contact plug 170 can penetrate the gate electrode 130 and the interlayer insulating layer 120 in the uppermost portion in the second region R2, and can be connected to the gate contact region 130P of the gate electrode 130. The contact plug 170 can be provided to penetrate at least a portion of the cell region insulating layer 190, extend toward the gate contact region 130P, and be connected to each of the gate contact regions 130P of the gate electrode 130.

[0039] The contact plug 170 can penetrate the second substrate 101, the second horizontal conductive layer 104, and the horizontal insulating layer 110 at a lower portion of the gate electrode 130, and can be connected to the circuit interconnection line 280 in the peripheral circuit region PERI. The contact plug 170 can be spaced apart from the second substrate 101, the second horizontal conductive layer 104, and the horizontal insulating layer 110 by the substrate insulating layer 121.

[0040] The contact plug 170 can be surrounded by the substrate insulating layer 121 and can be electrically isolated from the second substrate 101. In various example embodiments, a region including a lower end of the contact plug 170 can be surrounded by the pad layer 285 on the circuit interconnection line 280. However, in various example embodiments, the contact plug 170 can not extend in the pad layer 285, but can be in contact with the pad layer 285. The pad layer 285 can protect the circuit interconnection line 280 during a process of manufacturing the semiconductor device 100, and can include a conductive material such as polysilicon. However, example embodiments are not limited thereto.

[0041] For example, the contact plug 170 can include at least one of tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In various example embodiments, the contact plug 170 can further include a barrier layer (e.g., a conductive liner 173 in the tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) in FIG. 1B) on a sidewall and a bottom surface of a contact hole in which the contact plug 170 is disposed. For example, the barrier layer can include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). However, example embodiments are not limited thereto. FIG. 3A

[0042] The contact insulating layer 160 can be disposed alternately with the interlayer insulating layer 120 and can surround the contact plug 170. The contact insulating layer 160 can include a first contact insulating layer 161 disposed between the gate contact region 130P and the contact plug 170 and surrounding a side surface of the contact plug 170, and a second contact insulating layer 162 disposed at a lower portion of the gate contact region 130P and surrounding the side surface of the contact plug 170. An inner side surface of the contact insulating layer 160 can surround the contact plug 170, and an outer side surface of the contact insulating layer 160 can be surrounded by the gate electrode 130. The contact plug 170 can be physically and electrically connected to the gate contact region 130P through the contact insulating layer 160, and can be electrically isolated from the gate electrode 130 at a lower portion of the gate contact region 130P.

[0043] The through plug 175 can be disposed in the third region R3 of the memory cell region CELL which is an outer side region of the second substrate 101, can penetrate the cell region insulating layer 190, and can extend to the peripheral circuit region PERI. The through plug 175 can be disposed to connect the cell interconnection line 195 of the memory cell region CELL to the circuit interconnection line 280 of the peripheral circuit region PERI. The through plug 175 can include a conductive material, for example, a metallic material such as tungsten (W), copper (Cu), and aluminum (Al). However, example embodiments are not limited thereto. The through plug 175 can be formed in the same process as the contact plug 170, can include the same material as the material of the contact plug 170, and can have the same internal structure as the internal structure of the contact plug 170.

[0044] The cell region insulating layer 190 can be disposed to cover the second substrate 101, the gate electrode 130 located on the second substrate 101, and the peripheral region insulating layer 290. The cell region insulating layer 190 can be made of an insulating material and can include a plurality of insulating layers.

[0045] ​The cell interconnection line 195 can be included in an upper interconnection structure electrically connected to the memory cells in the memory cell region CELL. The cell interconnection line 195 can be connected to the contact plug 170 and the through plug 175, and can be electrically connected to the gate electrode 130 and the channel structure CH. In various example embodiments, the number of contact plugs and interconnection lines included in the upper interconnection structure can vary. The cell interconnection line 195 can include a metal, such as tungsten (W), copper (Cu), aluminum (Al), etc. However, example embodiments are not limited thereto.

[0046] In various example embodiments, the first direction (X direction) and the second direction (Y direction) can be perpendicular to each other. The first direction (X direction) and the second direction (Y direction) can be perpendicular to the third direction (Z direction). The horizontal direction can refer to the first direction (X direction) and the second direction (Y direction).

[0047] FIG. 2 is a magnified view of the region A of the semiconductor device shown in FIG. 1B

[0048] Referring to FIG. 2 The contact plug 170 can be connected to a gate electrode among the gate electrodes 130 through the gate contact region 130P.

[0049] Each gate electrode 130 can include a gate contact region 130P and a gate stack region 130G as a region other than the gate contact region 130P. The gate contact region 130P can be a region of the gate electrode layer that is not covered by other gate electrodes due to a step structure. The gate stack region 130G can be a region of the gate electrode layer that is covered by other gate electrodes. The gate contact region 130P can overlap the horizontally extended portion 170H of the contact plug 170 in the third direction (Z direction), and can be in contact with a lower side surface of the horizontally extended portion 170H.

[0050] The gate electrode 130 can include a first gate electrode portion 130a corresponding to the gate contact region 130P and a second gate electrode portion 130b corresponding to the gate stack region 130G. In various example embodiments, the first gate electrode portion 130a can be referred to as a gate contact pad, and the second gate electrode portion 130b can be referred to as a gate stack structure.

[0051] The contact insulating layer 160 can include a first contact insulating layer 161 disposed between the gate contact region 130P and the vertically extended portion 170V of the contact plug 170, and a second contact insulating layer 162 disposed between the gate stack region 130G and the vertically extended portion 170V. The contact plug 170 can be electrically isolated from the second gate electrode portion 130b in the lower portion of the gate contact region 130P by the second contact insulating layer 162.​

[0052] The length of the first contact insulating layer 161 and the second contact insulating layer 162 in the horizontal direction can be the same. In various example embodiments, the length of the first contact insulating layer 161 in the third direction (Z direction) can be smaller than the length of the second contact insulating layer 162 in the third direction (Z direction). In various example embodiments, the upper surface of the first contact insulating layer 161 can be disposed at a lower level than the horizontal level of the upper surface of the gate contact region 130P (or the first gate electrode portion 130a). However, example embodiments are not limited thereto, and the upper surface of the first contact insulating layer 161 can be disposed at the same horizontal level as the upper surface of the gate contact region 130P. In various example embodiments, the upper surface of the second contact insulating layer 162 can be disposed at the same horizontal level as the upper surface of the gate stack region 130G (or the second gate electrode portion 130b).

[0053] The contact plug 170 can have a shape that is enlarged in the horizontal direction toward the gate contact region 130P and the first contact insulating layer 161. In various example embodiments, the contact plug 170 can include a vertical extension portion 170V that penetrates the gate electrode 130 and the interlayer insulating layer 120 and extends in the third direction (Z direction), and a horizontal extension portion 170H that extends from the vertical extension portion 170V in the horizontal direction and contacts the upper surface of the gate contact region 130P and the upper surface of the first contact insulating layer 161. In various example embodiments, the horizontal extension portion 170H can be disposed along the circumference of the vertical extension portion 170V, the side surface and the upper surface of the horizontal extension portion 170H can be covered by the cell region insulating layer 190, and the lower surface of the horizontal extension portion 170H can be covered by the first gate electrode portion 130a and the first contact insulating layer 161.

[0054] FIG. 3A is an enlarged view illustrating a region B of the semiconductor device shown in FIG. 2 is an enlarged view illustrating a region B of the semiconductor device shown in FIG. 3B is an enlarged view illustrating a region C of the semiconductor device shown in FIG. 3A is an enlarged view illustrating a region C of the semiconductor device shown in

[0055] Referring to FIG. 3A and FIG. 3B , the semiconductor device 100a can include the contact plug 170, the first gate electrode portion 130a and the second gate electrode portion 130b, and the first contact insulating layer 161 and the second contact insulating layer 162.

[0056] The contact plug 170 may include a vertical extension portion 170V penetrating the gate electrode 130 and the interlayer insulating layer 120, a horizontal extension portion (eg, FIG. 2 The horizontal extension portion 170H in the vertical extension portion 170V is provided as a conductive liner 173 covering the side surfaces of the vertical extension portion 170V and the surface of the horizontal extension portion 170H. In various exemplary embodiments, the vertical extension portion 170V may penetrate the first and second gate electrode portions 130a and 130b and the interlayer insulating layer 120 and extend in the third direction (Z direction). The horizontal extension portion 170H may extend horizontally from the vertical extension portion 170V and may overlap and / or contact the first gate electrode portion 130a and the first contact insulating layer 161 in the third direction (Z direction). The horizontal extension portion 170H may include a first horizontal extension portion 170Ha in contact with the first contact insulating layer 161 and a second horizontal extension portion 170Hb in contact with the first gate electrode portion 130a. In various exemplary embodiments, the vertical height of the first horizontal extension portion 170Ha may be greater than the vertical height of the second horizontal extension portion 170Hb.

[0057] Conductive liner 173 may serve as a metal barrier layer for contact plug 170 . Conductive liner 173 may be positioned according to the surface profiles of vertical extension portion 170V and horizontal extension portion 170H. Conductive liner 173 may cover the side surfaces of vertical extension portion 170V, extend from the side surfaces of vertical extension portion 170V, and cover the surface of horizontal extension portion 170H. Specifically, conductive liner 173 may extend to the region between horizontal extension portion 170H and cell region insulating layer 190 , the region between second horizontal extension portion 170Hb and first gate electrode portion 130a , and the region between first horizontal extension portion 170Ha and first contact insulating layer 161 . Conductive liner 173 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). However, example embodiments are not limited thereto.

[0058] The first gate electrode portion 130a can include the first conductive layer CP1 and the first barrier layer PP1 extending from at least a portion of the outer surface of the first conductive layer CP1 and disposed on the lower surface of the first conductive layer CP1. The first barrier layer PP1 can be a barrier layer in which the conductive pad 173 can extend to a region between the first conductive layer CP1 and the first contact insulating layer 161 and can cover the lower surface of the first conductive layer CP1. The first conductive layer CP1 can be covered by the conductive pad 173 and the first barrier layer PP1. In various example embodiments, the first gate electrode portion 130a can further include the first barrier layer BP1 covering a portion of the first conductive layer CP1. The first barrier layer BP1 can extend from a region between the first barrier layer PP1 and the first contact insulating layer 161 and can cover the lower surface of the first barrier layer PP1.

[0059] The second gate electrode portion 130b can include the second conductive layer CP2 and the second barrier layer PP2 disposed according to the surface profile of the second conductive layer CP2. The second gate electrode portion 130b can further include the second barrier layer BP2 covering the second barrier layer PP2.

[0060] The height H1 from the lower surface of the first gate electrode portion 130a to the upper surface of the horizontally extending portion 170H can be greater than the height H3 of the second gate electrode portion 130b in the third direction (Z direction).

[0061] The height H2 of the first gate electrode portion 130a in the third direction (Z direction) can be less than the height H3 of the second gate electrode portion 130b in the third direction (Z direction). For example, the height H2 of the first gate electrode portion 130a can be about 17 nm to about 21 nm, and the height H3 of the second gate electrode portion 130b can be about 26 nm to about 27 nm.

[0062] The first conductive layer CP1 and the second conductive layer CP2 can include a metal material. For example, the first conductive layer CP1 and the second conductive layer CP2 can include tungsten (W). In various example embodiments, the first conductive layer CP1 and the second conductive layer CP2 can include the same material as the material of the vertically extending portion 170V and the horizontally extending portion 170H of the contact plug 170. However, example embodiments are not limited thereto, and the first conductive layer CP1 and the second conductive layer CP2 can include a metal material different from the material of the vertically extending portion 170V and the horizontally extending portion 170H of the contact plug 170.

[0063] The first and second barrier layers BP1 and BP2 can include a metal oxide. For example, the first and second barrier layers BP1 and BP2 can include aluminum oxide (AlO). However, example embodiments are not limited thereto.

[0064] The first and second barrier layers BP1 and BP2 can include a metal oxide. For example, the first and second barrier layers BP1 and BP2 can include aluminum oxide (AlO). However, example embodiments are not limited thereto.

[0065] The first contact insulating layer 161 can be disposed between the first gate electrode portion 130a and the vertically extending portion 170V. An outer side surface of the first contact insulating layer 161 adjacent to the first gate electrode portion 130a can be in contact with the first barrier layer BP1, and an upper surface of the first contact insulating layer 161 can be in contact with the conductive pad 173. In various example embodiments, the upper surface of the first contact insulating layer 161 can be disposed at a lower level than a level of an upper surface of the first gate electrode portion 130a.

[0066] The second contact insulating layer 162 can be disposed between the second gate electrode portion 130b and the vertically extending portion 170V. An outer side surface of the second contact insulating layer 162 can be in contact with the second barrier layer BP2, and an upper surface and a lower surface of the second contact insulating layer 162 can be in contact with the interlayer insulating layer 120. The upper surface and the lower surface of the second contact insulating layer 162 can be disposed at the same level as a level of an upper surface and a lower surface of the second gate electrode portion 130b.

[0067] The first contact insulating layer 161 can include a first insulating pattern IL1a and a second insulating pattern IL1b, and the second contact insulating layer 162 can include a first insulating pattern IL2a and a second insulating pattern IL2b, a portion of the second insulating pattern IL1b being surrounded by the first insulating pattern IL1a, and a portion of the second insulating pattern IL2b being surrounded by the first insulating pattern IL2a. The first contact insulating layer 161 can include a 1-1 insulating pattern IL1a and a 1-2 insulating pattern IL1b, the 1-2 insulating pattern IL1b having a portion surrounded by the 1-1 insulating pattern IL1a. The second contact insulating layer 162 can include a 2-1 insulating pattern IL2a and a 2-2 insulating pattern IL2b, the 2-2 insulating pattern IL2b having a portion surrounded by the 2-1 insulating pattern IL2a.

[0068] The first insulating pattern IL1a can include a first flat portion IL1a_1 which is flat in a horizontal direction, and a first protrusion IL1a_2 which extends from the first flat portion IL1a_1 and protrudes toward the interlayer insulating layer 120 between the first flat portion IL1a_1 and the vertically extending portion 170V, and the first insulating pattern IL2a can include a first flat portion IL2a_1 which is flat in a horizontal direction, and a first protrusion IL2a_2 which extends from the first flat portion IL2a_1 and protrudes toward the interlayer insulating layer 120 between the first flat portion IL2a_1 and the vertically extending portion 170V.

[0069] The second insulating pattern IL1b can include a second flat portion IL1b_1 which is surrounded by the first flat portion IL1a_1 of the first insulating pattern IL1a, a second protrusion IL1b_2 which is surrounded by the first protrusion IL1a_2 of the first insulating pattern IL1a and has a thickness which gradually increases toward the vertically extending portion 170V to correspond to the first protrusion IL1a_2, and a third protrusion IL1b_3 which protrudes from an end portion of the second protrusion IL1b_2 toward the vertically extending portion 170V, and the second insulating pattern IL2b can include a second flat portion IL2b_1 which is surrounded by the first flat portion IL2a_1 of the first insulating pattern IL2a, a second protrusion IL2b_2 which is surrounded by the first protrusion IL2a_2 of the first insulating pattern IL2a and has a thickness which gradually increases toward the vertically extending portion 170V to correspond to the first protrusion IL2a_2, and a third protrusion IL2b_3 which protrudes from an end portion of the second protrusion IL2b_2 toward the vertically extending portion 170V.

[0070] The first flat portions IL1a_1 and IL2a_1 can have a first height in a third direction (Z direction), and the first protrusions IL1a_2 and IL2a_2 can have a second height which is greater than the first height. Due to the height difference between the first flat portions IL1a_1 and IL2a_1 and the first protrusions IL1a_2 and IL2a_2, the first and second contact insulating layers 161 and 162 can include curved portions. In various example embodiments, due to the height difference in the third direction (Z direction) between the first flat portion IL1a_1 and the first protrusion IL1a_2, a curved portion can be disposed and / or formed on a lower surface of the first contact insulating layer 161. Due to the height difference in the third direction (Z direction) between the first flat portion IL2a_1 and the first protrusion IL2a_2, a curved portion can be disposed and / or formed on an upper surface and a lower surface of the second contact insulating layer 162.

[0071] In various example embodiments, the upper surface of the first flat portion IL1a_1 of the first contact insulating layer 161 can have a flat shape. In various example embodiments, the upper surface of the first flat portion IL1a_1 of the first contact insulating layer 161 can be disposed at a level lower than that of the upper surface of the first gate electrode portion 130a. The upper surface of the first flat portion IL2a_1 of the second contact insulating layer 162 can be disposed at the same level as that of the upper surface of the second gate electrode portion 130b.

[0072] Since the first protrusion IL1a_2 of the first contact insulating layer 161 and the first protrusion IL2a_2 of the second contact insulating layer 162 protrude toward the interlayer insulating layer 120, the thickness of the interlayer insulating layer 120 in contact with the lower portions of the first flat portions IL1a_1 and IL2a_1 can be greater than the thickness of the interlayer insulating layer 120 in contact with the lower portions of the first protrusions IL1a_2 and IL2a_2.

[0073] In various example embodiments, the second protrusions IL1b_2 and IL2b_2 can extend from the second flat portions IL1b_1 and IL2b_1 and can have a tapered shape in which the thickness in the third direction (Z direction) gradually increases toward the vertical extension portion 170V. The third protrusions IL1b_3 and IL2b_3 can extend from the end portions of the second protrusions IL1b_2 and IL2b_2 and can have a height less than that of the end portions of the second protrusions IL1b_2 and IL2b_2 in the third direction (Z direction).

[0074] In the same axis in the third direction (Z direction), the height of the first contact insulating layer 161 in the third direction (Z direction) can be less than the height of the second contact insulating layer 162 in the third direction (Z direction).

[0075] The distance from the upper surface of the second flat portion IL1b_1 of the first contact insulating layer 161 to the upper surface of the first flat portion IL1a_1 can be less than the distance from the lower surface of the second flat portion IL1b_1 of the first contact insulating layer 161 to the lower surface of the first flat portion IL1a_1. The upper surface of the first flat portion IL1a_1 of the first contact insulating layer 161 can be partially etched during a process of manufacturing the semiconductor device 100a and can have one flat surface.

[0076] The distance from the upper surface of the second flat portion IL2b_1 of the second contact insulating layer 162 to the upper surface of the first flat portion IL2a_1 can be substantially the same as the distance from the lower surface of the second flat portion IL2b_1 of the second contact insulating layer 162 to the lower surface of the first flat portion IL2a_1.

[0077] The conductive pad 173 can extend from a region between the horizontal extension portion 170H and the first flat portion IL1a_1 of the first contact insulating layer 161 to a region between the vertical extension portion 170V and the first contact insulating layer 161 and the second contact insulating layer 162, and to a region between the vertical extension portion 170V and the interlayer insulating layer 120. The conductive pad 173 can be disposed according to a surface profile of the third protrusion IL1b_3 protruding toward the vertical extension portion 170V. The conductive pad 173 can be disposed according to an uneven surface profile of the sidewall of the vertical extension portion 170V due to a difference in etching speed between the first insulating pattern IL1a of the first contact insulating layer 161 and the second insulating pattern IL1b and IL2b of the second contact insulating layer 162 in a process of manufacturing a semiconductor device.

[0078] The second insulating patterns IL1b and IL2b can include first and second voids 161V and 162V.

[0079] The second insulating pattern IL1b of the first contact insulating layer 161 can include the first void 161V. The first void 161V can include a 1-1 void 161Va and a 1-2 void 161Vb spaced apart from the 1-1 void 161Va in a horizontal direction and adjacent to the vertical extension portion 170V. In various example embodiments, the 1-1 void 161Va and the 1-2 void 161Vb can be spaced apart in the horizontal direction with the second protrusion IL1b_2 of the first contact insulating layer 161 interposed therebetween. The 1-1 void 161Va can be disposed in the second flat portion IL1b_1, and the 1-2 void 161Vb can be disposed in the third protrusion IL1b_3.

[0080] The second insulating pattern IL2b of the second contact insulating layer 162 can include the second void 162V. The second void 162V can include a 2-1 void 162Va and a 2-2 void 162Vb spaced apart from the 2-1 void 162Va horizontally and adjacent to the vertical extension portion 170V. In various example embodiments, the 2-1 void 162Va and the 2-2 void 162Vb can be spaced apart in the horizontal direction with the second protrusion IL2b_2 of the second contact insulating layer 162 interposed therebetween. The 2-1 void 162Va can be disposed in the second flat portion IL2b_1, and the 2-2 void 162Vb can be disposed in the third protrusion IL2b_3.

[0081] The first void 161V and the second void 162V may be void spaces not filled with insulating material. During the process of forming the second insulating patterns IL1b and IL2b, the 1-1st void 161Va may be formed in a narrow and deep shape in the second flat portion IL1b_1 disposed between the first flat portions IL1a_1 of the first insulating pattern IL1a, and the 2-1st void 162Va may be formed in a narrow and deep shape in the second flat portion IL2b_1 disposed between the first flat portions IL2a_1 of the first insulating pattern IL2a. During the manufacturing process, the 1-2nd void 161Vb and the 2-2nd void 162Vb may be disposed and / or formed in the third protrusions IL1b_3 and IL2b_3, respectively, and may be disposed in a narrow and deep shape.

[0082] By forming the first and second contact insulating layers 161 and 162 into protruding shapes protruding toward the interlayer insulating layer 120, the first insulating pattern IL1a may include a first flat portion IL1a_1 corresponding to the surface profile and a first protrusion IL1a_2 extending from the first flat portion IL1a_1, and the first insulating pattern IL2a may include a first flat portion IL2a_1 corresponding to the surface profile and a first protrusion IL2a_2 extending from the first flat portion IL2a_1. Therefore, the second protrusions IL1b_2 and IL2b_2 of the second insulating pattern IL1b and the second insulating pattern IL2b may have a tapered shape with thickness increasing toward the vertical extending portion 170V to correspond to the shape of the first protrusions IL1a_2 and IL2a_2, and first voids 161V and second voids 162V may be formed in the second insulating patterns IL1b and IL2b relative to the second protrusions IL1b_2 and IL2b_2.

[0083] The length of the 1-1th gap 161Va in the horizontal direction may be greater than the length of the 1-2th gap 161Vb in the horizontal direction, and the length of the 2-1st gap 162Va in the horizontal direction may be greater than the length of the 2-2nd gap 162Vb in the horizontal direction.

[0084] The first insulating patterns IL1a and IL2a and the second insulating patterns IL1b and IL2b may include an insulating material. In various exemplary embodiments, the first insulating patterns IL1a and IL2a may include a first insulating material, and the second insulating patterns IL1b and IL2b may include a second insulating material different from the first insulating material. For example, the first insulating patterns IL1a and IL2a may include silicon oxide, and the second insulating patterns IL1b and IL2b may include silicon nitride.

[0085] In various example embodiments, the semiconductor device can include a first contact insulating layer 161 disposed between the first gate electrode portion 130a and the vertically extending portion 170V, and a second contact insulating layer 162 disposed between the second gate electrode portion 130b and the vertically extending portion 170V. The second contact insulating layer 162 can include first insulating patterns IL2a having first protrusions protruding toward the interlayer insulating layer 120, and second insulating patterns IL2b disposed between the first insulating patterns IL2a and having second protrusions in a tapered shape to correspond to the first protrusions. Accordingly, in the horizontal direction, the 2-1st void 162Va and the 2-2nd void 162Vb spaced apart from each other can be formed in the second insulating patterns IL2b with respect to the tapered shape. Even when the 2-2nd void 162Vb adjacent to the vertically extending portion 170V is deformed or broken during a process of manufacturing the semiconductor device, the 2-1st void 162Va adjacent to the second gate electrode portion 130b can be protected with respect to the second protrusions in the tapered shape of the second insulating patterns IL2b. That is, since the contact plug 170 and the second gate electrode portion 130b can be normally insulated from each other by the second contact insulating layer 162, a semiconductor device having improved reliability can be provided.

[0086] FIG. 4A to FIG. 4C is an enlarged view illustrating a region B of the semiconductor device shown in FIG. 2

[0087] Referring to FIG. 4A , in the semiconductor device 100b, components other than the first contact insulating layer 161' can be the same as or correspond to those shown in FIG. 3A . Among the components other than the first contact insulating layer 161', an overlapping description of components the same as or corresponding to the examples shown in FIG. 3A will not be provided.

[0088] Referring to FIG. 4A , the first contact insulating layer 161' can include first insulating patterns IL1a' and second insulating patterns IL1b. An upper surface of the first insulating patterns IL1a' can be disposed at the same horizontal level as an upper surface of the first gate electrode portion 130a. The conductive pad 173 can be flat without a step difference on the first gate electrode portion 130a and the first contact insulating layer 161'.

[0089] Referring to FIG. 4B , in the semiconductor device 100c, components other than the sealing pattern 163 can be the same as or correspond to those shown in FIG. 3A . Among the components other than the sealing pattern 163, an overlapping description of components the same as or corresponding to the examples shown in FIG. 3A ​overlapping descriptions of the same or corresponding components shown in the examples.

[0090] Because the first and second insulating patterns IL1a and IL2a and IL1b and IL2b can include different insulating materials, the third protrusions IL1b_3 and IL2b_3 of the first and second insulating patterns IL1a and IL2a and IL1b and IL2b exposed toward the vertical extension portion 170V and protruding toward the vertical extension portion 170V can have different horizontal lengths toward the vertical extension portion 170V. In various example embodiments, the third protrusion IL1b_3 of the second insulating pattern IL1b can protrude toward the vertical extension portion 170V with respect to the first flat portion IL1a_1 of the first insulating pattern IL1a, and the third protrusion IL2b_3 of the second insulating pattern IL2b can protrude toward the vertical extension portion 170V with respect to the first flat portion IL2a_1 of the first insulating pattern IL2a.

[0091] The sealing pattern 163 can be in contact with lower portions of the third protrusions IL1b_3 of the second insulating pattern IL1b and the third protrusions IL2b_3 of the second insulating pattern IL2b, and can extend to regions between the first protrusions IL1a_2 of the first insulating pattern IL1a and the first protrusions IL2a_2 of the first insulating pattern IL2a and the vertical extension portion 170V and between the interlayer insulating layer 120 and the vertical extension portion 170V. The sealing pattern 163 can be disposed to eliminate unevenness (or step difference) between the first and second contact insulating layers 161 and 162 and the vertical extension portion 170V.

[0092] The sealing pattern 163 can include an insulating material, for example, can include silicon oxide, silicon nitride, or silicon oxynitride. In various example embodiments, the sealing pattern 163 can include the same insulating material as that of the second insulating patterns IL1b and IL2b. For example, the sealing pattern 163 can include silicon nitride. In this case, the interface surface between the sealing pattern 163 and the second insulating patterns IL1b and IL2b can not be apparent. That is, the sealing pattern 163 and the second insulating patterns IL1b and IL2b can extend to regions between the first insulating pattern IL1a of the first contact insulating layer 161 and the vertical extension portion 170V, between the interlayer insulating layer 120 and the vertical extension portion 170V, and between the first insulating pattern IL2a of the second contact insulating layer 162, and can be integrated with each other. The second insulating pattern IL1b of the first contact insulating layer 161 and the second insulating pattern IL2b of the second contact insulating layer 162 can be integrated with each other.

[0093] The conductive pad 173 can extend from a region between the horizontal extension portion 170H and the first contact insulating layer 161 to a region between one side surface of the second insulating patterns IL1b and IL2b and the vertical extension portion 170V and to a region between the sealing pattern 163 and the vertical extension portion 170V. The conductive pad 173 can be disposed along a side profile coplanar with the vertical extension portion 170V.

[0094] The semiconductor device according to various example embodiments can include a sealing pattern 163 filling an uneven or curved portion between the first contact insulating layer 161 and the second contact insulating layer 162 and the vertical extension portion 170V, so that the vertical extension portion 170V can have a flat sidewall structure. Accordingly, an electric field concentration phenomenon caused by an uneven sidewall structure can be addressed, and a void defect in the contact plug 170 can be reduced.

[0095] Reference FIG. 4C In the semiconductor device 100d, components other than the first contact insulating layer 161" and the second contact insulating layer 162", the interlayer insulating layer 120, and the sealing pattern 163 can be the same as those shown in the semiconductor device 100a. FIG. 3A Among the components other than the first contact insulating layer 161" and the second contact insulating layer 162" and the sealing pattern 163, an overlapping description of components identical or corresponding to the examples shown in the semiconductor device 100a will not be provided. FIG. 3A Among the components other than the first contact insulating layer 161" and the second contact insulating layer 162" and the sealing pattern 163, an overlapping description of components identical or corresponding to the examples shown in the semiconductor device 100a will not be provided.

[0096] The first contact insulating layer 161" can include a first insulating pattern IL1a" and a second insulating pattern IL1b" having a portion surrounded by the first insulating pattern IL1a", and the second contact insulating layer 162" can include a first insulating pattern IL2a" and a second insulating pattern IL2b" having a portion surrounded by the first insulating pattern IL2a". A height of the first contact insulating layer 161" in the third direction (Z direction) can be less than a height of the second contact insulating layer 162" in the third direction (Z direction).

[0097] The first contact insulating layer 161" can include a first insulating pattern IL1a" and a second insulating pattern IL1b" having a portion surrounded by the first insulating pattern IL1a". An upper surface of the second insulating pattern IL1b" can be in contact with the conductive pad 173. The first insulating pattern IL1a" can cover a side surface and a portion of a lower surface of the second insulating pattern IL1b". The second insulating pattern IL1b" can include a portion protruding toward the vertical extension portion 170V formed due to a difference in insulating material from the first insulating pattern IL1a" during a manufacturing process. In various example embodiments, a lower surface of the first contact insulating layer 161" can be disposed at the same horizontal level as a lower surface of the first gate electrode portion 130a.

[0098] The second contact insulating layer 162" can include a first insulating pattern IL2a" and a second insulating pattern IL2b" having a portion surrounded by the first insulating pattern IL2a". The second insulating pattern IL2b" can include a portion protruding toward the vertical extension portion 170V. An upper surface of the second contact insulating layer 162" can be disposed at the same horizontal level as an upper surface of the second gate electrode portion 130b. A lower surface of the second contact insulating layer 162" can be disposed at the same horizontal level as a lower surface of the second gate electrode portion 130b.

[0099] The sealing pattern 163 can surround the second insulating patterns IL1b" and IL2b" protruding toward the vertical extension portion 170V, and can extend to a region between the interlayer insulating layer 120 and the vertical extension portion 170V. The sealing pattern 163 can fill uneven and / or curved portions between the first and second contact insulating layers 161" and 162" and the vertical extension portion 170V.

[0100] The conductive pad 173 can extend from a region between the horizontal extension portion 170H and the first contact insulating layer 161" to a region between side surfaces of the second insulating patterns IL1b", IL2b" and the vertical extension portion 170V and to a region between the sealing pattern 163 and the vertical extension portion 170V, and can be disposed along a surface contour. The conductive pad 173 can cover one flat surface between the vertical extension portion 170V and the sealing pattern 163.

[0101] A thickness of the interlayer insulating layer 120 in the third direction (Z direction) can be substantially uniform.

[0102] The semiconductor device according to various example embodiments can include a sealing pattern 163 filling uneven or curved portions between the first contact insulating layer 161" and the second contact insulating layer 162" and the vertically extending portion 170V, so that the vertically extending portion 170V can have a flat sidewall structure. Accordingly, an electric field concentration phenomenon caused by an uneven sidewall structure can be addressed, and a void defect in the contact plug 170 can be reduced.

[0103] FIG. 5A to FIG. 5F are cross-sectional views illustrating various example embodiments of a method of manufacturing a semiconductor device in FIG. 1B will be described with reference to FIG. 5A to FIG. 5F with respect to the region D in FIG. 1B A method of manufacturing a semiconductor device will be described with respect to the region D in

[0104] With reference to FIG. 5A , a stack structure MS can be formed on the plate layer SS.

[0105] The stack structure MS can include a preliminary interlayer insulating layer 120P and a sacrificial insulating layer 122P. The preliminary interlayer insulating layer 120P and the sacrificial insulating layer 122P can be alternately stacked in the third direction (Z direction). By patterning the preliminary interlayer insulating layer 120P and the sacrificial insulating layer 122P, the stack structure MS can form a stepped form. Each sacrificial insulating layer 122P can form a pair with one preliminary interlayer insulating layer 120P adjacent thereto in the third direction (Z direction), and can extend in the first direction (X direction). The pairs provided by the preliminary interlayer insulating layer 120P and the sacrificial insulating layer 122P can extend to different lengths in the first direction (X direction) in the second region R2 and can form a stepped structure. A plurality of pad regions ST1-ST3 can be provided by the stepped structure. By forming the plurality of pad regions, at least a partial region of the sacrificial insulating layer 122P disposed at a lower portion in the third direction (Z direction) can be exposed.

[0106] The preliminary interlayer insulating layer 120P and the sacrificial insulating layer 122P can be formed of a material having a desired (and / or optionally predetermined) etching selectivity. In various example embodiments, the preliminary interlayer insulating layer 120P can include at least one of a silicon oxide layer and a silicon nitride layer, and the sacrificial insulating layer 122P can include one of a silicon layer, a silicon oxide layer, a silicon carbide layer, and a silicon nitride layer. However, example embodiments are not limited thereto. For example, its material can be different from that of the preliminary interlayer insulating layer 120P. For example, when the preliminary interlayer insulating layer 120P is a silicon oxide layer, the sacrificial insulating layer 122P can be a silicon nitride layer.

[0107] With reference to FIG. 5BA portion of the preliminary interlayer insulating layer 120P can be recessed, and the interlayer insulating layer 120 can be formed. By flowing an etching solution through one side surface of the preliminary interlayer insulating layer 120P having a different length in the stepped structure, only a portion of the preliminary interlayer insulating layer 120P disposed at a lower portion of the plurality of pad regions ST1-ST3 can be selectively removed, thereby forming the interlayer insulating layer 120.

[0108] Referring to FIG. 5C The pad structures 151P and 152P can be formed on the sacrificial insulating layer 122. The pad structures 151P and 152P can include a first sacrificial pad layer 151P and a second sacrificial pad layer 152P formed in order on the sacrificial insulating layer 122.

[0109] The first sacrificial pad layer 151P can be one of a silicon film, a silicon oxide film, a silicon carbide film, and a silicon nitride film. However, example embodiments are not limited thereto. For example, a material thereof can be different from that of the sacrificial insulating layer 122. For example, when the sacrificial insulating layer 122 is a silicon nitride layer, the first sacrificial pad layer 151P can include a silicon oxide layer. In various example embodiments, the first sacrificial pad layer 151P can include polysilicon.

[0110] A height of the first sacrificial pad layer 151P in the third direction (Z direction) can be less than a height of the second sacrificial pad layer 152P in the third direction (Z direction). For example, the height of the first sacrificial pad layer 151P can be about 5 nm. The height of the second sacrificial pad layer 152P can be about 17 nm.

[0111] Referring to FIG. 5D The first sacrificial pad layer 151P and the second sacrificial pad layer 152P can be node-separated for each of the plurality of pad regions ST1-ST3 such that the interlayer insulating layer 120 can be exposed, and the first sacrificial pad layer 151 and the second sacrificial pad layer 152 can be formed on the plurality of pad regions ST1-ST3. The first sacrificial pad layer 151 and the second sacrificial pad layer 152 can be formed through a patterning process.

[0112] The cell region insulating layer 190 can be formed to cover the first sacrificial pad layer 151 and the second sacrificial pad layer 152 disposed on the plurality of pad regions ST1-ST3 and the stack structure MS.

[0113] The first sacrificial pad layer 151 and the second sacrificial pad layer 152 can be regions replaced with a horizontal extension portion (e.g., a horizontal extension portion 170H) of a contact plug to be described later. FIG. 2

[0114] Referring to FIG. 5E The contact plug (e.g., a contact plug 170) can be formed in the second region R2. FIG. 1B ​A through-hole OPN is formed in a region of the contact plug 170 in the semiconductor device 100.

[0115] In the second region R2, the through-hole OPN can be formed to penetrate the unit region insulating layer 190, the first and second sacrificial pad layers 151 and 152, and the stepped structure of the stack structure MS. The through-hole OPN can be in a cylindrical hole shape.

[0116] Reference is made to FIG. 5F The trench TR can be formed by removing a portion of the sacrificial insulating layer 122 exposed by the through-hole OPN.

[0117] The trench TR can be formed by applying an etchant through the through-hole OPN and removing the sacrificial insulating layer 122 to a desired (and / or optionally predetermined) length around the through-hole OPN. In another example, the trench TR can be formed by performing a dry etching process on a side surface of the sacrificial insulating layer 122 exposed by the through-hole OPN. The length of the trench TR can be formed in various ways.

[0118] FIG. 6A to FIG. 6J is a cross-sectional view illustrating a method of manufacturing a semiconductor device in FIG. 3A is a cross-sectional view illustrating a method of manufacturing a semiconductor device in

[0119] FIG. 6A is an enlarged view illustrating a region E of a semiconductor device in FIG. 5F is an enlarged view illustrating a region E of a semiconductor device in FIG. 6A The first horizontal tunnel layer OH1 can be formed by removing the sacrificial insulating layer 122 to a desired (and / or optionally predetermined) length around the first vertical through-hole OV1 by applying an etchant through the first vertical through-hole OV1 penetrating the sacrificial insulating layer 122 and the interlayer insulating layer 120, with reference to

[0120] The sacrificial insulating layer 122 can include a first sacrificial insulating layer 122a disposed below the first sacrificial pad layer 151 and a second sacrificial insulating layer 122b disposed between the interlayer insulating layers 120. The first sacrificial insulating layer 122a can be a region replaced by a first gate electrode portion (e.g., the first gate electrode portion 130a in FIG. 6E The second sacrificial insulating layer 122b can be a region replaced by a second gate electrode portion (e.g., the second gate electrode portion 130b in FIG. 6E

[0121] A height of the first sacrificial insulating layer 122a in the third direction (Z direction) can be less than a height of the second sacrificial insulating layer 122b in the third direction (Z direction). In FIG. 5B ​In the process of recessing a portion of the preliminary interlayer insulation layer 120P, a portion of the upper surface of the sacrificial insulation layer 122P provided at a lower portion of the preliminary interlayer insulation layer 120P and having an upper portion exposed for each of the plurality of pad regions ST1-ST3 can be etched. Accordingly, the first sacrificial insulation layer 122a having the exposed upper surface and the second sacrificial insulation layer 122b covered by the interlayer insulation layer 120 and having the unexposed upper surface can be formed.

[0122] Referring to FIG. 6B The first horizontal tunnel layer OH1 can further expand in the third direction (Z direction) toward the interlayer insulation layer 120 and the first sacrificial pad layer 151 and the second horizontal tunnel layer OH2 can be formed. A portion of the first sacrificial pad layer 151 overlapping the first horizontal tunnel layer OH1 can be etched in the third direction (Z direction) using a dry etching process. The second horizontal tunnel layer OH2 can protrude toward the interlayer insulation layer 120 and the first sacrificial pad layer 151.

[0123] Referring to FIG. 6C The third horizontal tunnel layer OH3 can be formed on the side surface of the sacrificial insulation layer 122 exposed by the second horizontal tunnel layer OH2 through a pullback process or an etching process. The third horizontal tunnel layer OH3 can include a 3-1 horizontal tunnel layer OH3a having an expanded portion toward the first sacrificial pad layer 151 and the interlayer insulation layer 120 and a 3-2 horizontal tunnel layer OH3b extending horizontally toward the sacrificial insulation layer 122.

[0124] Referring to FIG. 6C and FIG. 6D The insulating structure 20 can be formed in the first vertical through-hole OV1 and the third horizontal tunnel layer OH3 connected to the first vertical through-hole OV1.

[0125] The insulating structure 20 can include a first insulating liner 25, a second insulating liner 23, and a sacrificial liner 21 extending on a side surface of the first vertical through-hole OV1 and / or into the third horizontal tunnel layer OH3 and sequentially formed through a deposition process. The deposition process can include an atomic layer deposition (ALD) process. The thickness of the sacrificial liner 21 can be greater than the respective thicknesses of the first insulating liner 25 and the second insulating liner 23.

[0126] The first insulating liner 25 can have a substantially uniform thickness, can extend from the side surface of the first vertical via hole OV1 into the third horizontal tunnel layer OH3, and can be conformally formed according to a surface profile of the third horizontal tunnel layer OH3. The second insulating liner 23 can be deposited on the first insulating liner 25. That is, the second insulating liner 23 can be deposited by extending to the area between the first insulating liner 25 formed on the side surface of the first vertical via hole OV1 into the first insulating liner 25 in the third horizontal tunnel layer OH3. The sacrificial liner 21 can be deposited on the second insulating liner 23 disposed on the side surface of the first vertical via hole OV1.

[0127] The first insulating liner 25 can include a first insulating material, and the second insulating liner 23 can include a second insulating material different from the first insulating material. The sacrificial liner 21 can include carbon (C) or polysilicon. However, example embodiments are not limited thereto. For example, the first insulating liner 25 can include silicon oxide, and the second insulating liner 23 can include silicon nitride.

[0128] The 1-1 void 161Va can be formed between the first insulating liner 25 adjacent to the first sacrificial insulating layer 122a in the 3-2 horizontal tunnel layer OH3b, and the 1-2 void 161Vb can be formed between the first insulating liner 25 in the 3-1 horizontal tunnel layer OH3a.

[0129] The 2-1 void 162Va can be formed in a process of forming the second insulating liner 23 between the first insulating liner 25 formed in the 3-2 horizontal tunnel layer OH3b adjacent to the second sacrificial insulating layer 122b, and the 2-2 void 162Vb can be formed in a process of forming the second insulating liner 23 between the first insulating liner 25 in the 3-1 horizontal tunnel layer OH3a.

[0130] The thickness of the second insulating liner 23 in the third horizontal tunnel layer OH3 adjacent to the first sacrificial insulating layer 122a can be less than the thickness of the second insulating liner 23 in the third horizontal tunnel layer OH3 adjacent to the second sacrificial insulating layer 122b.

[0131] Reference FIG. 6D and FIG. 6EBy removing the sacrificial insulating layer 122, the first gate electrode portion 130a and the second gate electrode portion 130b can be formed. The sacrificial insulating layer 122 can be removed by a wet etching process. Before the first gate electrode portion 130a and the second gate electrode portion 130b are formed, the first barrier layer BP1_P can be deposited in the space where the first sacrificial insulating layer 122a has been removed, and the second barrier layer BP2 can be deposited in the space where the second sacrificial insulating layer 122b has been removed. The first barrier layer BP1_P and the second barrier layer BP2 can be conformally formed according to a surface profile of inner walls of the spaces where the sacrificial insulating layer 122 has been removed. The first barrier layer BP1_P and the second barrier layer BP2 can have a desired (and / or optionally predetermined) thickness. The first barrier layer BP1_P and the second barrier layer BP2 can include a metal oxide. For example, the first barrier layer BP1_P and the second barrier layer BP2 can include aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), or aluminum oxycarbide (AlOC). However, example embodiments are not limited thereto.

[0132] The first gate electrode portion 130a can be formed on the first barrier layer BP1_P, and the second gate electrode portion 130b can be formed on the second barrier layer BP2. In various example embodiments, the first barrier layer BP1_P can be deposited in the space where the first sacrificial insulating layer 122a has been removed, and the second barrier layer BP2 can be deposited in the space where the second sacrificial insulating layer 122b has been removed. In various example embodiments, the first barrier layer BP1_P and the second barrier layer BP2 can be conformally formed according to a surface profile of inner walls of the spaces where the sacrificial insulating layer 122 has been removed.

[0133] Referring to FIG. 1A, the first barrier layer BP1_P and the second barrier layer BP2 can be formed on the first gate electrode portion 130a and the second gate electrode portion 130b, respectively. FIG. 6E and FIG. 6FThe insulating structure 20 surrounding the second vertical through-hole OV2 can be removed. An etching process including removing the sacrificial liner 21 from the second vertical through-hole OV2 and further removing a portion of the first insulating liner 25 and the second insulating liner 23 can be performed. The etching rate of the second insulating liner 23 can be lower than the etching rate of the first insulating liner 25. In various example embodiments, the first insulating liner 25 can be etched such that the first insulating patterns IL1a_P1 and IL2a_P1 can remain in the third horizontal tunnel layer OH3, and the second insulating liner 23 can be etched such that the second insulating patterns IL1b and IL2b including a portion protruding from the first insulating patterns IL1a_P1 and IL2a_P1 between the first insulating patterns IL1a_P1 and IL2a_P1 toward the second vertical through-hole OV2 can remain. In various example embodiments, the upper surfaces of the first insulating patterns IL1a_P1 and IL2a_P1 can be disposed on the same horizontal level as the upper surfaces of the first gate electrode portion 130a and the second gate electrode portion 130b.

[0134] Referring to FIG. 6G The fourth horizontal tunnel layer OH4 can be formed by removing the first sacrificial pad layer 151 and the second sacrificial pad layer 152. The first sacrificial pad layer 151 and the second sacrificial pad layer 152 can be removed by an etching process. The etching process can include a wet etching process and / or a dry etching process.

[0135] In the process of removing the first sacrificial pad layer 151 and the second sacrificial pad layer 152, the upper surface of the first insulating pattern IL1a_P1 in contact with the first sacrificial pad layer 151 can be partially etched and the first insulating pattern IL1a_P2 can be formed. The horizontal level of the upper surface of the first insulating pattern IL1a_P2 can be lower than the horizontal level of the upper surface of the first gate electrode portion 130a.

[0136] The first insulating pattern IL1a_P2 can be exposed through the 4-1 horizontal tunnel layer OH4a, and the first barrier layer BP1_P covering the first gate electrode portion 130a can be exposed through the 4-2 horizontal tunnel layer OH4b.

[0137] Referring to FIG. 6H The sacrificial film 183 covering the side surfaces of the third vertical through-hole OV3 and the fourth horizontal tunnel layer OH4 can be formed. The sacrificial film 183 can include a material having etching selectivity with respect to the interlayer insulating layer 120. For example, the sacrificial film 183 can include silicon nitride.

[0138] In various example embodiments, a process of forming the sacrificial film 183 according to the surface profile of the side surface of the third vertical via hole OV3 and the surface profile of the fourth horizontal tunnel layer OH4 can not be provided. In this case, after the process of removing the first and second sacrificial pad layers 151 and 152, the conductive liner 173 can be deposited according to the surface profile of the third vertical via hole OV3 and the fourth horizontal tunnel layer OH4.

[0139] Referring to FIG. 6I The first barrier layer BP1_P exposed through the sacrificial film 183 and the fourth horizontal tunnel layer OH4 can be removed. In various example embodiments, the sacrificial film 183 disposed according to the surface profile of the side surface of the third vertical via hole OV3 and the fourth horizontal tunnel layer OH4 can be removed through an etching process. In the process of removing the sacrificial film 183, a portion of the upper surface of the first insulating pattern IL1a_P2 can be etched, thereby forming the first insulating pattern IL1a. The upper surface of the first insulating pattern IL1a can be exposed through the 5-1 horizontal tunnel layer OH5a. In various example embodiments, because the first barrier layer BP1_P exposed through the fourth horizontal tunnel layer OH4 is removed, the upper surface of the first gate electrode portion 130a can be exposed through the 5-2 horizontal tunnel layer OH5b. In various example embodiments, the first potential barrier layer PP1 in contact with the upper surface of the first barrier layer BP1_P can be removed together with the first barrier layer BP1_P. However, example embodiments are not limited thereto, and the first potential barrier layer PP1 in contact with the upper surface of the first barrier layer BP1_P can not be removed. In this case, a portion of the first potential barrier layer PP1 in contact with the upper surface of the first barrier layer BP1_P can be removed or left through a separate process.

[0140] Referring to FIG. 6J The conductive liner 173 can be deposited according to the surface profile of the fourth vertical via hole OV4 and the fifth horizontal tunnel layer OH5. The conductive liner 173 can cover the upper surface of the first gate electrode portion 130a and the upper surface of the first contact insulating layer 161 exposed through the fifth horizontal tunnel layer OH5. The conductive liner 173 can extend from the upper surface of the first gate electrode portion 130a and the upper surface of the first contact insulating layer 161 along the side surfaces of the first and second contact insulating layers 161 and 162 and the side surface of the interlayer insulating layer 120.

[0141] Thereafter, referring to FIG. 3A The contact plug 170 can be formed by depositing a conductive material in the fourth vertical via hole OV4 and the fifth horizontal tunnel layer OH5.

[0142] FIG. 7A to FIG. 7C are cross-sectional views illustrating various example embodiments of a method of manufacturing a semiconductor device in FIG. 4B .

[0143] FIG. 7A to FIG. 7C The process can be performed in sequence as a process subsequent to the process of removing the insulating structure 20 surrounding the second vertical through-hole OV2 in FIG. 6F

[0144] Referring to FIG. 7A A sealing pattern 163P can be deposited on the side surface of the second vertical through-hole OV2. The sealing pattern 163P can fill spaces in the step difference between the first insulating patterns IL1a_P and IL2a and the second insulating patterns IL1b and IL2b exposed to the side surface of the second vertical through-hole OV2 due to a difference in etching speed in the process of removing the insulating structure 20 surrounding the second vertical through-hole OV2 and unevenness of the second contact insulating layer 162.

[0145] Referring to FIG. 7B A fourth horizontal tunnel layer OH4 can be formed by removing the first and second sacrificial pad layers 151 and 152. By performing a trimming process on the sealing pattern 163P, a sealing pattern 163 exposing the side surface of the second insulating pattern IL2b can be formed.

[0146] The first and second sacrificial pad layers 151 and 152 can be removed by an etching process. The etching process can include a wet etching process and / or a dry etching process. In the process of removing the first and second sacrificial pad layers 151 and 152, the upper surface of the first insulating pattern IL1a_P in contact with the first sacrificial pad layer 151 can be partially etched, thereby forming the first insulating pattern IL1a.

[0147] By the trimming process of the sealing pattern 163P, the sealing pattern 163P disposed on the side surface of the first and second sacrificial pad layers 151 and 152 and the second vertical through-hole OV2 in contact with the cell region insulating layer 190 can be removed. By partially etching the sealing pattern 163P in the horizontal direction on the lower surface of the second insulating patterns IL1b and IL2b protruding toward the third vertical through-hole OV3, the side surface of the second insulating patterns IL1b and IL2b can be exposed. The side surface of the second insulating patterns IL1b and IL2b exposed toward the third vertical through-hole OV3 and the outer side surface of the sealing pattern 163 can form a flat one surface in the third direction (Z direction).

[0148] ​After the process of removing the first and second sacrificial pad layers 151 and 152, one surface of the first barrier layer BP1_P can be exposed through the fourth horizontal tunnel layer OH4. The first barrier layer BP1 can be formed by removing the first barrier layer BP1_P exposed through the fourth horizontal tunnel layer OH4. Because the first barrier layer BP1_P exposed through the fourth horizontal tunnel layer OH4 is removed, the upper surface of the first gate electrode portion 130a can be exposed. In various example embodiments, the first barrier layer PP1 in contact with the upper surface of the first barrier layer BP1_P can be removed together with the first barrier layer BP1_P. However, example embodiments are not limited thereto, and the first barrier layer PP1 in contact with the upper surface of the first barrier layer BP1_P can not be removed.

[0149] Referring to FIG. 7C The conductive liner 173 can be deposited according to the surface profile of the third vertical through-hole OV3 and the fourth horizontal tunnel layer OH4. The conductive liner 173 can cover the upper surface of the first gate electrode portion 130a and the upper surface of the first contact insulating layer 161 exposed through the fourth horizontal tunnel layer OH4. The conductive liner 173 can extend from the upper surface of the first gate electrode portion 130a and the upper surface of the first contact insulating layer 161 along the side surfaces of the second insulating patterns IL1b and IL2b and the side surface of the sealing pattern 163.

[0150] Thereafter, referring to FIG. 4B The contact plug 170 can be formed by depositing a conductive material in the third vertical through-hole OV3 and the fourth horizontal tunnel layer OH4.

[0151] FIG. 8A to FIG. 8G is a cross-sectional view illustrating a method of manufacturing a semiconductor device in FIG. 4C .

[0152] FIG. 8A is an enlarged view illustrating a region E of a semiconductor device in FIG. 5F according to other various example embodiments. Referring to FIG. 8A , by applying an etchant through the first vertical through-hole OV1 penetrating the sacrificial insulating layer 122 and the interlayer insulating layer 120, the sacrificial insulating layer 122 can be removed to a desired (and / or optionally predetermined) length around the first vertical through-hole OV1, and the first horizontal tunnel layer OH1' can be formed.

[0153] Referring to FIG. 8B The first and second insulating liners 25 and 23 can be formed in the first horizontal tunnel layer OH1' connected to the first vertical through-hole OV1 and the first vertical through-hole OV1.

[0154] The first and second insulating liners 25 and 23 can extend into side surfaces of the first vertical via OVI and the first horizontal tunnel layer OH1', and can be formed in order by a deposition process.

[0155] The first insulating liner 25 can have a substantially uniform thickness, can extend from a side surface of the first vertical via OVI into the first horizontal tunnel layer OH1', and can be conformally formed according to a surface profile of the first horizontal tunnel layer OH1'. The second insulating liner 23 can be deposited on the first insulating liner 25. That is, the second insulating liner 23 can be deposited by extending into a region between the first insulating liners 25 formed on the side surface of the first vertical via OVI into the third horizontal tunnel layer OH3. The first insulating liner 25 can include a first insulating material, and the second insulating liner 23 can include a second insulating material different from the first insulating material.

[0156] Referring to FIG. 8C The first and second gate electrode portions 130a and 130b can be formed by removing the sacrificial insulating layer 122. The sacrificial insulating layer 122 can be removed by a wet etching process. The first barrier layer BP1_P can be deposited in a space in which the first sacrificial insulating layer 122a has been removed before the first and second gate electrode portions 130a and 130b are formed, and the second barrier layer BP2 can be deposited in a space in which the second sacrificial insulating layer 122b has been removed. The first and second barrier layers BP1_P and BP2 can be conformally formed according to a surface profile of an inner wall of the space in which the sacrificial insulating layer 122 has been removed.

[0157] The first gate electrode portion 130a can be formed on the first barrier layer BP1_P, and the second gate electrode portion 130b can be formed on the second barrier layer BP2. In various example embodiments, the first barrier layer BP1_P can be deposited in order on the first and second gate electrode portions 130a and 130b. The second barrier layer BP2 can be deposited in order on the first and second gate electrode portions 130a and 130b.

[0158] Referring to FIG. 8DThe first insulating liner 25 and the second insulating liner 23 surrounding the second vertical through-hole OV2 can be removed. The etching rate of the second insulating liner 23 can be lower than the etching rate of the first insulating liner 25. The first insulating liner 25 can be etched such that the first insulating patterns IL1a''_P and IL2a'' can remain in the first horizontal tunnel layer OH1', and the second insulating liner 23 can be etched such that the second insulating patterns IL1b''_P and IL2b'' include a portion formed between the first insulating patterns IL1a''_P and IL2a'' and protrude from end portions of the first insulating patterns IL1a''_P and IL2a'' toward the second vertical through-hole OV2. In various example embodiments, upper surfaces of the first insulating patterns IL1a''_P and IL2a'' can be disposed at the same horizontal level as upper surfaces of the first gate electrode portion 130a and the second gate electrode portion 130b. Lower surfaces of the first insulating patterns IL1a''_P and IL2a'' can be disposed at the same horizontal level as lower surfaces of the first gate electrode portion 130a and the second gate electrode portion 130b.

[0159] Referring to FIG. 8E A sealing pattern 163_P can be deposited on side surfaces of the second vertical through-hole OV2. The sealing pattern 163_P can fill a space in a step difference between the first insulating pattern IL1a''_P and the second insulating pattern IL1b''_P exposed to the side surfaces of the second vertical through-hole OV2 due to the etching rate difference in the process of removing the first insulating liner 25 and the second insulating liner 23 surrounding the second vertical through-hole OV2 and unevenness of the second contact insulating layer 162''.

[0160] Referring to FIG. 8F A fourth horizontal tunnel layer OH4 can be formed by removing the first sacrificial pad layer 151 and the second sacrificial pad layer 152. By performing a trimming process on the sealing pattern 163_P, a sealing pattern 163 exposing side surfaces of the second insulating patterns IL1b'' and IL2b'' can be formed.

[0161] The first sacrificial pad layer 151 and the second sacrificial pad layer 152 can be removed by an etching process. The etching process can include a wet etching process and / or a dry etching process. In the process of removing the first sacrificial pad layer 151 and the second sacrificial pad layer 152, an upper surface of the first insulating pattern IL1a''_P in contact with the first sacrificial pad layer 151 can be partially etched, and a first insulating pattern IL1a'' can be formed. In various example embodiments, an upper surface of the second insulating pattern IL1b''_P can be partially etched such that the upper surface of the second insulating pattern IL1b'' can be exposed through the fourth horizontal tunnel layer OH4.

[0162] The sealing pattern 163_P disposed on the side surface of the first and second sacrificial pad layers 151 and 152 and the second vertical via OV2 in contact with the cell region insulating layer 190 can be removed through a trimming process of the sealing pattern 163_P. A portion of the sealing pattern 163_P disposed on the lower surface of the second insulating patterns IL1b" and IL2b" protruding toward the third vertical via OV3 can be etched in a horizontal direction, and thus the side surfaces of the second insulating patterns IL1b" and IL2b" can be exposed. The side surfaces of the second insulating patterns IL1b" and IL2b" exposed toward the third vertical via OV3 and the outer side surface of the sealing pattern 163 can form a flat surface in the third direction (Z direction).

[0163] The first barrier layer BP1_P exposed through the fourth horizontal tunnel layer OH4 can be removed, and thus the first barrier layer BP1 covering one side surface and a bottom surface of the first gate electrode portion 130a can be formed. The upper surface of the first insulating pattern IL1a" can be exposed through the 4-1 horizontal tunnel layer OH4a. In various example embodiments, the upper surface of the first gate electrode portion 130a can be exposed by removing the first barrier layer BP1_P exposed through the fourth horizontal tunnel layer OH4.

[0164] Referring to FIG. 8G The conductive liner 173 can be deposited according to the surface profile of the third vertical via OV3 and the fourth horizontal tunnel layer OH4. The conductive liner 173 can cover the upper surface of the first gate electrode portion 130a and the upper surface of the first contact insulating layer 161" exposed through the fourth horizontal tunnel layer OH4. The conductive liner 173 can extend from the upper surface of the first gate electrode portion 130a and the upper surface of the first contact insulating layer 161" along the side surfaces of the second insulating patterns IL1b" and IL2b" and the side surface of the sealing pattern 163.

[0165] Thereafter, referring to FIG. 4C The contact plug 170 can be formed by depositing a conductive material in the third vertical via OV3 and the fourth horizontal tunnel layer OH4.

[0166] FIG. 9 and FIG. 10 are cross-sectional views illustrating semiconductor devices according to various example embodiments.

[0167] Referring to FIG. 9 In the semiconductor device 100e, the shapes of the gate structure GSe, the channel structure CHe, and the contact plug 170e can be different from those of the example embodiments in FIG. 1B .

[0168] The gate structure GSe can include a first stack structure GS1 and a second stack structure GS2 stacked vertically. Each of the channel structures CHe can include a first channel portion CH1 and a second channel portion CH2 penetrating the first stack structure GS1 and the second stack structure GS2, respectively. Each of the contact plugs 170e can include a first contact portion MC1 and a second contact portion MC2 stacked in the third direction (Z direction). The first contact portion MC1 and the second contact portion MC2 can penetrate the first stack structure GS1 and the second stack structure GS2 of the gate structure GSe, respectively. In various example embodiments, an interface surface between the first contact portion MC1 and the second contact portion MC2 can be disposed at the same level as an interface surface between the first channel portion CH1 and the second channel portion CH2.

[0169] As described above, in various example embodiments, the number of the stack structures included in the gate structure GSe can vary, and thus, the number of the stacked portions in each of the channel structures CHe and the contact plugs 170e in the third direction (Z direction) can vary.

[0170] Reference FIG. 10 The semiconductor device 100f can include a first semiconductor structure S1 and a second semiconductor structure S2 bonded to each other using a wafer bonding method.

[0171] The description of the peripheral circuit region PERI described above with reference to FIG. 1B The description of the peripheral circuit region PERI described above with reference to may be applied to the first semiconductor structure S1. However, the first semiconductor structure S1 can further include bonding structures such as a first bonding via 297, a first bonding metal layer 298, and a first bonding insulating layer 299. The first bonding via 297 can be disposed on an upper portion of the uppermost circuit interconnection line 280 and can be connected to the circuit interconnection line 280. At least a portion of the first bonding metal layer 298 can be connected to the first bonding via 297 on the first bonding via 297. The first bonding metal layer 298 can be connected to the second bonding metal layer 198 of the second semiconductor structure S2. The first bonding metal layer 298 together with the second bonding metal layer 198 can provide an electrical connection path according to bonding between the first semiconductor structure S1 and the second semiconductor structure S2. A portion of the first bonding metal layer 298 can not be connected to the lower circuit interconnection line 280 and can be disposed only for bonding. The first bonding via 297 and the first bonding metal layer 298 can include a conductive material, for example, copper (Cu). The first bonding insulating layer 299 can be disposed around the first bonding metal layer 298. The first bonding insulating layer 299 can also serve as a diffusion barrier for the first bonding metal layer 298 and can include, for example, at least one of SiN, SiON, SiCN, SiOC, SiOCN, and SiO. However, example embodiments are not limited thereto.

[0172] Unless otherwise indicated, the above references to FIG. 1A to FIG. 1C The description of the storage cell region CELL described above can apply to the second semiconductor structure S2. The second semiconductor structure S2 can further include a second bonding via 197, a second bonding metal layer 198, and a second bonding insulating layer 199 as a bonding structure. The second semiconductor structure S2 can further include a passivation layer 106 covering an upper surface of the second substrate 101.

[0173] The second bonding via 197 and the second bonding metal layer 198 can be disposed below the lowermost cell interconnect line 195. The second bonding via 197 can connect the cell interconnect line 195 to the second bonding metal layer 198, and the second bonding metal layer 198 can be bonded to the first bonding metal layer 298 of the first semiconductor structure S1. The second bonding insulating layer 199 can be bonded and connected to the first bonding insulating layer 299 of the first semiconductor structure S1. The second bonding via 197 and the second bonding metal layer 198 can include a conductive material, such as copper (Cu). The second bonding insulating layer 199 can include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN. However, example embodiments are not limited thereto.

[0174] The first semiconductor structure S1 and the second semiconductor structure S2 can be bonded to each other by a bonding between the first bonding metal layer 298 and the second bonding metal layer 198 and a bonding between the first bonding insulating layer 299 and the second bonding insulating layer 199. The bonding between the first bonding metal layer 298 and the second bonding metal layer 198 can be, for example, a copper (Cu)-copper (Cu) bonding, and the bonding between the first bonding insulating layer 299 and the second bonding insulating layer 199 can be, for example, a dielectric-dielectric bonding, such as a SiCN-SiCN bonding. The first semiconductor structure S1 and the second semiconductor structure S2 can be bonded to each other by a hybrid bonding including a copper (Cu)-copper (Cu) bonding and a dielectric-dielectric bonding. However, example embodiments are not limited thereto.

[0175] The passivation layer 106 can be disposed on the upper surface of the second substrate 101 and can protect the semiconductor device 100f. The passivation layer 106 can include at least one of an insulating material (e.g., silicon oxide, silicon nitride, and silicon carbide). However, example embodiments are not limited thereto. The substrate insulating layer 121 can be disposed relatively widely in the second region R2 to cover the upper ends of the contact plugs 170. However, in various example embodiments, the arrangement of the substrate insulating layer 121 can vary within a range such that the contact plugs 170 originating from the substrate insulating layer 121 are electrically isolated from each other.

[0176] FIG. 11 FIG. 1 is a diagram illustrating a data storage system including a semiconductor device according to various example embodiments.

[0177] Reference FIG. 11 The data storage system 1000 can include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 can be implemented as a storage device including one or more semiconductor devices 1100 or an electronic device including the storage device. For example, the data storage system 1000 can be implemented as a solid state disk (SSD) device including one or more semiconductor devices 1100, a universal serial bus (USB) device, a computing system, a medical device, or a communication device.

[0178] The semiconductor device 1100 can be implemented as a non-volatile memory device such as, for example, a NAND flash memory device described in the foregoing example embodiments with reference to FIGS. 1A to 1C. FIG. 1A to FIG. 1C The semiconductor device 1100 can include a first structure 1100F and a second structure 1100S located on the first structure 1100F. In various example embodiments, the first structure 1100F can be disposed at a side of the second structure 1100S. The first structure 1100F can be implemented as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S can be implemented as a memory cell structure including bit lines BL, a common source line CSL, word lines WL, first and second upper gate lines UL1 and UL2, first and second lower gate lines LL1 and LL2, and memory cell strings CSTR located between the bit lines BL and the common source line CSL.

[0179] In the second structure 1100S, each memory cell string CSTR can include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In various example embodiments, the number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 can vary.

[0180] In various example embodiments, the upper transistors UT1 and UT2 can include string selection transistors, and the lower transistors LT1 and LT2 can include ground selection transistors. The lower gate lines LL1 and LL2 can be configured as gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL can be configured as gate electrodes of the memory cell transistors MCT, and the upper gate lines UL1 and UL2 can be configured as gate electrodes of the upper transistors UT1 and UT2, respectively.

[0181] In various example embodiments, the lower transistors LT1 and LT2 can include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series with each other. The upper transistors UT1 and UT2 can include a string select transistor UT1 and an upper erase control transistor UT2 connected in series with each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 can be used in an erase operation for erasing data stored in the memory cell transistor MCT using a GIDL phenomenon.

[0182] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 can be electrically connected to the decoder circuit 1110 through a first connection interconnect 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 through a second connection interconnect 1125 extending from the first structure 110F to the second structure 1100S.

[0183] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 can be controlled by a logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0184] The controller 1200 can include a processor 1210, a NAND controller 1220, and a host interface 1230. In various example embodiments, the data storage system 1000 can include a plurality of semiconductor devices 1100, and in this case, the controller 1200 can control the plurality of semiconductor devices 1100.

[0185] The processor 1210 can control the overall operation of the data storage system 1000 including the controller 1200. The processor 1210 can operate according to desired (and / or optionally predetermined) firmware, and can access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 can include a controller interface 1221 that handles communication with the semiconductor device 1100. Through the controller interface 1221, control commands for controlling the semiconductor device 1100, data to be written to memory cell transistors MCTs of the semiconductor device 1100, and data to be read from the memory cell transistors MCTs of the semiconductor device 1100 can be transmitted. The host interface 1230 can provide a communication function between the data storage system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 can control the semiconductor device 1100 in response to the control command.

[0186] FIG. 12 FIG. 1 is a perspective view illustrating a data storage system including a semiconductor device according to various example embodiments.

[0187] Reference FIG. 12 The data storage system 2000 in various example embodiments can include a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 can be connected to the controller 2002 through an interconnection pattern 2005 formed on the main board 2001.

[0188] The main board 2001 can include a connector 2006 having a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 can vary according to a communication interface between the data storage system 2000 and the external host. In various example embodiments, the data storage system 2000 can communicate with the external host according to one of interfaces among Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS). In various example embodiments, the data storage system 2000 can operate by power supplied from the external host via the connector 2006. The data storage system 2000 can further include a Power Management Integrated Circuit (PMIC) for distributing the power supplied from the external host to the controller 2002 and the semiconductor packages 2003.

[0189] The controller 2002 can write data to or read data from the semiconductor packages 2003, and can improve the operation speed of the data storage system 2000.

[0190] The DRAM 2004 can be configured as a buffer memory for reducing a speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the data storage system 2000 can operate as a cache memory, and can provide a space for temporarily storing data in a control operation of the semiconductor package 2003. When the data storage system 2000 can include the DRAM 2004, the controller 2002 can include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0191] The semiconductor package 2003 can include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b can be configured as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b can include a package substrate 2100, the semiconductor chips 2200 located on the package substrate 2100, an adhesive layer 2300 disposed on a lower surface of each of the semiconductor chips 2200, respectively, a connection structure 2400 electrically connecting the semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0192] The package substrate 2100 can be configured as a printed circuit board including package upper pads 2130. Each of the semiconductor chips 2200 can include input / output pads 2210. The input / output pads 2210 can correspond to the input / output pads 1101 in FIG. 11 Each of the semiconductor chips 2200 can include a gate stack structure 3210 and a channel structure 3220. Each of the semiconductor chips 2200 can include a semiconductor device described in the foregoing example embodiments with reference to FIG. 1A to FIG. 1C

[0193] ​In various example embodiments, the connection structure 2400 can be configured to electrically connect the input / output pads 2210 to the bonding wires of the package-up pads 2130. Thus, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 can be electrically connected to each other by a bonding wire method, and can be electrically connected to the package-up pads 2130 of the package substrate 2100. In various example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 can be electrically connected to each other by the connection structure 2400 including through-silicon vias (TSVs) instead of a bonding wire method.

[0194] In various example embodiments, the controller 2002 and the semiconductor chips 2200 can be included in a single package. In various example embodiments, the controller 2002 and the semiconductor chips 2200 can be mounted on an interposer substrate different from the main board 2001, and the controller 2002 and the semiconductor chips 2200 can be connected to each other by interconnects formed on the interposer substrate.

[0195] FIG. 13 is a cross-sectional view illustrating a semiconductor package according to various example embodiments.

[0196] FIG. 13 is a cross-sectional view illustrating a semiconductor package according to various example embodiments. FIG. 12 Various example embodiments of the semiconductor package 2003 in

[0197] Referring to FIG. 13 , in the semiconductor package 2003, the package substrate 2100 can be implemented as a printed circuit substrate. The package substrate 2100 can include a package substrate body 2120, package-up pads 2130 disposed on an upper surface of the package substrate body 2120 (in FIG. 12 ), lower pads 2125 disposed on the upper surface of the package substrate body 2120 and exposed through a lower surface, and internal interconnects 2135 electrically connecting the package-up pads 2130 to the lower pads 2125 in the package substrate body 2120. The lower pads 2125 can be connected to the interconnect pattern 2005 of the main board 2001 of the data storage system 2000 through the conductive connection portions 2800, as FIG. 12 illustred.

[0198] Each semiconductor chip 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region having a peripheral interconnect 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 located on the common source line 3205, a channel structure 3220 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a word line ( FIG. 1B The gate electrode 130) is a contact plug ( FIG. 1B As shown in the enlarged view, the first structure 3100 may further include a contact insulating layer 160. The contact insulating layer 160 may include a first contact insulating layer 161 disposed between the gate contact region 130P and a vertical extension portion 170V of the contact plug 170, and a second contact insulating layer 162 disposed between the gate stack region 130G below the gate contact region 130P and the vertical extension portion 170V. The contact plug 170 may include a vertical extension portion 170V that penetrates the gate electrode 130 and the interlayer insulating layer 120, and a horizontal extension portion 170H that extends from the vertical extension portion 170V and contacts the first contact insulating layer 161 and the gate contact region 130P.

[0199] Each semiconductor chip 2200 may include a through-interconnect 3245 electrically connected to the peripheral interconnect 3110 of the first structure 3100 and extending into the second structure 3200. The through-interconnect 3245 may be disposed outside the gate stack structure 3210 and may further be disposed to penetrate the gate stack structure 3210. Each semiconductor chip 2200 may also include an input / output pad 2210 (at the outer edge of the first structure 3100) electrically connected to the peripheral interconnect 3110. FIG. 12 middle).

[0200] One or more of the elements disclosed above may include or be implemented in a processing circuit, such as hardware including logic circuitry; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like.

[0201] According to the foregoing example embodiments, the semiconductor device and the data storage system including the semiconductor device can include a gate electrode having a gate contact region and a contact plug connected to the gate contact region, and the gate contact region can be connected to the contact plug through a horizontally extending portion disposed on an upper surface of the gate contact region. Accordingly, deformation of a gate stack region disposed at a lower portion of the gate contact region and a contact insulating layer disposed between the gate stack region and the vertically extending portion depending on a contact position of the gate contact region and the contact plug and a decrease in reliability resulting therefrom can be reduced or prevented. A semiconductor device and a data storage system including the same having improved reliability can be provided.

[0202] While various example embodiments have been illustrated and described above, it will be clear to those skilled in the art that modifications and changes can be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device comprising: a first semiconductor structure including a substrate, a circuit device on the substrate, and a circuit interconnect on the circuit device; and a second semiconductor structure on the first semiconductor structure and having a first region and a second region, wherein the second semiconductor structure includes: a plate layer; gate electrodes stacked in a vertical direction on an upper surface of the plate layer and spaced apart from each other, extending different lengths in a first direction intersecting the vertical direction on the second region, and including a gate contact region; interlayer insulating layers stacked in alternation with the gate electrodes; channel structures penetrating the gate electrodes and the interlayer insulating layers in the first region and extending in the vertical direction; contact plugs penetrating the gate electrodes in the second region, extending in the vertical direction, and electrically connecting the gate electrodes to part of the circuit interconnects, respectively; and contact insulating layers stacked in alternation with the interlayer insulating layers, surrounding the contact plugs, and including a first contact insulating layer between the gate contact region and the contact plugs, wherein each of the contact plugs includes: a vertically extending portion extending in the vertical direction, a horizontally extending portion extending from the vertically extending portion in a horizontal direction and overlapping the gate contact region and the first contact insulating layer in the vertical direction, and a conductive pad extending to a region between the horizontally extending portion and the first contact insulating layer and to a region between the horizontally extending portion and the gate contact region.

2. The semiconductor device according to claim 1, the contact plugs include a first conductive material same as a material of the gate electrodes, and wherein the conductive pad includes a second conductive material different from the first conductive material. an upper surface of the gate contact region is located at a higher level than a level of an upper surface of each of the first contact insulating layers.

3. The semiconductor device of claim 1, wherein, a height of a first portion of the horizontally extending portion overlapping the gate contact region is smaller than a height of a second portion of the horizontally extending portion overlapping the first contact insulating layer.

4. The semiconductor device of claim 1, wherein, 5. The semiconductor device according to claim 1, the contact insulating layers further include second contact insulating layers surrounding the contact plugs at a lower portion of the gate contact region, and wherein, a height of each of the second contact insulating layers is greater than a height of each of the first contact insulating layers.

6. The semiconductor device according to claim 5, the gate electrodes further include a gate stack region in contact with the second contact insulating layers, and wherein, a height of the gate stack region is greater than a height of the gate contact region.

7. The semiconductor device according to claim 1, further comprising: ​ a sealing pattern extending from the contact insulating layer and located between the interlayer insulating layer and the vertically extending portion, wherein the sealing pattern includes silicon nitride.

8. The semiconductor device of claim 7, wherein, The conductive pad extends to a region between the contact insulating layer and the vertically extending portion and to a region between the sealing pattern and the vertically extending portion.

9. The semiconductor device according to claim 1, wherein, each of the contact insulating layers includes a first insulating pattern and a second insulating pattern having a portion surrounded by the first insulating pattern, wherein the first insulating pattern includes silicon oxide, and the second insulating pattern includes silicon nitride.

10. The semiconductor device of claim 9, wherein, A first thickness of the first insulating pattern of the first contact insulating layer on an upper surface of the second insulating pattern of the first contact insulating layer is smaller than a second thickness of the first insulating pattern of the first contact insulating layer on a lower surface of the second insulating pattern of the first contact insulating layer.

11. The semiconductor device of claim 9, wherein, The second insulating pattern includes a first void and a second void spaced apart from the first void in the first direction.

12. The semiconductor device of claim 11, wherein, A length of the first void in the first direction is greater than a length of the second void in the first direction.

13. The semiconductor device of claim 11, wherein, Each of the first insulating pattern and the second insulating pattern includes: a flat portion extending in the horizontal direction; and a protrusion extending from the flat portion, the protrusion extends between the flat portion and the vertically extending portion, and the protrusion further protrudes toward the interlayer insulating layer.

14. The semiconductor device of claim 13, wherein, The protrusion is located between the first void and the second void.

15. A semiconductor device, the semiconductor device comprising: a stack pattern having a memory cell array region and a staircase region; a stack structure extending on the stack pattern from the memory cell array region to the staircase region, wherein the stack structure includes interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, and the gate electrodes include gate contact pads arranged in a staircase form on the staircase region; a channel structure penetrating the stack structure in the memory cell array region and extending in the vertical direction; a contact plug penetrating the gate electrodes and the interlayer insulating layers in the staircase region; and a contact insulating layer alternately stacked with the interlayer insulating layers and surrounding the contact plug, wherein the contact insulating layer includes: a first contact insulating layer located between the gate contact pads and the contact plug, and a second contact insulating layer alternately stacked with the interlayer insulating layers at a lower portion of the gate contact pads and surrounding the contact plug, wherein each of the contact plugs includes: a vertically extending portion extending in the vertical direction, and a horizontally extending portion extending in a horizontal direction. a horizontal extension portion extending in a horizontal direction from the vertical extension portion, and contacting each of the first contact insulating layer and the gate contact pad, and wherein a height of each of the first contact insulating layer is less than a height of each of the second contact insulating layer.

16. The semiconductor device of claim 15, wherein, each of the interlayer insulating layers includes: a first interlayer insulating layer located at a lower portion of the first contact insulating layer, and a second interlayer insulating layer located at a lower portion of the second contact insulating layer, wherein each of the first contact insulating layer includes a first flat portion and a first protrusion extending from the first flat portion, and the first protrusion protrudes toward the first interlayer insulating layer, and wherein each of the second contact insulating layer includes a second flat portion and a second protrusion extending from the second flat portion, and the second protrusion protrudes toward the first interlayer insulating layer and the second interlayer insulating layer.

17. The semiconductor device of claim 15, wherein each of the contact insulating layers includes a first insulating pattern and a second insulating pattern including a first portion surrounded by the first insulating pattern and a second portion extending from the first portion, and the second portion protrudes toward the vertical extension portion, wherein the first insulating pattern includes a first insulating material, and wherein the second insulating pattern includes a second insulating material different from the first insulating material.

18. The semiconductor device of claim 17, further comprising: a sealing pattern extending from the second portion of the second insulating pattern to a region between the interlayer insulating layer and the vertical extension portion; and wherein each of the contact plugs further includes a conductive liner covering an upper surface of the gate contact pad, an upper surface of the first contact insulating layer, and an outer lateral surface of the sealing pattern.

19. A data storage system, the data storage system comprising: a semiconductor storage device including a first semiconductor structure, a second semiconductor structure, and an input / output pad, the first semiconductor structure including a circuit device and a circuit interconnect electrically connected to the circuit device, the second semiconductor structure located on one surface of the first semiconductor structure and including a first region and a second region, the input / output pad electrically connected to the circuit device; and a controller electrically connected to the semiconductor storage device through the input / output pad and controlling the semiconductor storage device, wherein the second semiconductor structure includes: a plate layer; gate electrodes stacked in a vertical direction on an upper surface of the plate layer and spaced apart from each other, the gate electrodes extending different lengths in a first direction intersecting the vertical direction on the second region and respectively including gate contact regions; interlayer insulating layers stacked alternately with the gate electrodes; and a contact plug electrically connected to each of the gate contact regions. a trench structure penetrating the gate electrodes and the interlayer insulating layers in the first region and extending in the vertical direction; contact plugs penetrating the gate contact regions of each of the gate electrodes in the second region, extending in the vertical direction, and electrically connecting the gate electrodes to the circuit interconnects, respectively; a first contact insulating layer stacked with the interlayer insulating layers alternately between the gate contact regions and the contact plugs, the first contact insulating layer surrounding the contact plugs; and a second contact insulating layer stacked with the interlayer insulating layers alternately at lower portions of the gate contact regions, and the second contact insulating layer surrounding the contact plugs, wherein each of the contact plugs includes: a vertically extending portion extending in the vertical direction, a horizontally extending portion extending from the vertically extending portion in a horizontal direction, the horizontally extending portion overlapping each of the first contact insulating layer and the gate contact regions, and a conductive liner extending to a region between the horizontally extending portion and the first contact insulating layer, and the conductive liner further extending to a region between the horizontally extending portion and the gate contact regions.

20. The data storage system of claim 19, wherein, the conductive liner further extends to a region between the first contact insulating layer and the vertically extending portion and a region between the second contact insulating layer and the vertically extending portion, and the conductive liner further extends to a region between the interlayer insulating layer and the vertically extending portion.

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