Memory device and method of manufacturing the same

Abstract

The invention provides a memory device and a manufacturing method thereof. The method includes providing a substrate, forming a select gate structure and a word line structure on the substrate, and forming a fill material to cover the select gate structure and the word line structure. The method further includes etching back the fill material to expose a top of the select gate structure and a top of the word line structure, sequentially forming a cap layer and a first dielectric layer over the substrate, and etching back the first dielectric layer and the cap layer to expose the fill material between the select gate structure and a dummy word line of the word line structure closest to the select gate structure. The method further includes removing the filling material in which protrusions of the cap layer remain on both sides of the select gate structure and one side of the dummy word line facing the select gate structure, and forming a second dielectric layer filled between the select gate structure and the dummy word line and covering the first dielectric layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor technology, and more particularly, to memory devices and methods of manufacturing the same. BACKGROUND

[0002] In current processes of forming memory devices (e.g., flash memory), as the feature size continues to shrink, the process margin also decreases. For example, after forming select gate structures and word line structures, a dielectric layer is typically formed to cover the select gate structures and the word line structures and to form air gaps between the word line structures and / or between the select gate structures and the word line structures. Although different designs are possible depending on different requirements, an air gap that is too large or too high between the select gate structures and the word line structures can affect the defect number performance or decrease the overall structure strength, which can undesirably affect the memory devices and cause electrical problems. Therefore, there is still a need to improve the manufacturing method of the memory devices to maintain the yield of the memory devices. SUMMARY

[0003] Embodiments of the present application provide a method of manufacturing a memory device, including providing a substrate; forming select gate structures and a plurality of word line structures on the substrate; forming a fill material to cover the select gate structures and the word line structures and to fill between the select gate structures and the word line structures; etching back the fill material to expose top portions of the select gate structures and top portions of the word line structures; sequentially forming a cap layer and a first dielectric layer above the substrate; etching back the first dielectric layer and the cap layer to expose the fill material between the select gate structures and dummy word lines of the word line structures closest to the select gate structures; removing the fill material, wherein both sides of the select gate structures and one side of the dummy word lines closest to the select gate structures have protrusions of the cap layer remaining thereon; and forming a second dielectric layer to fill between the select gate structures and the dummy word lines and to cover the first dielectric layer above the word line structures.

[0004] Embodiments of the present application provide a memory device, including a substrate; select gate structures disposed on the substrate; a plurality of word line structures disposed on the substrate and adjacent to the select gate structures; a cap layer overlying the select gate structures and each of the word line structures; and a dielectric layer filling between the select gate structures and dummy word lines of the word line structures closest to the select gate structures and covering the word line structures, wherein both sides of the select gate structures and one side of the dummy word lines closest to the select gate structures have protrusions of the cap layer thereon. BRIEF DESCRIPTION OF DRAWINGS

[0005] In order to make the features and advantages of the present application more clear, different embodiments are described in detail below, and are specifically explained in detail as follows with reference to the accompanying drawings:

[0006] Figures 1 to 10is a cross-sectional schematic diagram illustrating an intermediate stage of fabricating a memory device, according to embodiments of the present disclosure.

[0007] Glossary of symbols

[0008] 10: memory device

[0009] 100: substrate

[0010] 105a: tunnel dielectric layer

[0011] 105b: floating gate layer

[0012] 105c: inter-gate dielectric layer

[0013] 105d: control gate layer

[0014] 105e: metal layer

[0015] 105f: cap layer

[0016] 110: select gate structure

[0017] 120: word line structure

[0018] 121: dummy word line

[0019] 125: hard mask layer

[0020] 127: liner

[0021] 130: fill material

[0022] 135: etch back process

[0023] 140: cap layer

[0024] 142: protrusion

[0025] 145: first dielectric layer

[0026] 150: etch back process

[0027] 155: second dielectric layer

[0028] 160: first air gap

[0029] 165: second air gap

[0030] D1: distance

[0031] D2: pitch

[0032] D3: protrusion distance

[0033] T1: thickness

[0034] T2: thickness

[0035] W: width DETAILED DESCRIPTION

[0036] See first Figure 1 A substrate 100 is provided. In some embodiments, the substrate 100 may be an elemental semiconductor substrate, a compound semiconductor substrate, or an alloy semiconductor substrate. In other embodiments, the substrate 100 may be a semiconductor-on-insulator (SOI) substrate. The SOI substrate may include a base plate, a buried oxide (BOX) layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer.

[0037] Continue to see Figure 1 , forming a select gate structure 110 and a plurality of word line structures 120 on the substrate 100. The select gate structure 110 and the word line structure 120 can be formed by a deposition process in combination with one or more photolithography processes and etching processes. The select gate structure 110 and the word line structure 120 can each include stacked film layers, for example, from bottom to top, they can include a tunneling dielectric layer 105a, a floating gate layer 105b, an intergate dielectric layer 105c, a control gate layer 105d, a metal layer 105e, and a cap layer 105f. In some embodiments, the material of the tunneling dielectric layer 105a can be silicon oxide. In some embodiments, the material of the floating gate layer 105b can be a conductive material, such as doped polysilicon, undoped polysilicon, or a combination thereof. In some embodiments, the intergate dielectric layer 105c may be a composite layer composed of, for example, oxide / nitride / oxide (ONO), but the present application is not limited thereto, and the composite layer may also be a film layer of five or more layers. In some embodiments, the control gate layer 105d may be made of a conductive material such as doped polysilicon, undoped polysilicon, or a combination thereof. In some embodiments, the metal layer 105e may be made of, for example, W, TiN, or a combination thereof. In some embodiments, the cap layer 105f may be made of a dielectric material such as silicon nitride, silicon oxynitride, or a combination thereof.

[0038] In some embodiments, the top surface of the select gate structure 110 is planar with the top surface of the word line structures 120. The distance Dl between the select gate structure 110 and the dummy word line 121 closest to the select gate structure 110 in the word line structures 120 is greater than the spacing D2 between the word line structures 120. In some embodiments, after the formation of the select gate structure 110 and the word line structures 120, a hard mask layer 125 that has not been completely removed can still remain above both the select gate structure 110 and the word line structures 120. Due to the difference in etch loading, the hard mask layer 125 can have different thicknesses above the select gate structure 110 and above the word line structures 120. In some embodiments, the hard mask layer 125 can be a single layer or a multi-layer structure. In some embodiments, the material of the hard mask layer 125 includes polysilicon.

[0039] A liner layer 127 is then conformally formed over the substrate 100. The liner layer 127 covers the sidewalls of the select gate structure 110, the sidewalls of the word line structures 120, and the sidewalls and top surface of the hard mask layer 125. The liner layer 127 can further protect the select gate structure 110 and the word line structures 120 from oxidation or subsequent processes.

[0040] Referring to Figure 2 After the formation of the select gate structure 110 and the word line structures 120, a fill material 130 is formed to cover the select gate structure 110 and the word line structures 120, and to fill in the spaces between the select gate structure 110 and the word line structures 120. The fill material 130 is temporarily filled in the spaces between the select gate structure 110 and the word line structures 120, and will be removed in subsequent processes. In some embodiments, the fill material 130 can include a fluid material that helps fill in the gaps between the select gate structure 110 and the word line structures 120 or between the word line structures 120. In some embodiments, after the formation of the fill material 130, a curing process can be further performed on the fill material 130 to facilitate subsequent etching processes. In some embodiments, the fill material 130 can be spin-on-carbon (SoC) or photoresist.

[0041] Referring to Figure 3 A back-etching process 135 is performed on the fill material 130 to lower the top surface of the fill material 130 below the top surfaces of the select gate structure 110 and the word line structures 120. In some embodiments, the back-etching process 135 can include an anisotropic etching process (or directional etching process), such as a dry etching process.

[0042] Referring to Figure 4The back-etching process 135 can further remove the hard mask layer 125 formed over the select gate structure 110 and the word line structure 120, thereby exposing the top of the select gate structure 110 and the top of the word line structure 120. During the removal of the hard mask layer 125, the back-etching process 135 also removes a portion of the liner 127, and exposes a portion of the sidewalls of the select gate structure 110 and the word line structure 120.

[0043] Referring next Figure 5 A cap layer 140 is formed over the substrate 100. The cap layer 140 is conformally formed over the substrate 100, and the cap layer 140 is formed by a process with a better step coverage. In this way, the cap layer 140 can uniformly cover the exposed top and a portion of the sidewalls of the select gate structure 110 and the exposed top and a portion of the sidewalls of the word line structure 120 after the back-etching process 135. The cap layer 140 is used to define the size and the boundary of a subsequently formed associated air gap (e.g., the first air gap 160), which will be described in more detail below. In some embodiments, the cap layer 140 can be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a combination thereof. In some embodiments, the material of the cap layer 140 includes nitride, such as SiN.

[0044] Referring next Figure 6 A first dielectric layer 145 is formed over the substrate 100. The first dielectric layer 145 is conformally formed over the substrate 100, for example, conformally formed over the cap layer 140, and the first dielectric layer 145 is formed by a process with a worse step coverage. In this way, the first dielectric layer 145 will have different thicknesses over the cap layer 140. The formation of the first dielectric layer 145 with different thicknesses can enable a subsequent back-etching process to further etch the cap layer 140 at specific locations, which will be described further below. In some embodiments, the aforementioned process with a worse step coverage can include a physical vapor deposition (PVD) process and a chemical vapor deposition (CVD) process. In some embodiments, the thickness T1 of the first dielectric layer 145 over the word line structure 120 is greater than the thickness T2 of the first dielectric layer 145 over the fill material 130 between the select gate structure 110 and the dummy word line 121. In some embodiments, the material of the first dielectric layer 145 can include oxide, such as tetraethyl orthosilicate (TEOS) or silane.

[0045] Referring nextFigure 7 and Figure 8 The back-etching process 150 is performed to etch the first dielectric layer 145 and the cap layer 140, and expose the fill material 130 between the select gate structure 110 and the dummy word line 121. More specifically, as shown in Figure 7 the back-etching process 150 first removes a portion of the first dielectric layer 145. Due to the thickness difference of the first dielectric layer 145, the first dielectric layer 145 above the fill material 130 between the select gate structure 110 and the dummy word line 121 is almost completely removed, while a certain thickness of the first dielectric layer 145 above the word line structure 120 remains. Then, as shown in Figure 8 the back-etching process 150 further removes the first dielectric layer 145 and the cap layer 140 above the fill material 130 between the select gate structure 110 and the dummy word line 121, and exposes the top surface of the fill material 130 there. As shown in Figure 8 the back-etching process 150, the first dielectric layer 145 above the word line structure 120 remains. In other words, after the back-etching process 150, the fill material 130 between the select gate structure 110 and the dummy word line 121 is exposed, while the fill material 130 between the word line structures 120 is still covered by the cap layer 140 and the first dielectric layer 145. In addition, it is worth noting that although the back-etching process 150 removes the first dielectric layer 145 and the cap layer 140 above the fill material 130 between the select gate structure 110 and the dummy word line 121, the cap layer 140 and the first dielectric layer 145 still remain on both sides of the select gate structure 110 and on the side of the dummy word line 121 facing the select gate structure 110 due to the structural difference. In some embodiments, the back-etching process 150 can include an anisotropic etching process (or a directional etching process), such as a dry etching process.

[0046] Referring to Figure 9. The filling material 130 is removed so that no filling material 130 exists between the word line structures 120. In some embodiments, protrusions 142 of the capping layer 140 remain on both sides of the selection gate structure 110 and on the side of the dummy word line 121 facing the selection gate structure 110. That is, due to the difference in thickness of the first dielectric layer 145, the capping layer 140 on both sides of the selection gate structure 110 and on the side of the dummy word line 121 facing the selection gate structure 110 is not completely removed by the back etching process 150, and becomes a protrusion 142 after the filling material 130 is removed. In some embodiments, the filling material 130 can be removed by a wet etching process or an ashing process. In some embodiments, the capping layer 140 still covers the top surface and a portion of the sidewall of each word line structure 120 to form a hat-shaped structure. In some embodiments, the cap-shaped structures above each word line structure 120 are connected to each other. In some embodiments, a ratio of a protrusion distance D3 of the protrusion 142 of the capping layer 140 to a distance D1 between the select gate structure 110 and the dummy word line 121 ranges from 0.1 to 0.25.

[0047] See later Figure 10 . A second dielectric layer 155 is formed to fill between the select gate structure 110 and the dummy word line 121 and to cover the first dielectric layer 145 and the cap layer 140 above the word line structure 120. A first air gap 160 is provided between the word line structures 120, and the first air gap 160 is separated from the second dielectric layer 155 by the cap layer 140 and the first dielectric layer 145. In other words, the filling material 130 reserves space for the first air gap 160, and the first air gap 160 is formed after the filling material 130 is removed and the second dielectric layer 155 is formed. In this way, the size of the first air gap 160 can be ensured so that the first air gap 160 does not form a spindle shape, but maintains its original shape between the word line structures 120. In some embodiments, the width W of the first air gap 160 is equal to the spacing D2 between the word line structures. Furthermore, in some embodiments, the second dielectric layer 155 further forms a second air gap 165 between the select gate structure 110 and the dummy word line 121, and the first air gap 160 is larger than the second air gap 165. Thus, the overall structure of the memory device 10 is ensured to be secure against the impact of an excessively large second air gap 165 on its structural strength. In some embodiments, the material of the second dielectric layer 155 may include an oxide, such as tetraethoxysilane (TEOS) or monosilane.

[0048] After forming the second dielectric layer 155 , other semiconductor processes may be performed to form various components and elements of the memory device 10 (eg, a flash memory), such as various components and elements of a NAND flash memory, which will not be further described here.

[0049] In summary, by forming the filling material and the cap layer, the air gap size between the word line structures can be effectively maintained, and the air gap between the select gate structure and the word line structure can be minimized, the strength of the structure is maintained, and the yield of the memory device is maintained. In addition, the cap layer of the cap structure formed on the word line structure also helps to strengthen the structural stability of the word line structure.

[0050] Although the present application has been disclosed with the foregoing embodiments, it is not intended to limit the present application. Those skilled in the art to which the present application pertains can make some changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A method of manufacturing a memory device, characterized by, Comprising: providing a substrate; forming a select gate structure and a plurality of word line structures on the substrate; forming a fill material to cover the select gate structure and the word line structures and fill in between the select gate structure and the word line structures; etching back the fill material to expose top of the select gate structure and top of the word line structures; sequentially forming a cap layer and a first dielectric layer over the substrate; etching back the first dielectric layer and the cap layer to expose the fill material between the select gate structure and a dummy word line of the word line structures closest to the select gate structure; removing the fill material, wherein both sides of the select gate structure and a side of the dummy word line toward the select gate structure remain a protrusion of the cap layer; and forming a second dielectric layer to fill in between the select gate structure and the dummy word line and cover the first dielectric layer over the word line structures.

2. The method of manufacturing a memory device according to claim 1, wherein The word line structures have a first air gap therebetween, and the first air gap is separated by the cap layer and the first dielectric layer and the second dielectric layer.

3. The method of manufacturing a memory device according to claim 2, wherein, The second dielectric layer has a second air gap between the select gate structure and the dummy word line, and the first air gap is greater than the second air gap.

4. The method of fabricating a memory device of claim 1, wherein, The fill material is spin-on-carbon or photoresist.

5. The method of fabricating a memory device of claim 1, wherein, The cap layer and the first dielectric layer are conformally formed on the substrate, and the cap layer is formed by a process with better step coverage and the first dielectric layer is formed by a process with worse step coverage.

6. The method of fabricating a memory device of claim 5, wherein, The first dielectric layer has a thickness over the word line structures greater than a thickness of the first dielectric layer over the fill material between the select gate structure and the dummy word line.

7. The method of fabricating a memory device according to claim 1, wherein The cap layer covers a top surface and a portion of a sidewall of each word line structure to form a hat-shaped structure over each word line structure.

8. The method of fabricating a memory device according to claim 7, wherein, The hat-shaped structures over each word line structure are connected to each other.

9. A memory device, comprising: Comprising: a substrate; a select gate structure disposed on the substrate; a plurality of word line structures disposed on the substrate and adjacent to the select gate structure; a cap layer overlying the select gate structure and each word line structure; and a dielectric layer filling in between the select gate structure and a dummy word line of the word line structures closest to the select gate structure and covering the word line structures, wherein both sides of the select gate structure and a side of the dummy word line toward the select gate structure have a protrusion of the cap layer. The word line structures have a first air gap therebetween, and the first air gap is separated by the cap layer and the dielectric layer.

10. The memory device of claim 9, wherein, The dielectric layer has a second air gap between the select gate structure and the dummy word line, and the first air gap is greater than the second air gap.

11. The memory device of claim 10, wherein, The cap layer covers a top surface and a portion of a sidewall of each word line structure to form a hat-shaped structure over each word line structure.

12. The memory device of claim 9, wherein, The hat-shaped structures over each word line structure are connected to each other.

13. The memory device of claim 12, wherein, The cap layer comprises nitride.

14. The memory device of claim 9, wherein, ​

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