Semiconductor structure and preparation method thereof, three-dimensional memory and storage system

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a three-dimensional memory and a memory system, relates to the technical field of semiconductor chips, and aims to solve the problem that a gate layer is bent. The semiconductor structure includes a stacked structure, a first barrier layer, and a conductive structure. The stacked structure comprises a plurality of gate layers which are arranged in a stacked mode, and the gate layers are distributed at intervals; the stacked structure has a core region and a connection region. The first barrier layer is disposed on the stacked structure. The conductive structure is located in the connecting region; the conductive structure penetrates through the first barrier layer and penetrates through the part, close to the first barrier layer, of the stacked structure; and one end, far away from the first barrier layer, of the conductive structure is in contact with one gate layer. The semiconductor structure is applied to the three-dimensional memory.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a semiconductor structure, a preparation method thereof, a three-dimensional memory and a storage system. BACKGROUND

[0002] Planar semiconductor devices (e.g., memory) are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of semiconductor devices approaches the lower limit, planar processes and manufacturing technologies become challenging and costly. 3D semiconductor device architectures can solve some density limitations in planar semiconductor devices, such as flash memory devices.

[0003] 3D semiconductor devices can be formed by stacking semiconductor wafers or dies and interconnecting them vertically, which have smaller sizes, higher densities, and performance improvements compared to conventional planar semiconductor devices. SUMMARY

[0004] In one aspect, a semiconductor structure is provided. The semiconductor structure includes a stack structure, a first barrier layer, and a conductive structure. The stack structure includes a plurality of gate layers arranged in a stack, the plurality of gate layers being spaced apart; the stack structure has a core region and a connection region. The first barrier layer is disposed on the stack structure. The conductive structure is located in the connection region; the conductive structure penetrates the first barrier layer and a portion of the stack structure close to the first barrier layer; an end of the conductive structure away from the first barrier layer is in contact with one of the gate layers.

[0005] In some embodiments, the semiconductor structure further includes an isolation structure. The isolation structure penetrates the stack structure; a portion of the isolation structure is located in the core region, and another portion is located in the connection region. The first barrier layer covers the isolation structure.

[0006] In some embodiments, the conductive structure includes a first conductive part and a second conductive part. The first conductive part penetrates the first barrier layer. The second conductive part penetrates the portion of the stack structure close to the first barrier layer. The second conductive part is connected to the first conductive part; the first conductive part and the second conductive part are annular; an outer diameter of an end of the first conductive part close to the second conductive part is smaller than an outer diameter of an end of the second conductive part close to the first conductive part.

[0007] In some embodiments, an outer diameter of an end of the first conductive part away from the second conductive part is greater than the outer diameter of the end of the first conductive part close to the second conductive part.

[0008] In some embodiments, the outer diameter of the first conductive part gradually decreases in a direction close to the second conductive part.

[0009] In some embodiments, the conductive structure further comprises a contact portion. The contact portion is located on a side of the second conductive portion distal to the first conductive portion, and is in contact with the second conductive portion. Among them, the gate layer in the multi-layer gate structure which is in contact with the conductive structure is arranged in the same layer as the contact portion, and is in contact with the contact portion.

[0010] In some embodiments, the conductive structure further comprises a plug portion. The plug portion is in contact with an end of the first conductive portion distal to the second conductive portion.

[0011] In some embodiments, the conductive structure further comprises a filling portion. The first conductive portion and the second conductive portion surround the filling portion. Among them, in the case that the conductive structure further comprises a contact portion, the filling portion is also located on a side of the contact portion proximal to the second conductive portion. In the case that the conductive structure further comprises a plug portion, the filling portion is also located on a side of the plug portion proximal to the second conductive portion.

[0012] In some embodiments, the filling portion has an air gap inside.

[0013] In some embodiments, the semiconductor structure further comprises a first dielectric layer. The first dielectric layer is located between the stack structure and the first barrier layer, and the conductive structure penetrates the first dielectric layer. In the case that the semiconductor structure further comprises an isolation structure, the first dielectric layer covers the isolation structure. In the case that the conductive structure comprises a first conductive portion, the first conductive portion penetrates the first dielectric layer.

[0014] On the other hand, a method for manufacturing a semiconductor structure is provided, which comprises: forming a stack structure; forming a first barrier layer on the stack structure; and forming a conductive structure in a connection region. The stack structure comprises a plurality of gate layers arranged in layers, and the plurality of gate layers are distributed at intervals; the stack structure has a core region and a connection region. The conductive structure penetrates the first barrier layer and penetrates a portion of the stack structure proximal to the first barrier layer; an end of the conductive structure distal to the first barrier layer is in contact with a gate layer.

[0015] In some embodiments, the stack structure is formed by: forming an initial stack structure; the initial stack structure comprises a plurality of gate sacrificial layers arranged in layers, and the plurality of gate sacrificial layers are distributed at intervals.

[0016] Forming the conductive structure in the connection region includes: forming a first contact hole on the initial stack structure, and filling a first sacrificial material in the first contact hole; the first contact hole penetrates through a portion of the initial stack structure to a layer of gate sacrificial layers in the plurality of gate sacrificial layers; wherein the first barrier layer also covers the first sacrificial material; forming a second contact hole on the first barrier layer to expose the first sacrificial material; removing the first sacrificial material through the second contact hole; and depositing a conductive material in the first contact hole and the second contact hole to form a first initial conductive layer; a portion of the first initial conductive layer located in the second contact hole constitutes a first conductive part, and a portion of the first initial conductive layer located in the first contact hole constitutes a second conductive part and a contact part; the contact part is located on a side of the second conductive part away from the first conductive part. Among them, the gate layer in the plurality of gate layers which contacts the conductive structure is arranged in the same layer as the contact part and contacts the contact part.

[0017] In some embodiments, the aperture of the second contact hole at the end close to the first contact hole is smaller than the aperture of the first contact hole at the end close to the second contact hole.

[0018] In some embodiments, the aperture of the second contact hole at the end away from the first contact hole is larger than the aperture of the second contact hole at the end close to the first contact hole.

[0019] In some embodiments, the cross section of the second contact hole perpendicular to the gate layer includes an inverted trapezoidal cross section.

[0020] In some embodiments, forming the conductive structure in the connection region further includes: depositing an insulating material on the first initial conductive layer and in the first contact hole and the second contact hole to form an initial filling layer; a portion of the initial filling layer located in the first contact hole and the second contact hole constitutes a filling part.

[0021] In some embodiments, forming the conductive structure in the connection region further includes: removing a portion of the initial filling layer located on a side of the first initial conductive layer away from the stack structure and retaining the filling part; and removing a portion of the first initial conductive layer located on the first barrier layer and retaining the first conductive part, the second conductive part, and the contact part.

[0022] In some embodiments, the method for manufacturing the semiconductor structure further includes: thinning a portion of the filling layer located in the second contact hole to expose a portion of the first conductive part; forming a second initial conductive layer on a side of the first initial conductive layer away from the first barrier layer and on a side of the filling part away from the contact part, a portion of the second initial conductive layer located in the second contact hole constitutes a plug part; and removing a portion of the second initial conductive layer located on the first initial conductive layer and retaining the plug part.

[0023] In some embodiments, the method for preparing the semiconductor structure further comprises: forming an isolation structure in the core region and the connection region; the isolation structure penetrates through the stack structure; the first barrier layer covers the isolation structure;

[0024] The forming of the isolation structure comprises: forming an initial isolation structure; the isolation structure penetrates through the initial stack structure; removing the initial isolation structure to form a gate line slot; via the gate line slot, removing portions of the multilayer gate sacrificial layer in the core region and portions of the multilayer gate sacrificial layer in the connection region and close to the initial isolation structure to form a plurality of first gate line gaps; and forming the multilayer gate electrode layer in the plurality of first gate line gaps.

[0025] In some embodiments, among the multilayer gate electrode layer, the gate electrode layer in contact with the conductive structure is closer to the first contact hole than other gate electrode layers.

[0026] In some embodiments, the forming of the first contact hole and the filling of the first sacrificial material comprises: forming the first contact hole in the connection region; depositing an insulating material in the first contact hole and on the initial stack structure to form a second barrier layer; removing portions of the second barrier layer at the bottom of the first contact hole and exposing a layer of the gate sacrificial layer; removing portions of the exposed layer of the gate sacrificial layer via the bottom of the first contact hole to form a second gate line gap; filling the first contact hole and the second gate line gap with a second sacrificial material, the second sacrificial material being different from the material of the gate sacrificial layer; removing the second sacrificial material in the first contact hole and retaining the second sacrificial material in the second gate line gap; and filling the first contact hole with the first sacrificial material. In the process of removing portions of the gate sacrificial layer via the gate line slot, the second sacrificial material is removed.

[0027] In some embodiments, the method for preparing the semiconductor structure further comprises: forming a first dielectric layer; in the process of forming the second contact hole, the second contact hole also penetrates through the first dielectric layer. In the case that the method for preparing further comprises forming the isolation structure, the first dielectric layer covers the isolation structure.

[0028] In another aspect, a three-dimensional memory is provided. The three-dimensional memory comprises a peripheral device and the semiconductor structure as described above. The peripheral device is electrically connected with the semiconductor structure.

[0029] In yet another aspect, a storage system is provided. The storage system comprises a controller and the three-dimensional memory as described above. The controller is coupled with the three-dimensional memory to control the three-dimensional memory to store data. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description only represent some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, etc. of the product involved in the embodiments of the present disclosure.

[0031] Figure 1 A cross-sectional structure diagram of a semiconductor structure according to some embodiments;

[0032] Figure 2 Another cross-sectional structure diagram of a semiconductor structure according to some embodiments;

[0033] Figure 3 Yet another cross-sectional structure diagram of a semiconductor structure according to some embodiments;

[0034] Figure 4 Still another cross-sectional structure diagram of a semiconductor structure according to some embodiments;

[0035] Figure 5 Yet another cross-sectional structure diagram of a semiconductor structure according to some embodiments;

[0036] Figure 6 Still another cross-sectional structure diagram of a semiconductor structure according to some embodiments;

[0037] Figure 7A An equivalent circuit diagram of a memory cell string in a semiconductor structure according to some embodiments;

[0038] Figure 7B A structure diagram of a semiconductor structure according to some embodiments;

[0039] Figure 8 A structure diagram of a three-dimensional memory according to some embodiments;

[0040] Figure 9A A structure diagram of a memory system according to some embodiments;

[0041] Figure 9B Another structure diagram of a memory system according to some embodiments;

[0042] Figure 10 A structure diagram of an electronic device according to some embodiments;

[0043] Figure 11A flow chart of a method for fabricating a semiconductor structure according to some embodiments;

[0044] Figure 12A A cross-sectional view corresponding to step S1.1 or U1 in a method for fabricating a semiconductor structure according to some embodiments;

[0045] Figure 12B A cross-sectional view corresponding to step S3.1.1 in a method for fabricating a semiconductor structure according to some embodiments;

[0046] Figure 12C A cross-sectional view corresponding to step S3.1.2 in a method for fabricating a semiconductor structure according to some embodiments;

[0047] Figure 12D A cross-sectional view corresponding to step S3.1.3 in a method for fabricating a semiconductor structure according to some embodiments;

[0048] Figure 12E A cross-sectional view corresponding to step S3.1.4 in a method for fabricating a semiconductor structure according to some embodiments;

[0049] Figure 12F A cross-sectional view corresponding to step S3.1.5 in a method for fabricating a semiconductor structure according to some embodiments;

[0050] Figure 12G A cross-sectional view corresponding to step S3.1.6 in a method for fabricating a semiconductor structure according to some embodiments;

[0051] Figure 12H A cross-sectional view corresponding to step S3.1.7 in a method for fabricating a semiconductor structure according to some embodiments;

[0052] Figure 12I A cross-sectional view corresponding to step U1A in a method for fabricating a semiconductor structure according to some embodiments;

[0053] Figure 12J A cross-sectional view corresponding to step S1.2 or U2-U3 in a method for fabricating a semiconductor structure according to some embodiments;

[0054] Figure 12K A cross-sectional view corresponding to step U4-U5 in a method for fabricating a semiconductor structure according to some embodiments;

[0055] Figure 12L A cross-sectional view corresponding to step S2A in a method for fabricating a semiconductor structure according to some embodiments;

[0056] Figure 12M A cross-sectional view corresponding to step S2B in the method of fabricating a semiconductor structure according to some embodiments;

[0057] Figure 12N A cross-sectional view corresponding to step S2 in the method of fabricating a semiconductor structure according to some embodiments;

[0058] Figure 12O A cross-sectional view corresponding to step S3.2 in the method of fabricating a semiconductor structure according to some embodiments;

[0059] Figure 12P A cross-sectional view corresponding to step S3.2 in the method of fabricating a semiconductor structure according to some embodiments;

[0060] Figure 12Q A cross-sectional view corresponding to step S1.2 or S3.3-S3.4 in the method of fabricating a semiconductor structure according to some embodiments;

[0061] Figure 12R A cross-sectional view corresponding to step S3.5 in the method of fabricating a semiconductor structure according to some embodiments;

[0062] Figure 12S A cross-sectional view corresponding to step S3.6 in the method of fabricating a semiconductor structure according to some embodiments;

[0063] Figure 12T A cross-sectional view corresponding to step S3.7 in the method of fabricating a semiconductor structure according to some embodiments;

[0064] Figure 12U A cross-sectional view corresponding to steps R1-R2 in the method of fabricating a semiconductor structure according to some embodiments;

[0065] Figure 12V A cross-sectional view corresponding to step R3 in the method of fabricating a semiconductor structure according to some embodiments;

[0066] Figure 12W A cross-sectional view corresponding to step S3.7 in the method of fabricating a semiconductor structure according to some embodiments. DETAILED DESCRIPTION

[0067] In the following, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0068] In the description of the present disclosure, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only intended to facilitate the description of the present disclosure and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0069] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise", "comprising", and the like are to be construed in an open, inclusive and a non-exclusive sense, that is as "comprising, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplary embodiments" or "some examples" are intended to mean that a particular feature, structure, material, or characteristic included in the embodiment or example is included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0070] In the following, the terms "first", "second" are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "multiple" is two or more.

[0071] In describing some embodiments, "coupled" and "connected", and their derivatives, can be used. For example, the term "connected" can be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. For another example, the term "coupled" can be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. However, the term "coupled" can also mean that two or more components have no direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited by the content herein.

[0072] “A, B, and C at least one of” has the same meaning as “at least one of A, B, or C,” including the following combinations: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0073] “A and / or B” means that the following three combinations are included: A only, B only, and a combination of A and B.

[0074] The use of “adapted to” or “configured to” herein means an open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0075] Additionally, the use of “based on” means open and inclusive, as a process, step, calculation, or other action that is “based on” one or more recited conditions or values can in practice be based on additional conditions or values beyond those recited.

[0076] As used herein, “about,” “approximately,” or “around” includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0077] In the present disclosure, the meaning of “on,” “over,” and “above” should be interpreted in the broadest context, such that “on” means not only “directly on” but also includes the meaning of “on” with intervening features or layers therebetween, and “over” or “above” means not only “over” or “above” but also includes the meaning of “over” or “above” with no intervening features or layers therebetween (i.e., directly on).

[0078] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0079] The term “three-dimensional memory” refers to a semiconductor device formed with memory cell transistor strings (referred to herein as “memory cell strings”, e.g., NAND memory cell strings) arranged in an array on a major surface of a substrate or source layer and extending in a direction perpendicular to the major surface (i.e., lateral surface) of the substrate or source layer. As used herein, the term “perpendicular / vertically” means nominally perpendicular to the major surface of the substrate or source layer.

[0080] It is noted that the notation “A / B” appearing in the figures means that structure / region A and structure / region B can be referred to with the same structure / region, e.g., Figure 3 In the middle “H0 / H1” means that both the word line contact hole H0 and the first contact hole H1 can be referred to with this structure.

[0081] As used in the present disclosure, whether a component (e.g., a layer, structure, or device) is “on”, “above”, or “below” another component (e.g., a layer, structure, or device) is determined with respect to a substrate of the semiconductor device in a first direction X when the substrate is in a lowest plane of the semiconductor device. Throughout the present disclosure, the same concept is applied to describe spatial relationships.

[0082] Figure 1 And Figure 2 is a schematic diagram of one possible structure profile of the semiconductor structure 100 in some embodiments.

[0083] Referring to Figure 1 And Figure 2 , the semiconductor structure 100 includes a stack structure 110 and a conductive structure 120.

[0084] The stack structure 110 includes a plurality of gate layers 111 arranged in a stack, the plurality of gate layers 111 being spaced apart; in some examples, the stack structure 110 further includes dielectric layers 112 arranged in a stack alternately with the plurality of gate layers 111; the dielectric layers 112 can avoid short circuit between adjacent two gate layers 111, etc.

[0085] The stack structure 110 has a core region (not shown in the figure) and a connection region SS. The core region is arranged adjacent to the connection region SS. The core region can be used for storing data. The conductive structure 120 is located in the connection region SS and penetrates through a portion of the stack structure 110 close to a first side 110A; an end of the conductive structure 120 away from the first side 110A of the stack structure 110 is in contact with one gate layer 111.

[0086] In some embodiments, each gate layer 111 extends from the core region to the connection region SS. The portion of the gate layer 111 (i.e., word line) located in the connection region SS can be used for electrical connection with the conductive structure 120.

[0087] In this embodiment, the conductive structure 120 is located in the connection region SS and extends through the portion of the stack structure 110 close to the first side 110A, so that one end of the conductive structure 120 close to the first side 110A of the stack structure 110 can be connected with a word line contact (not shown in the figure), and the other end of the conductive structure 120 away from the first side 110A of the stack structure 110 can extend away from the first side 110A of the stack structure 110 and contact a gate layer 111, so as to realize the electrical connection between the gate layer 111 and the conductive structure 120 and between the conductive structure 120 and the word line contact.

[0088] In some embodiments, referring to Figure 2 , the conductive structure 120 further comprises a plug portion 124 arranged at one end of the conductive structure 120 close to the first side 110A of the stack structure 110. The plug portion 124 can increase the contact area when the conductive structure 120 is electrically connected with the word line contact, and reduce the difficulty of electrical connection between the conductive structure 120 and the word line contact.

[0089] In some implementations, the gate layer 111 is formed by a gate replacement process, and the gate layer 111 is formed before the conductive structure 120. As one possible implementation, the method for forming the gate layer 111 comprises the following steps: first, forming an initial stack structure, the initial stack structure comprising a plurality of layers of gate sacrificial layers (not shown in the figure) and a plurality of layers of dielectric layers 112 arranged alternately; then, removing the material of the plurality of layers of gate sacrificial layers to form a plurality of gate line gaps; then, filling the plurality of gate line gaps to form the gate layer 111; and finally, forming the conductive structure 120 in the connection region SS so that the conductive structure 120 is in electrical contact with one of the gate layers 111.

[0090] It is worth noting that in the above implementation, after the material of the plurality of layers of gate sacrificial layers is removed and before the plurality of gate line gaps are filled, the adjacent dielectric layers 112 are prone to collapse due to the existence of the plurality of gate line gaps, which causes the plurality of gate line gaps to bend. Thus, after the plurality of gate line gaps are filled to form the plurality of layers of gate layers 111, the plurality of layers of gate layers 111 formed will be bent, which is prone to leakage risk (LKG risk).

[0091] Based on the above, in some embodiments, before performing the gate replacement, a word line contact hole for setting the conductive structure 120 is formed, and a sacrificial material is filled in the word line contact hole. In this way, after the material of the multi-layer gate sacrificial layer is removed, and before the plurality of gate line gaps are filled, the sacrificial material in the word line contact hole can provide support for the multi-layer dielectric layer 112, and can prevent the gate line gap from being bent, so as to prevent the formed gate electrode layer 111 from being bent. In this case, after the gate electrode layer 111 is formed, the sacrificial material in the word line contact hole can be removed, and the material of the conductive structure 120 can be filled in the word line contact hole to form the conductive structure 120.

[0092] However, in some implementations, when the sacrificial material in the word line contact hole is removed, other structures of the semiconductor structure 100 (for example, other structures located in the core region and / or the connection region SS and penetrating the stack structure 110) can be affected.

[0093] For example, in some embodiments, the semiconductor structure 100 further includes an isolation structure 130. The isolation structure 130 can be formed by filling a gate line gap. Here, a part of the gate line gap can be located in the core region, and another part of the gate line gap can be located in the connection region SS. The gate line gap can be configured to form the gate line gap via the gate line gap in the process of forming the gate line gap. In this case, when the sacrificial material in the word line contact hole is removed, the isolation structure 130 can be affected.

[0094] Based on this, some embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof, a three-dimensional memory, and a storage system to overcome one or more of the above problems. The semiconductor structure and the preparation method thereof, the three-dimensional memory, and the storage system provided by some embodiments of the present disclosure are introduced respectively as follows.

[0095] Figures 3-6 A possible structure cross-sectional view of the semiconductor structure 200 in some embodiments. Figure 7A An equivalent circuit diagram of a memory cell string in the semiconductor structure 200 in some embodiments. Figure 7B A top view structure diagram of the semiconductor structure according to some embodiments, the top view direction is along the stacking direction X of the stack structure 210.

[0096] Reference Figures 3-6The semiconductor structure 200 includes a stack structure 210, a first barrier layer 240, and a conductive structure 220. The stack structure 210 includes a plurality of gate layers 211 arranged in a stack and spaced apart from each other. The stack structure 210 has a core region AA and a connection region SS. The first barrier layer 240 is disposed on the stack structure 210. The conductive structure 220 is located in the connection region SS. The conductive structure 220 penetrates the first barrier layer 240 and a portion of the stack structure 210 close to the first barrier layer 240. An end of the conductive structure 220 away from the first barrier layer 240 is in contact with one of the gate layers 211.

[0097] In some embodiments, the core region AA and the connection region SS can be multiple in number. The core region AA can be disposed between two connection regions SS, and multiple core regions AA can be spaced apart from multiple connection regions SS.

[0098] Here, the plurality of gate layers 211 are arranged in a stack and spaced apart from each other. Each of the gate layers 211 extends from the core region AA to the connection region SS, so that the core region AA and the connection region SS can be electrically connected through each of the gate layers 211. In this way, the conductive structure 220 and the gate layer 211 in the connection region SS are electrically connected, so that the operations of writing, reading, and erasing data can be implemented.

[0099] As a possible implementation manner, in the case that the conductive structure 220 is in electrical contact with the gate layer 211, an end of the conductive structure 220 close to the first barrier layer 240 can be in electrical contact with a word line contact (not shown in the figure), and a word line connection line (not shown in the figure) can be in electrical contact with the word line contact, so that an electrical signal can be transmitted between the word line connection line and the gate layer 211.

[0100] In some embodiments, referring to Figure 3 and Figure 4 , the electrical contact between the gate layer 211 and the word line contact is implemented through a self-align contact (SCT) architecture. The SCT architecture is to embed the conductive structure 220 in the connection region SS, and to lead out the gate layer 211 (i.e., a word line) through the conductive structure 220 to implement the electrical connection between the gate layer 211 and the word line contact, instead of forming a stepped structure.

[0101] It should be understood that, when the electrical contact between the gate layer 211 and the word line contact is implemented through the SCT architecture, compared with the case that the stepped structure is disposed in the connection region SS, the problem of difficult alignment between the word line contact hole H0 and the stepped structure can be avoided, so that the manufacturing process of the semiconductor structure 200 can be simplified, and the production cost can be reduced.

[0102] The following will exemplarily introduce the way of storing data by the core region AA and the way of writing, reading and erasing data and other operations by the gate layer 211.

[0103] In some examples, referring to Figure 5 and Figure 6 , the semiconductor structure 200 further comprises a plurality of (for example, arrayed) channel structures 250 located in the core region AA, the channel structures 250 penetrating the stack structure 210 along the stacking direction X of the stack structure 210. The channel structures 250 can be used for storing data, so that the core region AA can realize the storage function.

[0104] In some embodiments, referring to Figure 5 and Figure 6 , the channel structure 250 at least comprises a storage function layer 251 and a channel layer 252 successively away from the multilayer gate layer 211. Among them, the storage function layer 251 is used for storing data. In some embodiments, the storage function layer 251 comprises a charge blocking layer 253, a charge trapping layer 254 and a tunneling layer 255 successively away from the multilayer gate layer 211. The charge trapping layer 254 is used for storing charges; the charge blocking layer 253 is used for blocking the charges stored in the charge trapping layer 254 and providing electrical insulation between the charge trapping layer 254 and the gate layer 211; the tunneling layer 255 is used for generating charges (electrons or holes). The channel layer 252 is used for transporting the required charges.

[0105] Exemplarily, the material of the charge blocking layer 253 includes but is not limited to silicon oxide; the material of the charge trapping layer 254 includes but is not limited to silicon nitride, and the material of the tunneling layer 255 includes but is not limited to silicon oxide. The material of the channel layer 252 includes but is not limited to doped polysilicon.

[0106] In some embodiments, referring to Figure 5 and Figure 6 , the channel structure 250 can further comprise a channel filling medium 256, which is filled in the accommodation space formed by the channel layer 252 and plays a role in supporting the channel structure 250. Exemplarily, the material of the channel filling medium 256 can include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (such as aluminum oxide, hafnium dioxide, etc.) and silicate thereof, and organic insulating material. In some embodiments, the channel filling medium 256 filled in the channel structure 250 can also include air gap to reduce structural stress.

[0107] In some embodiments, referring to Figure 6 and Figure 7A , the channel structure 250 and the multilayer gate layer 211 corresponding thereto can form a plurality of transistors T, one transistor T (for example Figure 7AThe transistors T (e.g., T1-T6) in the memory cell can be configured as one memory cell, and the transistors T are connected together to form a memory cell string (e.g., a NAND memory cell string). One transistor T (e.g., each transistor T) can be formed by a channel structure 250 and a gate layer 211 (i.e., a word line WL) surrounding the channel structure 250. The gate layer 211 is configured to control the on-off state of the transistor T.

[0108] It should be noted that, Figure 7A The number of transistors T in the memory cell is only illustrative, and the semiconductor structure 200 provided by the embodiments of the present disclosure can also include other numbers of transistors, such as 4, 16, 32, 64.

[0109] For example, along the stacking direction X of the stack structure 210, the lowermost gate layer 211 (e.g., the gate layer 211 closest to the source layer) in the multi-layer gate layer 211 is configured as a source side select gate SGS, which is configured to control the on-off state of the transistor T6, and further control the on-off state of the source side channel in the memory cell string. The uppermost gate line (e.g., the gate layer 211 farthest from the source layer) in the multi-layer gate layer 211 is configured as a drain side select gate SGD, which is configured to control the on-off state of the transistor T1, and further control the on-off state of the drain side channel in the memory cell string. The gate layers 211 in the middle of the multi-layer gate layer 211 can be configured as a plurality of word lines WL, such as the word line WL0, the word line WL1, the word line WL2, and the word line WL3. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (e.g., transistor T) in the memory cell string can be achieved.

[0110] It should be understood that, in the case where the stack structure 210 includes the multi-layer gate layer 211, the number of conductive structures 220, and the number of word line contacts can also be multiple, and correspondingly, the number of word line connection lines can also be multiple. In this way, when one conductive structure 220 is in contact with one gate layer 211, the word line connection line electrically connected to the conductive structure 220 through the word line contact can be electrically connected to the corresponding gate layer 211. In this way, the corresponding electrical connection between the plurality of word line connection lines and the multi-layer gate layer 211 can be achieved to achieve data writing, reading, and erasing of the plurality of memory cells (e.g., transistors T).

[0111] In some embodiments, the material of the gate layer 211 includes at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicide. The material and thickness of each gate layer 211 can be the same or different.

[0112] In some embodiments, referring to Figures 3-6The stack structure 210 further includes a plurality of dielectric layers 212 which are alternately stacked with the gate layers 211. In this case, the conductive structure 220 penetrates not only the gate layers 211 close to the first barrier layer 240, but also the dielectric layers 212 close to the first barrier layer 240.

[0113] Here, the alternately stacked refers to that the plurality of dielectric layers 212 and the plurality of gate layers 211 are stacked in the stacking direction X of the stack structure 210, and the arrangement is in an alternating manner; for example, in the direction from the bottom layer to the top layer of the stack structure 210, a dielectric layer 212 is first arranged, then a gate layer 211 is arranged on the dielectric layer 212, and then a dielectric layer 212 is arranged on the gate layer 211, and so on, to form the stack structure 210. In some embodiments, by the above-mentioned manner, the number of stacked layers of the stack structure 210 can be 4, 16, 32, 64 or 128, and the number of stacked layers of the stack structure 210 is not limited by the embodiments of the present disclosure.

[0114] Each dielectric layer 212 extends from the core region AA to the connection region SS. As described above, the dielectric layer 212 can play an insulating role and can improve the reliability of the semiconductor structure 200.

[0115] Here, the thickness of the dielectric layer 212 can be the same as or different from that of the gate layer 211.

[0116] Exemplarily, the material of the dielectric layer 212 can include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (such as aluminum oxide, hafnium dioxide, etc.) and silicate thereof, and organic insulating material.

[0117] Exemplarily, the material of the first barrier layer 240 includes but is not limited to silicon oxide.

[0118] In some examples, referring to Figure 7B The semiconductor structure 200 further includes a plurality of virtual channel structures 250'. The plurality of virtual channel structures 250' are located in the connection region SS and penetrate the stack structure 210 (see Figure 5 ). In this way, the plurality of virtual channel structures 250' are arranged in the connection region SS and avoid the conductive structure 220, thereby playing a role of providing mechanical support for the semiconductor structure 200.

[0119] Exemplarily, the virtual channel structure 250' can be filled with at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (such as aluminum oxide, hafnium dioxide, etc.) and silicate thereof, and organic insulating material.

[0120] In the case where the semiconductor structure 200 includes a plurality of channel structures 250, a plurality of dummy channel structures 250’, and a plurality of conductive structures 220, the interface between the core area AA and the connection area SS is shown by the dashed line in FIG. 2B, for example. In this case, a plurality of channel structures 250 can be formed in the core area AA, and a plurality of dummy channel structures 250’ and a plurality of conductive structures 220 can be formed in the connection area SS. Exemplarily, the plurality of dummy channel structures 250’ can also be distributed in a portion of the core area AA close to the connection area SS, or across the core area AA and the connection area SS. In this case, the stack structure 210 can be divided into the core area AA and the connection area SS according to the plurality of channel structures 250 and the plurality of conductive structures 220. Figure 7B

[0121] It can be understood that, by the above arrangement, the word line contact hole H0 can be formed prior to the gate layer, and the risk of current leakage can be reduced. Moreover, when the first barrier layer 240 is arranged on the stack structure 210, the first barrier layer 240 can provide a barrier effect for other structures (e.g., the isolation structure 230 described in detail below) penetrating through the stack structure 210, so as to avoid the influence of the process of removing the sacrificial material in the word line contact hole H0 on the other structures penetrating through the stack structure 210.

[0122] Moreover, the conductive structure 220 penetrates through the first barrier layer 240 and a portion of the stack structure 210 close to the first barrier layer 240, and the conductive structure 220 is in contact with a layer of the gate layer 211, so that the conductive structure 220 can be used to lead out the gate layer 211 (i.e., the word line WL) to a side of the first barrier layer 240 away from the stack structure 210, and the electrical connection between the gate layer 211 and the word line contact can be achieved.

[0123] In some embodiments, referring to Figures 3-6 , the semiconductor structure 200 further includes an isolation structure 230. The isolation structure 230 penetrates through the stack structure 210; a portion of the isolation structure 230 is located in the core area AA, and another portion of the isolation structure 230 is located in the connection area SS. In this case, the first barrier layer 240 covers the isolation structure 230.

[0124] As described above, the isolation structure 230 can be formed by filling the gate line groove. In some embodiments, the isolation structure 230 can also be configured to separate the core area AA and the connection area SS, and / or divide the semiconductor structure 200 into a plurality of memory blocks.

[0125] A portion of the isolation structure 230 is located in the core area AA, and another portion of the isolation structure 230 is located in the connection area SS. As a possible implementation, referring to​Figure 7B The isolation structure 230 can include a first isolation structure 230a and a second isolation structure 230b. The first isolation structure 230a can be located in the core area AA and the connection area SS. The second isolation structure 230b can be located in the core area AA. The portion of the first isolation structure 230a passing through the core area AA can be configured to divide the portion of the stacked structure 210 corresponding to the core area AA into a plurality of memory blocks P. The second isolation structure 230b can pass through the memory block P to divide one memory block P into a plurality of (e.g., two) finger-shaped storage areas.

[0126] Exemplarily, referring to Figure 3 and Figure 4 The isolation structure 230 can include a second dielectric layer 231 and a third dielectric layer 232 arranged in sequence in a direction away from the multilayer gate layer 211. The material of the second dielectric layer 231 includes but is not limited to silicon oxide. The material of the third dielectric layer 232 includes but is not limited to silicon nitride. In some examples, the isolation structure 230 can further include a fourth dielectric layer 233 filled in the accommodation space formed by the third dielectric layer 232. The material of the fourth dielectric layer 233 includes but is not limited to a combination of one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0127] In some examples, referring to Figure 3 and Figure 4 The portion of the second dielectric layer 231 close to the gate layer 211 is arranged in the same layer as the gate layer 211; that is, the portion of the second dielectric layer 231 close to the gate layer 211 can be embedded in the gate line gap.

[0128] Understandably, when the first barrier layer 240 covers the isolation structure 230, and the sacrificial material in the word line contact hole H0 is removed to form the conductive structure 220, the first barrier layer 240 can provide a barrier effect for the isolation structure 230 to avoid the influence of the process of removing the sacrificial material in the word line contact hole H0 on the isolation structure 230.

[0129] In some embodiments, referring to Figures 3-6 The conductive structure 220 includes a first conductive part 221 and a second conductive part 222. The first conductive part 221 penetrates the first barrier layer 240. The second conductive part 222 penetrates the portion of the stacked structure 210 close to the first barrier layer 240. The second conductive part 222 is connected with the first conductive part 221; wherein the first conductive part 221 and the second conductive part 222 are annular; the outer diameter L1 of the end of the first conductive part 221 close to the second conductive part 222 is smaller than the outer diameter L2 of the end of the second conductive part close to the first conductive part.

[0130] It should be understood that, when the sacrificial material in the word line contact hole H0 is removed, a second contact hole H2 needs to be opened in the portion of the first barrier layer 240 that is directly opposite the sacrificial material, so as to expose the sacrificial material in the word line contact hole H0, thereby removing the sacrificial material in the word line contact hole H0. The process of removing the sacrificial material in the word line contact hole H0 is, for example, wet etching or dry etching.

[0131] In this case, the conductive material of the conductive structure 220 penetrates through the first barrier layer 240 in part, and penetrates through the portion of the stack structure 210 close to the first barrier layer 240 in part. The first conductive portion 221 includes the portion of the conductive material of the conductive structure 220 that penetrates through the first barrier layer 240. The second conductive portion 222 is the portion of the conductive material of the conductive structure 220 that penetrates through the portion of the stack structure 210 close to the first barrier layer 240. Moreover, by connecting the first conductive portion 221 and the second conductive portion 222, electrical contact between the first conductive portion 221 and the second conductive portion 222 can be achieved, so that an electrical signal can be transmitted between the first conductive portion 221 and the second conductive portion 222.

[0132] In some examples, referring to Figure 4 , the interface F between the first conductive portion 221 and the second conductive portion 222 is located in the same plane as the surface of the stack structure 210 close to the first barrier layer 240. That is, the conductive portion of the conductive structure 220 can be divided along the surface of the stack structure 210 close to the first barrier layer 240 to obtain the first conductive portion 221 that penetrates through the first barrier layer 240 and the second conductive portion 222 that penetrates through the portion of the stack structure 210 close to the first barrier layer 240. In this case, in the connecting portion (for example, the curved portion shown in Figure 4 due to the change in the outer diameter), the portion located on the side of the interface F close to the first barrier layer 240 belongs to the first conductive portion 221, and the portion located on the side of the interface F close to the stack structure 210 belongs to the second conductive portion 222.

[0133] It should be understood that, when the first barrier layer 240 is in contact with the stack structure 210, the interface F between the first conductive portion 221 and the second conductive portion 222 is the contact surface between the first barrier layer 240 and the stack structure 210.

[0134] In some embodiments, the first conductive portion 221 and the second conductive portion 222 can be an integrally formed structure, which improves the reliability of the electrical contact between the first conductive portion 221 and the second conductive portion 222.

[0135] For example, the material of the first conductive portion 221 and / or the second conductive portion 222 includes at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and a metal silicide. Here, the material of the first conductive portion 221, the second conductive portion 222, and the gate layer 211 can be the same or different.

[0136] In some examples, the thickness of the first conductive portion 221 and / or the second conductive portion 222 is the same as or substantially the same as the thickness of the gate layer 211.

[0137] It can be understood that, when the first conductive portion 221 and the second conductive portion 222 are annular, the conductive material used to form the conductive structure 220 can be less than when the first conductive portion 221 and the second conductive portion 222 are cylindrical, and cost can be saved. Moreover, when the outer diameter L1 of the end of the first conductive portion 221 close to the second conductive portion 222 is less than the outer diameter L2 of the end of the second conductive portion 222 close to the first conductive portion 221, the aperture of the second contact hole H2 is smaller relative to the word line contact hole H0; that is, a small hole is formed on the first barrier layer 240 to remove the sacrificial material in the word line contact hole H0, and thus, the conductive material used to form the second conductive portion 222 can be less than when the aperture of the word line contact hole H0 is the same as the aperture of the second contact hole H2, and cost can be saved.

[0138] In some embodiments, referring to Figures 3-6 , the outer diameter L3 of the end of the first conductive portion 221 away from the second conductive portion 222 is greater than the outer diameter L1 of the end of the first conductive portion 221 close to the second conductive portion 222.

[0139] By such an arrangement, the end of the first conductive portion 221 close to the second conductive portion 222 is a small-end, and the end of the first conductive portion 221 away from the second conductive portion 222 is a large-end; in this way, when the conductive structure 220 is formed, the material of the conductive structure 220 can more easily enter the second contact hole H2 and the word line contact hole H0, and the process feasibility when the conductive structure 220 is formed can be improved. Here, the material of the conductive structure 220 is, for example, the material (e.g., conductive material) of the first conductive portion 221 and the second conductive portion 222, and the material of the contact portion 223, the plug portion 224, and the filling portion 225 described in detail below.

[0140] In some embodiments, the outer sidewall of the first conductive portion 221 extends in a stepped manner or a wavy manner, etc. along the direction close to the second conductive portion 222; at this time, the outer diameter of the first conductive portion 221 changes in a stepped manner or a wavy manner along the direction close to the second conductive portion 222. In this case, the outer diameter of the first conductive portion 221 does not gradually decrease along the direction close to the second conductive portion 222. Correspondingly, the hole diameter of the second contact hole H2 does not gradually decrease along the direction close to the word line contact hole H0.

[0141] In some embodiments, referring to Figures 3-6 , the outer diameter of the first conductive portion 221 gradually decreases along the direction close to the second conductive portion 222.

[0142] It should be understood that, by so arranging, the hole diameter of the second contact hole H2 gradually decreases along the direction close to the word line contact hole H0; as one possible implementation, referring to Figures 3-6 , the second contact hole H2 is a reverse tapered hole.

[0143] It can be understood that, when the second contact hole H2 is a reverse tapered hole, on the one hand, the material of the conductive structure 220 is more likely to enter the word line contact hole H0 and the second contact hole H2; on the other hand, by so arranging, the height and taper of the second contact hole H2 can be adjusted, and thus the state of the material of the conductive structure 220 after entering the word line contact hole H0 and the second contact hole H2 can be adjusted; for example, the state of the material of the filling portion 225 described in detail below after entering the word line contact hole H0 and the second contact hole H2 can be adjusted, so that the filling portion 225 can seal the air gap that can exist inside it.

[0144] In some embodiments, referring to Figures 3-6 , the conductive structure 220 further includes a contact portion 223. The contact portion 223 is located on the side of the second conductive portion 222 away from the first conductive portion 221 and is connected with the second conductive portion 222. Among them, the gate layer 211 in the multi-layer gate layer 211 that contacts the conductive structure 220 is arranged in the same layer as the contact portion 223 and contacts the contact portion 223.

[0145] Here, the contact portion 223 is connected with the second conductive portion 222, which means that the contact portion 223 is electrically connected with the second conductive portion 222.

[0146] In some embodiments, referring to Figures 3-6 , the contact portion 223 can seal the opening formed by the end of the second conductive portion 222 away from the first conductive portion 221, so that the contact area between the second conductive portion 222 and the contact portion 223 can be increased, the contact resistance between the second conductive portion 222 and the contact portion 223 can be reduced, and the reliability of the electrical contact between the second conductive portion 222 and the contact portion 223 can be improved.

[0147] In this case, as one possible implementation, the first conductive part 221, the second conductive part 222, and the contact part 223 can be integrally formed, which improves the reliability of the electrical contact between the second conductive part 222 and the contact part 223.

[0148] It should be noted that, referring to Figure 3 , the size L7 of the contact part 223 along the stacking direction X of the stacking structure 210 can be the same as or different from the size L8 of the target gate layer 211X along the stacking direction X of the stacking structure 210, which is not limited here. Here, the target gate layer 211X is the gate layer 211 that is in contact with the conductive structure 220. For example, the size L7 of the contact part 223 along the stacking direction X of the stacking structure 210 can be greater than the size L8 of the target gate layer 211X along the stacking direction X of the stacking structure 210; for another example, the size L7 of the contact part 223 along the stacking direction X of the stacking structure 210 can be equal to the size L8 of the target gate layer 211X along the stacking direction X of the stacking structure 210; for yet another example, the size L7 of the contact part 223 along the stacking direction X of the stacking structure 210 can be less than the size L8 of the target gate layer 211X along the stacking direction X of the stacking structure 210.

[0149] For example, the material of the contact part 223 includes at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicide. Here, the material of the contact part 223 can be the same as or different from the material of the gate layer 211.

[0150] In some examples, the thickness of the contact part 223 is the same as or approximately the same as the thickness of one gate layer 211.

[0151] It can be understood that the gate layer 211 that is in contact with the conductive structure 220 is arranged in the same layer as the contact part 223, and when the contact part 223 is in contact with the contact part 223, the contact part 223 is the part of the conductive structure 220 that is in electrical contact with the part of the gate layer 211 in the connection region SS. Thus, the electrical signal can be transmitted between the gate layer 211 and the conductive structure 220. In this case, the electrical connection between the word line contact and the gate layer 211 can be realized through the first conductive part 221, the second conductive part 222, and the contact part 223 that are sequentially connected.

[0152] In some embodiments, referring to Figures 3-6 , the conductive structure 220 further includes a plug part 224. The plug part 224 is in contact with the end of the first conductive part 221 that is away from the second conductive part 222.

[0153] As a possible implementation, the end of the first conductive part 221 away from the second conductive part 222 encloses a plug opening, and the plug part 224 is disposed in the plug opening. At this time, the plug part 224 closes the end of the first conductive part 221 away from the second conductive part 222 by being embedded in the plug opening.

[0154] In this case, the plug opening can be a closed shape, such as a square, a circle, or an irregular polygon, etc. In other embodiments, the plug opening can also be an unclosed shape, such as a C shape, a U shape, or other unclosed irregular shapes, etc.

[0155] In some embodiments, referring to Figures 3-6 , the side of the plug part 224 away from the second conductive part 222 is flush or approximately flush with the side of the first conductive part 221 away from the second conductive part 222, so that the structural regularity of the semiconductor structure 200 can be improved, and the electrical contact of the word line contact with the plug part 224 and the first conductive part 221 can be facilitated.

[0156] For example, the material of the plug part 224 includes at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicide. Here, the material of the plug part 224 and the material of the gate layer 211 can be the same or different. The material of the plug part 224 and the material of the first conductive part 221 can be the same or different.

[0157] Here, the relationship between the thickness of the plug part 224 and the thickness of the first barrier layer 240 is not limited. For example, the thickness of the plug part 224 can be less than the thickness of the first barrier layer 240, at this time, the plug part 224 can be disposed in the opening enclosed by the first conductive part 221; that is, the plug part 224 can be disposed in the second contact hole H2; for another example, the thickness of the plug part 224 can be greater than the thickness of the first barrier layer 240, at this time, a part of the plug part 224 can be disposed in the opening enclosed by the first conductive part 221, and another part can be disposed in the opening enclosed by the second conductive part 222; that is, a part of the plug part 224 is disposed in the second contact hole H2, and another part can be disposed in the word line contact hole H0.

[0158] In some examples, the thickness of the plug part 224 is the same as or approximately the same as the thickness of a layer of the gate layer 211.

[0159] It can be understood that the plug portion 224 is in electrical contact with the end of the first conductive portion 221 away from the second conductive portion 222, so that the subsequently formed word line contact can be electrically connected to the gate layer 211 through at least one of the plug portion 224 and the first conductive portion 221. That is, the word line contact can be arranged to be in electrical contact with the end surface of the first conductive portion 221 away from the second conductive portion 222, or the surface of the plug portion 224 away from the stack structure 210, or both the end surface of the first conductive portion 221 away from the second conductive portion 222 and the surface of the plug portion 224 away from the stack structure 210.

[0160] In this way, the contact area between the subsequently formed word line contact and the gate layer 211 can be increased when they are electrically connected, and the landing window when the word line contact is electrically connected to the gate layer 211 can be larger, so as to reduce the difficulty of electrical connection between the word line contact and the gate layer 211. At the same time, the electrical resistance between the word line contact and the gate layer 211 can be smaller, so as to improve the reliability of electrical signal transmission.

[0161] In some embodiments, referring to Figures 3-6 The conductive structure 220 further includes a filling portion 225. The first conductive portion 221 and the second conductive portion 222 surround the filling portion 225. In the case where the conductive structure 220 further includes the contact portion 223, the filling portion 225 is also located on the side of the contact portion 223 close to the second conductive portion 222. In the case where the conductive structure 220 further includes the plug portion 224, the filling portion 225 is also located on the side of the plug portion 224 close to the second conductive portion 222.

[0162] For example, the material of the filling portion 225 can be an insulating material, which can include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxide (such as aluminum oxide, hafnium dioxide, etc.) and silicate thereof, and organic insulating material.

[0163] It can be understood that when the first conductive portion 221 and the second conductive portion 222 surround the filling portion 225, the filling portion 225 is filled in the accommodating cavity formed by the first conductive portion 221 and the second conductive portion 222, and in the case where the conductive structure 220 further includes the contact portion 223 and the plug portion 224, the accommodating cavity is a closed accommodating cavity. In this way, the filling portion 225 filled in the accommodating cavity can mechanically support the first conductive portion 221, the second conductive portion 222, and possibly the contact portion 223 and the plug portion 224, thereby improving the mechanical strength of the conductive structure 220 and the structural reliability of the semiconductor structure 200. Moreover, by arranging the conductive structure 220 to further include the filling portion 225, the use of conductive material can be reduced, and the production cost of the semiconductor structure 200 can be reduced.

[0164] In some embodiments, referring to Figures 3-6 , the inner portion of the filling portion 225 has an air gap 226.

[0165] Here, the number of the air gap 226 can be one or multiple, which is not limited here.

[0166] In some embodiments, the air gap 226 can be formed when filling the filling portion 225 with the material.

[0167] It can be understood that, by providing the air gap 226 in the inner portion of the filling portion 225, the structural stress can be reduced, and the reliability of the semiconductor structure 200 can be improved; and, as mentioned above, in the case that the inner portion of the filling portion 225 has the air gap 226 and the second contact hole H2 is a reverse tapered hole, the height and the taper of the second contact hole H2 can be adjusted, and thus the state of the material of the filling portion 225 entering the word line contact hole H0 and the second contact hole H2 can be adjusted, so that the filling portion 225 can seal the air gap 226.

[0168] In some embodiments, after the conductive structure 220 is formed, other contact structures (for example, a channel contact structure electrically connected to the channel structure 250) also need to be formed. In this way, when these contact structures are formed, the material of the first barrier layer 240 needs to be removed (for example, etched and removed). However, when the material of the first barrier layer 240 is silicon oxide or the like, after the material is removed, the interface formed will have fluctuations and be relatively uneven, which can affect the reliability of the contact structures after they are formed.

[0169] Based on the above, in some embodiments, referring to Figure 8 , the semiconductor structure 200 further includes a first dielectric layer 260. The first dielectric layer 260 is located between the stack structure 210 and the first barrier layer 240, and the conductive structure 220 penetrates the first dielectric layer 260. In the case that the semiconductor structure 200 further includes the isolation structure 230, the first dielectric layer 260 covers the isolation structure 230. In the case that the conductive structure 220 includes the first conductive portion 221, the first conductive portion 221 penetrates the first dielectric layer 260.

[0170] It should be understood that, in the case that the semiconductor structure 200 further includes the first dielectric layer 260, and the first dielectric layer 260 is in contact with the stack structure 210, the interface F between the first conductive portion 221 and the second conductive portion 222 is the contact surface between the first dielectric layer 260 and the stack structure 210.

[0171] Exemplarily, the material of the first dielectric layer 260 is, for example, a combination of one or more of silicon nitride and silicon oxynitride, and of course, can also be other suitable materials.

[0172] In some embodiments, the material of the first dielectric layer 260 is different from the material of the first blocking layer 240.

[0173] It should be appreciated that, in the case that the conductive structure 220 includes the first conductive portion 221, the first conductive portion 221 penetrates the first dielectric layer 260; that is, the second contact hole H2 penetrates the first dielectric layer 260, so that the second contact hole H2 can be connected to the sacrificial material that penetrates the stack structure 210 and is located in the word line contact hole H0.

[0174] It can be understood that, when the first dielectric layer 260 is arranged between the stack structure 210 and the first blocking layer 240, the difference in material properties (for example, the difference in etching ratio) between the first dielectric layer 260 and the first blocking layer 240 can be utilized to make the interface after the process of removing the first blocking layer 240 smoother and less fluctuant, so that the reliability of the subsequently formed contact structure can be improved.

[0175] Furthermore, when the first dielectric layer 260 is arranged between the stack structure 210 and the first blocking layer 240, the first dielectric layer 260 covers other structures (for example, the isolation structure 230 described in detail below) that penetrate the stack structure 210 in addition to the first blocking layer 240, so that the blocking effect of the first dielectric layer 260 and the first blocking layer 240 is stronger, and thus, compared with the case where the first dielectric layer 260 is not arranged, the blocking effect can be improved, and the influence of the process of removing the sacrificial material of the word line contact hole H0 on other structures that penetrate the stack structure 210 can be avoided.

[0176] Some embodiments of the present disclosure also provide a three-dimensional memory 300, which is described in detail with reference to Figure 8 , including a peripheral device 310 and the semiconductor structure 200 provided by any of the above embodiments. The peripheral device 310 is electrically connected to the semiconductor structure 200.

[0177] In some embodiments, the peripheral device 310 includes a peripheral circuit 311. The peripheral circuit 311 is configured to control and sense the semiconductor structure 200. The peripheral circuit 311 can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry for supporting the operation of the semiconductor structure 200, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) of the circuitry. The peripheral circuit 311 can also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., Programmable Logic Devices (PLDs), processors, and programmable logic devices) or memory circuitry (e.g., Static Random-Access Memory (SRAM)).

[0178] In some embodiments, referring to Figure 9A , the three-dimensional memory 300 further includes an array interconnect layer 320 disposed on a side of the semiconductor structure 200 proximate to the peripheral device 310, and the semiconductor structure 200 is electrically connected to the array interconnect layer 320. The peripheral device 310 further includes a peripheral interconnect layer 312 disposed on a side of the peripheral circuit 311 proximate to the semiconductor structure 200, and the peripheral circuit 311 is electrically connected to the peripheral interconnect layer 312. The semiconductor structure 200 and the peripheral circuit 311 are electrically connected through the array interconnect layer 320 and the peripheral interconnect layer 312.

[0179] Exemplarily, the array interconnect layer 320 and the peripheral interconnect layer 312 can achieve electrical connection in a manner of hybrid bonding. Here, hybrid bonding (also referred to as "metal / dielectric hybrid bonding") is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)) and can simultaneously obtain metal-metal bonding and dielectric-dielectric bonding.

[0180] It can be understood that the three-dimensional memory provided by the above embodiments of the present disclosure has the beneficial effects as described above for the semiconductor structure, which will not be repeated here.

[0181] Some embodiments of the present disclosure also provide a storage system 400. Referring to Figure 9B and Figure 9A , the storage system 400 includes a controller 410 and the three-dimensional memory 300 provided by any of the above embodiments. The controller 410 is coupled to the three-dimensional memory 300 to control the three-dimensional memory 300 to store data.

[0182] In some embodiments, referring toFigure 9B The memory system 400 includes a three-dimensional memory 300, and the memory system 400 can be integrated into a memory card.

[0183] The memory card includes, for example, any one of a PC card (Personal Computer Memory Card International Association, PCMCIA), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD) card, and a UFS.

[0184] The memory system 400 can be integrated into various types of memory devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the memory system 400 can be applied to and packaged into different types of electronic products, for example, a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a storage.

[0185] In some embodiments, the memory system 400 includes a three-dimensional memory 300, and the memory system 400 can be integrated into a memory card. Figure 10 The memory system 400 includes a controller 410 and a plurality of three-dimensional memories 300, and the memory system 400 can be integrated into a Solid State Drive (SSD).

[0186] In the memory system 400, in some embodiments, the controller 410 is configured to operate in a low duty cycle environment, for example, an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices for personal computers, digital cameras, mobile phones, etc.

[0187] In other embodiments, the controller 410 is configured for operating in a high duty cycle environment SSD or eMMC for data storage of mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays.

[0188] In some embodiments, the controller 410 can be configured to manage data stored in the semiconductor structure 200 and communicate with an external device (e.g., a host).

[0189] In some embodiments, the controller 410 can be further configured to control operations of the three-dimensional memory 300, such as read, erase, and program operations.

[0190] In some embodiments, the controller 410 can be further configured to manage various functions related to data stored or to be stored in the three-dimensional memory 300, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling.

[0191] In some embodiments, the controller 410 is further configured to process error correction codes related to data read from or written to the three-dimensional memory 300.

[0192] Of course, the controller 410 can also perform any other suitable functions, such as formatting the three-dimensional memory 300; for example, the controller 410 can communicate with an external device (e.g., a host) through at least one of various interface protocols.

[0193] It should be noted that the interface protocols include at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol.

[0194] It can be understood that the storage system provided by the above embodiments of the present disclosure has the beneficial effects as described above for the three-dimensional memory, which will not be repeated here.

[0195] Embodiments of the present disclosure also provide an electronic device 500, referring to Figure 10 The electronic device 500 includes the storage system 400.

[0196] The electronic device 500 includes, but is not limited to, any one of a mobile phone, a pad, a laptop, a television, a personal digital assistant (PDA), an ultra-mobile personal computer (UMPC), a netbook, a wearable device (for example, a smart watch, a smart bracelet, smart glasses), and the like. The type of the electronic device is not limited in the embodiments of the present application.

[0197] The electronic device can include the storage system 400 described above, and further include at least one of a central processing unit (CPU) and a cache.

[0198] In some embodiments, referring to Figure 11 , the electronic device 500 further includes a printed circuit board 510 coupled with the storage system 400.

[0199] It can be understood that the electronic device provided by the above embodiments of the present disclosure has the beneficial effects as described above for the storage system, which will not be described here again.

[0200] Figures 12A-12W A flowchart of a method for manufacturing the semiconductor structure 200 is provided for some embodiments of the present disclosure. Figure 11 A manufacturing process of the semiconductor structure 200 is provided for some embodiments of the present disclosure. The following will be described together Figures 12A-12W and Figure 11 . It should be understood that the operations shown in the preparation method are not exhaustive, and other operations can also be performed before, after or between any of the operations shown. In addition, some of the operations can be performed simultaneously, or in a different order from that shown in Figure 11 . In the following embodiments, the thin film deposition process includes, but is not limited to, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process or an electroplating process.

[0201] Some embodiments of the present disclosure also provide a method for manufacturing the semiconductor structure 200, referring to Figure 12A , including S1-S3.

[0202] S1: referring to Figure 12J , Figure 12K andFigure 12A The stack structure 210 is formed. The stack structure 210 includes a plurality of gate layers 211 arranged in a stack, the plurality of gate layers 211 being spaced apart; the stack structure 210 has a core area AA and a connecting area SS.

[0203] In some embodiments, the stack structure 210 is formed, including S1.1.

[0204] S1.1: Referring to Figure 12J An initial stack structure 210A is formed; the initial stack structure 210A includes a plurality of gate sacrificial layers 211A arranged in a stack, the plurality of gate sacrificial layers 211A being spaced apart.

[0205] In some examples, during the process of forming the initial stack structure 210A, a plurality of dielectric layers 212 are also formed, the plurality of dielectric layers 212 being arranged in a stack alternately with the plurality of gate sacrificial layers 211A. Here, exemplary descriptions about the dielectric layers 212 can be referred to the foregoing descriptions about the dielectric layers 212, which will not be elaborated herein.

[0206] In some examples, the initial stack structure 210A is formed on a substrate K, which can be a single-layer substrate or a composite substrate having a multi-layer structure. The composite substrate may, for example, include a base plate and a plurality of (e.g., two) sacrificial layers arranged in a stack on the base plate.

[0207] Exemplarily, in S1.1, the plurality of gate sacrificial layers 211A and the plurality of dielectric layers 212 arranged in a stack alternately are formed, for example, by a thin film deposition process.

[0208] Exemplarily, the material of the gate sacrificial layers 211A includes, but is not limited to, a combination of one or more of silicon nitride, silicon oxide and silicon oxynitride.

[0209] In some embodiments, the stack structure 210 is formed, further including S1.2.

[0210] S1.2: Referring to Figure 12K and Figure 12A A portion of the gate sacrificial layers 211A is removed to form a first gate line gap 213; and the first gate line gap 213 is filled to form the gate layers 211.

[0211] It should be understood that, after S1.2, the initial stack structure 210A (which can be referred to Figure 12J ) is converted into the stack structure 210.

[0212] In some embodiments, referring to Figure 12K and Figure 12A In some embodiments, the stack structure 210 is formed, further including S1.2.The first gate line slit 213 is formed via the gate line gap 214, and a formation region of the gate line gap 214 corresponds to a formation region of the isolation structure 230. At this time, the preparation method further includes: forming the isolation structure 230 in the core region AA and the connection region SS; and the isolation structure 230 penetrates the stack structure 210. The isolation structure 230 is formed, including U1-U4.

[0213] U1: refer to Figure 12J After S1.1 and before S1.2, an initial isolation structure 230A is formed; the initial isolation structure 230A penetrates the initial stack structure 210A.

[0214] Exemplarily, the material of the initial isolation structure 230A includes but is not limited to one or more of a combination of silicon nitride, silicon oxide and silicon oxynitride.

[0215] In some embodiments, in U1, a channel structure 250 is also formed; the channel structure 250 penetrates the initial stack structure 210A.

[0216] U2: refer to Figure 12A After U1 and before S1.2, the initial isolation structure 230A is removed (for reference Figure 12I ), and the gate line gap 214 is formed.

[0217] Exemplarily, the process of removing the initial isolation structure 230A to form the gate line gap 214 can be an isotropic etching process. For example, the isotropic etching can adopt selective wet etching or vapor phase etching.

[0218] In some embodiments, forming the isolation structure 230 further includes U1A.

[0219] U1A: refer to Figure 12J After U1 and before U2, a third barrier layer 280 is formed on one side of the initial stack structure 210A.

[0220] It can be understood that in this way, the third barrier layer 280 can cover other structures (for example, the first sacrificial material M1 described in detail below) penetrating the stack structure 210, so that the third barrier layer 280 can provide a barrier effect for other structures penetrating the stack structure 210, avoiding the influence of the process of removing the initial isolation structure 230A on other structures penetrating the stack structure 210.

[0221] U3: refer to Figure 12J After U2, via the gate line gap 214, the portions of the multilayer gate sacrificial layer 211A located in the core region AA and the portions located in the connection region SS and close to the initial isolation structure 230A are removed, forming a plurality of first gate line slits 213.

[0222] For example, in U3, referring to Figure 12K In the multi-layer gate sacrificial layer 211A close to the first contact hole H1, the material of the gate sacrificial layer 211A corresponding to the bottom of the first contact hole H1 is removed more than other gate sacrificial layers 211A; in this way, the first gate line gap 213 corresponding to the bottom of the first contact hole H1 can be longer, and the gate layer 211 formed in the first gate line gap 213 can be longer and can be in electrical contact with the conductive structure 220.

[0223] U4: referring to Figure 12J After U3, the multi-layer gate layer 211 is formed in the plurality of first gate line gaps 213.

[0224] For example, in the first gate line gap 213 of Figure 12A The deposition process includes but is not limited to a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a sputtering process.

[0225] It should be understood that in the above U1-U4, the process of forming the isolation structure 230 forms the multi-layer gate layer 211, that is, the initial stack structure 210A (referring to Figure 12K ) is converted into the stack structure 210. In this case, S1.2 can be implemented in two steps of U3 and U4.

[0226] In some embodiments, after U4, the multi-layer gate layer 211 is formed, and a top selective gate (TSG) is also formed. In some examples, the top selective gate is one of the source-end selective gate and the drain-end selective gate close to the first blocking layer 240.

[0227] In some embodiments, forming the isolation structure 230 further includes U5.

[0228] U5: referring to Figure 12N After U4, the isolation structure 230 is formed in the gate line gap 214.

[0229] The material of the isolation structure 230 can include an insulating material, and the process of filling the insulating material can be a chemical vapor deposition process, an atomic layer deposition process, a plasma deposition process, etc.

[0230] S2: referring to Figure 12L The first blocking layer 240 is formed on the stack structure 210.

[0231] For example, S2 can be performed after S1.2; or, in the case where the preparation method further includes forming the isolation structure 230, S2 can be performed after U4 or U5.

[0232] It should be understood that, in the case that the preparation method further comprises forming the isolation structure 230, the first barrier layer 240 covers the isolation structure 230.

[0233] Exemplarily, in S2, the process of forming the first barrier layer 240 can be a thin film deposition process.

[0234] In some embodiments, in the case that the preparation method comprises U1-U5, the preparation method further comprises S2A.

[0235] S2A: refer to Figure 12M After U5, and before S2, the semiconductor structure 200 is polished to expose the material of the isolation structure 230 and the first sacrificial material M1 which will be described in detail below.

[0236] Exemplarily, the semiconductor structure 200 can be polished by a chemical mechanical polishing (CMP) process.

[0237] In some embodiments, the preparation method of the semiconductor structure 200 further comprises S2B.

[0238] S2B: refer to Figures 12B-12H After S1, and before S2, or after S2A, and before S2, the first dielectric layer 260 is formed. In the case that the preparation method further comprises forming the isolation structure 230, the first dielectric layer 260 covers the isolation structure 230.

[0239] Exemplarily, in S2B, the process of forming the first dielectric layer 260 can be a thin film deposition process.

[0240] S3: refer to Figures 12O-12W and Figures 12B-12H The conductive structure 220 is formed in the connection region SS. The conductive structure 220 penetrates the first barrier layer 240, and penetrates the portion of the stack structure 210 close to the first barrier layer 240; the end of the conductive structure 220 away from the first barrier layer 240 is in contact with one of the gate layers 211.

[0241] In some embodiments, forming the conductive structure 220 in the connection region SS comprises S3.1-S3.3.

[0242] S3.1: refer to Figure 12N The first contact hole H1 is formed on the initial stack structure 210A, and the first sacrificial material M1 is filled in the first contact hole H1; the first contact hole H1 penetrates a portion of the initial stack structure 210 to one of the gate sacrificial layers 211A. In S2, the first barrier layer 240 further covers the first sacrificial material M1 (for details, refer to Figure 12M ).

[0243] For example, S3.1 can be performed after S1.1 and before S1.2; or, in the case that the preparation method comprises U1-U4 and U1A, S3.1 can also be performed after U1 and before U1A.

[0244] For example, referring to Figure 12B In the case that the preparation method further comprises S2B, the first dielectric layer 260 also covers the first sacrificial material M1.

[0245] It should be understood that the first contact hole H1 is the word line contact hole H0 described above; and the first sacrificial material M1 is the sacrificial material in the word line contact hole H0 described above.

[0246] It can be understood that by penetrating the first contact hole H1 through a portion of the initial stack structure 210 to one of the gate sacrificial layers 211A, the gate sacrificial layer 211A can be replaced by a gate electrode layer 211 in electrical contact with the conductive structure 220, so that electrical contact between the conductive structure 220 and the gate electrode layer 211 can be achieved. Here, the process of gate replacement is, for example, U2-U4.

[0247] In some embodiments, forming the first contact hole H1 and filling the first sacrificial material M1 comprise S3.1.1-S3.1.7.

[0248] S3.1.1: referring to Figure 12B The first contact hole H1 is formed in the connection region SS.

[0249] For example, the first contact hole H1 can be formed by dry etching or wet etching.

[0250] For example, referring to Figure 12C The aperture of the first contact hole H1 near one end of the substrate K is smaller than the aperture of the first contact hole H1 away from the one end of the substrate K.

[0251] S3.1.2: referring to Figure 12D The second barrier layer 270 is formed by depositing an insulating material in the first contact hole H1 and on the initial stack structure 210A.

[0252] For example, in S3.1.2, the process of depositing the insulating material can be a thin film deposition process.

[0253] S3.1.3: referring to Figure 12E The portion of the second barrier layer 270 at the bottom of the first contact hole H1 is removed, and one of the gate sacrificial layers 211A is exposed.

[0254] It should be appreciated that the exposed gate sacrificial layer 211A corresponds to the gate layer 211 that is in electrical contact with the conductive structure 220.

[0255] Exemplarily, in S3.1.3, a punch process can be employed to remove the portion of the second blocking layer 270 at the bottom of the first contact hole H1 and expose a layer of the gate sacrificial layer 211A.

[0256] S3.1.4: Referring to Figure 12F , a portion of the exposed gate sacrificial layer 211A is removed via the bottom of the first contact hole H1 to form a second gate line gap 215.

[0257] Exemplarily, a dry etching, a wet etching or an acid etching can be employed to remove the portion of the exposed gate sacrificial layer 211A.

[0258] S3.1.5: Referring to Figure 12E , the first contact hole H1 (may refer to Figure 12E ) and the second gate line gap 215 (may refer to Figure 12G ) are filled with a second sacrificial material M2, which is different from the material of the gate sacrificial layer 211A.

[0259] Exemplarily, a high aspect ratio process (HARP) can be employed to fill the first contact hole H1 and the second gate line gap 215 with the second sacrificial material M2.

[0260] Exemplarily, the material of the second sacrificial material M2 includes, but is not limited to, a combination of one or more of silicon nitride, silicon oxide and silicon oxynitride, and the second sacrificial material M2 is different from the material of the gate sacrificial layer 211A.

[0261] S3.1.6: Referring to Figure 12H , the second sacrificial material M2 in the first contact hole H1 is removed and the second sacrificial material M2 in the second gate line gap 215 is retained.

[0262] Exemplarily, a dry etching or a wet etching can be employed to remove the second sacrificial material M2 in the first contact hole H1.

[0263] S3.1.7: Referring to Figure 12J , the first contact hole H1 is filled with a first sacrificial material M1.

[0264] Exemplarily, a high aspect ratio process (HARP) can be employed to fill the first contact hole H1 with the first sacrificial material M1.

[0265] Exemplarily, the material of the first sacrificial material M1 includes, but is not limited to, a combination of one or more of silicon nitride, silicon oxide and silicon oxynitride, and the material of the first sacrificial material M1 and the material of the second sacrificial material M2 can be the same or different.

[0266] It should be understood that in the case that the forming of the first contact hole H1 and the filling of the first sacrificial material M1 include S3.1.1-S3.1.7, in U3, the second sacrificial material M2 is removed in the process of removing part of the gate sacrificial layer 211A via the gate line gap 214. Moreover, since the material of the second sacrificial material M2 is different from that of the gate sacrificial layer 211A, the material of the gate sacrificial layer 211A close to the first contact hole H1 is reserved when the second sacrificial material M2 is removed by using the performance difference (for example, the difference in etching rate) of the materials (for reference Figure 12K ).

[0267] Based on the process of S3.1.1-S3.1.7, in some embodiments, referring to Figure 12T , the gate layer 211 of the multi-layer gate layer 211 which is in contact with the conductive structure 220 (for reference Figure 12O ) is closer to the first contact hole H1 than other gate layers 211.

[0268] Here, the gate layer 211 in contact with the conductive structure 220 can also be understood as the target gate layer 211X.

[0269] It can be understood that through the above arrangement, the target gate layer 211X can be closer to the first contact hole H1 than other gate layers 211, so that when the conductive structure 220 is formed in the first contact hole H1, the material of the conductive structure 220 can be more easily in contact with the target gate layer 211X, and the reliability of the contact between the conductive structure 220 and the target gate layer 211X can be improved.

[0270] S3.2: After S2, referring to Figure 12P , a second contact hole H2 is formed on the first barrier layer 240 to expose the first sacrificial material M1; referring to Figure 12O , the first sacrificial material M1 is removed through the second contact hole H2.

[0271] It should be understood that in the case that the preparation method further includes S2A, referring to Figure 12O , in the process of forming the second contact hole H2, the second contact hole H2 also penetrates through the first dielectric layer 260.

[0272] In some examples, referring to Figure 12P , in the process of forming the second contact hole H2, part of the first sacrificial material M1 is removed.

[0273] Exemplarily, the second contact hole H2 can be formed by dry etching or wet etching to expose the first sacrificial material M1.

[0274] Exemplarily, the first sacrificial material M1 can be removed by dry etching, wet etching or acid etching.

[0275] In some embodiments, the outer side of the gate layer 211 is covered by a high dielectric constant material layer; in this case, in the process of removing the first sacrificial material M1 in S3.2, the high dielectric constant material layer close to the first contact hole H1 in the target gate layer 211X is also removed, so that the conductive structure 220 can be in contact with the target gate layer 211X.

[0276] In some embodiments, referring to Figure 12P , the aperture L4 of the second contact hole H2 close to the first contact hole H1 is smaller than the aperture L5 of the first contact hole H1 close to the second contact hole H2.

[0277] It can be understood that, by such arrangement, a small hole is opened on the first blocking layer 240 (or the first blocking layer 240 and the first dielectric layer 260), so that the first sacrificial material M1 in the first contact hole H1 can be removed, and thus, compared with the case where the aperture L4 of the second contact hole H2 close to the first contact hole H1 is the same as the aperture L5 of the first contact hole H1 close to the second contact hole H2, the material (for example, conductive material) used to form the conductive structure 220 can be less, and the cost can be saved.

[0278] In some embodiments, referring to Figure 12P , the aperture L6 of the second contact hole H2 away from the first contact hole H1 is greater than the aperture L4 of the second contact hole H2 close to the first contact hole H1.

[0279] It can be understood that, by such arrangement, the end of the second contact hole H2 close to the first contact hole H1 is a small end, and the end of the second contact hole H2 away from the first contact hole H1 is a large end; thus, when forming the conductive structure 220, the material of the conductive structure 220 can more easily enter the first contact hole H1 and the second contact hole H2, and the process feasibility when forming the conductive structure 220 can be improved.

[0280] In some embodiments, referring to Figure 12Q , the cross section of the second contact hole H2 perpendicular to the gate layer 211 includes an inverted trapezoidal cross section.

[0281] Here, the cross section of the second contact hole H2 perpendicular to the gate layer 211 includes an inverted trapezoidal cross section; as a possible implementation manner, the second contact hole H2 is an inverted conical hole.

[0282] It can be understood that, by setting in this way, on the one hand, the material of the conductive structure 220 is more likely to enter the first contact hole H1 and the second contact hole H2; on the other hand, by setting in this way, the height and taper of the second contact hole H2 can be adjusted, and thus the state of the material of the conductive structure 220 after entering the first contact hole H1 and the second contact hole H2 can be adjusted; for example, the filling part 225 can seal the air gap that can exist in the inside thereof.

[0283] S3.3: referring to Figure 12P After S3.2, a conductive material is deposited in the first contact hole H1 and the second contact hole H2 (for reference Figure 12Q ) to form a first initial conductive layer 221A; the part of the first initial conductive layer 221A located in the second contact hole H2 constitutes a first conductive part 221, and the part of the first initial conductive layer 221A located in the first contact hole H1 constitutes a second conductive part 222 and a contact part 223; the contact part 223 is located on the side of the second conductive part 222 away from the first conductive part 221. Among them, the gate layer 211 in the multi-layer gate layer 211 that contacts the conductive structure 220 (i.e., the target gate layer 211X) is disposed in the same layer as the contact part 223 and contacts the contact part 223.

[0284] Exemplarily, in S3.3, the process of depositing the conductive material can be a thin film deposition process.

[0285] In some embodiments, in addition to forming the conductive structure 220 in the connection area SS, S3.4 is further included. S3.4 can be performed after S3.3.

[0286] S3.4: referring to Figure 12P An insulating material is deposited on the first initial conductive layer 221A and in the first contact hole H1 and the second contact hole H2 (for reference Figure 12R ) to form an initial filling layer 225A; the part of the initial filling layer 225A located in the first contact hole H1 and the second contact hole H2 constitutes the filling part 225.

[0287] Exemplarily, in S3.4, the process of depositing the insulating material can be a thin film deposition process.

[0288] In some embodiments, during the process of forming the initial filling layer 225A, the air gap 226 located in the inside of the filling part 225 is also formed.

[0289] In some embodiments, in addition to forming the conductive structure 220 in the connection area SS, S3.5-S3.6 are further included. S3.5-S3.6 can be performed after S3.4.

[0290] S3.5: referring to Figure 12Q, the initial filling layer 225A (refer to Figure 12S ) on the side of the first initial conductive layer 221A away from the stack structure 210, and the filling part 225 is retained.

[0291] Illustratively, in S3.5, a CMP process can be employed to remove the portion of the initial filling layer 225A on the side of the first initial conductive layer 221A away from the stack structure 210.

[0292] S3.6: referring to Figure 12R , the first initial conductive layer 221A (refer to Figure 12U ) on the first barrier layer 240 is removed, and the first conductive part 221, the second conductive part 222, and the contact part 223 are retained.

[0293] Illustratively, in S3.6, a CMP process can be employed to remove the portion of the first initial conductive layer 221A on the first barrier layer 240.

[0294] In some embodiments, after S3.5 and before S3.6, R1-R3 are performed to form the conductive structure 220 in the connection region SS.

[0295] R1: referring to Figure 12P , the portion of the filling part 225 inside the second contact hole H2 (refer to Figure 12U ) is thinned to expose a portion of the first conductive part 221.

[0296] Illustratively, dry etching or wet etching can be employed to thin the portion of the filling part 225 inside the second contact hole H2.

[0297] R2: referring to Figure 12V , on the side of the first initial conductive layer 221A away from the first barrier layer 240, and on the side of the filling part 225 away from the contact part 223, a second initial conductive layer 224A is formed, and the portion of the second initial conductive layer 224A inside the second contact hole H2 constitutes the plug part 224.

[0298] Illustratively, in R2, the process of forming the second initial conductive layer 224A can be a thin film deposition process.

[0299] It should be understood that the material of the first initial conductive layer 221A and the material of the second initial conductive layer 224A can be the same or different. Moreover, when the material of the first initial conductive layer 221A and the material of the second initial conductive layer 224A are the same, the first initial conductive layer 221A and the second initial conductive layer 224A can be connected as one layer.

[0300] R3: referring toFigure 12U , removing a portion of the second initial conductive layer 224A (see Figure 12U ) on the first initial conductive layer 221A (see Figure 12T ), and retaining the plug portion 224.

[0301] Exemplarily, in R3, a CMP process can be employed to remove the portion of the second initial conductive layer 224A on the first initial conductive layer 221A.

[0302] It should be appreciated that when the material of the first initial conductive layer 221A is the same as or similar to that of the second initial conductive layer 224A, the material of the first initial conductive layer 221A can be removed by the same process as that for removing the second initial conductive layer 224A, that is, S3.6 and R3 can be implemented by the same process (e.g., one CMP process).

[0303] In some embodiments, the preparation method further comprises S3.7. Referring to Figure 12W , S3.7 can be performed after S3.6, or, referring to Figure 12T , S3.7 can also be performed after R3.

[0304] S3.7: Referring to Figure 12W and ​ , a channel contact structure 290 is formed on a side of the channel structure 250 close to the first blocking layer 240.

[0305] Exemplarily, the channel contact structure 290 can be configured to implement electrical connection between the channel structure 250 and a bit line (not shown in the figure).

[0306] It should be appreciated that the preparation method of the semiconductor structure provided by the above embodiments of the present disclosure has the beneficial effects as described above for the semiconductor structure, which will not be repeated here.

[0307] The above only describes specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any changes or replacements within the technical scope disclosed by the present application can be easily thought of by those skilled in the art, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a stack structure comprising a plurality of gate layers arranged in a stack, the plurality of gate layers being spaced apart; the stack structure has a core region and a connecting region; a first barrier layer is formed on the stack structure; and a conductive structure is formed in the connecting region; the conductive structure penetrates the first barrier layer and a portion of the stack structure close to the first barrier layer; an end of the conductive structure away from the first barrier layer is in contact with one of the gate layers. The semiconductor structure further comprises:

2. The semiconductor structure of claim 1, wherein, an isolation structure penetrating the stack structure; a portion of the isolation structure is in the core region and another portion of the isolation structure is in the connecting region; the first barrier layer covers the isolation structure. The conductive structure comprises:

3. The semiconductor structure of claim 1, wherein, a first conductive part penetrating the first barrier layer; and a second conductive part penetrating the portion of the stack structure close to the first barrier layer; the second conductive part is connected to the first conductive part; the first conductive part and the second conductive part are annular; an outer diameter of an end of the first conductive part close to the second conductive part is smaller than an outer diameter of an end of the second conductive part close to the first conductive part. An outer diameter of an end of the first conductive part away from the second conductive part is greater than the outer diameter of the end of the first conductive part close to the second conductive part.

4. The semiconductor structure of claim 3, wherein, The outer diameter of the first conductive part gradually decreases in a direction close to the second conductive part.

5. The semiconductor structure of claim 4, wherein, The conductive structure further comprises:

6. The semiconductor structure of claim 3, wherein, a contact part located on a side of the second conductive part away from the first conductive part and connected to the second conductive part; the gate layer of the plurality of gate layers in contact with the conductive structure is arranged in the same layer as the contact part and is in contact with the contact part. The conductive structure further comprises:

7. The semiconductor structure of claim 3, wherein, a plug part in contact with the end of the first conductive part away from the second conductive part. The conductive structure further comprises:

8. The semiconductor structure according to any one of claims 3 to 7, characterized in that a filling part; the first conductive part and the second conductive part surround the filling part; in the case that the conductive structure further comprises the contact part, the filling part is also located on a side of the contact part close to the second conductive part; in the case that the conductive structure further comprises the plug part, the filling part is also located on a side of the plug part close to the second conductive part. An inner part of the filling part has an air gap.

9. The semiconductor structure of claim 8, wherein, The semiconductor structure further comprises:

10. The semiconductor structure of any one of claims 1-7, wherein, a first dielectric layer between the stack structure and the first barrier layer, the conductive structure penetrating the first dielectric layer; in the case that the semiconductor structure further comprises the isolation structure, the first dielectric layer covers the isolation structure; in the case that the conductive structure comprises the first conductive part, the first conductive part penetrates the first dielectric layer. The semiconductor structure comprises:

11. A method of fabricating a semiconductor structure, characterized by, forming a stack structure comprising a plurality of gate layers arranged in a stack, the plurality of gate layers being spaced apart; the stack structure has a core region and a connecting region; forming a first barrier layer on the stack structure; and forming a conductive structure in the connecting region; ​ The conductive structure penetrates the first barrier layer and a portion of the stack structure close to the first barrier layer; an end of the conductive structure away from the first barrier layer is in contact with one of the gate layers.

12. The method of claim 11, wherein the semiconductor structure is prepared by a method comprising: The stack structure is formed by: forming an initial stack structure; the initial stack structure comprises a plurality of gate sacrificial layers arranged in layers; the plurality of gate sacrificial layers are distributed at intervals; The conductive structure formed in the connection region comprises: A first contact hole is formed in the initial stack structure, and a first sacrificial material is filled in the first contact hole; the first contact hole penetrates a portion of the initial stack structure to one of the plurality of gate sacrificial layers; wherein the first barrier layer also covers the first sacrificial material; A second contact hole is formed in the first barrier layer to expose the first sacrificial material; The first sacrificial material is removed through the second contact hole; and A conductive material is deposited in the first contact hole and the second contact hole to form a first initial conductive layer; a portion of the first initial conductive layer in the second contact hole constitutes a first conductive part, and a portion of the first initial conductive layer in the first contact hole constitutes a second conductive part and a contact part; the contact part is located on a side of the second conductive part away from the first conductive part; Among the plurality of gate layers, the gate layer in contact with the conductive structure is arranged in the same layer as the contact part and is in contact with the contact part.

13. The method of claim 12, wherein the semiconductor structure is prepared by a method comprising: The aperture of the second contact hole close to the first contact hole is smaller than the aperture of the first contact hole close to the second contact hole.

14. The method of claim 13, wherein the semiconductor structure is prepared by a method comprising: The aperture of the second contact hole away from the first contact hole is larger than the aperture of the second contact hole close to the first contact hole.

15. The method of claim 14, wherein the semiconductor structure is prepared by a method comprising: The cross section of the second contact hole perpendicular to the gate layer comprises an inverted trapezoidal cross section.

16. The method of claim 12, wherein the semiconductor structure is prepared by a method comprising: The conductive structure formed in the connection region further comprises: An insulating material is deposited on the first initial conductive layer and in the first contact hole and the second contact hole to form an initial filling layer; a portion of the initial filling layer in the first contact hole and the second contact hole constitutes a filling part.

17. The method of claim 16, wherein the semiconductor structure is prepared by a method comprising: The conductive structure formed in the connection region further comprises: A portion of the initial filling layer on a side of the first initial conductive layer away from the stack structure is removed, and the filling part is retained; and A portion of the first initial conductive layer on the first barrier layer is removed, and the first conductive part, the second conductive part, and the contact part are retained.

18. The method of claim 17, wherein the semiconductor structure is prepared by a method comprising: Further comprising: A portion of the filling layer in the second contact hole is thinned to expose a portion of the first conductive part; A second initial conductive layer is formed on a side of the first initial conductive layer away from the first barrier layer and on a side of the filling part away from the contact part; a portion of the second initial conductive layer in the second contact hole constitutes a plug part; And A portion of the second initial conductive layer on the first initial conductive layer is removed, and the plug part is retained.

19. The method of claim 12, wherein Further comprising: The isolation structure is formed in the core region and the connection region; The isolation structure penetrates through the stack structure; The first barrier layer covers the isolation structure; The isolation structure is formed by: forming an initial isolation structure; the initial isolation structure penetrates through the initial stack structure; removing the initial isolation structure to form a gate line slot; via the gate line slot, removing portions of the multi-layer gate sacrificial layer in the core region and portions of the multi-layer gate sacrificial layer in the connection region and close to the initial isolation structure to form a plurality of first gate line gaps; and forming the multi-layer gate electrode layer in the plurality of first gate line gaps.

20. The method of claim 19, wherein the semiconductor structure is prepared by a method comprising: Among the multi-layer gate electrode layer, the gate electrode layer in contact with the conductive structure is closer to the first contact hole than other gate electrode layers.

21. The method for preparing a semiconductor structure according to claim 19, wherein: The first contact hole is formed by filling the first sacrificial material, including: forming the first contact hole in the connection region; depositing an insulating material in the first contact hole and on the initial stack structure to form a second barrier layer; removing portions of the second barrier layer at the bottom of the first contact hole and exposing a layer of the gate sacrificial layer; via the bottom of the first contact hole, removing a portion of the material of the exposed layer of the gate sacrificial layer to form a second gate line gap; filling a second sacrificial material in the first contact hole and the second gate line gap, the second sacrificial material being different from the material of the gate sacrificial layer; removing the second sacrificial material in the first contact hole and retaining the second sacrificial material in the second gate line gap; and filling a first sacrificial material in the first contact hole; wherein the second sacrificial material is removed during the process of removing portions of the gate sacrificial layer via the gate line slot.

22. The method of fabricating a semiconductor structure according to any one of claims 12 to 21, wherein Further comprising: forming a first dielectric layer; during the process of forming the second contact hole, the second contact hole also penetrates through the first dielectric layer; in the case where the preparation method further comprises forming an isolation structure, the first dielectric layer covers the isolation structure.

23. A three-dimensional memory, comprising: Comprise: a semiconductor structure, as claimed in any one of claims 1-10; a peripheral device, electrically connected with the semiconductor structure.

24. A storage system, comprising: Comprise: a three-dimensional memory, as claimed in claim 23; a controller, coupled with the three-dimensional memory to control the three-dimensional memory to store data.

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