Memory element and manufacturing method thereof
By employing a composite stacking structure and a double-layer barrier design in the three-dimensional memory element, the problems of word line interference and insufficient programming capability are solved, achieving a more efficient memory programming effect.
Patent Information
- Application Number
- CN202410533212.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-04-23
- Filing Date
- 2024-04-29
- Publication Date
- 2025-10-24
AI Technical Summary
Three-dimensional memory devices face problems such as interference between word lines and insufficient programming capability.
A composite stacking structure is adopted, including alternately stacked insulating layers and conductive layers, to form multiple charge storage units. A double-layer blocking layer design is used to form blocking layers in the grooves and during the gate replacement process, respectively, to ensure isolation between the charge storage unit and the conductive layer, thereby increasing the area of the charge storage unit.
Effectively reduce interference between word lines and improve the programming capability of memory elements.
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Figure CN120835561A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor device and a method for fabricating the same, and more particularly to a memory device and a method for fabricating the same. BACKGROUND
[0002] Non-volatile memory has the advantage that the stored data will not disappear after power-off, and thus is widely used in personal computers and other electronic devices. Currently, three-dimensional memory commonly used in the industry includes NOR (not-OR) memory and NAND (not-AND) memory. In addition, another three-dimensional memory is AND memory, which can be applied in a multi-dimensional memory array to have high integration and high area utilization, and has the advantage of fast operating speed. Therefore, the development of three-dimensional memory devices has gradually become the current trend. However, three-dimensional memory devices face problems such as interference between word lines and insufficient programming capability. SUMMARY
[0003] The present application provides a memory device and a method for fabricating the same, which can reduce or avoid interference between word lines, and effectively improve the programming capability of the memory device.
[0004] An embodiment of the present application provides a memory device, which includes a composite stack structure, a channel pillar, a plurality of charge storage units, a tunneling layer, a first blocking layer, and a plurality of second blocking layers. The composite stack structure includes a first stack structure and a second stack structure. The first stack structure includes a plurality of insulating layers and a plurality of conductor layers alternately stacked, and is located above a first region. The second stack structure includes the plurality of insulating layers and a plurality of intermediate layers alternately stacked, and is located above a second region. The channel pillar extends through the first stack structure. The plurality of charge storage units are embedded in the first stack structure and located between the channel pillar and the plurality of conductor layers. The tunneling layer is disposed between the channel pillar and the plurality of charge storage units. At least one blocking layer is disposed between the plurality of charge storage units and the plurality of conductor layers. The thickness of one of the plurality of charge storage units is greater than the thickness of the corresponding conductor layer.
[0005] An embodiment of the present invention provides a method for manufacturing a memory element, comprising the following steps: forming a stack structure. The stack structure includes a plurality of insulating layers and a plurality of intermediate layers stacked alternately. forming an opening in the stack structure. laterally removing the plurality of insulating layers exposed in the opening to form a plurality of grooves. forming a first blocking layer on the sidewalls of the opening and in the plurality of grooves. filling the remaining space of the plurality of grooves with a plurality of charge storage units. forming a tunneling layer and a channel column on the first blocking layer and the plurality of sidewalls of the plurality of charge storage units. removing portions of the plurality of intermediate layers to form a plurality of horizontal openings. forming a plurality of second blocking layers and a plurality of conductive layers in the plurality of horizontal openings.
[0006] Based on the above, in the embodiment of the present invention, since the multiple charge storage units are separated from each other, interference between word lines can be reduced or avoided. Since the area of the charge storage unit is increased, the programming capability of the memory device can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figures 1A-1G is a cross-sectional schematic diagram of a manufacturing process of a memory device according to an embodiment of the present invention.
[0008] Figure 2 yes Figure 1G A partial enlarged schematic diagram.
[0009] Figure 3 FIG. 1 is a cross-sectional view of a complementary metal oxide semiconductor (CMOS under array, CuA) structured memory device according to an embodiment of the present invention.
[0010] Figure 4 FIG. 1 is a cross-sectional view of a complementary metal oxide semiconductor (CMOS) bonding array (CbA) structure memory device according to an embodiment of the present invention.
[0011] Description of reference numerals:
[0012] 50: Second base
[0013] 100: Base
[0014] 60: Component layer
[0015] 70, 138: Internal connection structure
[0016] 80: Joint structure
[0017] 80A, 80B: Bonding layer
[0018] 102: Insulation layer
[0019] 103: dielectric layer
[0020] 104: intermediate layer
[0021] 106: recess
[0022] 108: barrier layer
[0023] 108a: first barrier layer
[0024] 108b: second barrier layer
[0025] 110: charge storage layer
[0026] 110a: charge storage cell
[0027] 112: tunneling layer
[0028] 114: channel layer
[0029] 116: insulating pillar
[0030] 117: channel plug
[0031] 118: horizontal opening
[0032] 120: dielectric layer
[0033] 122: conductor layer
[0034] 124: barrier layer
[0035] 126: metal layer
[0036] 136: via
[0037] 140: protective layer
[0038] 200: region
[0039] BL: bit line
[0040] COA1, COA2: conductor plug
[0041] CP: channel pillar
[0042] CSK: composite stack
[0043] D1, D2, D3: direction
[0044] GSK, SK1: stack
[0045] MC: memory cell
[0046] OP1: opening
[0047] P1, P2, P3, P4, Q1, Q2, Q3: portion
[0048] R1: array region
[0049] R2: second region
[0050] RS: staircase region
[0051] SC: staircase structure
[0052] SL: source line layer
[0053] SLT: spacer wall
[0054] bs1: bottom surface
[0055] d1: first distance
[0056] d2: second distance
[0057] d3: third distance
[0058] sw1, sw2: sidewall
[0059] ts1: top surface
[0060] Ta, Tb, T1, T2, T 21 , T 22 3: thickness DETAILED DESCRIPTION
[0061] Figures 1A-1G is a cross-sectional schematic diagram of a manufacturing flow of a memory element according to an embodiment of the present application.
[0062] Referring to Figure 1A , a stack structure SK1 is formed. The stack structure SK1 can also be referred to as an insulating stack structure SK1. In the present embodiment, the stack structure SK1 includes insulating layers 102 and intermediate layers 104 which are sequentially and alternately stacked along a direction D3. The insulating layers 102 and the intermediate layers 104 extend in directions D1 and D2. The direction D3 is perpendicular to the directions D1 and D2. The insulating layers 102 are, for example, silicon oxide layers. The intermediate layers 104 are, for example, silicon nitride layers. The intermediate layers 104 are locally removed in a subsequent process. In Figures 1A-1G only three insulating layers 102 and two intermediate layers 104 are shown. In practice, more layers of insulating layers 102 and more layers of intermediate layers 104 can be included, as shown in Figure 3 and Figure 4 .
[0063] At this stage, similar to Figure 3 , the stack structure SK1 is formed in an array region R1, a staircase region RS (shown in Figure 3) and a peripheral region R2. However, the stacked structure GSK is not formed at this stage. The stacked structure GSK can be formed by converting a portion of the stacked structure SK1 in the following processes. The element layer 60, the interconnection structure 70, and the source line layer SL can also be formed between the substrate 100 and the stacked structure SK1. The element layer 60 can include complementary metal-oxide semiconductor elements. In other embodiments, the stacked structure SK1 is formed on the substrate 100 without the element layer 60, the interconnection structure 70, and the source line layer SL between the substrate 100 and the stacked structure SK1.
[0064] Next, referring to Figure 1B , a photolithography and etching process is performed to form openings OP1 in the array region R1 of the stacked structure SK1. The etching process can be a dry etching process, a wet etching process, or a combination thereof. The openings OP1 pass through the stacked structure SK1 and can further extend to an underlying layer (not shown). The openings OP1 are, for example, holes. In the present embodiment, the openings OP1 have a circular profile (not shown) as viewed from the top, but the present application is not limited thereto.
[0065] Next, a portion of the plurality of intermediate layers 104 exposed to the openings OP1 is laterally removed to form a plurality of recesses 106. The recesses 106 are formed by the sidewalls sw2 of the intermediate layers 104 and the bottom surfaces bs1 of the adjacent upper insulating layers 102 and the top surfaces ts1 of the underlying insulating layers 102. Due to the formation of the recesses 106, the sidewalls sw2 of the intermediate layers 104 exposed by the openings OP1 are not aligned with the sidewalls sw1 of the exposed insulating layers 102.
[0066] Referring to Figure 1C , a first barrier layer 108a and a charge storage layer 110 are formed in the openings OP1. The first barrier layer 108a covers the sidewalls sw1 of the plurality of insulating layers 102 and fills in the plurality of recesses 106. The first barrier layer 108a can be a conformal layer. The first barrier layer 108a is, for example, silicon oxide. The charge storage layer 110 is, for example, silicon nitride or other material capable of trapping or storing charges. The charge storage layer 110 fills the remaining space of the recesses 106 and extends to cover the sidewalls of the first barrier layer 108a on the sidewalls sw1 of the plurality of insulating layers 102.
[0067] Referring to Figure 1D , thereafter, a back etching is performed to remove the charge storage layer 110 except for the plurality of recesses 106, so that the first barrier layer 108a covering the sidewalls sw1 of the plurality of insulating layers 102 is exposed. Thus, the plurality of charge storage units 110a remaining in the plurality of recesses 106 are formed in the stacked structure SK1 of the array region R1 and are separated from each other.
[0068] Referring to Figure 1E andFigure 3 A tunneling layer 112, a channel layer 114, insulating pillars 116, and a channel plug 117 (shown in Figure 3 ) are formed in the opening OP1. The tunneling layer 112 can include silicon oxide, silicon oxynitride / silicon oxide, or a combination of silicon oxide / silicon nitride (e.g., oxide / nitride / oxide). The channel layer 114 is, for example, polysilicon. The insulating pillars 116 are, for example, silicon oxide. The channel plug 117 is, for example, polysilicon. The tunneling layer 112 is between the first blocking layer 108a and the channel layer 114, and between the charge storage unit 110a and the channel layer 114. The channel layer 114 is between the tunneling layer 112 and the insulating pillars 116. The tunneling layer 112 and the channel layer 114 are, for example, conformal layers, respectively. The first blocking layer 108a, the tunneling layer 112, and the channel layer 114 do not fill the opening OP1. The channel plug 117 is above the insulating pillars 116. The channel plug 117 and the insulating pillars 116 fill the remaining space of the opening OP1. The channel plug 117, the insulating pillars 116, and the channel layer 114 can be collectively referred to as a channel pillar CP (shown in Figure 3 ).
[0069] Referring to Figure 1F , a gate replacement process is then performed on the stack structure SK1 of the array region R1. First, an etching process, such as a wet etching process, is performed to remove the multi-layered intermediate layer 104 to form a plurality of horizontal openings 118. The openings 118 expose the sidewalls of the first blocking layer 108a and the upper and lower surfaces of the insulating layer 102.
[0070] Thereafter, referring to Figure 1GA second blocking layer 108b, a high-k dielectric layer 120, and a conductor layer 122 are formed in the horizontal openings 118. The second blocking layer 108b can be the same material as the first blocking layer 108a, such as silicon oxide. The high-k dielectric layer 120 includes a dielectric material having a dielectric constant greater than 3.9, and even greater than 7. The high-k dielectric layer 120 can be, for example, aluminum oxide (AI2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), a transition metal oxide, a lanthanide oxide, or a combination thereof. The conductor layer 122 can include a barrier layer 124 and a metal layer 126. The barrier layer 124 can be, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The metal layer 126 can be, for example, tungsten, cobalt, ruthenium. The high-k dielectric layer 120, the barrier layer 124, and the metal layer 126 can be formed, for example, by sequentially forming a high-k material, a barrier material, and a conductor material in the horizontal openings 118, and performing an etch back process to form the high-k dielectric layer 120, the barrier layer 124, and the metal layer 126 in the horizontal openings 118. At this point, a stack structure GSK composed of a plurality of memory cells MC is formed in the array region Rl. Each memory cell MC is formed by the channel layer 114, the tunneling layer 112, the charge storage unit 110a, the blocking layer 108 (the first blocking layer 108a and the plurality of second blocking layers 108b), and the conductor layer 122.
[0071] The insulating layers 102 and the intermediate layers 104 of the stack structure SKl in the peripheral region R2 are not removed and alternate with each other. The stack structure GSK and the stack structure SKl are collectively referred to as a composite stack structure CSK.
[0072] Figure 2 is Figure 1G a partial enlarged view of the region 200.
[0073] Referring to Figure 2 , the memory element of the embodiment includes the composite stack structure CSK, the channel pillar CP, the tunneling layer 112, the plurality of charge storage units 110a, and the blocking layer 108. In the embodiment, the blocking layer 108 includes the first blocking layer 108a and the plurality of second blocking layers 108b.
[0074] The composite stack structure CSK includes the stack structure GSK and the stack structure SKl. The stack structure GSK is located in the array region Rl. The stack structure GSK includes a plurality of insulating layers 102 and a plurality of conductor layers (word line layers) 122 alternately stacked. The conductor layer 122 can include a barrier layer 124 and a metal layer 126. In some embodiments, the memory element further includes a plurality of high-k dielectric layers 120. Each high-k dielectric layer 120 is disposed between the blocking layer 108 and each conductor layer 122.
[0075] The stack structure SK1 is located in the peripheral region R2. The stack structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 which are alternately stacked. Each intermediate layer 104 of the stack structure SK1 and each conductor layer 122 of the stack structure GSK are disposed at a corresponding height in the peripheral region R2 and the array region R1. Thus, there is a corresponding conductor layer 122 for each intermediate layer 104 at a particular height. Likewise, there is a corresponding intermediate layer 104 for each conductor layer 122 at a particular height.
[0076] The channel pillar CP and the tunneling layer 112 continuously extend along the direction D3 and through the stack structure GSK. The tunneling layer 112 is disposed between the channel pillar CP and the plurality of charge storage units 110a.
[0077] The plurality of charge storage units 110a are embedded in the recesses 106 of the stack structure GSK and adjacent to the plurality of conductor layers 122. The plurality of charge storage units 110a are surrounded by the tunneling layer 112 and the first barrier layer 108a. More specifically, in the direction D1, the plurality of charge storage units 110a are located between the channel pillar CP and the plurality of conductor layers 122. More specifically, in the direction D1, the plurality of charge storage units 110a are located between the tunneling layer 112 and the first barrier layer 108a. In the direction D3, the plurality of charge storage units 110a are separated from each other by the insulating layers 102 and the first barrier layer 108a. In other words, the plurality of charge storage units 110a are discontinuous and separated from each other along the direction D3.
[0078] The first barrier layer 108a of the barrier layer 108 continuously extends along the direction D3 and has a contoured profile. The first barrier layer 108a includes a plurality of portions P1, P2, P3, and P4. The portion P1 is disposed on the sidewalls sw1 of the plurality of insulating layers 102. The portion P1 is disposed between and in contact with the plurality of insulating layers 102 and the tunneling layer 112. The portions P2, P4, and P3 are disposed on the sidewalls and the bottom of the recesses 106. The portions P2, P4 are disposed between and in contact with the plurality of insulating layers 102 and the plurality of charge storage units 110a. The portion P3 is disposed between the charge storage units 110a and the plurality of conductor layers 122. More specifically, the portion P3 is disposed between and in contact with the charge storage units 110a and the second barrier layer 108b. The plurality of second barrier layers 108b of the barrier layer 108 includes portions Q1, Q2, and Q3. The portions Q1 and Q3 are disposed between the plurality of insulating layers 102 and the conductor layers 122. The portion Q2 is disposed between the portion P3 of the first barrier layer 108a and the conductor layers 122.
[0079] In an embodiment of the present invention, the thickness Ta of the first barrier layer 108a is greater than the thickness Tb of the corresponding second barrier layer 108b. That is, Ta>Tb. The thickness Ta+Tb of the barrier layer 108 (i.e., the combined layer comprising the first barrier layer 108a and the second barrier layer 108b) between the charge storage unit 110a and the conductive layer 122 is greater than the thickness Ta of the first barrier layer 108a above and below the charge storage unit 110a, and greater than the thickness Tb of the second barrier layer 108b above and below the conductive layer 122. That is, Ta+Tb>Ta>Tb.
[0080] In the embodiment of the present invention, the thickness T1 of the charge storage unit 110a is smaller than the thickness T of the corresponding conductive layer 122. 21 The thickness T of the high-k dielectric layer 120 is twice as large as 22 The sum of (i.e. thickness T2). That is, T2 = T 21 +2×T 22 , and T1<T2. The thickness T1 of the charge storage unit 110a is greater than the thickness T of the corresponding conductive layer 122. 21 That is, T1>T 21 In some embodiments, T1 and T 21 The difference is about 50 angstroms to 100 angstroms. Since the thickness T1 of the charge storage unit 110a is increased, the area of the charge storage unit 110a can be increased, thereby effectively improving the programming capability of the memory device.
[0081] In the embodiment of the present invention, the thickness T3 of the intermediate layer 104 is greater than the thickness T1 of the corresponding charge storage unit 110a. That is, T3>T1. The thickness T3 of the intermediate layer 104 is greater than the thickness T1 of the corresponding conductive layer 122. 21 The thickness T of the high-k dielectric layer 120 corresponding to twice 22 The sum of (i.e. thickness T2). That is, T2 = T 21 +2×T 22 , and T3>T2. In some embodiments, the ratio of thickness T2 to thickness T3 (T2 / T3) is 0.7-0.8. Since T2>T1, therefore, T3>T2>T1.
[0082] A first distance d1 between two adjacent charge storage units 110a is greater than a second distance d2 between two adjacent high-k dielectric layers 120. The second distance d2 is greater than a third distance d3 between two adjacent intermediate layers 104. That is, d1>d2>d3.
[0083] In embodiments of the application, since the plurality of charge storage units 110a are separated from each other, interference between word line layers (conductor layers 122) can be reduced or avoided. Further, embodiments of the application split the blocking layer 108 into two layers, with the first blocking layer 108a and the second blocking layer 108b each contributing a portion of the thickness, such that the combined blocking layer 108 can have a desired thickness (Ta+Tb) to insulate the plurality of charge storage units 110a from the plurality of conductor layers 122. The first blocking layer 108a is formed in the recess 106 and surrounds the charge storage units 110a. The second blocking layer 108b surrounds the conductor layers 122. Since the blocking layer 108 having the desired thickness (Ta+Tb) is not entirely formed in the recess 106, the height and space in the recess 106 for forming the charge storage units 110a can be increased. Since the height of the charge storage units 110a is increased, the area of the charge storage units 110a is also increased, and thus the programming capability of the memory element can be effectively improved.
[0084] The composite stack structure CSK described above can be applied to a complementary metal-oxide-semiconductor (CMOS) under array (CuA) type memory element and a CMOS bonding array (CbA) type memory element.
[0085] Figure 3 is a cross-sectional view of a complementary metal-oxide-semiconductor (CMOS) under array (CuA) type memory element according to embodiments of the application.
[0086] Referring to Figure 3 In some embodiments, as described in the previous paragraph, the stack structure (with a memory array) GSK of the application can have element layers 60, interconnect structures 70, and source line layers SL below the stack structure GSK and above the substrate 100. The element layers 60 can include complementary metal-oxide-semiconductor (CMOS) elements. In some embodiments, these CMOS elements and the interconnect structures 70 can be formed prior to the formation of the stack structure GSK, and thus are located below the memory array, which is referred to as a complementary metal-oxide-semiconductor (CMOS) under array (CuA) type memory.
[0087] Referring to Figure 3 In some embodiments, the staircase region RS of the memory element has a staircase structure SC and a dielectric layer 103. The staircase structure SC can be formed in the substrate 100 prior to the formation of the opening OP1 (shown in Figure 1B) before the stack structure SK1 is patterned to form the stepped structure SC. The dielectric layer 103 can be formed on the stepped structure SC after the stepped structure SC is formed. The material of the dielectric layer 103 is, for example, silicon oxide. The dielectric layer 103 can be planarized via a planarization process, such as a chemical mechanical polishing process.
[0088] Referring to Figure 3 In some embodiments, the memory element further includes a separation wall SLT. The separation wall SLT can be formed in the stack structure SK1 by performing a lithography and etching process before the horizontal opening 118 is formed. Then, the separation wall SLT is formed in the separation trench after the gate replacement process is performed. The top view of the separation wall SLT has a long strip shape (not shown). In some embodiments, the memory element further includes a plurality of conductor plugs COA1 and a plurality of conductor plugs COA2 on the stack structure GSK and the stack structure SK1. The plurality of conductor plugs COA1 are each connected to the conductor layer 122 and the via plug 117. The plurality of conductor plugs COA2 are each connected to the conductor plug COA1. In some embodiments, the memory element further includes a via window 136, a bit line BL, an interconnect structure 138, and a protection layer 140, etc.
[0089] Figure 4 is a cross-sectional view of a complementary metal-oxide-semiconductor element bonded memory array (CbA) structure type memory element according to an embodiment of the present application.
[0090] Referring to Figure 4 In other embodiments, a source line layer SL is first formed on a first substrate (not shown) before the stack structure GSK is formed. After the stack structure SK1, the stack structure GSK, the conductor plugs COA1, COA2, the via window 136, and the bit line BL are formed on the first substrate according to the method of the aforementioned embodiments, a bonding layer 80A is first formed. A second substrate 50 having the element layer 60 and the interconnect structure 70 and the bonding layer 80B as described in the previous paragraph is then provided. The first substrate (not shown) is then flipped. The bonding layer 80A and the bonding layer 80B are bonded to each other to form a bonding structure 80. The first substrate (not shown) can be polished to be completely removed or thinned (not shown) before the interconnect structure 138 and the protection layer 140 are formed on the stack structure GSK. The second substrate 50, the element layer 60, the interconnect structure 70, and the bonding structure 80 are located below the stack structure GSK. This type of complementary metal-oxide-semiconductor element is formed below the memory array by bonding, and this type is also called a complementary metal-oxide-semiconductor element bonded memory array (CbA) structure.
[0091] Based on the above, the memory element and the manufacturing method thereof can separate the plurality of charge storage units of the plurality of memory cells from each other. Furthermore, the embodiment of the present application adopts a double-layer method to form a double barrier layer, one of which is formed in the recess before forming the charge storage layer, and the other is formed during the gate replacement process. By controlling the thickness of the double barrier layer, the height of the charge storage unit is greater than the height of the word line layer (i.e. the conductor layer), so that a better operation window can be obtained.
Claims
1. A memory element, comprising: a composite stack structure, comprising: a first stack structure comprising a plurality of insulating layers and a plurality of conductor layers alternately stacked, over a first region; and a second stack structure comprising the plurality of insulating layers and a plurality of intermediate layers alternately stacked, over a second region; a channel pillar extending through the first stack structure; a plurality of charge storage units embedded in the first stack structure and located between the channel pillar and the plurality of conductor layers; a tunneling layer disposed between the channel pillar and the plurality of charge storage units; at least one blocking layer disposed between the plurality of charge storage units and the plurality of conductor layers, wherein a thickness of one of the plurality of charge storage units is greater than a thickness of a corresponding conductor layer.
2. The memory element of claim 1, further comprising a plurality of high dielectric constant dielectric layers disposed between the at least one blocking layer and the plurality of conductor layers.
3. The memory element of claim 2, wherein the thickness of the one of the plurality of charge storage units is less than a sum of the thickness of the corresponding conductor layer and twice a thickness of a corresponding high dielectric constant dielectric layer.
4. The memory element of claim 2, wherein a thickness of one of the plurality of intermediate layers is greater than the thickness of the corresponding conductor layer and twice the thickness of a corresponding high dielectric constant dielectric layer.
5. The memory element of claim 2, wherein a ratio of the thickness of the one of the plurality of conductor layers and twice a thickness of a corresponding high dielectric constant dielectric layer to a thickness of a corresponding intermediate layer is 0.7-0.
8.
6. The memory element of claim 2, wherein the thickness of one of the plurality of intermediate layers is greater than the thickness of a corresponding charge storage unit.
7. The memory element of claim 2, wherein a first distance between two adjacent charge storage units is greater than a second distance between two adjacent high dielectric constant dielectric layers.
8. The memory element of claim 7, wherein the second distance is greater than a third distance between two adjacent intermediate layers.
9. The memory element of claim 1, wherein the at least one blocking layer comprises: a first blocking layer disposed between the plurality of charge storage units and the plurality of conductor layers; and a plurality of second blocking layers disposed between the first blocking layer and the plurality of conductor layers.
10. The memory element of claim 9, wherein a thickness of the first blocking layer is greater than a thickness of a corresponding second blocking layer.
11. A method of fabricating a memory element, comprising: forming a stack structure, wherein the stack structure comprises a plurality of insulating layers and a plurality of intermediate layers alternately stacked; forming an opening in the stack structure; laterally removing the plurality of insulating layers exposed to the opening to form a plurality of recesses; forming a first blocking layer on sidewalls of the opening and in the plurality of recesses; filling a plurality of charge storage units in spaces remaining in the plurality of recesses; forming a tunneling layer and a channel pillar on the first blocking layer and sidewalls of the plurality of charge storage units; removing portions of the plurality of intermediate layers to form a plurality of horizontal openings; and forming a plurality of second barrier layers and a plurality of conductor layers among the plurality of horizontal openings.
12. The method of claim 11, wherein the first barrier layer is thicker than one of the second barrier layers.
13. The method of claim 12, further comprising forming a plurality of high dielectric constant dielectric layers between the plurality of second barrier layers and the plurality of conductor layers.
14. The method of claim 13, wherein a thickness of one of the plurality of charge storage cells is less than a sum of a thickness of a corresponding conductor layer and twice a thickness of a corresponding high dielectric constant dielectric layer.
15. The method of claim 13, wherein a thickness of one of the plurality of charge storage cells is greater than a thickness of a corresponding conductor layer.
16. The method of claim 15, wherein a thickness of one of the plurality of intermediate layers is greater than a sum of a thickness of a corresponding conductor layer and twice a thickness of a corresponding high dielectric constant dielectric layer.
17. The method of claim 15, wherein a ratio of a sum of a thickness of one of the plurality of conductor layers and twice a thickness of a corresponding high dielectric constant dielectric layer to a thickness of a corresponding intermediate layer is 0.7 to 0.
8.
18. The method of claim 15, wherein a thickness of one of the plurality of intermediate layers is greater than a thickness of a corresponding charge storage cell.
19. The method of claim 15, wherein a first distance between two adjacent charge storage cells is greater than a second distance between two adjacent high dielectric constant dielectric layers.
20. The method of claim 19, wherein the second distance is greater than a third distance between two adjacent intermediate layers.