Method of forming capacitor or ion capacitor having electrode comprising noble metal

Abstract

Methods of forming a capacitor or ion capacitor having an electrode comprising a noble metal are disclosed. A method of forming an integrated component, such as a capacitor or an ion capacitor, includes forming a stack structure on a substrate (400, 405, AAO), the stack structure including a bottom electrode, an intermediate layer (420) including a layer of dielectric material or an ion conductor layer, and a top electrode, where forming the top electrode and / or the bottom electrode includes a liner layer (430) of forming material, the liner layer (430) including a layer of dielectric material or an ion conductor layer (430); and forming a metal layer (435) on the liner layer, the metal layer comprising a noble metal, where the metal layer is thicker than the liner layer.

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of integration, and more specifically to electronic products comprising capacitors or ion capacitors and methods of manufacturing the same. BACKGROUND

[0002] Various techniques have been developed for integrating passive components (e.g., energy storage components, capacitive devices, etc.) in / on a substrate (e.g., a silicon wafer).

[0003] It is generally desirable to construct integrated energy storage components that provide high energy storage density. Various approaches have been attempted in this regard. In the case of capacitive devices, conventional approaches for increasing capacitance include reducing the thickness of the dielectric layer (subject to constraints to avoid dielectric breakdown when an operating voltage is applied) and selecting a material with a high dielectric constant as the material of the dielectric layer.

[0004] Recently, it has been proposed to form the conductive and dielectric layers of an integrated energy storage component conformally on a contoured surface (i.e., form the conductive and dielectric layers such that their shape conforms to the shape of the underlying surface), rather than employing planar layers. This type of energy storage component can be referred to as a "three-dimensional" component (to distinguish them from planar devices). As an example, the PICS technology proposed by Murata Integrated Passive Solutions employs three-dimensional capacitive components and enables integration of high-density capacitive components into a silicon substrate.

[0005] Recently, three-dimensional capacitive components have been fabricated by embedding a metal-insulator-metal (MIM) structure into a porous anodized material, such as porous anodized aluminum (PAA). This technology provides highly integrated capacitors that can be used for many applications. The technology implements a capacitive stack (e.g., a MIM stack) in a porous structure formed over a substrate, such as a silicon wafer. The porous structure can result from anodization of a thin layer of aluminum deposited over the substrate (e.g., deposited on the substrate or deposited on one or more layers that are themselves formed on the substrate). The anodization process converts the Al to a porous aluminum oxide (PAA). A mask can optionally be formed on the aluminum layer prior to anodization occurs, such that the anodization process forms islands of porous material. These components, which use a dielectric in the MIM stack, are referred to as capacitors in this specification.

[0006] There also exist devices that use between the electrodes an ionic conductor (referred to in this application as an ion conductor) with electronic insulating properties, these devices being called ion capacitors, the ion conductor being an electrolyte such as LiPON. These ion capacitors can also be housed in a porous anodized aluminum structure.

[0007] Forming (non-ionic) capacitors or ionic capacitors inside the pores of an anodic porous oxide or inside other types of 3D structures can be particularly difficult to achieve. In particular, the layers of the capacitor or ionic capacitor must be deposited in a conformal manner, must be particularly thin to enable conformal deposition to occur on all pores or reliefs, and must remain low ESR (for the electrode layers).

[0008] In many devices, titanium nitride, TiN, is used as electrode material. This material is typically deposited using a CI-based precursor, such as TiCl4, as it leads to electrode layers with an acceptable resistivity (of the order of 100 μOhm.cm).

[0009] The use of other precursors can be problematic, in particular I-based precursors or Br-based precursors.

[0010] It has been observed that, after deposition of TiN, CI-based elements can be trapped in the capacitor or ionic capacitor. This is particularly the case for the top electrode layer, i.e. the electrode formed directly on the dielectric layer or ion conductor layer. The material of the dielectric layer or ion conductor layer can be chemically affected by the presence of CI-based elements. This can lead to an increase in leakage current or corrosion in the obtained device.

[0011] There exist ALD methods for forming TiN electrodes that do not use CI-based precursors. For example, one can use tetrakis(dimethylamino) titanium (TDMAT), tetrakis(diethylamino) titanium (IV) (TDEAT), titanium tetrabromide (TiBr4) as precursors. However, these cannot be used to form capacitor electrodes as the resulting TiN can have a resistivity higher than 1 kOhm.cm.

[0012] There is a need for electrode materials that avoid the presence of CI-based elements and that maintain an acceptable ESR.

[0013] The present invention has been made in view of the above problems. SUMMARY

[0014] The present invention provides a device comprising integrated components, comprising:

[0015] a substrate,

[0016] a stack structure on the substrate, the stack structure comprising a bottom electrode, an intermediate layer comprising a dielectric material layer or an ion conductor layer (or a combination of both), and a top electrode (the top electrode layer on the intermediate layer),

[0017] wherein the top electrode and / or the bottom electrode comprises:

[0018] a liner layer of a material (for the top electrode layer on the intermediate layer, for the bottom electrode layer on the substrate),

[0019] a metal layer on the spacer layer, the metal layer comprising a noble metal (one or more noble metals) or an intermetallic material (one or more intermetallic materials) or a refractory metal (one or more refractory metals),

[0020] wherein the metal layer is thicker than the spacer layer, for example at least five times thicker.

[0021] The above-mentioned components can be a capacitor (for example in case the intermediate layer comprises a dielectric material layer), or an ionic capacitor (for example in case the intermediate layer comprises an ionic conductor layer), or even a via.

[0022] Thus, the present invention proposes to use a layer of noble metal or intermetallic material or refractory metal to mitigate the high resistivity of layers that can be deposited using any appropriate technique and in particular for precursors that are not based on CI (or based on I or based on Br, etc.). This enables to benefit from the low resistivity of the selected material.

[0023] Moreover, it has been observed that noble metals (or intermetallic materials or refractory metals) can be deposited without using CI -based precursors (or others) and that their resistivity is generally lower than 50 μOhm.cm. However, their deposition is particularly difficult to achieve. For example for noble metals, and in particular for thin layers up to 15 nanometers, because they generally nucleate as discontinuous islands during the ALD process (which also leads to a non-uniform thickness if the deposition process is performed for a given duration). However, it has been observed that a spacer of a suitable material can minimize the formation of islands (for example compared to noble metals deposited on an insulating layer), which leads to a more uniform thickness and to a continuous layer. In particular, the word spacer denotes a continuous layer (i.e. a monolayer without interruptions).

[0024] Moreover, since the formation of a continuous metal layer occurs at a reduced thickness, this enables to achieve thinner conductive electrodes. This is particularly interesting when this is used to achieve a bottom electrode. Indeed, from the prior art (cylindrical capacitor solution), it is known that for a given pore diameter (when the capacitor is implemented within a porous structure), the thinner the bottom electrode, the larger the effective capacitance area. Because of the delayed nucleation for 3D applications, it is generally advantageous to implement such a composite conductive layer as a bottom electrode compared to a monolayer in terms of capacitance density, typically when the capacitor is implemented within a porous structure.

[0025] It should be noted that noble metals are also blocking electrodes when using ionic conductors. Typically and for example for ionic applications, the delayed nucleation of noble metals is more pronounced due to the potential chemical surface inhibition caused by the important use of ionic elements (Li, Na...). Thus, it is clear that the ALD conformality of an ultra-thin top electrode layer on an ionic layer changes with the increase of the porous structure density.

[0026] It should be noted that the top electrode layer is called "top" because it is the last electrode layer to be formed when formed on a pre-existing structure, and the bottom electrode layer is called "bottom" because it is the first electrode layer to be formed on the substrate.

[0027] According to a particular embodiment, the metal layer has a thickness comprised between 5 and 20 nanometers, and / or wherein the spacer layer is thinner than 1 nanometer.

[0028] These thicknesses are suitable for devices housed in the pores of an anodic porous oxide, said pores generally having a diameter of about 100 nanometers.

[0029] According to a particular embodiment, the spacer layer has a greater resistivity than the metal layer, for example, the spacer layer has a resistivity less than 50 μOhm.cm and the metal layer has a resistivity exceeding 50 μOhm.cm.

[0030] According to a particular embodiment, the material of the spacer layer is an electronically conducting material (i.e. they can be conductors or conduct electrons by other mechanisms including tunneling), for example metals or compound transition metals or low bandgap dielectrics or trap-rich dielectrics, for example chosen from the list comprising: TiN, TiOx, AlOx, AlN, TaN, TaOx, MoN, WN.

[0031] According to a particular embodiment, the metal layer comprises a noble metal chosen from the list comprising: Pt, Ru, Au, or the metal layer comprises an intermetallic material chosen from the list comprising: Ni-Al, Ti-Al, or the metal layer comprises a refractory metal chosen from the list comprising: Cr, Mo.

[0032] According to a particular embodiment, the intermediate layer comprises at least one material chosen from the list comprising: SiON, HfSiO x , Si x O y , Si x N y , Al x O y , Hf x O y , Zr x O y , Ti x O y , Li x P y O z N x1 , Li x Si y P z O x1 N y1、N x M' y M” z (P x1 O y1 ) z , wherein M′ and M″ are metals from the group consisting of Al, Ti, Fe, and N is an element from the group consisting of Li, Na, K.

[0033] For example, the intermediate layer has a thickness comprised between 5 and 30 nanometers.

[0034] Furthermore, combinations of materials from this list are also contemplated.

[0035] According to a specific embodiment, the top electrode includes a liner layer and a metal layer, and wherein the bottom capacitor layer comprises a material selected from the list consisting of: TiN, Ru, Pt, Au, Cu, W, Mo, AlN, Si, Ti, Al, Co.

[0036] According to a specific embodiment, the stacked structure is a 3D structure, wherein the bottom capacitor electrode is contoured, and wherein the intermediate layer, the liner layer, and the metal layer are conformal.

[0037] By contoured, it is meant that the bottom electrode has a surface that extends in three dimensions. For example, it is shaped in the form of a straight hole, a groove, a hole, a wall.

[0038] According to a particular embodiment, the substrate includes an anode porous oxide region (AAO) comprising a plurality of substantially straight pores extending from a top surface of the anode porous oxide region, and wherein the bottom capacitor electrode layer, the intermediate layer, and the top capacitor electrode layer are conformally arranged within the pores of the anode porous oxide region.

[0039] The present invention also provides a method for forming an integrated component, comprising:

[0040] forming a stack structure on a substrate, the stack structure including a bottom electrode, an intermediate layer including a dielectric material layer or an ion conductor layer (or a combination of both; furthermore, the intermediate layer is on the bottom electrode layer), and a top electrode (the top electrode layer is on the intermediate layer),

[0041] wherein forming the top electrode and / or the bottom electrode comprises forming a liner layer of material (on the intermediate layer for the top electrode layer and on the substrate for the bottom electrode layer),

[0042] forming a metal layer on the liner layer, the metal layer comprising a noble metal or an intermetallic material or a refractory metal,

[0043] The metal layer is thicker than the liner layer, for example, at least five times thicker.

[0044] The above-mentioned components can be capacitors (for example, in the case where the intermediate layer comprises a layer of dielectric material), or ionic capacitors (for example, in the case where the intermediate layer comprises a layer of ionic conductor), or even vias.

[0045] The application thus proposes to mitigate the high resistivity of the layer that can be deposited using any appropriate technique and in particular a technique that is not based on CI (or based on I or based on Br, etc.) with a layer of noble metal or intermetallic material or refractory metal.

[0046] According to a particular embodiment, the spacer layer is formed by deposition under Frank-Van der Merwe growth mode (also called 2D or planar growth mode).

[0047] This makes it possible for the spacer layer to be as continuous as possible even for sub-nanometric thicknesses.

[0048] The spacer in this embodiment causes the next deposited layer (i.e. the noble metal layer or the intermetallic material layer or the refractory metal layer) to grow in a more 2D / planar mode (Frank-Van Der Merwe mode) when it would naturally grow in a 3D / island mode (Volmer Weber) or in a mixed 3D / 2D mode (Stranski Krastanov mode). This arrangement is particularly beneficial when the resistivity of the metal layer (for example, in the case where a metal is used) is lower than the resistivity of the spacer layer.

[0049] According to a particular embodiment, the metal layer has a thickness comprised between 5 nanometers and 20 nanometers and / or wherein the spacer layer is thinner than 1 nanometer.

[0050] These thicknesses are suitable for devices housed in the pores of an anodic porous oxide, the pores generally having a diameter of the order of 100 nanometers.

[0051] According to a particular embodiment, the spacer layer has a greater resistivity than the metal layer, for example, the spacer layer has a resistivity of less than 50 μOhm.cm and the metal layer has a resistivity of more than 50 μOhm.cm.

[0052] According to a particular embodiment, the material of the spacer layer is an electronically conductive material (i.e. they can be conductors or conduct electrons by other mechanisms including tunneling), for example a metal or a compound transition metal or a low bandgap dielectric or a trap-rich dielectric, for example chosen from the list comprising: TiN, TiOx, AlOx, AlN, TaN, TaOx, MoN, WN.

[0053] According to a particular embodiment, the spacer layer is deposited by ALD using an organic metal precursor, for example comprising TDMAT or TDEAT or TMA or Al-TDMA.

[0054] These organic metal precursors are not Cl-based (or other, for example halide-free) and thus cannot contaminate the underlying structure.

[0055] According to a particular embodiment, the metal layer comprises a noble metal selected from the list comprising Pt, Ru, Au, or the metal layer comprises an intermetallic material selected from the list comprising Ni-Al, Ti-Al, or the metal layer comprises a refractory metal selected from the list comprising Cr, Mo.

[0056] It has been observed that these materials are particularly suitable for the manufacture of capacitors or ion capacitors.

[0057] According to a particular embodiment, the intermediate layer comprises at least one material selected from the list comprising SiON, HfSiO x , Si x O y , Si x N y , Al x O y , Hf x O y , Zr x O y , Ti x O y , Li x P y O z N x1 , Li x Si y P z O x1 N y1 , N x M' y M” z (P x1 O y1 ) z , with M' and M" being a metal from the group comprising Al, Ti, Fe and N being an element from the group comprising Li, Na, K.

[0058] For example, the intermediate layer has a thickness comprised between 5 nanometers and 30 nanometers.

[0059] Furthermore, combinations of materials from this list can also be considered.

[0060] According to a particular embodiment, the top electrode comprises a liner layer and a metal layer, and the bottom electrode layer comprises the same liner layer and the same metal layer, or a material selected from the list comprising: TiN, Ru, Pt, Au, Cu, W, Mo, AIN, Si, Ti, Al, Co.

[0061] For example, the bottom electrode layer has a thickness lower than 30 nanometers, preferably comprised between 5 nanometers and 10 nanometers.

[0062] According to a particular embodiment, the liner layer and the metal layer are formed by ALD.

[0063] In particular, the liner layer and the metal layer are formed in the same ALD sequence, without any air break between the two depositions.

[0064] According to a particular embodiment, the stack structure is a 3D structure, wherein the bottom electrode is contoured, and wherein the intermediate layer, the liner layer and the metal layer are conformal.

[0065] By contoured, it is meant that the bottom electrode has a surface extending in three dimensions. For example, it is shaped in the form of straight holes, trenches, cavities, walls.

[0066] According to a particular embodiment, the substrate comprises an anodic porous oxide region comprising a plurality of substantially straight pores extending from a top surface of the anodic porous oxide region, and wherein the bottom electrode layer, the intermediate layer and the top electrode layer are conformally arranged inside the pores of the anodic porous oxide region. BRIEF DESCRIPTION OF DRAWINGS

[0067] Further features and advantages of the application will become apparent from the following description of certain embodiments thereof, given by way of example only, with reference to the accompanying drawings, in which:

[0068] - Figure 1 is a schematic representation of a device according to an example;

[0069] - Figure 2 is a schematic representation of a device according to an example;

[0070] - Figure 3 is a schematic representation of a device according to an example; and

[0071] - Figure 4 is a schematic representation of a device according to an example, arranged on an anodic porous oxide region. DETAILED DESCRIPTION

[0072] We will now describe capacitors and ion capacitors, as well as methods and steps for obtaining these capacitors and ion capacitors.

[0073] Other integrated features are also contemplated, such as through-holes.

[0074] Figure 1 is an exemplary apparatus comprising a substrate 100. The substrate may comprise a semiconductor region, typically silicon, or may also comprise glass or other materials.

[0075] Figure 1 The substrate 100 is planar. The present invention is applicable to both planar devices and three-dimensional devices, but is particularly advantageous for three-dimensional devices. Figure 4 Such a three-dimensional device is shown.

[0076] A bottom electrode 110 is formed above and on the substrate. Figure 1 In the example of , the bottom electrode is a single layer (this is non-limiting, other options described below present bottom electrodes comprising multiple layers) and may have a thickness below 30 nm and preferably close to 5 nm. It may also comprise a material selected from the list comprising: TiN, Ru, Pt, Au, Cu, W, Mo, AlN, Si, Ti, Al, Co. For example, if titanium nitride is used, it may be deposited using ALD techniques, for example using Cl-based precursors to obtain a layer with low resistivity.

[0077] Subsequently, an intermediate layer 120 is deposited as a (non-ionic) dielectric layer or an ion conductor layer. By way of example, the intermediate layer comprises a material selected from the list comprising: SiON, HfSiO x 、Si x O y 、Si x N y 、Al x O y , Hf x O y 、Zr x O y 、Ti x O y 、Li x P y O z N x1 、Li x Si y P z O x1 N y1 、N x M' y M” z (P x1 O y1 ) zwith M' and M" being metals from the group comprising Al, Ti, Fe and N being an element from the group comprising Li, Na, K. The intermediate layer can also comprise a combination of materials from this list.

[0078] Furthermore, the intermediate layer can have a thickness comprised between 5 and 30 nanometers.

[0079] A liner layer 130 is deposited on the intermediate layer by ALD. This liner layer has a thickness preferably lower than 1 nanometer. Furthermore, the liner layer 130 can comprise a material selected from the list comprising: TiN, TiOx, AlOx, AlN, TaN, TaOx, MoN, WN. In particular, the liner layer 130 is preferably conducting electrons, for example a metal or a compound transition metal or a low bandgap dielectric or a dielectric rich in traps allowing direct or indirect electron tunneling. These materials can be deposited by ALD using organometallic precursors not containing chlorine to avoid contamination within the structure and in particular TDMAT or TDEAT or TMA or Al-TDMA can be used.

[0080] The liner layer can have a high resistivity or allow electron conduction by direct or indirect tunneling effect (for example, its resistivity can be lower than the resistivity of the metal layer comprising noble metals) and is thus preferably kept thin.

[0081] Furthermore, the liner layer is selected to have a low (ideally non-existent) bandgap in order to accept charge conduction.

[0082] On the liner layer, a metal layer 135 is deposited. The metal layer comprises a noble metal, preferably Pt or Ru or Au in the illustrated embodiment. However, the application is not limited to noble metals and is also applicable to the use of intermetallic materials (for example Ni-Al, Ti-Al) or refractory metals (for example Cr, Mo). Combinations of said materials can also be used.

[0083] While it has been observed that the direct deposition of noble metals on SiO2or LiPON (for example) is particularly difficult, as the material aggregates and forms separate islands (in particular for thicknesses lower than 15 nanometers), this behavior is mitigated by the presence of the conductive material liner. In fact, the presence of the liner layer has been observed to have an impact such that the surface is in more favorable thermodynamic conditions for uniform growth.

[0084] As illustrated, the noble metal can still form islands, although these islands are all in contact with each other and the resulting surface can not be perfectly flat.

[0085] The noble metal is advantageous when an ionic conductor is used, as it serves as a blocking electrode for the diffusion of ions.

[0086] Moreover, it is advantageous since its resistivity can be lower than 50 μOhm.cm, and the thickness of the metal layer can be comprised between 5 and 20 nanometers for a reduced ESR.

[0087] A capacitor or an ionic capacitor is obtained, wherein the liner layer 130 and the metal layer 135 form a top electrode of the capacitor or the ionic capacitor.

[0088] Figure 2 Another configuration is shown, in which the bottom electrode of the capacitor or the ionic capacitor comprises a liner layer and a metal layer.

[0089] In particular, a substrate 200 similar to the substrate 100 of Figure 1 is provided above, Figure 2 The device of comprises a liner layer 210 similar to the liner layer 130 of Figure 1 a metal layer 215 similar to the metal layer 135 of Figure 1 an intermediate layer 220 similar to the intermediate layer 120 of Figure 1 a top electrode 230 similar to the bottom electrode 110 of Figure 1 .

[0090] Figure 3 Another configuration is shown, in which both the bottom electrode and the top electrode of the capacitor or the ionic capacitor comprise a liner layer and a metal layer.

[0091] In particular, a substrate 300 similar to the substrate 100 of Figure 1 is provided above, Figure 3 The device of comprises a liner layer 310 similar to the liner layer 210 of Figure 2 a metal layer 315 similar to the metal layer 215 of Figure 2 an intermediate layer 320 similar to the intermediate layer 120 of Figure 1 a further liner layer 330 similar to the liner layer 130 of Figure 1 a metal layer 335 similar to the metal layer 135 of Figure 1 .

[0092] Figure 4 Another example is shown, in which a structure such as the structure of Figure 1 is arranged on a contoured substrate.

[0093] Here, a capacitor or an ionic capacitor is formed on a substrate comprising:

[0094] a support 400 (e.g. a glass or semiconductor wafer);

[0095] an anodization barrier layer 405 (e.g. tungsten);

[0096] an anodic porous material AAO.

[0097] This substrate can be obtained using the technique described in document WO 2015 / 063420. In particular, here, straight holes are formed in the anodic porous oxide, said straight holes extending from the top surface to reach the anodization barrier layer in which the holes are open.

[0098] The capacitive stack structure or the ionic capacitive stack structure comprises the following layers deposited in a conformal manner inside the holes, on the walls of the holes and at the bottom of the holes:

[0099] a bottom electrode layer 410 similar to the layer 110 of Figure 1 the bottom electrode,

[0100] an intermediate layer 420 similar to the intermediate layer 120 of Figure 1 the intermediate layer,

[0101] a spacer layer 430 similar to the spacer layer 130 of Figure 1 the spacer layer,

[0102] a metal layer 435 similar to the metal layer 135 of Figure 1 the metal layer.

[0103] Furthermore, in order to form an electrical contact above the top electrode, the holes are filled with an electrically conductive material 440, for example doped polysilicon.

[0104] Figures 1 to 4 The device illustrated makes it possible to have a noble metal material for the capacitor electrode or the ionic capacitor electrode, with a substantially flat / good uniformity surface thanks to the presence of a spacer which facilitates the deposition of the noble metal. In fact, this good uniformity is obtained quickly and even for thin films (lower than 10 nm, whereas a deposition without the spacer can lead to a non-uniform / discontinuous metal layer).

[0105] The above-mentioned devices are also advantageous in that they make it possible to deposit without introducing Cl-based contaminants, while preserving a low resistivity of the electrode.

[0106] Furthermore, the use of a noble metal is particularly advantageous because it prevents parasitic chemical reactions such as oxidation, nitridation, etc. from occurring between the electrode (surface or volume) and the intermediate layer during the MIM deposition.

[0107] Additional variants

[0108] While the application has been described above with reference to certain specific embodiments thereof, it is to be understood that the application is not limited to the particular details thereof. Various modifications, changes and adaptations will come to those skilled in the art, within the scope of the appended claims.

Claims

1. A device comprising integrated components, comprising: a substrate (100, 200, 300, 400, 405, AAO), a stack structure on the substrate, the stack structure comprising a bottom electrode, an intermediate layer (120,..., 420) comprising a layer of a dielectric material or a layer of an ion conductor, and a top electrode, wherein the top electrode and / or the bottom electrode comprises: a liner layer (130, 210, 310, 330, 430) of a material, a metal layer (135, 215, 315, 335, 435) on the liner layer, the metal layer comprising a noble metal or an intermetallic material or a refractory metal, wherein the metal layer is thicker than the liner layer.

2. The apparatus of claim 1, wherein, The metal layer has a thickness comprised between 5 nm and 20 nm, and / or wherein the liner layer is thinner than 1 nm.

3. The apparatus of any one of claims 1 or 2, wherein, The liner layer has a higher resistivity than the metal layer, for example the liner layer has a resistivity of less than 50 μOhm.cm and the metal layer has a resistivity of more than 50 μOhm.cm.

4. The apparatus of any one of claims 1 to 3, wherein, The material of the liner layer is an electron conducting material, for example a metal or a compound transition metal or a low band gap dielectric or a trap rich dielectric, for example selected from the list comprising: TiN, TiOx, AlOx, AlN, TaN, TaOx, MoN, WN.

5. The apparatus of any one of claims 1 to 4, wherein, The metal layer comprises a noble metal selected from the list comprising: Pt, Ru, Au, or the metal layer comprises an intermetallic material selected from the list comprising: Ni-Al, Ti-Al, or the metal layer comprises a refractory metal selected from the list comprising: Cr, Mo.

6. The apparatus of any one of claims 1 to 5, wherein, The intermediate layer comprises at least one material selected from the list comprising SiON, HfSiO x , Si x O y , Si x N y , Al x O y , Hf x O y , Zr x O y , Ti x O y , Li x P y O z N x1 , Li x Si y P z O x1 N y1 , N x M' y M” z (P x1 O y1 ) z wherein M' and M" are metals from the group comprising Al, Ti, Fe and N is an element from the group comprising Li, Na, K.

7. The apparatus of any one of claims 1 to 6, wherein, The top electrode comprises the liner layer and the metal layer, and wherein the bottom electrode comprises a material selected from the list comprising: TiN, Ru, Pt, Au, Cu, W, Mo, AlN, Si, Ti, Al, Co.

8. The apparatus of any one of claims 1-7, wherein, The stack structure is a 3D structure, wherein the bottom electrode is contoured, and wherein the intermediate layer, the liner layer and the metal layer are conformal.

9. The apparatus of claim 8, wherein, The substrate comprises an anodic porous oxide region (AAO) comprising a plurality of substantially straight pores extending from a top surface of the anodic porous oxide region, and wherein the bottom electrode, the intermediate layer and the top electrode are conformally arranged inside the pores of the anodic porous oxide region.

10. A method of forming integrated components, comprising: forming a stack structure on a substrate (100, 200, 300, 400, 405, AAO), the stack structure comprising a bottom electrode, an intermediate layer (120,..., 420) comprising a layer of a dielectric material or a layer of an ion conductor, and a top electrode, wherein forming the top electrode and / or the bottom electrode comprises forming a liner layer (130, 210, 310, 330, 430) of a material, and forming a metal layer (135, 215, 315, 335, 435) on said liner layer, said metal layer comprising a noble metal or an intermetallic material or a refractory metal, wherein said metal layer is thicker than said liner layer.

11. The method of claim 10, wherein, said liner layer is formed by deposition in Frank-Van der Merwe growth mode.

12. The method of any one of claims 10 or 11, wherein, said liner layer is of an electron-conducting material, for example a metal or a compound transition metal or a low bandgap dielectric or a trap-rich dielectric, for example selected from the list comprising: TiN, TiOx, AlOx, AlN, TaN, TaOx, MoN, WN.

13. The method of claim 12, wherein, said liner layer is deposited by ALD using an organometallic precursor, for example comprising TDMAT or TDEAT or TMA or Al-TDMA.

14. The method of any one of claims 10 to 13, wherein, said liner layer and said metal layer are formed by ALD.

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