Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and belongs to the field of semiconductors. The semiconductor structure comprises a collector layer, a P + injection layer, a gradient transition layer, a drift region, a P-type base region and an N + emission layer which are stacked in sequence, wherein the gradient transition layer is configured to be used for improving the lattice adaptation degree of the injection layer and the drift region in the growth process and buffering thermal stress in the growth process; the drift region is an N-type diamond drift region.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor, and particularly relates to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] Traditional IGBT devices are mostly made of silicon or silicon carbide materials. Limited by intrinsic characteristics of the materials, there are problems such as high on-resistance, large switching loss, and reliability decline at high temperature, which are difficult to meet the demand of high-frequency high-voltage devices in the fields of 5G communication and electric vehicles. Diamond, as a super-wide bandgap semiconductor (bandgap width 5.47 eV), has super-high thermal conductivity (>2000 W / m·K), high breakdown field strength (>10 MV / cm) and extremely high electron mobility (4500 cm2 / V·s), which is an ideal high-frequency power device material. However, the preparation of n-type diamond faces significant challenges. First, the doping problem: the traditional phosphorus-doped diamond has low activation efficiency (<30%), and high-concentration doping easily causes lattice distortion; interface defects will lead to high interface state density due to the lattice mismatch between diamond and hetero-materials (such as SiC), and the carrier transport is limited; ohmic contact: the barrier height between n-type diamond and metal electrode is high (>1 eV), and the contact resistivity is generally higher than 10-6 Ω·cm.

[0003] In the prior art, n-type diamond is mainly used in simple devices such as Schottky diodes. The hetero-interface mismatch makes the lattice constant difference between diamond and SiC reach 16%, and the interface dislocation density during epitaxial growth is more than 10<8> cm-2, which leads to more than 50% attenuation of carrier mobility. Moreover, the P / N heterojunction and multi-layer epitaxial structure required by IGBT are still limited by the interface charge accumulation effect, such as the band mutation between the P-type SiC base region and the n-type diamond drift layer. Solving the problems of n-type diamond interface stress mismatch and band mutation between different regions is the key to realizing high-performance diamond-based IGBT. SUMMARY

[0004] Therefore, the present application provides a semiconductor structure and a preparation method thereof, aiming to reduce stress adaptation and lattice adaptation during growth, so as to improve the performance of IGBT devices.

[0005] In a first aspect, the present application provides a semiconductor structure, comprising: a collector layer, a P+ injection layer, a gradient transition layer, a drift region, a P-type base region and an N+ emitter layer which are sequentially stacked; The gradient transition layer is configured to improve the lattice adaptation degree of the injection layer and the drift region during growth and to buffer thermal stress during growth. The drift region is an N-type diamond drift region.

[0006] Optionally, the gradient transition layer comprises Al​​​x Ga （1-x） N superlattice layer, the Al x Ga （1-x） N superlattice layer includes multiple Al x Ga （1-x） N layers, and x is in the range of 0 to 1.

[0007] Optionally, the Al x Ga （1-x） N superlattice layer, the Al x Ga （1-x） N layers is 15 to 30.

[0008] Optionally, the thickness of the gradient transition layer is 100 to 150 nm.

[0009] Optionally, the thickness of the N-type diamond drift region is 20 to 70 microns.

[0010] Optionally, the semiconductor structure further comprises: An N-type buffer layer disposed between the P+ injection layer and the gradient transition layer.

[0011] In a second aspect, the application provides a method for manufacturing a semiconductor structure, comprising: providing a collector layer; forming a P+ injection layer on the collector layer; forming a gradient transition layer on the P+ injection layer; wherein the gradient transition layer is configured to improve the lattice matching of the injection layer and the drift region during growth and to buffer thermal stress during growth; forming a drift region on the gradient transition layer; the drift region is an N-type diamond drift region; forming a P-type base region on the drift region; forming an N+ emitter layer on the P-type base region.

[0012] Optionally, the step of forming a gradient transition layer on the P+ injection layer comprises: using an atomic layer deposition process to increase the pulse ratio of TMAl to TMAl in the Al x Ga （1-x） N superlattice layer as a buffer layer; wherein the Al x Ga （1-x） N superlattice layer includes multiple Al x Ga （1-x） N layers, and x is in the range of 0 to 1.

[0013] Optionally, the step of forming a drift region on the surface of the gradient transition layer comprises: The MPCVD process is used to grow an N-type diamond layer as a drift region by introducing a carbon source, hydrogen, and hydrogen sulfide at a temperature of 850°C to 950°C and a pressure of 80 torr to 100 torr.

[0014] Optionally, the method further includes: An N-type buffer layer is formed between the P+ injection layer and the gradient transition layer.

[0015] The technical solution provided by this application has the following beneficial effects: The n-type diamond drift region is used to replace the traditional N-drift region, and its ultra-high breakdown field strength (>10 MV / cm) and high electron mobility are used to achieve a breakthrough in voltage resistance. An AlN gradient transition layer is introduced, and through composition gradient and superlattice design, the interface dislocation density is reduced to < , the composition gradient is passed through 20 layers of Al x Ga (1-x) N gradient (x from 0 to 1), the lattice mismatch rate is reduced from 52% to <5%. In addition, this layer can also buffer thermal stress, reducing the thermal expansion coefficient from aluminum nitride ( / K) to diamond ( / K), the structure also promotes a smooth transition of the conduction band offset from aluminum nitride (3.0eV) to diamond (5.5eV), and a multi-layer composite structure is designed to synergistically exert the physical advantages of n-type diamond.

[0016] A new n-type diamond-based IGBT device has been constructed, filling a gap in the industry. Compared to traditional Si-IGBTs (1.8V–3.0V), its on-state voltage drop is 30%–50% lower, its on-state resistance is 40% lower than that of SiC-IGBTs, and its power loss is reduced by 45% (at 20kHz). The thermal conductivity of the diamond layer is >1500W / m·K, and the chip-to-case thermal resistance is <0.15K / W, compared to 0.8–1.2K / W for traditional Si modules. Mechanical reliability is improved, and the gradient transition layer reduces interfacial thermal stress to <50MPa (compared to >200MPa for traditional structures). The proposed method provides important technical support for the development of high-efficiency, high-power electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1A structural schematic diagram of a semiconductor structure provided by an embodiment of the present application.

[0019] Figure 2 A structural schematic diagram of an IGBT device provided by an embodiment of the present application.

[0020] Figure 3 A flow chart of a preparation method of a semiconductor structure provided by an embodiment of the present application.

[0021] Figure 4 A flow chart of a preparation method of a semiconductor structure provided by another embodiment of the present application.

[0022] Figure 5 A flow chart of a preparation method of an IGBT device provided by an embodiment of the present application.

[0023] The reference signs are as follows: 11: collector layer; 12: P+ injection layer; 13: N-type buffer layer; 14: gradient transition layer; 15: drift region; 16: P-type base region; 17: N+ emitter layer; 18: gate dielectric layer; 19: emitter; 20: gate. DETAILED DESCRIPTION

[0024] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0025] Figure 1 A structural schematic diagram of a semiconductor structure provided by an embodiment of the present application. Referring to Figure 1 , comprising: a collector layer 11, a P+ injection layer 12, a gradient transition layer 14, a drift region 15, a P-type base region 16 and an N+ emitter layer 17 which are sequentially laminated; The gradient transition layer 14 is configured to improve the lattice matching degree of the injection layer 12 and the drift region 15 during growth and to buffer thermal stress during growth. The drift region 15 is an N-type diamond drift region.

[0026] In an example, the collector layer 11 is a main electrode for current output, connects an external circuit, adopts a high-thermal-conductivity metal (such as Mo or Cu) to realize a heat dissipation capacity of >400 W / m·K, and the contact resistance is <10-6Ω·cm2, thereby ensuring low-loss conduction.

[0027] The P+ injection layer 12 is a hole injection source and injects holes into the n-type diamond drift region during conduction.​

[0028] In an example, the gradient transition layer 14 comprises Al x Ga （1-x） N superlattice layer, the Al x Ga （1-x） N superlattice layer comprises multiple layers of Al x Ga （1-x） N layers with increasing Al

[0029] In an example, the Al x Ga （1-x） N superlattice layer comprises 15-30 layers of Al x Ga （1-x） N layers.

[0030] In an example, the gradient transition layer 14 has a thickness of 100-150 nm.

[0031] In an example, the N-type diamond drift region has a thickness of 20-70 μm.

[0032] In this embodiment, the n-type diamond drift region has high voltage bearing strength and a breakdown field strength > 10 MV / cm, which is 10 times that of Si, and an electron mobility > 450 cm2 / V·s. The use of n-type diamond helps to dissipate heat, with a thermal conductivity of about 2000 W / m·K, allowing a current density > 500 A.

[0033] In this embodiment, the P-type base region 16 forms a PN junction with the drift region 15 (N-type diamond drift region), and a gate voltage forms an inversion layer.

[0034] In this embodiment, the N+ emitter layer 17, as a switch, has a contact resistance < 10-5 Ω·cm2 with a metal electrode (emitter).

[0035] In an example, the P-type base region 16 and the N+ emitter layer 17 are obtained by doping the drift region.

[0036] In an example, the semiconductor structure further comprises: an N-type buffer layer 13 disposed between the P+ implant layer 12 and the gradient transition layer 14.

[0037] The N-type buffer layer 13 can be used to suppress punch-through, with a thickness of 5-15 μm, which can cause the electric field of the drift region 15 to be trapezoidal in distribution (peak electric field < 3 MV / cm), and a reduction in stored charge of 30-50%.

[0038] Figure 2A structural schematic diagram of an IGBT device is provided for an embodiment of the present application. Referring to Figure 2 , comprising: A collector layer 11, a P+ injection layer 12, an N-type buffer layer 13, a gradient transition layer 14, a drift region 15, a P-type base region 16, and an N+ emitter layer 17 are sequentially stacked, and a gate dielectric layer 18, an emitter 19, and a gate 20.

[0039] The gradient transition layer 14 is configured to improve the lattice matching of the injection layer 12 and the drift region 15 during growth and to buffer thermal stress during growth; and the drift region 15 is an N-type diamond drift region.

[0040] In an example, the gate dielectric layer is The layer.

[0041] Figure 3 A flow chart of a preparation method of a semiconductor structure is provided for an embodiment of the present application. Referring to Figure 3 , comprising: S101, providing a collector layer.

[0042] The collector layer is a main electrode for current output, is connected to an external circuit, adopts a high-thermal-conductivity metal (such as Mo or Cu) to achieve a heat dissipation capacity of > 400 W / m·K, and has a contact resistance < 10-6Ω·cm2, thereby ensuring low-loss conduction.

[0043] In an example, the collector layer includes a high-purity molybdenum (Mo) substrate with a thickness of 80 μm to 150 μm, a surface that is chemically mechanically polished to a roughness < 0.5 nm, and a Ti / Pt / Au multi-layer metal (total thickness 200 nm) deposited thereon, with a contact resistance as low as 10-6Ω·cm2. Meanwhile, the excellent thermal conductivity (138 W / m·K) of molybdenum is utilized to achieve high-efficiency heat dissipation.

[0044] S102, forming a P+ injection layer on the collector layer.

[0045] In an example, step S102 includes: A hydride vapor phase epitaxy (HVPE) process is adopted, silane, propane, and borane are introduced into an environment with a temperature of 1600°C to 1800°C, and a SiC layer P+ injection layer is obtained by epitaxy on the surface of the collector layer.

[0046] In an example, the flow ratio of the silane, propane, and borane is 10:1:0.1.

[0047] In another example, step S102 includes: ​The P-type diamond layer is epitaxially obtained on the surface of the collector layer as the P+ injection layer by using the MPCVD process, with a microwave power of 5 kW, a pressure of 220 torr, and a temperature of 950 ℃.

[0048] In an example, the P-type diamond layer is longitudinally doped by The flow dynamic adjustment realizes the longitudinal doping gradient of the P-type diamond layer, and the growth rate is stabilized at 3 μm / h.

[0049] In another example, the P-type diamond layer is longitudinally doped by The flow ratio is controlled at 1:200:0.1, and the P-type diamond layer with a thickness of 6 μm and a doping concentration of is obtained as the P+ injection layer, and the room-temperature hole mobility reaches 1800 , which is more than 20 times higher than that of traditional Si-based materials.

[0050] S103, forming a gradient transition layer on the P+ injection layer; wherein the gradient transition layer is configured to improve the lattice adaptation of the injection layer and the drift region during the growth process and to buffer thermal stress during the growth process.

[0051] In an example, step S103 includes: The atomic layer deposition process is used to increase the pulse proportion of TMAl in the growth process and The Al x Ga （1-x） N superlattice layer is deposited as a buffer layer; wherein the Al x Ga （1-x） N superlattice layer includes a plurality of Al x Ga （1-x） N layers with increasing Al composition, and the value of x ranges from 0 to 1.

[0052] In an example, the gradient transition layer is made by using the atomic layer deposition (ALD) process, and the pulse time of the precursors TMA and is 0.1 s and 0.5 s, respectively, and an in-situ annealing step (750 ℃ / 30 s) is inserted between the layers to reduce the interface dislocation density to or less.

[0053] In another example, the gradient transition layer is deposited by using an ALD device, the pulse proportion of TMAl is gradually increased by 200 cycles, and after depositing 10 nm, the is introduced to perform 800 ℃ in-situ annealing, and the interface roughness is controlled to be within 0.3 nm.

[0054] S104, forming a drift region on the gradient transition layer; the drift region is an N-type diamond drift region. ​​

[0055] In an example, step S104 comprises: In an example, the N-type diamond layer is grown by a MPCVD process under a temperature of 850-950℃ and a pressure of 80-100 torr, and carbon source, hydrogen and hydrogen sulfide are introduced.

[0056] S105, forming a P-type base region on the drift region.

[0057] In an example, step S105 comprises: First, a patterned blocking layer is formed, which exposes the area to be ion implanted.

[0058] In an example, the blocking layer can be a photoresist layer.

[0059] Second, ion implantation is performed under the blocking effect of the blocking layer to form a P-type base region.

[0060] In an example, the implanted element can be aluminum, the implantation energy can be 100-200 keV, and the dose can be 1e15-1e16 cm-2. ~ .

[0061] In another example, the P-type base region is defined by a photoetching mask, and a deep 2.5 μm acceptor region with a concentration of 1e13 cm-3 is formed by aluminum ion implantation (implantation energy of 120 keV and dose of 1e15 cm-2), and the activation rate reaches 95% after laser-assisted annealing (laser wavelength of 355 nm and power density of 25 W / cm2), which avoids graphitization of the diamond layer due to high-temperature annealing.

[0062] Third, the photoresist layer is removed.

[0063] S106, forming an N+ emitter layer on the P-type base region.

[0064] In an example, step S106 comprises: First, a patterned blocking layer is formed, which exposes the area to be ion implanted.

[0065] As an example, the blocking layer can be a photoresist layer.

[0066] Second, ion implantation is performed under the blocking effect of the blocking layer to form an N+ emitter layer.

[0067] In an example, the N+ emitter is formed by ion implantation, and the implanted element can be phosphorus, the implantation energy can be 50-100 keV, and the dose can be 1e15-1e16 cm-2. ~ .​​​

[0068] In another example, the N⁺ emitter layer is implanted with phosphorus ions (implantation energy is 60keV, dose is ) combined with rapid thermal annealing (annealing temperature is 1000℃, annealing time is 30s) to achieve electron concentration> .

[0069] In this embodiment, the N+ emitter layer acts as a switch, and the contact resistance with the metal electrode (such as the emitter) is less than .

[0070] The third step is to remove the barrier layer.

[0071] Figure 4 This is a flow chart of another method for manufacturing a semiconductor structure provided by an embodiment of the present application. Figure 4 ,include: S201. Provide a collector layer.

[0072] See S101.

[0073] S202 , forming a P+ injection layer on the collector layer.

[0074] See S102.

[0075] S203 , forming an N-type buffer layer on the P+ injection layer.

[0076] As an example, the N-type buffer layer is made of nitrogen-doped 4H-SiC with a thickness of 1.2 μm and a doping concentration of , grown at 1550°C by hydride vapor phase epitaxy (HVPE), the V / III ratio was precisely controlled to 280, forming a steep doping gradient to suppress electric field punch-through.

[0077] S204 , forming a gradient transition layer on the N-type buffer layer; wherein the gradient transition layer is configured to improve the lattice adaptability between the injection layer and the drift region during the growth process and to buffer thermal stress during the growth process.

[0078] See S103.

[0079] S205 , forming a drift region on the gradient transition layer; the drift region is an N-type diamond drift region.

[0080] See S104.

[0081] S206 , forming a P-type base region on the drift region.

[0082] See S105.

[0083] S207 , forming an N+ emitter layer on the P-type base region.

[0084] See S106.

[0085] Figure 5 A flow chart of a method for manufacturing an IGBT device is provided for an embodiment of the present application. See Figure 5 , comprising: S301, providing a collector layer.

[0086] See S101.

[0087] S302, forming a P+ injection layer on the collector layer.

[0088] See S102.

[0089] S303, forming an N-type buffer layer on the P+ injection layer.

[0090] See step S203.

[0091] S304, forming a gradient transition layer on the N-type buffer layer; wherein the gradient transition layer is configured for improving lattice matching between the injection layer and the drift region during growth and for thermal stress buffering during growth.

[0092] See S103.

[0093] S305, forming a drift region on the gradient transition layer; the drift region is an N-type diamond drift region.

[0094] See S104.

[0095] S306, forming a P-type base region on the drift region.

[0096] See S105.

[0097] S307, forming an N+ emitter layer on the P-type base region.

[0098] See S106.

[0099] S308, manufacturing a gate dielectric layer.

[0100] As an example, the gate dielectric layer can be an oxide layer, and the manufacturing method can select an atomic layer deposition process for preparation.

[0101] S309, manufacturing a collector electrode.

[0102] As an example, the emitter is a metal electrode, and the manufacturing method can select an electron beam evaporation process for preparation.

[0103] S310, manufacturing a gate electrode.

[0104] As an example, the gate electrode is a metal electrode, and the manufacturing method can select an electron beam evaporation process for preparation.

[0105] After the electrode fabrication, the device was packaged with AuGe / Ni solder in a vacuum reflow furnace, with the peak temperature controlled at 280℃ to avoid material thermal degradation.

[0106] The tested device has a turn-on voltage drop of 1.05V (current density of 100 mA / cm2) at room temperature, a breakdown voltage of 12.8kV, a turn-off time of only 22ns, and a power loss reduced by 62% compared to traditional Si-IGBT. After 1000 hours of continuous operation at 200℃, the threshold voltage drift is <5%, showing excellent reliability.

[0107] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present application, and not to limit it; although the present application has been described in detail with reference to the foregoing examples, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing examples, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a collector layer, a P+ injection layer, a gradient transition layer, a drift region, a P-type base region and an N+ emission layer which are sequentially stacked; the gradient transition layer is configured to improve the lattice matching degree of the injection layer and the drift region during growth and to buffer thermal stress during growth; the drift region is an N-type diamond drift region.

2. The semiconductor structure of claim 1, wherein, The gradient transition layer comprises Al x Ga （1-x） N superlattice layer, the Al x Ga （1-x） N superlattice layer comprises multiple Al x Ga （1-x） N layers with increasing Al composition, and x ranges from 0 to 1.

3. The semiconductor structure of claim 2, wherein, The Al x Ga （1-x） N superlattice layer has 15 to 30 layers. x Ga （1-x） N layers.

4. The semiconductor structure of claim 2, wherein, The thickness of the gradient transition layer is 100 nm to 150 nm.

5. The semiconductor structure of claim 1, wherein, The thickness of the N-type diamond drift region is 20 μm to 70 μm.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that The semiconductor structure further comprises: an N-type buffer layer disposed between the P+ injection layer and the gradient transition layer.

7. A method of fabricating a semiconductor structure, the method comprising: The method comprises: providing a collector layer; forming a P+ injection layer on the collector layer; forming a gradient transition layer on the P+ injection layer; wherein the gradient transition layer is configured to improve the lattice matching degree of the injection layer and the drift region during growth and to buffer thermal stress during growth; forming a drift region on the gradient transition layer; the drift region is an N-type diamond drift region; forming a P-type base region on the drift region; forming an N+ emission layer on the P-type base region.

8. The semiconductor structure of claim 7, wherein, The step of forming the gradient transition layer on the P+ injection layer comprises: The atomic layer deposition process is adopted, TMAl and TMAl pulse proportion in the middle of the growth process is increased, and Al x Ga （1-x） N superlattice layer is deposited as a buffer layer; wherein the Al x Ga （1-x） N superlattice layer comprises a plurality of Al x Ga （1-x） N layers with increasing Al composition, and the value range of x is 0-1.

9. The semiconductor structure of claim 7, wherein, The step of forming the drift region on the gradient transition layer comprises: using an MPCVD process, under the conditions of a temperature of 850 ℃ to 950 ℃ and a pressure of 80 torr to 100 torr, introducing a carbon source, hydrogen and hydrogen sulfide to grow an N-type diamond layer as the drift region.

10. The semiconductor structure according to any one of claims 7 to 9, characterized in that The method further comprises: forming an N-type buffer layer between the P+ injection layer and the gradient transition layer.

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