An epitaxial structure and a method of fabricating the same

Abstract

The application provides an epitaxial structure and a preparation method thereof. The epitaxial structure is deposited and grown by using an MOCVD method. The epitaxial structure comprises a substrate, an N-type semiconductor layer, a QW-QB-QDs coupling layer and a P-type semiconductor layer which are sequentially stacked from bottom to top. The QW-QB-QDs coupling layer comprises at least one period of a QW layer, a QB layer and a QDs layer which are grown from bottom to top. The QW layer is an InGaN carrier accumulation layer. The QB layer is a GaN-AlGaN-GaN tunnel barrier layer. The QDs layer is an InGaN quantum dot layer. The QW-QB-QDs coupling structure is arranged, the problem of low carrier injection efficiency to the QDs is solved, the growth morphology and stress of the QDs can be adjusted, the crystal quality of the QDs is improved, and the light emitting efficiency of the device is effectively improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to an epitaxial structure and its preparation method. Background Technology

[0002] III-V GaN-based materials have attracted widespread attention and application in electrical and optical fields due to their excellent physical and chemical properties (large bandgap, high breakdown electric field, high electron saturation mobility, etc.), such as the currently popular Micro and Mini LEDs. However, in actual semiconductor structure design, most adopt heteroepitaxial growth, which inevitably leads to problems such as strong polarization electric fields and deterioration of material crystal quality, limiting further improvement of device luminous efficiency. QDs (Quantum Dots, referring to semiconductor crystals with nanometer-scale dimensions) have attracted widespread attention due to their strong quantum confinement benefits and ability to effectively weaken polarization electric fields and improve carrier radiative recombination power. However, because their crystal quality is difficult to control, their size, density, and other properties are often randomly distributed, severely affecting carrier transport and recombination, greatly reducing device luminous efficiency. Therefore, adjusting the growth morphology and stress of QDs, improving their crystal quality, and reducing carrier transport imbalance have become urgent problems to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide an epitaxial structure and its fabrication method, which sets up a QW-QB-QDs coupling structure, solves the problem of low efficiency in directly injecting carriers into QDs, and can adjust the growth morphology and stress of QDs, improve the crystal quality of QDs, and effectively improve the luminous efficiency of the device.

[0004] To achieve the above objectives, the solution of the present invention is as follows:

[0005] An epitaxial structure is provided, comprising a substrate, an N-type semiconductor layer, a QW-QB-QDs coupling layer, and a P-type semiconductor layer stacked sequentially from bottom to top;

[0006] The QW-QB-QDs coupling layer includes a QW layer, a QB layer, and a QDs layer grown from bottom to top for at least one cycle. The QW layer is an InGaN carrier storage layer, the QB layer is a GaN-AlGaN-GaN tunneling barrier layer, and the QDs layer is an InGaN quantum dot layer.

[0007] The thickness of the QW layer is W, and its In component content is X. The thickness of the QB layer is D, wherein X / 5≤D / W≤3X.

[0008] Optionally, the number of growth cycles for the QW-QB-QDs coupling layer is 2-5, including endpoint values.

[0009] Optionally, in each cycle of the QW-QB-QDs coupling layer, a GaN capping layer is provided on the QDs layer.

[0010] Optionally, a low-temperature nucleation layer and a buffer layer are further provided between the substrate and the N-type semiconductor layer, wherein the buffer layer is an undoped GaN layer; a low-temperature N-type GaN layer and an SSL layer are further provided between the N-type semiconductor layer and the QW-QB-QDs coupling layer, wherein the SSL layer is a superlattice structure of InGaN / GaN grown for 5-10 cycles, including endpoint values; a low-temperature P-type GaN layer is further provided between the QW-QB-QDs coupling layer and the P-type semiconductor layer.

[0011] This application also provides a method for preparing the above-mentioned epitaxial structure, including:

[0012] A substrate is provided, and an N-type semiconductor layer, a QW-QB-QDs coupling layer, and a P-type semiconductor layer are grown sequentially from bottom to top on the substrate using the MOCVD method;

[0013] The QW-QB-QDs coupling layer includes a QW layer, a QB layer, and a QDs layer grown from bottom to top for at least one cycle. The QW layer is an InGaN carrier storage layer, the QB layer is a GaN-AlGaN-GaN tunneling barrier layer, and the QDs layer is an InGaN quantum dot layer. The QDs layer is grown using a method that interrupts the growth of Ga and In sources and controls the alternation of high and low V / III ratios.

[0014] Optionally, during the growth of the QDs layer, an In source, a Ga source, and an N source are introduced to grow InGaN with a thickness of 0.5~2.5 nm. Then, the In source and Ga source are interrupted at time t' to allow the adsorbed atoms to migrate on the surface and reach the most energy-optimal position. After approaching thermodynamic equilibrium, the low V / III ratio at time t1 and the high V / III ratio at time t2 are controlled in a cyclic manner to complete the growth of the QDs layer. The V / III ratio is the molar ratio of the N source and the Ga source.

[0015] Optionally, when growing QDs layers, t' is 10-30s, t1 and t2 are both 3-10s, t1 / t2 is 0.3-3; 2000 < high V / III ratio ≤ 8000, 500 ≤ low V / III ratio ≤ 2000, and the number of alternation cycles between high and low V / III ratios is 3-10, including endpoint values.

[0016] Optionally, after the QDs layer is grown, a GaN capping layer is grown on the QDs layer to complete the growth of one cycle of the QW-QB-QDs coupling layer.

[0017] Optionally, when growing the QW and QB layers, an In source, a Ga source, and an N source are first introduced to grow an InGaN carrier storage layer with a thickness of W and an In content of X; then, an H2 and an Al source are introduced to grow a GaN-AlGaN-GaN tunneling barrier layer, wherein the thickness of the QB layer is D, and X / 5 ≤ D / W ≤ 3X.

[0018] Optionally, during the growth of AlGaN in the QB layer, the influx flow rate of Al first gradually increases and then gradually decreases, while the influx flow rate of H2 first gradually decreases and then gradually increases.

[0019] After adopting the above solution, the beneficial effects of the present invention are as follows:

[0020] 1. The active region of this application is provided with a QW-QB-QDs coupling structure. The QW layer serves as a carrier storage layer, which can confine carriers to the maximum extent. At the same time, through the tunneling effect of the QB layer, carriers can be injected into the QDs layer, thereby improving the carrier injection efficiency and solving the problem of low efficiency of directly injecting carriers into the QDs layer, thus effectively improving the luminous efficiency of the device.

[0021] 2. The QB layer of this application adopts a GaN-AlGaN-GaN structure. While protecting the crystal quality of the QW layer, its band structure characteristics can be used to increase the conduction band barrier height of AlGaN, thereby reducing electron overflow and further improving luminescence efficiency. In addition, the growth process of GaN is treated with H2, and the AlGaN gradient is treated with Al and H2, which can suppress dislocation propagation, reduce interface defects, and improve the crystal quality of the material.

[0022] 3. The QDs layer of this application employs a growth method that involves interrupting the growth of Ga and In sources and controlling the alternation of high and low V / III ratios during growth. Interrupting the growth by introducing Ga and In sources allows atoms sufficient time to migrate on the surface, reaching their most energy-optimal positions and approaching thermodynamic equilibrium, thereby releasing stress and reducing QCSE (quantum confinement Stark effect). Simultaneously, controlling the low V / III ratio first promotes three-dimensional growth, forming a high-density nucleation site, and then increasing the V / III ratio to promote two-dimensional growth. This alters the size, dimensions, and density of the QDs layer, reshaping its morphology and improving its crystal quality. Therefore, this application's control of alternating high and low V / III ratios enhances quantum confinement and improves the device's luminous efficiency.

[0023] 4. The QW-QB-QDs coupling layer can also be used to construct a multi-period structure, further expanding the above-mentioned beneficial effects. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the extensional structure of the present invention.

[0025] Figure 2 This is a schematic diagram of the conduction band of the QW-QB-QDs coupling layer of the present invention.

[0026] Figure 3 This is a schematic diagram of the growth path of the QW-QB-QDs coupling layer of the present invention.

[0027] Figure 4 This is a flowchart of the preparation method of the present invention.

[0028] Label Explanation:

[0029] 1. Substrate; 2. Buffer layer; 3. N-type semiconductor layer; 4. Low-temperature N-type GaN layer; 5. SSL layer; 6. QW-QB-QDs coupling layer; 7. Low-temperature P-type GaN layer; 8. P-type semiconductor layer. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. The scope value described in this invention includes two endpoint values.

[0031] like Figure 1 As shown, this application provides an epitaxial structure comprising a substrate 1, an N-type semiconductor layer 3, a QW-QB-QDs coupling layer 6, and a P-type semiconductor layer 8 stacked sequentially from bottom to top. The QW-QB-QDs coupling layer 6 comprises a QW layer, a QB layer, and a QDs layer grown from bottom to top for at least one cycle. The QDs layer is an InGaN quantum dot layer, and the QW layer is an InGaN carrier retention layer. As a carrier retention layer, it can maximally confine carriers. Simultaneously, through the tunneling effect of the QB layer, carriers can be injected into the QDs layer, improving the carrier injection efficiency and solving the problem of low efficiency when directly injecting carriers into the QDs layer, thus effectively improving the luminous efficiency of the device. The QB layer is a GaN-AlGaN-GaN tunneling barrier layer. While protecting the crystal quality of the QW layer, its band structure characteristics can be used to increase the conduction band barrier height of AlGaN, reducing electron overflow and further improving luminous efficiency.

[0032] Optional, such as Figure 2As shown, the QW layer has a thickness of W, a potential well depth of H, and an In content of X; the QB layer has a thickness of D. Increasing the potential well depth H and thickness W of the QW layer enhances the carrier confinement capability, thereby increasing carrier injection into the QDs layer; simultaneously, decreasing the tunneling barrier thickness D of the QB layer increases the tunneling probability. However, increasing W and H exacerbates the QCSE (quantum confinement Stark effect), and the In content X is positively correlated with H (X∝H). Therefore, to balance the carrier confinement strength and the suppression of QCSE, the constraint condition X / 5 ≤ D / W ≤ 3X must be satisfied. Furthermore, the value of H needs to be indirectly determined by precisely controlling X and combining it with bandgap testing.

[0033] Optionally, the QW-QB-QDs coupling layer 6 can also be constructed with a multi-period structure to further amplify the above-mentioned beneficial effects. In a preferred embodiment, the QW-QB-QDs coupling layer 6 is constructed with 2-5 periods.

[0034] Preferred, such as Figure 3 As shown, in each cycle of the QW-QB-QDs coupling layer 6, a GaN capping layer (Cap) can be set on the QDs layer. The GaN capping layer can protect the QDs layer from damage and complete the growth of a single cycle.

[0035] Optionally, the N-type semiconductor layer 3 is an N-type doped GaN layer, which serves to provide an N-type contact layer. Its growth thickness is 1-2 nm, and the doping concentration is 1-5 × 10⁻⁶. 19 cm -3 The p-type semiconductor layer 8 is p-type doped GaN, which serves to provide p-type contacts, and its doping concentration is 5-10 × 10⁻⁶. 19 cm -3 .

[0036] A low-temperature nucleation layer (not shown in the figure) and a buffer layer 2 are also provided between the substrate 1 and the N-type semiconductor layer 3. The low-temperature nucleation layer is undoped GaN with a thickness of 15-25nm, and the buffer layer 2 is an undoped GaN layer with a thickness of 2.0-2.5μm.

[0037] Between the N-type semiconductor layer 3 and the QW-QB-QDs coupling layer 6, there is also a low-temperature N-type GaN layer 4 and an SSL layer 5. The low-temperature N-type GaN layer 4 can form V-pits by utilizing the growth difference of Ga at different polarity surfaces at low temperature. The SSL layer 5 is a superlattice structure of InGaN / GaN grown for 5-10 cycles, which can control the spatial distribution of V-pits and release stress.

[0038] A low-temperature P-type GaN layer 7 is further disposed between the QW-QB-QDs coupling layer 6 and the P-type semiconductor layer 8, the doping concentration of the low-temperature P-type GaN layer 7 being 1-5 × 10⁻⁶. 19 cm -3 .

[0039] This application also provides a method for fabricating the above-mentioned epitaxial structure, specifically employing metal-organic chemical vapor deposition (MOCVD) to sequentially grow a low-temperature nucleation layer, a buffer layer 2, an N-type semiconductor layer 3, a low-temperature N-type GaN layer 4, an SSL layer 5, a QW-QB-QDs coupling layer 6, a low-temperature P-type GaN layer 7, and a P-type semiconductor layer 8 on a substrate 1 from bottom to top. The QW-QB-QDs coupling layer 6 comprises at least one cycle of QW, QB, and QDs layers grown from bottom to top. The QW layer is an InGaN carrier storage layer, the QB layer is a GaN-AlGaN-GaN tunneling barrier layer, and the QDs layer is an InGaN quantum dot layer.

[0040] Optionally, the substrate 1 includes, but is not limited to, a sapphire substrate. In this embodiment, a sapphire substrate is used as an example. Trimethyl / ethyl gallium™Ga / TEGa, trimethylaluminum™Al, and ammonia NH3 are used as Ga source, Al source, and N source, respectively, and N2 is used as carrier gas. The N-type and P-type doping sources are silane SiH4 and magnesium cerene CP2Mg, respectively.

[0041] Please refer to Figure 4 The preparation method includes the following steps:

[0042] S1. Growing a low-temperature nucleation layer on substrate 1, including:

[0043] The sapphire substrate 1 is placed in the MOCVD reaction chamber and hydrogenated with high-purity hydrogen gas at a high temperature of 1100℃ for 5-10 minutes. Then, the temperature is lowered to 800-900℃ and TEGa source and N source are introduced to grow a 15-25nm thick undoped GaN low-temperature nucleation layer.

[0044] S2. A buffer layer 2 is grown on the low-temperature nucleation layer, comprising:

[0045] After the low-temperature nucleation layer is grown, the temperature is raised to 1000-1100℃, the TEGa source is turned off, and the TMGa source is introduced to grow a 2.0-2.5μm thick undoped GaN buffer layer 2. The purpose of growing the buffer layer 2 is to reduce the lattice mismatch between the sapphire substrate 1 and the subsequent growth materials by growing a high-quality GaN layer.

[0046] S3. Growing an N-type semiconductor layer 3 on the buffer layer 2, including:

[0047] After the buffer layer 2 is grown, silane is introduced to grow a 1-2 μm thick Si-doped N-type semiconductor layer 3, specifically a GaN layer with a doping concentration of 1-5 × 10⁻⁶. 19 cm -3 The purpose of growing the N-type semiconductor layer 3 is to provide N-type contacts.

[0048] S4. Growing a low-temperature N-type GaN layer 4 on the N-type semiconductor layer 3, including:

[0049] After growing the N-type semiconductor layer 3, the temperature is lowered to 700-800℃ to grow a low-temperature N-type GaN layer 4. By utilizing the difference in growth of Ga on different polarity surfaces at low temperature, V-pits can be formed.

[0050] S5. Grow the SSL layer 5 on the low-temperature N-type GaN layer 4, including:

[0051] After growing the low-temperature N-type GaN layer 4, the temperature is raised to 800-850℃, and In source and Ga source are introduced to alternately grow 5-10 cycles of InGaN / GaN superlattice structure, which is the SSL layer 5. It can control the spatial distribution of V-pits and release stress.

[0052] S6. Grow a QW-QB-QDs coupling layer 6 on the SSL layer 5, including:

[0053] After growing the SSL layer 5, an In source, a TEGa source, and an N source are introduced, and the temperature is lowered to 700-800℃ to grow an InGaN carrier storage layer, i.e., the QW layer, with a thickness of W, a potential well depth of H, and an In composition content of X. Then, the temperature is raised to 800-850℃, and H2 and Al are introduced to grow a GaN-AlGaN-GaN tunneling barrier layer, i.e., the QB layer, with an overall thickness of D.

[0054] Since the QW layer acts as a carrier storage layer, it can confine carriers. Through tunneling in the QB layer, carriers can be injected into the QDs layer. Increasing both W and H increases carrier injection into the QDs layer. Simultaneously, decreasing the tunneling barrier thickness D of the QB layer increases the tunneling probability. However, increasing W and H exacerbates the QCSE (quantum confinement Stark effect), and the In content X is positively correlated with H (X∝H). Therefore, to balance the carrier confinement strength and the suppression of QCSE, the constraint condition X / 5 ≤ D / W ≤ 3X must be satisfied. Furthermore, the value of H needs to be indirectly determined by precisely controlling X and combining it with bandgap measurements.

[0055] Furthermore, during the growth of the QB layer in AlGaN, the flux of Al gradually increases and then gradually decreases, while the flux of H2 is the opposite of that of Al, gradually decreasing and then gradually increasing. This setting can suppress dislocation propagation, reduce interface defects, and improve the crystal quality of the material.

[0056] Then, QDs layers are grown, specifically using a growth method that alternates between interrupted Ga and In sources and controlled high and low V / III ratios, such as... Figure 3 As shown, the temperature is first lowered to 600-700℃, and Ga, In, and N sources are introduced to grow a 0.5-2.5 nm InGaN layer. This InGaN layer serves as a template layer before QDs growth, essentially acting as a substrate layer to facilitate subsequent QDs growth. Then, the Ga and In sources are interrupted for a time t', allowing adsorbed atoms to migrate to their optimal energy positions and approach thermodynamic equilibrium, releasing stress and reducing QCSE. However, the QDs layer in this state exhibits a disordered distribution, with uncontrollable size, dimensions, and density. Therefore, a growth method alternating between high and low V / III (N / Ga source) flux ratios is employed to reshape the morphology and improve the QDs layer. The crystal quality is determined by the V / III ratio, which is the molar ratio of the N source to the Ga source. Specifically, a lower V / III ratio is first used, which can be 500-2000 (inclusive) to promote three-dimensional growth and form high-density nucleation sites, with a growth time of t1. Then, the V / III ratio is increased, which can be 2000-8000 (exclusive) to promote two-dimensional growth and change the size, dimensions, and density of the QDs layer, with a growth time of t2. This cycle of growth can enhance the quantum confinement effect and improve the luminous efficiency of the device.

[0057] Specifically, t' is 10-30s, t1 and t2 are both 3-10s. By adjusting the ratio of t1 / t2, a QDs layer with uniform size and high density can be obtained. The ratio of t1 / t2 is preferably 0.3-3. In addition, the number of alternating cycles of high and low V / III ratios is preferably 3-10.

[0058] After growing the QDs layer, a GaN cap layer (Cap) is grown to ensure that the QDs layer is not damaged, completing a single growth cycle. The above steps can then be repeated to grow multiple cycles of the QW-QB-QDs coupling layer, which can increase the beneficial effects of the QW-QB-QDs coupling layer. The preferred number of growth cycles is 2-5.

[0059] S7. A low-temperature p-type GaN layer 7 is grown on the QW-QB-QDs coupling layer 6, including:

[0060] After growing the QW-QB-QDs coupling layer 6, the temperature was increased to 700-800℃, and the P-type doping concentration was controlled to be 1-5×10⁻⁵. 19 cm -3 7. Low-temperature P-type GaN layer growth.

[0061] S8. Growing a P-type semiconductor layer 8 on a low-temperature P-type GaN layer 7, including:

[0062] After growing the low-temperature p-type GaN layer 7, a p-type doping source, Mg2+, was introduced, and the layer was annealed at 850-900℃ for 20-30 minutes under a N2 atmosphere, with a growth doping concentration of 5-10×10⁻⁶. 19 cm -3 The P-type semiconductor layer 8 is grown under a pressure of 100-300 torr. The purpose of growing the P-type semiconductor layer 8 is to provide P-type contacts.

[0063] It is worth noting that the thicknesses of the substrate 1, buffer layer 2, N-type semiconductor layer 3, low-temperature N-type GaN layer 4, SSL layer 5, QW-QB-QDs coupling layer 6, low-temperature P-type GaN layer 7, and P-type semiconductor layer 8 shown in the accompanying drawings are merely examples and do not represent their actual thicknesses. Furthermore, the actual proportions between the substrate 1, buffer layer 2, N-type semiconductor layer 3, low-temperature N-type GaN layer 4, SSL layer 5, QW-QB-QDs coupling layer 6, low-temperature P-type GaN layer 7, and P-type semiconductor layer 8 are not as shown in the drawings and are for reference only.

[0064] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0065] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An epitaxial structure, characterized by: The substrate, the N-type semiconductor layer, the QW-QB-QDs coupling layer and the P-type semiconductor layer are sequentially stacked from bottom to top. The QW-QB-QDs coupling layer includes at least one period of QW layer, QB layer and QDs layer grown from bottom to top, the QW layer is an InGaN carrier storage layer, the QB layer is a GaN-AlGaN-GaN tunnel barrier layer, and the QDs layer is an InGaN quantum dot layer. The thickness of the QW layer is W, and the In content of the QW layer is X, the thickness of the QB layer is D, and X / 5≤D / W≤3X.

2. An epitaxial structure as claimed in claim 1, characterized in that: The number of growth periods of the QW-QB-QDs coupling layer is 2-5, including the end point.

3. An epitaxial structure as claimed in claim 1, characterized in that: A GaN cap layer is arranged on the QDs layer in each period of the QW-QB-QDs coupling layer.

4. An epitaxial structure as claimed in claim 1, characterized in that: A low-temperature nucleation layer and a buffer layer are further arranged between the substrate and the N-type semiconductor layer, the buffer layer is an undoped GaN layer, a low-temperature N-type GaN layer and an SSL layer are further arranged between the N-type semiconductor layer and the QW-QB-QDs coupling layer, the SSL layer is a superlattice structure of InGaN / GaN with 5-10 growth periods, including the end point, and a low-temperature P-type GaN layer is further arranged between the QW-QB-QDs coupling layer and the P-type semiconductor layer.

5. A method of producing an epitaxial structure as claimed in any one of claims 1-4, characterized in that The substrate, the N-type semiconductor layer, the QW-QB-QDs coupling layer and the P-type semiconductor layer are sequentially grown from bottom to top on the substrate by MOCVD method. The QW-QB-QDs coupling layer includes at least one period of QW layer, QB layer and QDs layer grown from bottom to top, the QW layer is an InGaN carrier storage layer, the QB layer is a GaN-AlGaN-GaN tunnel barrier layer, and the QDs layer is an InGaN quantum dot layer, the QDs layer is grown by interrupting Ga source and In source and alternating high and low V / III ratio in growth. When the QDs layer is grown, In source, Ga source and N source are introduced, 0.5-2.5nm InGaN is grown, then In source and Ga source are interrupted for t' time, so that the adsorbed atoms migrate on the surface, after reaching a thermodynamic equilibrium state, low V / III ratio for t1 time and high V / III ratio for t2 time are controlled in turn to complete the growth of the QDs layer; wherein t' is 10-30s, including the end point, t1 and t2 are both 3-10s, including the end point, t1 / t2 is 0.3-3, including the end point; the V / III ratio is the molar ratio of N source and Ga source, 2000 6. The method of claim 5, wherein: After the growth of the QDs layer is completed, a GaN cap layer is grown on the QDs layer to complete the growth of one period of QW-QB-QDs coupling layer.

7. The method of claim 5, wherein: ​ 8. The method of claim 5, wherein: In the growth of the QW layer and the QB layer, firstly, the In source, the Ga source and the N source are introduced, the InGaN carrier storage layer is grown, the growth thickness is W, and the In component content is X; then, the H2 and the Al source are introduced, the GaN-AlGaN-GaN tunnel barrier layer is grown, and the thickness of the QB layer is D, wherein, X / 5≤D / W≤3X.

9. The method of claim 8, wherein: In the growth of the QB layer, the introduction flow of Al is gradually increased first and then gradually decreased, and the introduction flow of H2 is gradually decreased first and then gradually increased.

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