Apparatus and method for manufacturing display device, and electronic device

Abstract

The invention relates to an apparatus and method for manufacturing a display device, and an electronic device. The apparatus for manufacturing a display device includes: an alignment unit; a carrier disposed on the alignment unit, in which the carrier includes an accommodating portion in which the wafer is accommodated; the pressing unit is arranged on the carrier; a first vision device disposed on the carrier on one side of the pressing unit; and a controller controlling alignment of the wafer and the carrier.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0051497, filed on April 17, 2024, and all benefits accruing therefrom, the contents of which are incorporated herein in their entirety. TECHNICAL FIELD

[0002] Embodiments of the disclosure relate to an apparatus for manufacturing a display device and a method of manufacturing a display device. BACKGROUND

[0003] Recently, as electronic devices and display devices capable of implementing extended reality are developed, interest in extended reality is increasing. Extended reality includes virtual reality (VR), augmented reality (AR), and mixed reality (MR).

[0004] Various display devices are emerging to implement extended reality. For example, a head-mounted display (HMD) and AR glasses are examples of display devices for implementing extended reality.

[0005] Recently, due to a trend toward weight reduction and miniaturization, research on small displays is actively being conducted. Examples of small displays or electronic devices including small displays include smart watches, watch phones, head-up displays (HUDs) in cars, and Internet of Things (IOT) devices.

[0006] Display devices for implementing extended reality can be provided in a compact manner and disposed close to a user's eyes to magnify and display a video or an image using a plurality of lenses. Further, even in the case of small displays, it can be desirable to display a large amount of information on a small screen and provide a clear video or image. Accordingly, display devices for implementing extended reality and small displays need to provide a high-resolution image, for example, an image having a resolution of 3000 pixels per inch (PPI) or more.

[0007] To this end, an organic light emitting diode on silicon (OLEDoS) that is a high-resolution small organic light emitting display device is used. The OLEDoS is an image display device in which an organic light emitting diode (OLED) is disposed on a semiconductor wafer substrate including a complementary metal-oxide semiconductor (CMOS). SUMMARY

[0008] Embodiments of the disclosure provide an apparatus for manufacturing a display device and a method of manufacturing a display device, which includes a carrier accommodating a wafer so that a display process apparatus using a conventional mother substrate can be used in a display process using a wafer.

[0009] Embodiments of the disclosure also provide an apparatus for manufacturing a display device and a method of manufacturing a display device in which alignment accuracy between a carrier and a wafer is improved.

[0010] Embodiments of the disclosure also provide an apparatus for manufacturing a display device and a method of manufacturing a display device, in which damage to a wafer is minimized when the wafer is separated from a carrier.

[0011] However, embodiments of the disclosure are not limited to the embodiments set forth herein. The above and other embodiments of the disclosure will become more apparent by describing in detail embodiments thereof with reference to the accompanying drawings, as follows.

[0012] According to embodiments of the disclosure, an apparatus for manufacturing a display device includes an alignment unit, a carrier disposed on the alignment unit, wherein the carrier includes an accommodation portion in which a wafer is accommodated, a pressing unit disposed on the carrier, a first vision device disposed on the carrier at one side of the pressing unit, and a controller that controls alignment of the wafer and the carrier.

[0013] In an embodiment, the carrier can further include a first alignment mark disposed at one side of the accommodation portion, and the first vision device can capture an image of the first alignment mark of the carrier and a second alignment mark of the wafer.

[0014] In an embodiment, the first vision device can include a camera, and the number of the camera in the first vision device can be equal to the number of the first alignment mark in the carrier.

[0015] In an embodiment, the carrier can further include a bonding portion disposed on a bottom surface of the accommodation portion, the bonding portion can be disposed between the wafer and the bottom surface of the accommodation portion, and the wafer and the carrier can be bonded to each other through the bonding portion.

[0016] In an embodiment, the bonding portion can include an adhesive chuck or an electrostatic chuck.

[0017] In an embodiment, the carrier can further include a buffer portion disposed on a portion of the bottom surface of the accommodation portion other than a portion on which the bonding portion is disposed, and a step compensation portion disposed under the bonding portion, wherein a thickness of the buffer portion can be equal to a sum of a thickness of the bonding portion and a thickness of the step compensation portion.

[0018] In an embodiment, the alignment unit can include a pin extending in a direction toward the carrier, the carrier can further include a pin hole disposed in a lower portion of the accommodation portion, and the pin can be moved through the pin hole.

[0019] In an embodiment, the wafer can be mounted on the pin.

[0020] In an embodiment, the alignment unit can further include a pin driver disposed under the pin, and the pin driver can include a vertical driver and a rotation driver.

[0021] In an embodiment, the alignment unit can further include a first pressure sensor disposed under the pin, and the first pressure sensor can measure a pressing force applied to the pin when separating the wafer from the carrier.

[0022] In an embodiment, the pin can be provided in a plurality to include a plurality of pins, and the first pressure sensor can be provided in a plurality one-to-one corresponding to the plurality of pins.

[0023] In an embodiment, the pressing unit can include a pressing member disposed on a first surface of the pressing unit facing the carrier, and a second pressure sensor disposed between the first surface and the pressing member, and the second pressure sensor can measure a pressing force applied to the pressing member when the carrier and the wafer are bonded to each other.

[0024] In an embodiment, the first vision device can capture a first image after the initial alignment of the wafer and before the initial pressing of the wafer, and capture a second image after the initial pressing of the wafer, the controller can include an alignment correction value calculation unit, wherein the alignment correction value calculation unit can calculate a correction value by comparing the first image with the second image, and the alignment unit can align the wafer by offsetting the correction value during the secondary pressing of the wafer.

[0025] In an embodiment, the apparatus can further include a second vision device disposed on the carrier, wherein the second vision device can capture an image of the carrier and the alignment unit.

[0026] In an embodiment, the apparatus can further include a carrier transfer unit to place the carrier on the alignment unit.

[0027] In an embodiment, the apparatus can further include a wafer transfer unit to place the wafer on the carrier.

[0028] In an embodiment, the controller can include an alignment processing unit, the alignment processing unit can provide a driving signal to the wafer transfer unit, the wafer transfer unit can place the wafer on the carrier based on the driving signal, the first vision device can provide a captured image of the carrier and the wafer to the alignment processing unit, and the alignment processing unit can provide the driving signal to the wafer transfer unit again based on the captured image to align the wafer with the carrier in real time.

[0029] In an embodiment, in a plan view, the carrier can have a quadrilateral shape, and the wafer can have a circular shape.

[0030] According to an embodiment of the disclosure, a method of manufacturing a display device includes performing a first alignment process including aligning a wafer with a reference point of a carrier, performing a wafer first pressing process including pressing the wafer, performing a first deformation inspection process including measuring a first degree of deformation of the wafer and the carrier, performing a separation process including separating the wafer from the carrier, performing a second alignment process including aligning the wafer with the carrier, performing a wafer second pressing process including pressing the wafer, and performing a second deformation inspection process including measuring a second degree of deformation of the wafer and the carrier, wherein the performing of the second alignment process includes aligning the wafer by offsetting a correction value from the reference point by using the first degree of deformation measured in the first deformation inspection process as the correction value.

[0031] In an embodiment, when, in the second deformation inspection process, the second degree of deformation is less than or equal to a threshold value, the method can end.

[0032] In an embodiment, when, in the second deformation inspection process, the second degree of deformation exceeds the threshold value, the method can further include performing a correction value recalculation and wafer realignment process including recalculating a correction value and realigning the wafer.

[0033] In an embodiment, the performing of the correction value recalculation and wafer realignment process can include performing a correction value recalculation process including recalculating a correction value, performing a wafer realignment process including realigning the wafer, performing a process including pressing the wafer again, and performing a deformation re-inspection process including measuring a third degree of deformation of the wafer and the carrier.

[0034] In an embodiment, the performing of the correction value recalculation process can include calculating a correction value of a current wafer using correction values of previous wafers.

[0035] In an embodiment, when, in the deformation re-inspection process, the third degree of deformation is less than or equal to a threshold value, the method of manufacturing a display device can end.

[0036] In an embodiment, when, in the deformation re-inspection process, the third degree of deformation exceeds the threshold value, the method can further include performing the correction value recalculation and wafer realignment process again.

[0037] In an embodiment, each of the correction values of the previous wafers can include at least one sub-correction value, and the number of the sub-correction values of the correction values of the previous wafers is equal to the number of repetitions of the performing of the correction value recalculation process.

[0038] In an embodiment, a final sub-correction value among the sub-correction values of each of the correction values of the previous wafers can be the correction value of the previous wafer.

[0039] In an embodiment, in each of the execution of the wafer primary pressing process and the execution of the wafer secondary pressing process, the pressing force applied when the wafer is combined with the carrier can be corrected in real time based on the pressing force measured by the pressure sensor.

[0040] In an embodiment, in the execution of the separation process including separation of the wafer from the carrier, the pressing force applied when the wafer is separated from the carrier can be corrected in real time based on the pressing force measured by the pressure sensor.

[0041] According to an aspect of the disclosure, there is provided an electronic device including a head-mounted display device manufactured by the apparatus as described above, wherein the head-mounted display device includes at least one display device, a display device housing configured to accommodate the at least one display device, and an optical member configured to magnify a display image of the at least one display device or change an optical path, and wherein the at least one display device includes a semiconductor substrate, a plurality of conductive layers sequentially stacked on the semiconductor substrate, and a plurality of light emitting elements on the plurality of conductive layers.

[0042] According to an aspect of the disclosure, there is provided an electronic device including a head-mounted display device manufactured by the method as described above, wherein the head-mounted display device includes at least one display device, a display device housing configured to accommodate the at least one display device, and an optical member configured to magnify a display image of the at least one display device or change an optical path, and wherein the at least one display device includes a semiconductor substrate, a plurality of conductive layers sequentially stacked on the semiconductor substrate, and a plurality of light emitting elements on the plurality of conductive layers.

[0043] According to embodiments of the apparatus for manufacturing a display device and the method of manufacturing a display device, a carrier accommodating a wafer can be provided in a manner such that a display manufacturing process apparatus using a conventional mother substrate can be used for a display manufacturing process using a wafer.

[0044] According to embodiments of the apparatus for manufacturing a display device and the method of manufacturing a display, alignment accuracy of the carrier and the wafer can be improved.

[0045] According to embodiments of the apparatus for manufacturing a display device and the method of manufacturing a display device, damage to the wafer can be minimized when the wafer is separated from the carrier.

[0046] However, effects according to embodiments of the disclosure are not limited to the above exemplified effects, and various other effects are included herein. BRIEF DESCRIPTION OF DRAWINGS

[0047] Embodiments of the disclosure will become more fully understood from the detailed description given herein below, and the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present disclosure, and wherein:

[0048] Figure 1 is an exploded perspective view showing a display device according to an embodiment;

[0049] Figure 2 is a block diagram illustrating a display device according to an embodiment;

[0050] Figure 3 is an equivalent circuit diagram of a first sub-pixel according to an embodiment;

[0051] Figure 4 is a plan view illustrating an example of a display panel according to an embodiment;

[0052] Figure 5 and Figure 6 is a plan view illustrating an embodiment of a display area of Figure 4

[0053] Figure 7 is a cross-sectional view illustrating an example of a display panel taken along a line X1-X1’ of Figure 5

[0054] Figure 8 is an exploded perspective view showing a head-mounted display according to an embodiment;

[0055] Figure 9 is a perspective view showing an augmented reality content providing apparatus according to an embodiment;

[0056] Figure 10A is a rear exploded perspective view of the augmented reality content providing apparatus of Figure 9

[0057] Figure 10B is a front exploded perspective view of the augmented reality content providing apparatus of Figure 9

[0058] Figure 11 is a perspective view showing an apparatus for manufacturing a display device according to an embodiment;

[0059] Figure 12 is a cross-sectional view showing an apparatus for manufacturing a display device according to an embodiment;

[0060] Figure 13 is a perspective view showing a carrier according to an embodiment;

[0061] Figure 14 is a cross-sectional view showing a carrier taken along a line X2-X2’ of Figure 13

[0062] Figure 7 is a block diagram showing a controller according to an embodiment;

[0063] Figure 15 ​​​​​is a flowchart illustrating a method of manufacturing a display device according to an embodiment;

[0064] Figure 16 It shows Figure 17 A cross-sectional view of the process S100;

[0065] Figure 16 and Figure 18 It shows Figure 19 A cross-sectional view of process S200;

[0066] Figure 16 and Figure 20 It shows Figure 21 A cross-sectional view of the process S300;

[0067] Figure 16 It shows Figure 15 A cross-sectional view of process S400;

[0068] Figure 16 is a plan view illustrating a method for measuring the degree of deformation of a wafer;

[0069] Figure 22 It shows Figure 16 A cross-sectional view of process S500;

[0070] Figure 15 and Figure 16 It shows Figure 23 A cross-sectional view of process S600;

[0071] Figure 24 is a schematic diagram illustrating alignment correction data processed by a controller;

[0072] Figure 16 It shows Figure 15 A cross-sectional view of process S700;

[0073] Figure 16 It shows Figure 25 A cross-sectional view of process S800; and

[0074] Figure 26 It shows Figure 16 FIG. 5 is a cross-sectional view of the process S900. DETAILED DESCRIPTION

[0075] The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which preferred embodiments of the present invention are shown. However, the present invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and these embodiments will fully convey the scope of the present invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0076] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0077] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus,“a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

[0078] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the terms“a,”“an” and“at least one” do not denote a limitation of quantity, and are intended to cover both the singular and plural forms. Thus, reference to“a” or“the” element, component, or section, followed by reference to“the” element, component, or section, includes both the individual element, component, or section, and a plurality of elements, components, or sections. For example, reference to“a” element has the same meaning as“at least one” element. “At least one” should not be interpreted as limiting“a.” “Or” means“and / or.” As used herein, the term“and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms“comprises” and / or“comprising,” or“includes” and / or“including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0079] In addition, relative terms such as“lower” or“bottom” and“upper” or“top” can be used herein to describe one element’s or portion’s relationship to another element or portion as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the“lower” side of other elements would then be oriented on the“upper” sides of the other elements. The term“lower” can then include both an“lower” and“upper” orientation. Likewise, if the device in one of the figures is turned over, elements described as“below” or“beneath” other elements would then be oriented“above” the other elements. The terms“below” or“beneath” can then include both an“above” and“below” orientation. The terms“upper” and“lower” are used herein only to facilitate the description of the figures.

[0080] “About” or “approximately,” as used in this document, includes the stated value and means within an acceptable range of deviations for the particular value as determined by one of ordinary skill in the art. For example, “about” can mean within one or more standard deviations or within ±30%, 20%, 10%, or 5% of the stated value.

[0081] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0082] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected. Thus, embodiments described herein are not to be construed as limited to the particular shapes illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an area illustrated or described as flat can often have rough and / or nonlinear features. Moreover, sharp angles illustrated can be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

[0083] Embodiments of the present disclosure will be described in detail below with reference to the attached drawings.

[0084] Figure 15 FIG. 1 is an exploded perspective view illustrating a display device according to an embodiment. Figure 16 FIG. 2 is a block diagram illustrating a display device according to an embodiment.

[0085] Reference Figure 27 and Figure 15According to an embodiment, the display device 10 can be a device that displays a moving image or a still image. The display device 10 according to an embodiment can be applied to a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player (PMP), a navigation system, or an ultra-mobile PC (UMPC). For example, the display device 10 according to an embodiment can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) terminal. Alternatively, the display device 10 according to an embodiment can be applied to a smart watch, a watch phone, and a head-mounted display (HMD) for implementing virtual reality and augmented reality, etc.

[0086] The display device 10 according to an embodiment can include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit (or a timing controller) 400, and a power supply circuit (or a power supply unit) 500.

[0087] The display panel 100 can have a planar shape similar to a quadrilateral shape. In an embodiment, for example, the display panel 100 can have a planar shape similar to a quadrilateral shape having a short side in a first direction DR1 and a long side in a second direction DR2 that crosses the first direction DR1. In the display panel 100, a corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet can be a right angle or rounded with a predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and can be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. The planar shape of the display device 10 can conform to the planar shape of the display panel 100, but embodiments of the disclosure are not limited thereto.

[0088] In the drawings, the first direction DR1 and the second direction DR2 cross each other as horizontal directions. For example, the first direction DR1 and the second direction DR2 are orthogonal to each other. Also, a third direction DR3 crosses the first direction DR1 and the second direction DR2, and the first direction DR1 to the third direction DR3 are vertical directions that are, for example, orthogonal to each other. Unless otherwise defined, in the disclosure, a direction indicated by an arrow of the first direction to the third direction DR1, DR2, and DR3 is referred to as one side, and a direction opposite thereto is referred to as the other side. Here, the third direction DR3 can be a thickness direction of the display panel 100. Further, as used herein, the terms "upper surface", "upper side", "upper portion", "top", and "top surface" refer to a direction indicated by an arrow in the third direction DR3 based on the drawings, and as used herein, the terms "lower surface", "lower side", "lower portion", "bottom", and "bottom surface" refer to a direction opposite to the direction indicated by the arrow in the third direction DR3 based on the drawings.

[0089] As shown in Figure 16 The display panel 100 can include a display area DAA in which an image is displayed and a non-display area NDA in which an image is not displayed.

[0090] The display area DAA can include a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0091] The plurality of pixels PX can be arranged in a matrix form in a first direction DR1 and a second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL can extend in the first direction DR1 while being disposed or arranged along the second direction DR2. The plurality of data lines DL can extend in the second direction DR2 while being disposed or arranged along the first direction DR1.

[0092] The plurality of scan lines SL can include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of emission control lines EL can include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0093] The plurality of pixels PX can include a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 can include a plurality of pixel transistors as shown in Figure 23 later will be described) and the plurality of pixel transistors can be formed by a semiconductor process and disposed on a semiconductor substrate SSUB (see Figure 25 to Figure 27 In an embodiment, for example, the plurality of pixel transistors of the data driver 700 can include or be formed of a complementary metal-oxide semiconductor (CMOS).

[0094] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to a corresponding one of the plurality of write scan lines GWL, a corresponding one of the plurality of control scan lines GCL, a corresponding one of the plurality of bias scan lines GBL, a corresponding one of the plurality of first emission control lines EL1, a corresponding one of the plurality of second emission control lines EL2, and a corresponding one of the plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL and emit light from a light emitting element based on the data voltage.

[0095] The non-display area NDA can include the scan driver 610, the emission driver 620, and the data driver 700.

[0096] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of emission transistors. The plurality of scan transistors and the plurality of emission transistors can be formed by a semiconductor process, and disposed on a semiconductor substrate SSUB (see Figure 27 ). In an embodiment, for example, the plurality of scan transistors and the plurality of emission transistors can include CMOS, or be formed by CMOS. Although Figure 30 embodiment, for example, the scan driver 610 and the emission driver 620 can be disposed on both left and right sides of the display area DAA.

[0097] The scan driver 610 includes a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 can receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 can generate a write scan signal in response to the scan timing control signal SCS of the timing control circuit 400, and sequentially output the write scan signal to the write scan lines GWL. The control scan signal output unit 612 can generate a control scan signal in response to the scan timing control signal SCS, and sequentially output the control scan signal to the control scan lines GCL. The bias scan signal output unit 613 can generate a bias scan signal in response to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan lines GBL.

[0098] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 can receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 can generate a first emission control signal in response to the emission timing control signal ECS, and sequentially output the first emission control signal to the first emission control lines EL1. The second emission control driver 622 can generate a second emission control signal in response to the emission timing control signal ECS, and sequentially output the second emission control signal to the second emission control lines EL2.

[0099] The data driver 700 can include a plurality of data transistors, and the plurality of data transistors can be formed by a semiconductor process and disposed on a semiconductor substrate SSUB (see Figure 28In an embodiment, for example, the plurality of data transistors may include or be formed of CMOS.

[0100] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 may convert the digital video data DATA into an analog data voltage based on the data timing control signal DCS and output the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0101] The heat dissipation layer 200 may overlap the display panel 100 in a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on one surface of the display panel 100, for example, on the rear surface thereof. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include graphite having high thermal conductivity or a metal layer such as silver (Ag), copper (Cu), or aluminum (Al).

[0102] The circuit board 300 may be electrically connected to the first pad portion PDA1 of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film (see FIG. Figure 16 ) of a plurality of first pads PD1 (see Figure 15 ). The circuit board 300 may be a flexible printed circuit board having a flexible material or a flexible film. In an embodiment, the circuit board 300 may be in a Figure 16 , or the circuit board 300 may be bent. In the bent state, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 may be connected to the first pad portion PDA1 of the display panel 100 (see FIG. 1 ) by using a conductive adhesive member. Figure 29 ) of a plurality of first pads PD1 (see Figure 30 ) at the opposite end of the other end.

[0103] The timing control circuit 400 can receive digital video data and timing signals input from the outside. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 can also output the digital video data and the data timing control signal DCS to the data driver 700.

[0104] The power supply circuit 500 can generate a plurality of panel driving voltages according to a power supply voltage from the outside. In an embodiment, for example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be described later in connection with Figure 30 the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0105] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC), and be attached to one surface of the circuit board 300. In an embodiment, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Further, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0106] Alternatively, each of the timing control circuit 400 and the power supply circuit 500 can be disposed in the non-display area NDA of the display panel 100, similarly to the scan driver 610, the emission driver 620, and the data driver 700. In such an embodiment, the timing control circuit 400 can include a plurality of timing transistors, and each of the power supply circuits 500 can include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors can be formed by a semiconductor process, and be disposed on a semiconductor substrate SSUB (see Figure 16 ). In an embodiment, for example, the plurality of timing transistors and the plurality of power transistors can include CMOS, or be formed of CMOS. Each of the timing control circuit 400 and the power supply circuit 500 can be disposed between the data driver 700 and the first pad portion PDA1 (see Figure 15 ).

[0107] Figure 16 is an equivalent circuit diagram of a first sub-pixel according to an embodiment.

[0108] In addition to Figure 30 and Figure 25 , reference is made to Figure 26In an embodiment, the first sub-pixel SP1 of each pixel can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Further, the first sub-pixel SP1 can be connected to the first drive voltage line VSL to which the first drive voltage VSS corresponding to the low potential voltage is applied, the second drive voltage line VDL to which the second drive voltage VDD corresponding to the high potential voltage is applied, and the third drive voltage line VIL to which the third drive voltage VINT corresponding to the initialization voltage is applied. That is, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. In such an embodiment, the first drive voltage VSS can be lower than the third drive voltage VINT. In such an embodiment, the second drive voltage VDD can be higher than the third drive voltage VINT.

[0109] The first sub-pixel SP1 can include a plurality of transistors T1 to T6, a light emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0110] The light emitting element LE can emit light in response to a drive current (a source-drain current) flowing through a channel of the first transistor T1. The amount of light emitted by the light emitting element LE can be proportional to the drive current. The light emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. A first electrode of the light emitting element LE can be connected to a drain electrode of the fourth transistor T4, and a second electrode thereof can be connected to the first drive voltage line VSL. In an embodiment, the first electrode of the light emitting element LE can be an anode electrode, and the second electrode of the light emitting element LE can be a cathode electrode. In an embodiment, the light emitting element LE can be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode, but embodiments of the present disclosure are not limited thereto. In another embodiment, for example, the light emitting element LE can be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode, and the light emitting element LE can be, for example, a micro light emitting diode.

[0111] The first transistor T1 can be a drive transistor that controls a drive current flowing between a source electrode and a drain electrode thereof based on a voltage applied to a gate electrode thereof. The first transistor T1 can include the gate electrode connected to the first node N1, the source electrode connected to the drain electrode of the sixth transistor T6, and the drain electrode connected to the second node N2.

[0112] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 can be turned on by a write scan signal of the write scan line GWL to connect the one electrode of the first capacitor CP1 to the data line DL. Accordingly, when the second transistor T2 is turned on, a data voltage of the data line DL can be applied to the one electrode of the first capacitor CP1. The second transistor T2 can include a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the one electrode of the first capacitor CP1.

[0113] The third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 can be turned on by a write control signal of the control scan line GCL to connect the first node N1 to the second node N2. In such an embodiment, when the third transistor T3 is turned on, the gate electrode and the drain electrode of the first transistor T1 are connected to each other such that the first transistor T1 can operate like a diode. The third transistor T3 can include a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0114] The fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 can be turned on by a first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Accordingly, when the fourth transistor T4 is turned on, a driving current of the first transistor T1 can be supplied to the light emitting element LE. The fourth transistor T4 can include a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0115] The fifth transistor T5 can be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 can be turned on by a bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Accordingly, when the fifth transistor T5 is turned on, a third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light emitting element LE. The fifth transistor T5 can include a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0116] The sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 can be turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Accordingly, when the sixth transistor T6 is turned on, the second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 can include a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0117] The first capacitor CP1 can be disposed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 can include one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0118] The second capacitor CP2 can be disposed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 can include one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0119] The first node N1 can be a junction point between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and the one electrode of the second capacitor CP2. The second node N2 can be a junction point between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 can be a junction point between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0120] Each of the first to sixth transistors T1 to T6 can be a metal oxide semiconductor field effect transistor (MOSFET). In an embodiment, for example, each of the first to sixth transistors T1 to T6 can be a P-type MOSFET, but embodiments of the specification are not limited thereto. In another embodiment, each of the first to sixth transistors T1 to T6 can be an N-type MOSFET. Alternatively, some of the first to sixth transistors T1 to T6 can be P-type MOSFETs, and each of the remaining transistors can be an N-type MOSFET.

[0121] Although Figure 28 Although an embodiment in which the sub-pixel includes the first sub-pixel SP1 including the six transistors T1 to T6 and the two capacitors CP1 and CP2 is illustrated, an equivalent circuit diagram of the first sub-pixel SP1 is not limited to Figure 29The equivalent circuit diagram of the first sub-pixel SP1 of each pixel is substantially the same as that described above with reference to FIG. 6A. Thus, any repetitive detailed description of the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 will be omitted.

[0122] In an embodiment, the equivalent circuit diagram of the second sub-pixel SP2 of each pixel and the equivalent circuit diagram of the third sub-pixel SP3 of each pixel can be substantially the same as that described above with reference to Figure 30 The equivalent circuit diagram of the first sub-pixel SP1 of each pixel described above is substantially the same. Thus, any repetitive detailed description of the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 will be omitted.

[0123] ​ is a plan view illustrating an example of a display panel according to an embodiment.

[0124] Referring to ​ , the display area DAA of the display panel 100 according to an embodiment can include a plurality of pixels PX arranged in a matrix form. The non-display area NDA of the display panel 100 according to an embodiment can include a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2. In an embodiment, the pixels can not be disposed or included in the non-display area NDA.

[0125] The scan driver 610 can be disposed at a first side of the display area DAA, and the emission driver 620 can be disposed at a second side of the display area DAA. In an embodiment, for example, the scan driver 610 can be disposed at the other side of the display area DAA in the first direction DR1, and the emission driver 620 can be disposed at the side of the display area DAA in the first direction DR1. That is, the scan driver 610 can be disposed at the left side of the display area DAA, and the emission driver 620 can be disposed at the right side of the display area DAA. However, embodiments of the present disclosure are not limited thereto, and in another embodiment, for example, each of the scan driver 610 and the emission driver 620 can be disposed at both the first side and the second side of the display area DAA.

[0126] The first pad portion PDA1 can include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 through conductive adhesive members. The first pad portion PDA1 can be disposed at a third side of the display area DAA. In an embodiment, for example, the first pad portion PDA1 can be disposed at the other side of the display area DAA in the second direction DR2. That is, the first pad portion PDA1 can be disposed at the lower side of the display area DAA.

[0127] The first pad portion PDA1 can be disposed outside the data driver 700 in the second direction DR2. That is, the first pad portion PDA1 can be disposed closer to an edge of the display panel 100 than the data driver 700.

[0128] The second pad portion PDA2 can include a plurality of second pads PD2 corresponding to inspection pads for testing whether the display panel 100 normally operates. The plurality of second pads PD2 can be connected to a jig or a probe during an inspection process, or can be connected to a circuit board for inspection. The circuit board for inspection can be a printed circuit board including or made of a rigid material, or a flexible printed circuit board including or made of a flexible material.

[0129] The first distribution circuit 710 can distribute data voltages applied through the first pad portion PDA1 to the plurality of data lines DL. In an embodiment, for example, the first distribution circuit 710 can distribute data voltages applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or more) data lines DL, and as a result, the number of the plurality of first pads PD1 can be reduced. The first distribution circuit 710 can be disposed at a third side of the display area DAA of the display panel 100. In an embodiment, for example, the first distribution circuit 710 can be disposed at the other side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 can be disposed at the lower side of the display area DAA.

[0130] The second distribution circuit 720 can distribute signals applied through the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data lines DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to inspect the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be disposed at a fourth side of the display area DAA of the display panel 100. In an embodiment, for example, the second distribution circuit 720 can be disposed at one side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 can be disposed at the upper side of the display area DAA.

[0131] ​ and ​ is a plan view illustrating an embodiment of a display area of the display panel 100. ​

[0132] Referring to ​ and ​ In an embodiment, each of the pixels PX can include a first emission area EA1 that is an emission area of the first sub-pixel SP1, a second emission area EA2 that is an emission area of the second sub-pixel SP2, and a third emission area EA3 that is an emission area of the third sub-pixel SP3.​

[0133] In some embodiments, as shown in ​ and ​ In some embodiments, as shown in

[0134] In some embodiments, as shown in ​ In some embodiments, as shown in

[0135] ​ In some embodiments, as shown in

[0136] In some embodiments, as shown in ​ In some embodiments, as shown in

[0137] ​ In another embodiment, as shown in

[0138] ​​In the illustrated drawings, the first diagonal direction DD1 intersects each of the first direction DR1 and the second direction DR2, which are horizontal directions. For example, the first diagonal direction DD1 can be a direction inclined by 45 degrees with respect to each of the first direction DR1 and the second direction DR2, but the present disclosure is not limited thereto. The second diagonal direction DD2 intersects each of the first direction DR1 and the second direction DR2, which are horizontal directions. For example, the second diagonal direction DD2 can be a direction inclined by 45 degrees with respect to the opposite direction of each of the first direction DR1 and the second direction DR2, but the present disclosure is not limited thereto. The second diagonal direction DD2 is a direction perpendicular to the first diagonal direction DD1.

[0139] The first emission area EA1 can emit light of a first color, the second emission area EA2 can emit light of a second color, and the third emission area EA3 can emit light of a third color. Here, the light of the first color can be light of a red color band, the light of the second color can be light of a green color band, and the light of the third color can be light of a blue color band. For example, the blue color band is a band of light whose peak wavelength is in the range of about 370 nanometers (nm) to about 460 nm, the green color band is a band of light whose peak wavelength is in the range of about 480 nm to about 560 nm, and the red color band is a band of light whose peak wavelength is in the range of about 600 nm to about 750 nm.

[0140] ​ and ​ Embodiments of the present disclosure are not limited thereto. In another embodiment, for example, each of the plurality of pixels PX can include four or more emission areas.

[0141] In addition, the shape and arrangement of the emission areas of the plurality of pixels PX are not limited to ​ and ​ illustrated in FIG. 10. In an embodiment, for example, as illustrated in FIG. 11, the emission areas of the plurality of pixels PX can be arranged in a bar structure in which the emission areas are arranged in the first direction DR1, a ​ structure in which the emission areas are arranged in a diamond shape, or a hexagonal structure in which the emission areas having a hexagonal shape in a plan view are arranged side by side.

[0142] ​ is a cross-sectional view illustrating an example of a display panel taken along a line X1-X1’ of ​

[0143] Referring to ​ ​​The embodiment of the display panel 100 can include a semiconductor backplane SBP, an emission element backplane EBP, a display element layer EML, a sealing layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL.

[0144] The semiconductor backplane SBP can include a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. The plurality of pixel transistors PTR can be referred to as pixel transistors PTR. ​ The first to sixth transistors T1 to T6 described above (see FIG. 1) can be included in the semiconductor backplane SBP. ​ ).

[0145] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. A plurality of well regions WA can be provided on a top surface of the semiconductor substrate SSUB. The plurality of well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. In an embodiment, for example, in a case where the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. Alternatively, when the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0146] Each of the plurality of well regions WA can include a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode thereof, and a channel region CH provided between the source region SA and the drain region DA.

[0147] A lower insulating film BINS can be provided between the gate electrode GE and the well region WA. A side insulating film SINS can be provided on a side surface of the gate electrode GE. The side insulating film SINS can be provided on the lower insulating film BINS.

[0148] Each of the source region SA and the drain region DA can be a region doped with the first type of impurity. The gate electrode GE of the pixel transistor PTR can overlap the well region WA in a third direction DR3. The channel region CH can overlap the gate electrode GE in the third direction DR3. The source region SA can be provided on one side of the gate electrode GE, and the drain region DA can be provided on the other side of the gate electrode GE.

[0149] Each of the plurality of well regions WA can further include a first low-concentration impurity region LDD1 provided between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 provided between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 can be a region having a lower impurity concentration than that of the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 can be a region having a lower impurity concentration than that of the drain region DA due to the lower insulating film BINS. Due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA can be increased. Thus, the length of the channel region CH of each of the pixel transistors PTR is increased, so that punch-through and hot carrier phenomena that can be caused by a short channel are effectively prevented.

[0150] The first semiconductor insulating film SINS1 can be provided on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can include a silicon carbonitride (SiCN) or silicon oxide (SiO x ) type inorganic film, or be formed of a silicon carbonitride (SiCN) or silicon oxide (SiO x ) type inorganic film, but embodiments of the present disclosure are not limited thereto.

[0151] The second semiconductor insulating film SINS2 can be provided on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can include a silicon oxide (SiO x ) type inorganic film, or be formed of a silicon oxide (SiO x ) type inorganic film, but embodiments of the present disclosure are not limited thereto.

[0152] The plurality of contact terminals CTE can be provided on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE can be connected to at least one selected from the gate electrode GE, the source region SA, and the drain region DA of each of the pixel transistors PTR through a hole defined or formed by passing through the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The plurality of contact terminals CTE can include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a combination or alloy thereof, or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a combination or alloy thereof.

[0153] The third semiconductor insulating film SINS3 may be provided on a side surface of each of the plurality of contact terminals CTE. The top surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 may include silicon oxide (SiO x ) type inorganic film, or silicon oxide (SiO x ) type inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0154] In another embodiment, the semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate such as polyimide. In such an embodiment, the thin film transistor may be provided on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that does not bend, and the polymer resin substrate may be a flexible substrate that can be bent or curved.

[0155] The light emitting element backplane EBP may include a plurality of conductive layers ML1 to ML8 , a plurality of vias VA1 to VA9 , and a plurality of insulating films INS1 to INS9 .

[0156] The first conductive layer ML1 to the eighth conductive layer ML8 are used to connect the plurality of contact terminals CTE exposed from the semiconductor base plate SBP to achieve ​ . In the embodiment, for example, the first to sixth transistors T1 to T6 are disposed solely on the semiconductor substrate SBP, and the connection lines between the first to sixth transistors T1 to T6 and the first and second capacitors CP1 and CP2 may be disposed in the first to eighth conductive layers ML1 to ML8. Furthermore, the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the connection portion between the first electrode of the light-emitting element LE may also be disposed in the first to eighth conductive layers ML1 to ML8.

[0157] The first insulating film INS1 may be provided on the semiconductor substrate SBP. Each of the first through-vias VA1 may penetrate the first insulating film INS1 (or extend through the first insulating film INS1) to connect to the contact terminal CTE exposed from the semiconductor substrate SBP. Each of the first conductive layers ML1 may be provided on the first insulating film INS1 and may be connected to the first through-vias VA1.

[0158] A second insulating film INS2 can be provided on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 can penetrate (or extend through) the second insulating film INS2 and be connected to the exposed first conductive layer ML1. Each of the second conductive layers ML2 can be provided on the second insulating film INS2 and can be connected to the second via VA2.

[0159] A third insulating film INS3 can be provided on the second insulating film INS2 and the second conductive layer ML2. Each of the third vias VA3 can penetrate (or extend through) the third insulating film INS3 and be connected to the exposed second conductive layer ML2. Each of the third conductive layers ML3 can be provided on the third insulating film INS3 and can be connected to the third via VA3.

[0160] A fourth insulating film INS4 can be provided on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth vias VA4 can penetrate (or extend through) the fourth insulating film INS4 and be connected to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 can be provided on the fourth insulating film INS4 and can be connected to the fourth via VA4.

[0161] A fifth insulating film INS5 can be provided on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 can penetrate (or extend through) the fifth insulating film INS5 and be connected to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 can be provided on the fifth insulating film INS5 and can be connected to the fifth via VA5.

[0162] A sixth insulating film INS6 can be provided on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 can penetrate (or extend through) the sixth insulating film INS6 and be connected to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 can be provided on the sixth insulating film INS6 and can be connected to the sixth via VA6.

[0163] A seventh insulating film INS7 can be provided on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 can penetrate (or extend through) the seventh insulating film INS7 and be connected to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 can be provided on the seventh insulating film INS7 and can be connected to the seventh via VA7.

[0164] The eighth insulating film INS8 may be disposed on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth through-holes VA8 may penetrate the eighth insulating film INS8 (or extend through the eighth insulating film INS8) and be connected to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 may be disposed on the eighth insulating film INS8 and may be connected to the eighth through-holes VA8.

[0165] The first to eighth conductive layers ML1 to ML8 and the first to eighth through holes VA1 to VA8 may include substantially the same material as each other, or be formed of substantially the same material. The first to eighth conductive layers ML1 to ML8 and the first to eighth through holes VA1 to VA8 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a combination or alloy thereof, or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a combination or alloy thereof. The first to eighth insulating films INS1 to INS8 may include silicon oxide (SiO x ) type inorganic film, or silicon oxide (SiO x ) type inorganic film is formed, but the embodiments of the present disclosure are not limited thereto.

[0166] The thickness of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be respectively greater than the thickness of the first through hole VA1, the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5 and the sixth through hole VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5 and the thickness of the sixth conductive layer ML6 may be substantially the same. In an embodiment, for example, the thickness of the first conductive layer ML1 is approximately 1360 angstroms. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 is approximately And the thickness of each of the first through hole VA1, the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5 and the sixth through hole VA6 is about However, the thicknesses of the first to sixth conductive layers ML1, ML2, ML3, ML4, ML5, and ML6 and the first to sixth vias VA1, VA2, VA3, VA4, VA5, and VA6 are not limited thereto.

[0167] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be substantially the same. In an embodiment, for example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 is about 100 nm to about 200 nm, and the thickness of each of the seventh via VA7 and the eighth via VA8 is about 100 nm to about 200 nm. and the thickness of each of the seventh via VA7 and the eighth via VA8 is about 100 nm to about 200 nm. However, the thicknesses of the seventh conductive layer ML7, the eighth conductive layer ML8, the seventh via VA7, and the eighth via VA8 are not limited thereto.

[0168] The ninth insulating film INS9 can be disposed on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can include a silicon oxide (SiO x ) type inorganic film, or be formed of a silicon oxide (SiO x ) type inorganic film, but embodiments of the present disclosure are not limited thereto.

[0169] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 and be connected to the exposed eighth conductive layer ML8. The ninth via VA9 can include or be formed of at least one selected from the group consisting of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a combination or alloy thereof. The thickness of the ninth via VA9 is about 100 nm to about 200 nm. However, the thickness of the ninth via VA9 is not limited thereto.

[0170] The display element layer EML can be disposed on the light emitting element base plate EBP. The display element layer EML can include light emitting elements LE each including a reflective electrode layer RL, a tenth insulating film INS10, and an eleventh insulating film INS11, a tenth via hole VA10, a first electrode AND, a light emitting stack ES, and a second electrode CAT; a pixel definition film PDL; and a plurality of trenches TRC.

[0171] The reflective electrode layer RL can be disposed on the ninth insulating film INS9. The reflective electrode layer RL can include at least one reflective electrode RL1, RL2, RL3, and RL4. In an embodiment, for example, as shown in FIG. 1B, the reflective electrode layer RL can include first to fourth reflective electrodes RL1, RL2, RL3, and RL4, but is not limited thereto. ​

[0172] Each of the first reflective electrodes RL1 can be disposed on the ninth insulating film INS9 and can be connected to the ninth via hole VA9. The first reflective electrode RL1 can include or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a combination or alloy thereof. In an embodiment, for example, the first reflective electrode RL1 can include titanium nitride (TiN).

[0173] Each of the second reflective electrodes RL2 can be disposed on the first reflective electrode RL1. The second reflective electrode RL2 can include or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a combination or alloy thereof. In an embodiment, for example, the second reflective electrode RL2 can include aluminum (Al).

[0174] ​Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a combination or alloy thereof, or may be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a combination or alloy thereof. In an embodiment, for example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0175] The fourth reflective electrode RL4 may be disposed on each of the third reflective electrodes RL3. The fourth reflective electrode RL4 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a combination or alloy thereof. Alternatively, the fourth reflective electrode RL4 may be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a combination or alloy thereof. In an embodiment, for example, the fourth reflective electrode RL4 may include titanium (Ti).

[0176] In such an embodiment, since the second reflective electrode RL2 is an electrode that substantially reflects light from the light emitting element LE, the thickness of the second reflective electrode RL2 may be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. In an embodiment, for example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 is approximately And the thickness of the second reflective electrode RL2 is about However, the thicknesses of the first to fourth reflective electrodes RL1 , RL2 , RL3 , and RL4 are not limited thereto.

[0177] The tenth insulating film INS10 may be provided on the ninth insulating film INS9. The tenth insulating film INS10 may be provided in a space between the reflective electrode layers RL adjacent to each other in a horizontal direction. The tenth insulating film INS10 may include silicon oxide (SiO x ) type inorganic film, or silicon oxide (SiO x In some embodiments, although not shown in the drawings, the tenth insulating film INS10 may be disposed not only between the reflective electrode layers RL but also on the reflective electrode layer RL.

[0178] The eleventh insulating film INS11 can be provided on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 can include a silicon oxide (SiO x ) type inorganic film, or be formed of a silicon oxide (SiO x ) type inorganic film, but embodiments of the present disclosure are not limited thereto. The tenth insulating film INS10 and the eleventh insulating film INS11 can be optical auxiliary layers through which light emitted from the light emitting element LE and reflected by the reflective electrode layer RL passes.

[0179] In some embodiments, in at least any one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the total thickness of the insulating film provided between the first electrode AND and the reflective electrode layer RL can be different among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, to adjust the resonance distance of light emitted from the light emitting element LE.

[0180] In embodiments, as shown in the drawings, in a case where the tenth insulating film INS10 is not provided between the first electrode AND and the reflective electrode layer RL but the eleventh insulating film INS11 is provided therebetween, the thickness of the eleventh insulating film INS11 provided in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be different from each other. In embodiments, for example, the thickness of the eleventh insulating film INS11 provided in the first sub-pixel SP1 can be smaller than the thickness of the eleventh insulating film INS11 provided in the second sub-pixel SP2, and the thickness of the eleventh insulating film INS11 provided in the second sub-pixel SP2 can be smaller than the thickness of the eleventh insulating film INS11 provided in the third sub-pixel SP3.

[0181] In another embodiment, in the first sub-pixel SP1, neither the tenth insulating film INS10 nor the eleventh insulating film INS11 can be provided between the first electrode AND and the reflective electrode layer RL, in the second sub-pixel SP2, at least one selected from the tenth insulating film INS10 and the eleventh insulating film INS11 can be provided between the first electrode AND and the reflective electrode layer RL, and in the third sub-pixel SP3, both the tenth insulating film INS10 and the eleventh insulating film INS11 can be provided between the first electrode AND and the reflective electrode layer RL.

[0182] In another embodiment, a twelfth insulating film (not shown) may be further provided between the first electrode AND and the reflective electrode layer RL. In such an embodiment, in the first sub-pixel SP1, at least one selected from the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be provided between the first electrode AND and the reflective electrode layer RL, in the second sub-pixel SP2, any two of the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be provided between the first electrode AND and the reflective electrode layer RL, and in the third sub-pixel SP3, all of the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be provided between the first electrode AND and the reflective electrode layer RL.

[0183] In such an embodiment, the distance between the first electrode AND and the reflective electrode layer RL may be different in the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. That is, the presence / absence or thickness of the tenth insulating film INS10 and the eleventh insulating film INS11 may be set in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the dominant wavelength of light emitted from each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0184] In an embodiment, ​ As shown in , the total thickness of the insulating film disposed between the first electrode AND and the reflective electrode layer RL may increase in the order of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, but the present disclosure is not limited thereto. In such an embodiment, the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1, but embodiments of the present disclosure are not limited thereto. The dimensional relationship of the total thickness of the insulating film disposed between the first electrode AND and the reflective electrode layer RL in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may be variously modified depending on the resonance distance.

[0185] Each of the tenth vias VA10 can be connected to the reflective electrode layer RL exposed through the tenth insulating film INS10 and / or the eleventh insulating film INS11. The tenth via VA10 can include or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a combination or alloy thereof. The thickness of the tenth via VA10 in the second sub-pixel SP2 can be smaller than the thickness of the tenth via VA10 in the third sub-pixel SP3 and the thickness of the tenth via VA10 in the first sub-pixel SP1 can be smaller than the thickness of the tenth via VA10 in the second sub-pixel SP2, but the present disclosure is not limited thereto.

[0186] The first electrode AND of each of the light emitting elements LE can be disposed on the eleventh interlayer insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each of the light emitting elements LE can be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements LE can include or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a combination or alloy thereof. In an embodiment, for example, the first electrode AND of each of the light emitting elements LE can be titanium nitride (TiN).

[0187] The pixel definition film PDL can be disposed on a portion of the first electrode AND of each of the light emitting elements LE. The pixel definition film PDL can cover an edge of the first electrode AND of each of the light emitting elements LE. The pixel definition film PDL can serve to separate the first to third emission areas EA1 to EA3.

[0188] The first emission area EA1 may be defined as a region where the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission area EA2 may be defined as a region where the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission area EA3 may be defined as a region where the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0189] The pixel definition film PDL may include first to third pixel definition films PDL1, PDL2, and PDL3. The first pixel definition film PDL1 may be provided on the edge of the first electrode AND of each of the light emitting elements LE, the second pixel definition film PDL2 may be provided on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be provided on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may include silicon oxide (SiO x ) type inorganic layer, or silicon oxide (SiO x ) type inorganic layer is formed, but the embodiment of the present disclosure is not limited thereto. The first pixel definition film PDL1, the second pixel definition film PDL2 and the third pixel definition film PDL3 may each have an area of ​​about thickness.

[0190] In an embodiment where the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 are formed as one pixel defining film, the height of one pixel defining film increases, so that the first encapsulating inorganic film TFE1 may be cut due to step coverage. Step coverage refers to the ratio of the degree of film coating on the inclined portion to the degree of film coating on the flat portion. The lower the step coverage, the more likely the film will be cut at the inclined portion.

[0191] Therefore, in order to effectively prevent the first encapsulating inorganic film TFE1 from being cut due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure with a stepped portion. In an embodiment, for example, the width of the first pixel defining film PDL1 may be greater than the width of the second pixel defining film PDL2 and the width of the third pixel defining film PDL3, and the width of the second pixel defining film PDL2 may be greater than the width of the third pixel defining film PDL3. Each of the widths of the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 refers to a length in a horizontal direction perpendicular to the third direction DR3.

[0192] Each of the plurality of trenches TRC can penetrate the first, second, and third pixel definition films PDL1, PDL2, and PDL3. Also, each of the plurality of trenches TRC can be defined or formed through the eleventh insulating film INS11. The eleventh insulating film INS11 can be partially recessed at each of the plurality of trenches TRC.

[0193] At least one trench TRC can be disposed between adjacent sub-pixels SP1, SP2, and SP3. Although ​ Embodiments of the disclosure are not limited to the embodiment in which two trenches TRC are disposed between adjacent sub-pixels SP1, SP2, and SP3.

[0194] The light emitting stack ES can include a plurality of intermediate layers. ​ Embodiments of the disclosure are not limited to the embodiment in which the light emitting stack ES has a three-series structure including the first, second, and third stack layers IL1, IL2, and IL3. In another embodiment, for example, the light emitting stack ES can have a two-series structure including two intermediate layers.

[0195] In the three-series structure, the light emitting stack ES can have a series structure including a plurality of stack layers IL1, IL2, and IL3 that respectively emit different light. In an embodiment, for example, the light emitting stack ES can include a first stack layer IL1 that emits light of a first color, a second stack layer IL2 that emits light of a third color, and a third stack layer IL3 that emits light of a second color. The first, second, and third stack layers IL1, IL2, and IL3 can be sequentially stacked one on another.

[0196] The first stack layer IL1 can have a structure in which a first hole transport layer, a first organic light emitting layer that emits light of a first color, and a first electron transport layer are sequentially stacked one on another. The second stack layer IL2 can have a structure in which a second hole transport layer, a second organic light emitting layer that emits light of a third color, and a second electron transport layer are sequentially stacked one on another. The third stack layer IL3 can have a structure in which a third hole transport layer, a third organic light emitting layer that emits light of a second color, and a third electron transport layer are sequentially stacked one on another.

[0197] A first charge generation layer for supplying holes to the second stack layer IL2 and supplying electrons to the first stack layer IL1 can be disposed between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer can include an N-type charge generation layer that supplies electrons to the first stack layer IL1 and a P-type charge generation layer that supplies holes to the second stack layer IL2. The N-type charge generation layer can include a dopant of a metallic material.

[0198] A second charge generation layer for supplying holes to the third stack layer IL3 and for supplying electrons to the second stack layer IL2 can be disposed between the second stack layer IL2 and the third stack layer IL3. The second charge generation layer can include an N-type charge generation layer for supplying electrons to the second stack layer IL2 and a P-type charge generation layer for supplying holes to the third stack layer IL3.

[0199] The first stack layer IL1 can be disposed on the first electrode AND and the pixel definition film PDL, and can be disposed on a bottom surface of each of the trenches TRC. The first stack layer IL1 can be cut between the adjacent sub-pixels SP1, SP2, and SP3 due to the trenches TRC. The second stack layer IL2 can be disposed on the first stack layer IL1. The second stack layer IL2 can be cut between the adjacent sub-pixels SP1, SP2, and SP3 due to the trenches TRC. The cavity ESS or the blank space can be disposed between the first stack layer IL1 and the second stack layer IL2. The third stack layer IL3 can be disposed on the second stack layer IL2. The third stack layer IL3 is not cut by the trenches TRC, and can be disposed to cover the second stack layer IL2 in each of the trenches TRC. That is, in the three-series structure, each of the plurality of trenches TRC can be a structure for cutting the first stack layer IL1 and the second stack layer IL2 of the display element layer EML, the first charge generation layer, and the second charge generation layer between the sub-pixels SP1, SP2, and SP3 adjacent to each other. In addition, in the two-series structure, each of the trenches TRC can be a structure for cutting the charge generation layer disposed between the lower intermediate layer and the upper intermediate layer and the lower intermediate layer.

[0200] In an embodiment, a height of each of the plurality of trenches TRC can be greater than a height of the pixel definition film PDL to stably cut the first stack layer IL1 and the second stack layer IL2 of the display element layer EML between the adjacent sub-pixels SP1, SP2, and SP3. The height of each of the plurality of trenches TRC refers to a length of each of the plurality of trenches TRC in the third direction DR3. The height of the pixel definition film PDL refers to a length of the pixel definition film PDL in the third direction DR3. In an embodiment, another structure configured to cut the first to third stack layers IL1, IL2, and IL3 of the display element layer EML between the adjacent sub-pixels SP1, SP2, and SP3 can be present or provided instead of the trenches TRC. In an embodiment, for example, instead of the trenches TRC, an inverted taper-shaped partition wall can be disposed on the pixel definition film PDL.

[0201] The number of the stack layers IL1, IL2, and IL3 emitting different light is not limited to ​The number of intermediate layers is illustrated in FIG. 1. In an embodiment, for example, the light emitting stack ES can include two intermediate layers. In such an embodiment, one of the two intermediate layers can be substantially the same as the first stack layer IL1, and the other intermediate layer can include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In such an embodiment, a charge generation layer for supplying electrons to one intermediate layer and holes to the other intermediate layer can be disposed between the two intermediate layers.

[0202] In addition, ​ FIG. 1 illustrates an embodiment in which the first to third stack layers IL1, IL2, and IL3 are all disposed in the first, second, and third emission areas EA1, EA2, and EA3, but embodiments of the present disclosure are not limited thereto. In another embodiment, for example, the first stack layer IL1 can be disposed in the first emission area EA1 and can not be disposed in the second and third emission areas EA2 and EA3. In such an embodiment, the second stack layer IL2 can be disposed in the second emission area EA2 and can not be disposed in the first and third emission areas EA1 and EA3. In such an embodiment, the third stack layer IL3 can be disposed in the third emission area EA3 and can not be disposed in the first and second emission areas EA1 and EA2. In such an embodiment, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL can be omitted.

[0203] The second electrode CAT can be disposed on the third stack layer IL3. The second electrode CAT can be disposed on the third stack layer IL3 in each of the plurality of trenches TRC. The second electrode CAT can include or be formed of a transparent conductive material (TCO) such as ITO or IZO, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag, which is capable of transmitting light. In an embodiment in which the second electrode CAT is formed of a semi-transmissive conductive material, light emission efficiency can be improved in each of the first to third sub-pixels SP1, SP2, and SP3 due to a microcavity effect.

[0204] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE can include at least one inorganic film TFE1 and TFE2 for effectively preventing oxygen or moisture from permeating into the display element layer EML. In an embodiment, for example, the encapsulation layer TFE can include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0205] The first encapsulation inorganic film TFE1 can be disposed on the second electrode CAT. The first encapsulation inorganic film TFE1 can be formed of a plurality of layers in which one or more inorganic films each including at least one selected from silicon nitride (SiN x ), silicon oxynitride (SiON), and silicon oxide (SiO x ) are alternately stacked. The first encapsulation inorganic film TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0206] The second encapsulation inorganic film TFE2 can be disposed on the first encapsulation inorganic film TFE1. The second encapsulation inorganic film TFE2 can include or be formed of titanium oxide (TiO x ) or aluminum oxide (AlO x ), but embodiments of the present disclosure are not limited thereto. The second encapsulation inorganic film TFE2 can be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0207] The display panel 100 can further include an organic film APL. The organic film APL can be a layer for improving the interface adhesion between the encapsulation layer TFE and the optical layer OPL. The organic film APL can be an organic film such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0208] The optical layer OPL can include a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a fill layer FIL. The plurality of color filters CF1, CF2, and CF3 can include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 can be disposed on the organic film APL.

[0209] The first color filter CF1 can overlap the first emission area EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of a first color (i.e., light of a red wavelength band). The red wavelength band refers to a wavelength band of about 600 nm to about 750 nm. Accordingly, the first color filter CF1 can transmit light of the first color among light emitted from the first emission area EA1.

[0210] The second color filter CF2 can overlap the second emission area EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color (i.e., light of a green wavelength band). The green wavelength band refers to a wavelength band of about 480 nm to about 560 nm. Accordingly, the second color filter CF2 can transmit light of the second color among light emitted from the second emission area EA2.

[0211] The third color filter CF3 can overlap the third emission area EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of a third color (i.e., light of a blue wavelength band). The blue wavelength band refers to a wavelength band of about 370 nm to about 460 nm. Accordingly, the third color filter CF3 can transmit light of the third color among light emitted from the third emission area EA3.

[0212] The plurality of lenses LNS can be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS can be a structure for increasing a ratio of light directed to the front of the display device 10. Each of the plurality of lenses LNS can have a cross-sectional shape that is convex in the upward direction.

[0213] The filling layer FIL can be disposed on the plurality of lenses LNS. The filling layer FIL can have a predetermined refractive index such that light propagates in the third direction DR3 at an interface between the filling layer FIL and the plurality of lenses LNS. Further, the filling layer FIL can be a planarization layer. The filling layer FIL can be an organic film such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0214] The cover layer CVL can be disposed on the filling layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. In an embodiment in which the cover layer CVL is a glass substrate, the cover layer CVL can be attached onto the filling layer FIL. In such an embodiment, the filling layer FIL functions to bond the cover layer CVL. In an embodiment in which the cover layer CVL is a glass substrate, the cover layer CVL functions as an encapsulation substrate. In an embodiment in which the cover layer CVL is a polymer resin, the cover layer CVL can be directly coated onto the filling layer FIL.

[0215] The polarizing plate POL can be disposed on one surface of the cover layer CVL. The polarizing plate POL can be a structure for preventing visibility reduction caused by reflection of external light. The polarizing plate POL can include a linear polarizing plate and a phase retardation film. In an embodiment, for example, the phase retardation film can be a λ / 4 plate (a quarter wave plate), but embodiments of the disclosure are not limited thereto. However, when visibility reduction caused by reflection of external light is sufficiently overcome by the first to third color filters CF1, CF2, and CF3, the polarizing plate POL can be omitted.

[0216] ​ is an exploded perspective view illustrating a head-mounted display according to an embodiment.

[0217] Reference ​ Embodiments of the head-mounted display 1000 are formed in the form of glasses or a head-mounted to provide an image to a user using the display device 10_1.

[0218] The head-mounted display 1000 can include a see-through type that provides augmented reality based on actual external objects and a see-closed type that provides virtual reality to a user on a screen independent of external objects.

[0219] The head-mounted display 1000 can include a main frame MF mounted on a user's body, a display device 10_1 mounted on the main frame MF to display an image, and a cover frame CF covering the display device 10_1.

[0220] The display device 10_1 can be integrally provided in the head-mounted display 1000 that can be carried by a user and can be easily attached to or detached from a face or a head, and can be formed to be assembled to the head-mounted display 1000. The display device 10_1 can be substantially the same as the display device 10 described in conjunction with ​ and ​ The display device 10 described is substantially the same.

[0221] The display device 10_1 can include a display panel DP displaying an image, a first lens frame OS1 and a second lens frame OS2 refracting image display light, and a first multi-channel lens LS1 and a second multi-channel lens LS2 forming an optical path such that the image display light of the display panel DP is visible to a user.

[0222] The main frame MF can be worn on a face and a head of a user. The main frame MF can be formed in a shape corresponding to a head and face structure of a user.

[0223] The main frame MF can be integrally provided in the display device 10_1, that is, the display panel DP, the first lens frame OS1 and the second lens frame OS2, and the first multi-channel lens LS1 and the second multi-channel lens LS2. Alternatively, the display panel DP, the first lens frame OS1 and the second lens frame OS2, and the first multi-channel lens LS1 and the second multi-channel lens LS2 can be assembled and mounted to the main frame MF. In such an embodiment, the main frame MF can have a space or a structure for accommodating the display panel DP, the first lens frame OS1 and the second lens frame OS2, and the first multi-channel lens LS1 and the second multi-channel lens LS2. The main frame MF can further include a structure such as a strap or a band for facilitating mounting, and a controller, an image processing unit, and a lens accommodation unit can be further included in the main frame MF.

[0224] The display panel DP can be divided into a front surface DP_FS displaying an image and a rear surface DP_RS located on the opposite side of the front surface DP_FS. Image display light can be emitted from the front surface DP_FS of the display panel DP. As will be described later, the first lens frame OS1 and the second lens frame OS2 can be disposed on the front surface DP_FS of the display panel DP, and the first multi-channel lens LS1 and the second multi-channel lens LS2 can be disposed on the front surfaces of the first lens frame OS1 and the second lens frame OS2. In an embodiment, although not shown, at least one infrared camera can be disposed on at least one of the front surface DP_FS or the rear surface DP_RS of the display panel DP. The display panel DP can be substantially the same as the display panel 100 described in connection with ​

[0225] In a state in which the first lens frame OS1 and the second lens frame OS2 and the first multi-channel lens LS1 and the second multi-channel lens LS2 are mounted and fixed, the display panel DP can be built in the main frame MF or can be detachably fitted to the main frame MF. Depending on the design of the display device 10_1 (e.g., the type of use of the display device 10_1), the display panel DP can be opaque, transparent, or translucent.

[0226] Each of the first lens frame OS1 and the second lens frame OS2 can have an area corresponding to an image display surface of the display panel DP, and can be formed in a shape corresponding to a shape of the image display surface. Further, the first lens frame OS1 and the second lens frame OS2 can be formed to have areas and shapes corresponding to areas and shapes of rear surfaces of the first multi-channel lens LS1 and the second multi-channel lens LS2, respectively. The rear surfaces of the first lens frame OS1 and the second lens frame OS2 can be attached to the image display surface of the display panel DP, and the first multi-channel lens LS1 and the second multi-channel lens LS2 can be attached to the front surfaces of the first lens frame OS1 and the second lens frame OS2, respectively. The first lens frame OS1 and the second lens frame OS2 refract image display light emitted from the image display surface of the display panel DP at a predetermined angle and provide it to the first multi-channel lens LS1 and the second multi-channel lens LS2 disposed on the front surfaces thereof, respectively.

[0227] ​In an embodiment, the first and second lens frames OS1 and OS2 can refract image display light emitted from an image display surface of the display panel DP toward an outer side (or toward an outer circumferential side) compared to a front side, and provide the refracted image display light to the first and second multi-lens LS1 and LS2 disposed on a front surface thereof, respectively. Specifically, the first and second lens frames OS1 and OS2 can refract image display light incident on a rear surface thereof toward an outer side (or toward an outer circumferential side), and provide the refracted image display light to a rear surface of the first and second multi-lens LS1 and LS2, respectively.

[0228] The first and second multi-lens LS1 and LS2 can form a path of light emitted through the first and second lens frames OS1 and OS2 such that the image display light is visible to the eyes of a user on the front side.

[0229] The first and second multi-lens LS1 and LS2 can provide a plurality of channels (or paths) through which the image display light emitted from the display panel DP passes. The plurality of channels can provide the image display light emitted from the display panel DP to the user through different paths. The image display light emitted through the first and second lens frames OS1 and OS2 can be incident on each of the channels, and the image amplified through each of the channels can be focused on the eyes of the user.

[0230] The first and second multi-lens LS1 and LS2 can be disposed on a front surface of the first and second lens frames OS1 and OS2, respectively, to correspond to positions of the left and right eyes of the user. The first and second multi-lens LS1 and LS2 can be accommodated in the main frame MF.

[0231] The first and second multi-lens LS1 and LS2 can refract and / or reflect the image display light emitted through the first and second lens frames OS1 and OS2 at least once to form a path to the eyes of the user. At least one infrared light source can be further disposed at the main frame MF, or on a side of each of the first and second multi-lens LS1 and LS2 facing the eyes of the user.

[0232] The cover frame CF can be disposed on a rear surface DP_RS of the display panel DP to cover the display panel DP, and can protect the display panel DP. The cover frame CF can be attached to the main frame MF while covering the display panel DP.

[0233] In an embodiment, the display apparatus 10_1 can further include a controller (not shown) for controlling overall operations of the display apparatus 10_1 including the display panel DP. The controller can control an image display operation of the display panel DP and an audio apparatus. In such an embodiment, the controller performs image processing (e.g., image mapping) according to the magnification and an image display path corresponding to the first and second lens frames OS1 and OS2 and the first and second multi-lens LS1 and LS2, and controls the mapped image to be displayed on the display panel DP. The controller can be implemented as a special-purpose processor including an embedded processor and / or a general-purpose processor including a central processing unit or an application processor, but is not limited thereto.

[0234] ​ is a perspective view illustrating an augmented reality content providing apparatus according to an embodiment. ​ is ​ a rear exploded perspective view of the augmented reality content providing apparatus of ​ is ​ a front exploded perspective view of the augmented reality content providing apparatus of

[0235] Referring to ​ , ​ and ​ , an embodiment of the augmented reality content providing apparatus 1000_1 can include a support frame 1002 supporting at least one transparent lens 1001, at least one image display module 1010, a surrounding environment detector 1040, and a control module 1020.

[0236] The support frame 1002 can be formed in the form of glasses including a frame supporting edges of the at least one transparent lens 1001 and temple pieces of the glasses. The shape of the support frame 1002 is not limited to the glasses type, and can be formed in a type of goggles including the transparent lens 1001 or a head-mounted type.

[0237] The transparent lens 1001 can include left and right portions formed integrally with each other or first and second transparent lenses formed separately from each other. The transparent lens 1001 including the integral left and right portions or the separate first and second transparent lenses can include or be made of transparent or translucent glass or plastic. Accordingly, a user can view a real image through the transparent lens 1001 including the integral left and right portions or the separate first and second transparent lenses. Here, the transparent lens 1001 (i.e., the integral lens or the first and second transparent lenses) can have a refractive power in consideration of the user's eyesight.

[0238] The transparent lens 1001 can further include at least one reflecting member that reflects an augmented reality content image provided from the at least one image display module 1010 toward the transparent lens 1001 or the user's eyes, and an optical member that adjusts a focal point and a size. One or more reflecting members can be built in the transparent lens 1001 to be integrated with the transparent lens 1001, and can be formed as a plurality of refractive lenses or a plurality of prisms having a predetermined curvature.

[0239] The at least one image display module 1010 can include a micro LED display device (micro LED), a nano LED display device (nano LED), an organic light emitting display device (OLED), an inorganic light emitting display device (inorganic EL), a quantum dot light emitting display device (QED), a cathode ray display (CRT), or a liquid crystal display (LCD), etc. The image display module 1010 can substantially include the display device 10 described with reference to ​ and ​ described above.

[0240] The surrounding environment detector 1040 is assembled or integrally formed with the support frame 1002, and detects a distance (or depth) from an object of the front side of the support frame 1002, an illuminance, a moving direction, a moving distance, or a tilt of the support frame 1002, etc. To this end, the surrounding environment detector 1040 includes a depth sensor 1041 such as an infrared sensor or a LiDAR sensor, and an image sensor 1050 such as a camera. Further, the surrounding environment detector 1040 can further include at least one motion sensor among an illumination sensor, a human body detection sensor, a gyro sensor, a tilt sensor, and an acceleration sensor. Further, the surrounding environment detector 1040 can further include a first biological sensor 1031 and a second biological sensor 1032 for detecting motion information of the user's eyes or pupils.

[0241] The surrounding environment detector 1040 can transmit sensing signals generated by the depth sensor 1041 and the at least one motion sensor to the control module 1020 in real time. Further, the image sensor 1050 can transmit image data generated in real time in units of at least one frame to the control module 1020. The first biological sensor 1031 and the second biological sensor 1032 of the surrounding environment detector 1040 can transmit detected pupil detection signals to the control module 1020.

[0242] The control module 1020 can be assembled to at least one side of the support frame 1002 together with the at least one image display module 1010, or can be formed integrally with the support frame 1002. The control module 1020 supplies augmented reality content data to the at least one image display module 1010, so that the at least one image display module 1010 displays augmented reality content (e.g., augmented reality content images). At the same time, the control module 1020 can receive sensing signals, image data, and pupil detection signals from the surrounding environment detector 1040 in real time.

[0243] Hereinafter, an apparatus for manufacturing the display devices 10 and 10_1 according to an embodiment will be described.

[0244] ​ is a perspective view illustrating an apparatus for manufacturing a display device according to an embodiment. ​ is a cross-sectional view illustrating an apparatus for manufacturing a display device according to an embodiment. ​ is a perspective view showing a carrier according to an embodiment. ​ It is shown along ​ A cross-sectional view of the carrier taken along line X2-X2'.

[0245] Apart from ​ In addition, reference ​ An embodiment of a display device manufacturing apparatus 2000 may be an apparatus that combines a wafer WF and a carrier 2200. The wafer WF may be the semiconductor substrate SSUB of the display devices 10 and 101 according to the above-described embodiments. The carrier 2200 is a transport device used to mount and transport the wafer WF during the manufacturing process of the display devices 10 and 101 according to the embodiments.

[0246] Unlike conventional display processes for performing micro-scale patterning processes, in embodiments of the manufacturing process of display devices 10 and 10_1, finer patterning processes and semiconductor processes capable of unit integration can be performed to achieve high resolution. In embodiments where semiconductor processes are performed, semiconductor process equipment is used instead of conventional display process equipment. However, to reduce costs, conventional display process equipment can be used in logistics / transport equipment for moving or storing target wafers WF between various semiconductor processes. In addition, to reduce costs, conventional display process equipment can be used in processes other than semiconductor processes for achieving high resolution where conventional display process equipment can be used.

[0247] The shape and size of a conventional mother substrate using a polymer resin substrate such as polyimide or a glass substrate are different from the shape and size of the wafer WF included in the display apparatuses 10 and 10_1 according to the above-described embodiments. Accordingly, in order to use a conventional display process equipment, the display apparatus manufacturing equipment 2000 according to the embodiments can bind the wafer WF to a carrier 2200 having the same shape and size as those of the conventional mother substrate. The wafer WF bound to the carrier 2200 can correspond to an object in the conventional display process equipment.

[0248] The display apparatus manufacturing equipment 2000 according to the embodiments can include a carrier transfer unit 2100, a carrier 2200, an alignment unit 2300, a first vision device 2400, a wafer transfer unit 2500, a second vision device 2600, a pressing unit 2700, and a controller 2800.

[0249] The carrier transfer unit 2100 carries and transfers the carrier 2200. The carrier transfer unit 2100 can adjust the position of the carrier 2200 on the alignment unit 2300. The carrier transfer unit 2100 can mount the carrier 2200 on the alignment unit 2300.

[0250] The carrier 2200 is a transport device for mounting and transferring the wafer WF. As described above, the carrier 2200 can have the same shape and size as those of a mother substrate used in a conventional display process. In embodiments, for example, the carrier 2200 can have a quadrilateral shape in a plan view, but is not limited thereto.

[0251] In some embodiments, the carrier 2200 can have the same size as that of a 10.5th generation mother substrate having a width of 2940 millimeters (mm) and a height of 3370 mm, the same size as that of an 8th generation mother substrate having a width of 2200 mm and a height of 2500 mm, the same size as that of a 7th generation mother substrate having a width of 1870 mm and a height of 2200 mm, the same size as that of a 6th generation mother substrate having a width of 1500 mm and a height of 1850 mm, the same size as that of a 5.5th generation mother substrate having a width of 1300 mm and a height of 1500 mm, the same size as that of a 4th generation mother substrate having a width of 730 mm and a height of 920 mm, the same size as that of a 3rd generation mother substrate having a width of 550 mm and a height of 650 mm, the same size as that of a 2nd generation mother substrate having a width of 370 mm and a height of 470 mm, or the same size as that of a 1st generation mother substrate having a width of 270 mm and a height of 360 mm. However, the size of the carrier 2200 is not limited thereto.

[0252] The carrier 2200 can include a carrier body 2210, a wafer receiving portion 2220, a pin hole 2230, a carrier mark 2240, a bonding portion 2250, a buffer portion 2260, and a step compensation portion 2270.

[0253] The carrier body 2210 constitutes the overall shape of the carrier 2200. The carrier body 2210 can support the wafer WF. In the display device manufacturing method S1 (see ​ ), the carrier 2210 can be mounted on the alignment unit 2300. In the manufacturing process of the display device 10 and 10_1 according to the above-described embodiments, the carrier 2210 can be mounted on a manufacturing process apparatus.

[0254] The wafer receiving portion 2220 can be provided on the carrier body 2210. In an embodiment, for example, the wafer receiving portion 2220 can be a recess that is recessed from the top surface of the carrier body 2210 to the bottom surface. The wafer receiving portion 2220 provides a space in which the wafer WF can be received. The shape of the wafer receiving portion 2220 can correspond to the shape of the wafer WF. The size of the wafer receiving portion 2220 can be greater than or equal to the size of the wafer WF.

[0255] The pin hole 2230 can be defined or formed in the carrier body 2210. In an embodiment, for example, the pin hole 2230 can be a hole that extends in the third direction DR3 from the bottom surface of the wafer receiving portion 2220 to the bottom surface of the carrier body 2210. At least one pin hole 2230 can be provided in the carrier body 2210, and preferably, a plurality of pin holes can be provided. The pin hole 2230 can be a passage through which the pin 2320 of the alignment unit 2300 can reciprocate in the third direction DR3.

[0256] The carrier mark 2240 can be located on the carrier body 2210. In an embodiment, for example, the carrier mark 2240 can be located on the top surface of the carrier body 2210. The carrier mark 2240 can be disposed outside the wafer receiving portion 2220. At least one carrier mark 2240 can be provided on the carrier body 2210, for example, a plurality of carrier marks can be provided. In an embodiment, as shown in ​ , four carrier marks 2240 can be provided, but the present disclosure is not limited thereto, and the shape of the carrier mark 2240 is also not limited to the shape shown in the drawings.

[0257] The carrier mark 2240 is an alignment mark for aligning the wafer WF and the carrier 2200. In an embodiment, for example, the wafer WF can include wafer marks WF_M. At least one wafer mark WF_M can be disposed on the wafer WF, and preferably, a plurality of wafer marks can be provided. In an embodiment, for example, the number of wafer marks WF_M can be the same as the number of carrier marks 2240, but the present disclosure is not limited thereto. Whether the carrier 2200 and the wafer WF are properly aligned with each other can be determined by the relative positions of the carrier marks 2240 and the wafer marks WF_M.

[0258] As shown in FIGS. 1A and 1B, the wafer WF can be coupled to the carrier 2200. The wafer WF can be coupled to the carrier 2200 by the coupling portion 2250. The coupling portion 2250 can be disposed in the wafer accommodating portion 2220. The coupling portion 2250 can be disposed on the bottom surface of the wafer accommodating portion 2220. When the wafer WF and the carrier 2200 are coupled, the coupling portion 2250 can be located between the wafer WF and the bottom surface of the wafer accommodating portion 2220. The coupling portion 2250 is a coupling device for coupling the wafer WF and the carrier 2200 to each other. ​ ​ As shown in FIGS. 1A and 1B, the wafer WF can be coupled to the carrier 2200. The wafer WF can be coupled to the carrier 2200 by the coupling portion 2250. The coupling portion 2250 can be disposed in the wafer accommodating portion 2220. The coupling portion 2250 can be disposed on the bottom surface of the wafer accommodating portion 2220. When the wafer WF and the carrier 2200 are coupled, the coupling portion 2250 can be located between the wafer WF and the bottom surface of the wafer accommodating portion 2220. The coupling portion 2250 is a coupling device for coupling the wafer WF and the carrier 2200 to each other.

[0259] In an embodiment, the coupling portion 2250 can include an adhesive material or a tacky material. In an embodiment, for example, the coupling portion 2250 can include a physical adhesive chuck.

[0260] In another embodiment, the coupling portion 2250 can use an electrostatic force to participate in coupling and decoupling between the wafer WF and the carrier 2200. In an embodiment, for example, the coupling portion 2250 can include an electrostatic chuck. In some embodiments, when the coupling portion 2250 includes the electrostatic chuck, the display device manufacturing apparatus 2000 can further include a separate electrostatic power supply unit capable of supplying an electrostatic force to the electrostatic chuck and a lead wire connecting the electrostatic power supply unit to the electrostatic chuck.

[0261] As shown in FIGS. 1A and 1B, the wafer WF can be coupled to the carrier 2200. The wafer WF can be coupled to the carrier 2200 by the coupling portion 2250. The coupling portion 2250 can be disposed in the wafer accommodating portion 2220. The coupling portion 2250 can be disposed on the bottom surface of the wafer accommodating portion 2220. When the wafer WF and the carrier 2200 are coupled, the coupling portion 2250 can be located between the wafer WF and the bottom surface of the wafer accommodating portion 2220. The coupling portion 2250 is a coupling device for coupling the wafer WF and the carrier 2200 to each other. ​ ​ ​​As shown in FIG. 22A, a buffer portion 2260 can be provided in the wafer accommodation portion 2220. The buffer portion 2260 can be provided on a bottom surface of the wafer accommodation portion 2220. The buffer portion 2260 can be provided on a portion of the bottom surface of the wafer accommodation portion 2220 other than a portion on which the bonding portion 2250 is provided. The buffer portion 2260 can be located between the wafer WF and the bottom surface of the wafer accommodation portion 2220 when the wafer WF and the carrier 2200 are bonded. In some embodiments, the buffer portion 2260 can be positioned closer to the center of the wafer accommodation portion 2220 than the bonding portion 2250 in a plan view. That is, the bonding portion 2250 can be positioned closer to the outer edge of the wafer accommodation portion 2220 than the buffer portion 2260 in a plan view. The buffer portion 2260 reduces the amount of impact applied to the wafer WF when the wafer WF and the carrier 2200 are bonded. In embodiments, for example, the buffer portion 2260 can include an embossed material.

[0262] In some embodiments, as shown in FIG. 22B, the buffer portion 2260 can be a stepped structure. Accordingly, when the wafer WF and the carrier 2200 are bonded, the amount of impact is dispersed, and bubbles are effectively prevented from accumulating at the center portion. ​

[0263] As shown in FIG. 22A, a step compensation portion 2270 can be provided in the wafer accommodation portion 2220. The step compensation portion 2270 can be provided on a bottom surface of the wafer accommodation portion 2220. The step compensation portion 2270 can be provided between the bonding portion 2250 and the bottom surface of the wafer accommodation portion 2220. ​

[0264] The step compensation portion 2270 is a means for compensating for a difference in height between the bonding portion 2250 and the buffer portion 2260. For example, in some embodiments, a thickness H2 of the buffer portion 2260 can be greater than a thickness H1 of the bonding portion 2250. In this case, the step compensation portion 2270 can be provided below the bonding portion 2250. The thickness H2 of the buffer portion 2260 can be substantially equal to a sum of the thickness H1 of the bonding portion 2250 and a thickness H3 of the step compensation portion 2270.

[0265] The alignment unit 2300 is an alignment means for aligning the carrier 2200 and the wafer WF. The alignment unit 2300 can be provided below the carrier 2200. The alignment unit 2300 can adjust a position of the wafer WF in a first direction DR1 (e.g., x), a position in a second direction DR2 (e.g., y), a position in a third direction DR3, and a rotation angle of the wafer WF (e.g., θ). ​ ​ ​ ​​​​θ) of the alignment unit 2300. In an embodiment, for example, the alignment unit 2300 can be a UVW (three-phase) stage.

[0266] The alignment unit 2300 can include a base 2310, pins 2320, a pin driver 2330, a carrier fixing member 2340, and a first pressure sensor 2350.

[0267] The base 2310 provides a space in which other components such as the pins 2320, the pin driver 2330, the carrier fixing member 2340, and the first pressure sensor 2350 of the alignment unit 2300 can be disposed. The base 2310 can support other components of the alignment unit 2300. Although ​ Embodiments in which the base 2310 has a quadrangular shape are illustrated, but the present disclosure is not limited thereto.

[0268] The pins 2320 can be disposed on the base 2310. The pins 2320 can be disposed between the base 2310 and the carrier 2200. The pins 2320 can have a shape extending in the third direction DR3. The pins 2320 can be posts extending from a top surface of the base 2310 in the third direction DR3. At least one pin 2320 can be disposed on the base 2310, for example, a plurality of pins can be provided. The number of pins 2320 can be substantially the same as the number of pin holes 2230. The pins 2320 can pass through the pin holes 2230 to support the wafer WF. The pins 2320 can mount the wafer WF in the wafer receiving portion 2220 of the carrier 2200 while moving in the opposite direction of the third direction DR3 by the pin driver 2330. Alternatively, the pins 2320 can separate the wafer WF bonded to the carrier 2200 from the carrier 2200 while moving in the third direction DR3 by the pin driver 2330.

[0269] In some embodiments, as shown in FIG. 22B, the width W2 of the pin hole 2230 can be greater than or equal to the width W1 of the pin 2320. Although ​ Embodiments in which the pin 2320 has a cylindrical shape are illustrated, but the present disclosure is not limited thereto. ​ Embodiments in which the pin 2320 has a cylindrical shape are illustrated, but the present disclosure is not limited thereto.

[0270] The pin driver 2330 can be disposed on the base 2310. The pin driver 2330 can be disposed between the pins 2320 and the base 2310 in the third direction DR3. The pin driver 2330 can be a driving device for adjusting the position of the pins 2320. In some embodiments, the pin driver 2330 can include a vertical driver 2331 and a rotational driver 2332.

[0271] The vertical driver 2331 can move the pin 2320 in the third direction DR3. In an embodiment, for example, the vertical driver 2331 can extend or contract in the third direction DR3 to move the pin 2320 in the third direction DR3. Accordingly, the wafer WF mounted on the pin 2320 can be moved in the third direction DR3. The rotational driver 2332 can adjust the rotation angle of the pin 2320. Accordingly, the rotation angle of the wafer WF mounted on the pin 2320 can be adjusted.

[0272] The carrier fixing member 2340 can be provided on the base 2310. The carrier fixing member 2340 can be provided between the base 2310 and the carrier 2200. In some embodiments, as shown in the drawings, the carrier fixing member 2340 can have a shape extending in the third direction DR3. The carrier fixing member 2340 can be a column extending from the top surface of the base 2310 in the third direction DR3. However, the present disclosure is not limited thereto, and the carrier fixing member 2340 can have various shapes capable of supporting the carrier 2200 between the base 2310 and the carrier 2200.

[0273] In some embodiments, at least one carrier fixing member 2340 can be provided on the base 2310, and preferably, a plurality of carrier fixing members can be provided. In an embodiment, for example, as shown in the drawings, four carrier fixing members 2340 can be provided adjacent to the corners of the base 2310. However, the present disclosure is not limited thereto, and the carrier fixing member 2340 can be one wall provided around the pin 2320 and along the outer edge of the base 2310. The number and shape of the carrier fixing member 2340 are not limited to the number and shape shown in the drawings.

[0274] The carrier fixing member 2340 can support the carrier 2200. The carrier 2200 can be mounted on the carrier fixing member 2340. When the carrier 2200 and the wafer WF are combined with each other, the carrier fixing member 2340 can fix the carrier 2200.

[0275] The first pressure sensor 2350 can be provided between the base 2310 and the pin 2320 in the third direction DR3. In an embodiment, for example, the first pressure sensor 2350 can be provided between the pin driver 2330 and the pin 2320 in the third direction DR3. The first pressure sensor 2350 can be provided under the pin 2320. In some embodiments, the first pressure sensor 2350 can be provided one-to-one for each pin 2320. When the wafer WF is separated in the wafer separation inspection process (process S500) (see ​ ), the first pressure sensor 2350 can measure the pressing force applied to each pin 2320.

[0276] In an embodiment, the alignment unit 2300 can further include a base driver (not shown). The base driver can be a driving device for adjusting the position of the base 2310 and other components disposed on the base 2310. In an embodiment, for example, the base driver can move the base 2310 and other components disposed on the base 2310 in the first direction DR1, the second direction DR2, and the third direction DR3. When the base driver moves the base 2310 in the first direction DR1 and the second direction DR2, the wafer WF can move in the first direction DR1 and the second direction DR2 along the pin 2320. When the base driver moves the base 2310 in the third direction DR3, the carrier fixing member 2340 can move in the third direction DR3 to mount the carrier 2200.

[0277] In an embodiment, the alignment unit 2300 can further include a housing (not shown) that can be spaced apart from the outside space and accommodate other components of the alignment unit 2300 such as the base 2310, the pin 2320, the pin driver 2330, the carrier fixing member 2340, and the first pressure sensor 2350. The housing can be disposed on the side surface of the alignment unit 2300 to surround the base 2310, the pin 2320, the pin driver 2330, the carrier fixing member 2340, and the first pressure sensor 2350.

[0278] The first vision device 2400 can be disposed on the carrier 2200 and the alignment unit 2300. The first vision device 2400 can capture images of the carrier 2200 and the alignment unit 2300. The first vision device 2400 provides the captured images of the carrier 2200 and the alignment unit 2300 to the controller 2800.

[0279] In some embodiments, the first vision device 2400 can include first to fourth cameras 2410, 2420, 2430, and 2440. The first to fourth cameras 2410, 2420, 2430, and 2440 can be disposed on the corners of the carrier 2200 and the corners of the alignment unit 2300. The first to fourth cameras 2410, 2420, 2430, and 2440 can capture images of the corners of the carrier 2200 and the corners of the alignment unit 2300, and the controller 2800 can determine whether the corners of the carrier 2200 and the corners of the alignment unit 2300 are properly aligned with each other. However, the number of cameras included in the first vision device 2400 is not limited thereto and can be variously changed. In an embodiment, for example, the number of cameras included in the first vision device 2400 can be equal to the number of corners of the carrier 2200.

[0280] The wafer transfer unit 2500 carries and transfers the wafer WF. The wafer transfer unit 2500 can adjust the position of the wafer WF on the carrier 2200 and the alignment unit 2300. The wafer transfer unit 2500 can mount the wafer WF on the pins 2320 of the alignment unit 2300.

[0281] The second vision device 2600 can be disposed on the carrier 2200 and the wafer WF. In some embodiments, the second vision device 2600 can be disposed on the side wall of the pressing unit 2700, but the present disclosure is not limited thereto. The second vision device 2600 can capture images of the carrier 2200 and the wafer WF. The second vision device 2600 provides the captured images of the carrier 2200 and the wafer WF to the controller 2800.

[0282] In some embodiments, the second vision device 2600 can include fifth to eighth cameras 2610, 2620, 2630, and 2640. The fifth to eighth cameras 2610, 2620, 2630, and 2640 can be disposed on the outer edge (or side wall) of the wafer accommodation portion 2220. The fifth to eighth cameras 2610, 2620, 2630, and 2640 can capture images of the carrier mark 2240 of the carrier 2200 and the wafer mark WF_M of the wafer WF, and the controller 2800 can determine whether the carrier mark 2240 and the wafer mark WF_M of the wafer WF are properly aligned with each other. However, the number of cameras included in the second vision device 2600 is not limited thereto and can be variously changed. In an embodiment, for example, the number of cameras included in the second vision device 2600 can be equal to the number of carrier marks 2240.

[0283] The pressing unit 2700 can be disposed on the carrier 2200 and the wafer WF. The pressing unit 2700 provides a pressing force to the wafer WF mounted on the carrier 2200. The wafer WF can be bonded to the carrier 2200 by the pressing force of the pressing unit 2700.

[0284] In some embodiments, the pressing unit 2700 can include a pressing member body 2710, a pressing member 2720, and a second pressure sensor 2730.

[0285] The pressing member body 2710 constitutes the overall shape of the pressing unit 2700. The pressing member body 2710 provides a space in which the pressing member 2720 and the second pressure sensor 2730 are disposed. Although ​ and ​ Embodiments in which the pressing member body 2710 has a cuboid shape are illustrated, but the shape of the pressing member body 2710 is not limited thereto.

[0286] The pressing part 2720 may be provided on the pressing part body 2710. In an embodiment, for example, the pressing part 2720 may be provided on the bottom surface of the pressing part body 2710. The pressing part 2720 may be provided between the pressing part body 2710 and the carrier 2200 or between the pressing part body 2710 and the wafer WF. When pressing the wafer WF, the pressing part 2720 may be in direct contact with the wafer WF. The pressing part 2720 may include an elastic material to minimize damage to the wafer WF. A plurality of pressing parts 2720 may be provided to distribute the pressing force applied to the wafer WF. In such an embodiment, the pressing parts 2720 of the island structure may be evenly distributed on the bottom surface of the pressing part body 2710. Although for ease of illustration, in ​ Three pressing members 2720 are shown in the figure, but the number of pressing members 2720 is not limited thereto.

[0287] The second pressure sensor 2730 may be provided between the pressing member body 2710 and the pressing member 2720. In an embodiment, for example, the second pressure sensor 2730 may be provided between the pressing member body 2710 and the pressing member 2720 in the third direction DR3. The second pressure sensor 2730 may be provided on the pressing member 2720. In some embodiments, the second pressure sensor 2730 may be provided one-to-one for each pressing member 2720. When the wafer is initially pressed (process S300) (see ​ ), wafer secondary pressing process (process S700) (see ​ ) and wafer pressing process again (process S930) (see ​ ) when the wafer WF is pressed, the second pressure sensor 2730 may measure the pressing force applied to each pressing member 2720.

[0288] In an embodiment, the pressing unit 2700 may further include a pressing driver (not shown). The pressing driver may be a driving device for adjusting the position of the pressing unit 2700. In an embodiment, for example, the pressing driver may move the pressing unit 2700 in the third direction DR3. When the pressing driver moves the pressing unit 2700 in the third direction DR3, the pressing member 2720 may press the wafer WF to couple the wafer WF to the carrier 2200.

[0289] The controller 2800 can perform operations for controlling other components of the display device manufacturing apparatus 2000, and generate and provide processing signals to the other components. In an embodiment, for example, the controller 2800 can determine whether the carrier 2200 and the alignment unit 2300 are aligned, and control the carrier transfer unit 2100, the alignment unit 2300, and the first vision device 2400 to align the carrier 2200 and the alignment unit 2300. In another embodiment, for example, the controller 2800 can determine whether the carrier 2200 and the wafer WF are aligned, and control the alignment unit 2300, the wafer transfer unit 2500, and the second vision device 2600 to align the carrier 2200 and the wafer WF. In another embodiment, for example, when the wafer WF and the carrier 2200 are combined, the controller 2800 can control the pressing unit 2700 to control the pressing force. In another embodiment, for example, the controller 2800 can control the alignment unit 2300 to control the pressing force when the wafer WF is separated.

[0290] Hereinafter, further reference will be made to ​ The controller 2800 is described.

[0291] ​ is a block diagram illustrating a controller according to an embodiment.

[0292] In addition to ​ , with reference to ​ , an embodiment of the controller 2800 can include an alignment processing unit 2810, an alignment correction value calculation unit 2820, a pressing processing unit 2830, and a separation processing unit 2840.

[0293] The alignment processing unit 2810 can control alignment between the carrier 2200 and the alignment unit 2300, and alignment between the carrier 2200 and the wafer WF.

[0294] In an embodiment, for example, the alignment processing unit 2810 can provide a driving signal to the carrier transfer unit 2100 to position the carrier 2200 on the alignment unit 2300. The alignment processing unit 2810 can provide a driving signal to the first vision device 2400 to capture an image of the carrier 2200 and the alignment unit 2300. The alignment processing unit 2810 can determine whether the carrier 2200 and the alignment unit 2300 are properly aligned with each other based on the image captured by the first vision device 2400. When the carrier 2200 and the alignment unit 2300 are properly or correctly aligned, the alignment processing unit 2810 can provide a driving signal to the alignment unit 2300 to mount and fix the carrier 2200 on the carrier fixing part 2340 of the alignment unit 2300.

[0295] In another embodiment, for example, the alignment processing unit 2810 can provide a driving signal to the wafer transfer unit 2500 to position the wafer WF on the carrier 2200. The alignment processing unit 2810 can provide a driving signal to the second vision device 2600 to capture an image of the carrier mark 2240 of the carrier 2200 and the wafer mark WF M of the wafer WF. The alignment processing unit 2810 can determine whether the carrier 2200 and the wafer WF are properly aligned with each other based on the image captured by the second vision device 2600. When the carrier 2200 and the wafer WF are correctly or properly aligned with each other, the alignment processing unit 2810 can provide a driving signal to the pin driver 2330 of the alignment unit 2300 to mount the wafer WF in the wafer-receiving portion 2220 of the carrier 2200.

[0296] The alignment correction value calculation unit 2820 can calculate the degree of deformation of the wafer WF due to the pressing. The alignment correction value calculation unit 2820 can calculate the degree of deformation of the wafer WF due to the pressing as a correction value, and reflect the correction value in advance when re-aligning the wafer WF.

[0297] In an embodiment, for example, after pressing the wafer WF, the alignment correction value calculation unit 2820 can provide a driving signal to the second vision device 2600 to capture an image of the carrier mark 2240 of the carrier 2200 and the wafer mark WF M of the wafer WF again. The alignment correction value calculation unit 2820 can calculate the degree of deformation of the wafer WF based on the image captured by the second vision device 2600 after the pressing by comparing the image before the pressing with the image after the pressing. The alignment correction value calculation unit 2820 can calculate the degree of deformation of the wafer WF after the pressing as a correction value, and provide the correction value to the alignment unit 2300. The alignment unit 2300 can align the wafer WF and the carrier 2200 by offsetting the correction value from the previous alignment position, and in this state, the secondary pressing of the wafer WF can be performed again.

[0298] In an embodiment, when deformation occurs between the wafer WF and the carrier 2200 even after the secondary pressing, the alignment correction value calculation unit 2820 can calculate a new correction value using accumulated data of the previous correction values. This will be described later with reference to FIGS. 11A to 11C. ​ This will be described.

[0299] In the display device manufacturing apparatus 2000 according to the embodiment, the alignment accuracy of the carrier 2200 and the wafer WF can be improved by the alignment correction value calculation unit 2820 calculating the correction value.

[0300] The pressing processing unit 2830 can control the pressing force of the pressing unit 2700 when pressing the wafer WF.

[0301] In an embodiment, for example, the pressing processing unit 2830 can provide a driving signal to the pressing unit 2700 to cause the pressing member 2720 to press the wafer WF mounted on the carrier 2200. Meanwhile, the pressing processing unit 2830 can receive, in real time, the pressing force applied to the pressing member 2720 from the second pressure sensor 2730 of the pressing unit 2700. Accordingly, the pressing processing unit 2830 can cause the pressing unit 2700 to provide an appropriate pressing force to the wafer WF in real time, thereby effectively preventing damage to the wafer WF.

[0302] The separation processing unit 2840 can control the pressing force of the alignment unit 2300 when separating the wafer WF.

[0303] In an embodiment, for example, the separation processing unit 2840 can provide a driving signal to the alignment unit 2300 to cause the pin 2320 to press the wafer WF bonded to the carrier 2200. Meanwhile, the separation processing unit 2840 can receive, in real time, the pressing force applied to the pin 2320 from the first pressure sensor 2350 of the alignment unit 2300. Accordingly, the separation processing unit 2840 can cause the alignment unit 2300 to provide an appropriate pressing force to the wafer WF in real time, thereby effectively preventing damage to the wafer WF.

[0304] Hereinafter, a method of manufacturing a display device according to an embodiment will be described.

[0305] ​ is a flowchart illustrating a method of manufacturing a display device according to an embodiment.

[0306] Reference ​ According to the display device manufacturing method S1 of the embodiment, the carrier and alignment unit alignment process (process S100), the wafer primary alignment and mounting process (process S200), the wafer primary pressing process (process S300), the primary deformation inspection process (process S400), the wafer separation inspection process (process S500), the wafer secondary alignment and mounting process (process S600), the wafer secondary pressing process (process S700), the secondary deformation inspection process (process S800), and the alignment correction value recalculation and wafer realignment process (process S900) can be included.

[0307] The alignment correction value recalculation and wafer realignment process (process S900) can include the alignment correction value recalculation process (process S910), the wafer realignment and mounting process (process S920), the wafer re-pressing process (process S930), and the deformation re-inspection process (process S940).

[0308] ​ is a cross-sectional view illustrating ​ process S100 of FIG. 10.

[0309] In addition to ​ and ​ , with reference to ​ , in the carrier and alignment unit alignment process (process S100), the carrier transfer unit 2100 (see ​ ) can receive a driving signal from the alignment processing unit 2810 of the controller 2800 to position the carrier 2200 on the alignment unit 2300.

[0310] The first vision device 2400 can receive a driving signal from the alignment processing unit 2810 of the controller 2800 to capture images of the carrier 2200 and the alignment unit 2300. The first vision device 2400 can provide the captured images to the alignment processing unit 2810 of the controller 2800.

[0311] The alignment processing unit 2810 can determine whether the carrier 2200 and the alignment unit 2300 are properly aligned with each other based on the images captured by the first vision device 2400 and provided thereto. The alignment processing unit 2810 can provide a driving signal to the carrier transfer unit 2100 (see ​ ) in real time to align the carrier 2200 with the alignment unit 2300.

[0312] When the carrier 2200 and the alignment unit 2300 are properly or properly aligned, the alignment unit 2300 can receive a driving signal from the alignment processing unit 2810 and move in the third direction DR3. Accordingly, the carrier 2200 can be mounted and fixed on the carrier fixing part 2340 of the alignment unit 2300.

[0313] ​ and ​ are sectional views showing the process S200 of ​ .

[0314] In addition to ​ and ​ , with reference to ​ and ​ , in the wafer primary alignment and mounting process (process S200), the wafer transfer unit 2500 (see ​ ) can receive a driving signal from the alignment processing unit 2810 of the controller 2800 to position the wafer WF on the carrier 2200.

[0315] The second vision device 2600 can receive a driving signal from the alignment processing unit 2810 of the controller 2800 to capture images of the carrier mark 2240 of the carrier 2200 and the wafer mark WF_M of the wafer WF. The second vision device 2600 can provide the captured images to the alignment processing unit 2810 of the controller 2800.

[0316] The alignment processing unit 2810 may determine whether the carrier 2200 and the wafer WF are properly aligned with each other based on the image captured and provided thereto by the first vision device 2400. The alignment processing unit 2810 may provide a driving signal to the wafer transfer unit 2500 (see FIG. ​ ) to align the wafer WF with the carrier 2200.

[0317] When the carrier 2200 and the wafer WF are correctly or properly aligned with each other, the pin driver 2330 of the alignment unit 2300 may receive a driving signal from the alignment processing unit 2810 and move in the third direction DR3. Accordingly, the wafer WF may be mounted on the pins 2320.

[0318] When the wafer WF is mounted on the pins 2320 , the pin driver 2330 of the alignment unit 2300 may receive a driving signal from the alignment processing unit 2810 and move in the opposite direction of the third direction DR3 .

[0319] ​ and ​ It shows ​ FIG. 5 is a cross-sectional view of the process S300 .

[0320] Apart from ​ and ​ In addition, reference ​ and ​ In the wafer initial pressing process (process S300), the pressing unit 2700 may receive a driving signal from the pressing processing unit 2830 and move in the opposite direction of the third direction DR3. Accordingly, the pressing member 2720 of the pressing unit 2700 may press the top surface of the wafer WF mounted on the carrier 2200.

[0321] While pressing, the second pressure sensor 2730 of the pressing unit 2700 can provide the pressing force applied to the pressing component 2720 to the pressing processing unit 2830 in real time. The pressing processing unit 2830 can store preset first pressing data so that when the wafer WF and the carrier 2200 are combined with each other, the pressing unit 2700 can apply an appropriate pressing force to the wafer WF. The first pressing data may include information about the maximum pressure and pressing time when combining the wafer WF and the carrier 2200. The pressing processing unit 2830 can provide the first pressing data to the pressing unit 2700 in real time so that the pressing unit 2700 can press the wafer WF with an appropriate pressing force. Accordingly, damage to the wafer WF can be effectively prevented.

[0322] In an embodiment,​ As shown in FIG, when the wafer WF is pressed, a slip phenomenon may occur depending on the pressing angle of the pressing member 2720, the thickness difference of the bonding portion 2250, or the friction between the wafer WF and the bonding portion 2250. Accordingly, the alignment of the wafer WF and the carrier 2200 may be distorted.

[0323] ​ It shows ​ FIG. 5 is a cross-sectional view of the process S400 . ​ is a plan view illustrating an embodiment of a method of measuring the degree of deformation of a wafer.

[0324] Apart from ​ and ​ In addition, reference ​ and ​ , in the primary deformation inspection process (process S400 ), the pressing unit 2700 may receive a driving signal from the pressing processing unit 2830 and move in the third direction DR3 .

[0325] After the initial pressing process, the second vision device 2600 may receive a driving signal from the alignment correction value calculation unit 2820 of the controller 2800 to recapture an image of the carrier mark 2240 of the carrier 2200 and the wafer mark WF_M of the wafer WF. The second vision device 2600 may provide the recaptured image to the alignment correction value calculation unit 2820 of the controller 2800.

[0326] The alignment correction value calculation unit 2820 may calculate the degree of distortion of the wafer WF based on the image captured by the second vision device 2600 after pressing and provided thereto by comparing the image captured before pressing with the image captured after pressing.

[0327] like ​ As shown in , the wafer WF" after pressing may be deformed to a certain extent compared to the wafer WF' before pressing. In an embodiment, for example, the center C" of the wafer WF" after pressing may be offset by x in the first direction DR1 and by y in the second direction DR2 from the center C' of the wafer WF' before pressing. Further, the wafer WF" after pressing may be rotated by θ compared to the wafer WF' before pressing.

[0328] The alignment correction value calculation unit 2820 may convert the degree of deformation of (x, y, θ) into a correction value of (-x, -y, -θ). The alignment correction value calculation unit 2820 may provide the correction value of (-x, -y, -θ) to the alignment unit 2300. The alignment unit 2300 may use the correction value in the wafer secondary alignment and mounting process (process S600). ​ and ​This is described together with the description of the wafer secondary alignment and mounting process (process S600).

[0329] ​ is a cross-sectional view illustrating the process S500 of ​ .

[0330] In addition to ​ and ​ , with reference to ​ , in the wafer separation inspection process (process S500), the pin driver 2330 of the alignment unit 2300 can receive a driving signal from the separation processing unit 2840 and move in the third direction DR3. Accordingly, the pin 2320 can press the bottom surface of the wafer WF bonded to the carrier 2200.

[0331] While being pressed, the first pressure sensor 2350 of the alignment unit 2300 can provide the pressing force applied to the pin 2320 to the separation processing unit 2840 in real time. The separation processing unit 2840 can store the second pressure data that is preset so that the alignment unit 2300 can apply an appropriate pressing force to the wafer WF when separating the wafer WF. The second pressing data can include information on the maximum pressure and the pressing time when the wafer WF is separated. The separation processing unit 2840 can provide the second pressing data to the alignment unit 2300 in real time so that the alignment unit 2300 can press the wafer WF with an appropriate pressing force. Accordingly, damage to the wafer WF can be effectively prevented.

[0332] The display device manufacturing method S1 according to the embodiment includes the wafer separation inspection process (process S500) so that process loss that occurs when the wafer WF is not separated after the manufacturing process of the display device is completely finished or when damage is caused by separation is checked in advance. Accordingly, the separation defective wafer WF can be selected in advance, thereby minimizing the process loss.

[0333] ​ and ​ is a cross-sectional view illustrating the process S600 of ​ . ​ is a schematic view illustrating alignment correction data processed by the controller.

[0334] In addition to ​ , ​ and ​ , with reference to ​ , in the wafer secondary alignment and mounting process (process S600), the alignment unit 2300 can receive the alignment correction value from the alignment correction value calculation unit 2820 of the controller 2800.

[0335] The alignment unit 2300 can move the wafer WF from the previous alignment position (e.g., the center C' of the wafer WF before pressing) by the above-mentioned correction values (-x, -y, -θ) based on the alignment correction values provided thereto from the alignment correction value calculation unit 2820 of the controller 2800 to align the wafer WF on the carrier 2200.

[0336] In the process in which the alignment unit 2300 aligns the wafer WF on the carrier 2200 by offsetting the alignment correction values, the second vision device 2600 can provide the captured images of the carrier mark 2240 and the wafer mark WF_M of the wafer WF to the alignment correction value calculation unit 2820 in real time. The alignment processing unit 2810 can provide a driving signal to the alignment unit 2300 based on the images from the second vision device 2600 to adjust the position and the rotation angle of the wafer WF.

[0337] When the carrier 2200 and the wafer WF are moved by the correction values and are properly aligned with each other, the pin driver 2330 of the alignment unit 2300 can receive a driving signal from the alignment correction value calculation unit 2820 and move in the opposite direction of the third direction DR3. Accordingly, the wafer WF can be mounted in the wafer receiving portion 2220 of the carrier 2200.

[0338] In an embodiment, as shown in ​ , the alignment correction value data ADT provided to the alignment unit 2300 by the alignment correction value calculation unit 2820 can include the alignment correction values t-10 to t-1 of the previous wafer WF and the correction value t of the current wafer WF. The correction value t of the current wafer WF refers to the correction value (-x, -y, -θ) calculated by the alignment correction value calculation unit 2820 after the first pressing of the current wafer WF. The alignment correction values t-10 to t-1 of the previous wafer WF will be described later with reference to ​ .

[0339] In the wafer secondary alignment and mounting process (process S600), the secondary alignment of the wafer WF can be performed using only the correction value t of the current wafer WF without using the alignment correction values t-10 to t-1 of the previous wafer WF.

[0340] ​ is a cross-sectional view showing ​ process S700.

[0341] In addition to ​ and ​ , with reference to ​ , in the wafer secondary pressing process (process S700), the pressing unit 2700 can press the wafer WF. Since the wafer secondary pressing process (process S700) is the same as that described with reference to ​The wafer primary pressing process (process S300) described is basically the same, so any repetitive detailed description of elements identical or similar to the above-described elements will be omitted.

[0342] ​ is a cross-sectional view illustrating ​ the process S800.

[0343] In addition to ​ and ​ , with reference to ​ , in the secondary deformation inspection process (process S800), the pressing unit 2700 can receive a driving signal from the pressing processing unit 2830 and move in the third direction DR3.

[0344] After the secondary pressing process, the second vision device 2600 can receive a driving signal from the alignment correction value calculation unit 2820 of the controller 2800 to capture images of the carrier mark 2240 of the carrier 2200 and the wafer mark WF_M of the wafer WF again. The second vision device 2600 can provide the recaptured images to the alignment correction value calculation unit 2820 of the controller 2800.

[0345] The alignment correction value calculation unit 2820 can calculate the degree of deformation of the wafer WF after pressing based on the images provided thereto from the second vision device 2600 by comparing the images captured before pressing with the images captured after pressing.

[0346] When the degrees of deformation of the wafer WF before the primary pressing and the wafer WF after the secondary pressing are less than or equal to a threshold value (good), the display device manufacturing method S1 according to the embodiment ends.

[0347] On the other hand, when the degrees of deformation of the wafer WF before the primary pressing and the wafer WF after the secondary pressing exceed the threshold value (bad), an alignment correction value recalculation and wafer realignment process (process S900) is performed.

[0348] In some embodiments, the threshold value can be in the range of about 10 micrometers (μm) to about 50 μm. In embodiments, for example, in the case where the threshold value is 10 μm, when the degree of deformation of the wafer WF before the first pressing and the wafer WF after the second pressing is 10 μm or less, the display device manufacturing method S1 according to the embodiments ends, and when the degree of deformation of the wafer WF before the first pressing and the wafer WF after the second pressing exceeds 10 μm, the alignment correction value recalculation and wafer realignment process (process S900) is performed. Alternatively, in another embodiment where the threshold value is 30 μm, when the degree of deformation of the wafer WF before the first pressing and the wafer WF after the second pressing is 30 μm or less, the display device manufacturing method S1 according to the embodiments ends, and when the degree of deformation of the wafer WF before the first pressing and the wafer WF after the second pressing exceeds 30 μm, the alignment correction value recalculation and wafer realignment process (process S900) is performed. Depending on the process conditions of the display device manufacturing method S1 according to the embodiments, the threshold value can be set differently in the range of about 10 μm to about 50 μm.

[0349] Hereinafter, when the degree of deformation of the wafer WF before the first pressing and the wafer WF after the second pressing exceeds the threshold value (bad), reference will be made to ​ The alignment correction value recalculation and wafer realignment process (process S900) will be described.

[0350] ​ is a cross-sectional view showing ​ the process S900.

[0351] In addition to ​ and ​ , reference will be made to ​ , in the alignment correction value recalculation process (process S910), the alignment correction value calculation unit 2820 can recalculate the alignment correction value. The wafer realignment and mounting process (process S920), the wafer re-pressing process (process S930), and the deformation re-checking process (process S940) can be performed using the recalculated alignment correction value.

[0352] The wafer realignment and mounting process (process S920), the wafer re-pressing process (process S930), and the deformation re-checking process (process S940) are substantially the same as the wafer second alignment and mounting process (process S600) described with reference to ​ and ​ the wafer second pressing process (process S700) described with reference to ​ and the second deformation checking process (process S800) described with reference to ​ and will omit any repetitive detailed description of elements that are the same or similar to the above-described elements.

[0353] In the deformation re-inspection process (process S940), when the degree of deformation of the wafer WF before the initial pressing and the wafer WF after the re-pressing is less than or equal to a threshold value (good), the display device manufacturing method S1 according to the embodiment ends.

[0354] In such a process, when the degree of deformation of the wafer WF before the initial pressing and the wafer WF after the re-pressing exceeds the threshold value (bad), the alignment correction value recalculation and wafer realignment processes (process S900) are repeatedly performed.

[0355] More specifically, in the alignment correction value recalculation process (process S910), unlike the wafer secondary alignment and mounting process (process S600), the alignment correction values t-10 to t-1 of the previous wafers WF included in the alignment correction value data ADT can be further used.

[0356] The alignment correction values t-10 to t-1 of the previous wafers WF can each include sub-correction values. In the embodiment, for example, the t-1th alignment correction value includes sub-correction values S t-1 1, S t-1 2, S t-1 3, and S t-1 4, the t-2th alignment correction value includes sub-correction values S t-2 1 and S t-2 2, and the t-3th alignment correction value includes sub-correction values S t-3 1, S t-3 2, and S t-3 3.

[0357] The number of sub-correction values included in each of the alignment correction values t-10 to t-1 can be equal to the number of correction value calculations of each of the wafers WF, that is, the number of repetitions of the alignment correction value recalculation process (process S910). In the embodiment, for example, the correction value calculated in the initial deformation inspection process (process S400) can be the first sub-correction value S t 1, S t-1 1, S t-2 1, S t-3 1, … The second sub-correction value and the subsequent sub-correction values S t 2, S t-1 2, S t-2 2, S t- 32, … can be the correction value calculated in the secondary deformation inspection process (process S800) or the deformation re-inspection process (process S940). The final sub-correction value S t-10 , S t-9 , St-8 ,..., S t-3 3, S t-2 2, S t-1 4may be a final correction value obtained when the degree of deformation of the wafer WF is less than or equal to the threshold value in the secondary deformation inspection process (process S800) or the deformation re-inspection process (process S940).

[0358] When the degree of deformation of the wafer WF exceeds the threshold value in the secondary deformation inspection process (process S800) of the current wafer WF, the alignment correction value calculation unit 2820 can use the average of the correction values t-10 to t-1 of the previous wafers WF as a new correction value in the first cycle R1 (e.g., S t 2). In an embodiment, for example, the average of the t-10th to t-1st alignment correction values can be used as the new correction value.

[0359] When the degree of deformation of the wafer WF exceeds the threshold value in the deformation re-inspection process (process S940) of the first cycle R1, the alignment correction value calculation unit 2820 can use the average of the alignment correction values t-9 to t-1 of the previous wafers WF and the previous sub-correction value S t 1 of the current wafer WF as a new correction value in the second cycle R2 (e.g., S t 3). In an embodiment, for example, the average of the t-9th to t-1st alignment correction values and the S t 1st sub-alignment correction value can be used as the new correction value.

[0360] When the degree of deformation of the wafer WF exceeds the threshold value in the deformation re-inspection process (process S940) of the second cycle R2, the alignment correction value calculation unit 2820 can use the average of the alignment correction values t-8 to t-1 of the previous wafers WF and the previous sub-correction values S t 1 and S t 2 of the current wafer WF as a new correction value in the third cycle R3. In an embodiment, for example, the average of the t-8th to t-1st alignment correction values, the S t 1st sub-alignment correction value, and the S t 2nd sub-alignment correction value can be used as the new correction value.

[0361] In an embodiment, as shown in ​ , ten previous alignment correction values can be used to calculate a new correction value, but the present disclosure is not limited thereto. In another embodiment, the number of previous alignment correction values used to calculate a new correction value can be variously changed.

[0362] In the display device manufacturing method S1 according to the embodiment, it is possible to minimize the deformation of the wafer WF by previously reflecting the correction value calculated from the primary deformation inspection in the secondary pressing process performed after the separation inspection of the wafer WF.

[0363] In such an embodiment, when the wafer WF is still deformed even after the secondary pressing, the correction value is recalculated using the alignment correction values t-10 to t-1 of the previous wafer WF, so that it is possible to quickly perform the alignment process of the wafer WF and the carrier 2200, and it is possible to improve the alignment accuracy of the wafer WF and the carrier 2200.

[0364] The present application should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the application to those skilled in the art.

[0365] While the present application has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit or scope of the application as defined by the appended claims.

Claims

1. An apparatus for manufacturing a display device, the apparatus comprising: an alignment unit; a carrier disposed on the alignment unit, wherein the carrier includes a receiving portion in which a wafer is received; a pressing unit disposed on the carrier; a first vision device disposed on the carrier at a side of the pressing unit; and a controller that controls alignment of the wafer and the carrier. 2.The apparatus of claim 1, wherein the carrier further includes first alignment marks disposed at a side of the receiving portion, and the first vision device captures images of the first alignment marks of the carrier and second alignment marks of the wafer. 3.The apparatus of claim 2, wherein the first vision device includes cameras, and a number of the cameras in the first vision device is equal to a number of the first alignment marks in the carrier. 4.The apparatus of claim 1, wherein the carrier further includes a bonding portion disposed on a bottom surface of the receiving portion, the bonding portion is disposed between the wafer and the bottom surface of the receiving portion, and the wafer and the carrier are bonded to each other through the bonding portion.

5. The apparatus of claim 4, wherein, The bonding portion includes a viscous chuck or an electrostatic chuck.

6. The apparatus of claim 4, wherein, The carrier further includes: a buffer portion disposed on a portion of the bottom surface of the receiving portion other than a portion on which the bonding portion is disposed; and a step compensation portion disposed below the bonding portion, wherein a thickness of the buffer portion is equal to a sum of a thickness of the bonding portion and a thickness of the step compensation portion. 7.The apparatus of claim 1, wherein the alignment unit includes a pin extending in a direction toward the carrier, the carrier further includes a pin hole disposed in a lower portion of the receiving portion, and the pin is moved through the pin hole.

8. The apparatus of claim 7, wherein, The wafer is mounted on the pin. 9.The apparatus of claim 7, wherein the alignment unit further includes a pin driver disposed below the pin, and the pin driver includes a vertical driver and a rotational driver. 10.The apparatus of claim 7, wherein the alignment unit further includes a first pressure sensor disposed below the pin, and the first pressure sensor measures a pressing force applied to the pin when the wafer is separated from the carrier. 11.The apparatus of claim 10, wherein the pin is provided in a plurality to include a plurality of pins, and the first pressure sensor is provided in a plurality one-to-one corresponding to the plurality of pins.

12. The apparatus of claim 1, wherein, The pressing unit includes: a pressing member disposed on a first surface of the pressing unit facing the carrier; and a second pressure sensor disposed between the first surface and the pressing member, and wherein the second pressure sensor measures a pressing force applied to the pressing member when the carrier and the wafer are bonded to each other. 13.The apparatus of claim 1, wherein, the first vision device captures a first image after a primary alignment of the wafer and before a primary pressing of the wafer, and captures a second image after the primary pressing of the wafer, the controller includes an alignment correction value calculation unit, the alignment correction value calculation unit calculates a correction value by comparing the first image with the second image, and the alignment unit aligns the wafer by offsetting the correction value during a secondary pressing of the wafer.

14. The apparatus of claim 1, further comprising: a second vision device disposed on the carrier, wherein the second vision device captures images of the carrier and the alignment unit.

15. The apparatus of claim 1, further comprising: a carrier transfer unit that places the carrier on the alignment unit.

16. The apparatus of claim 1, further comprising: a wafer transfer unit that places the wafer on the carrier.

17. The apparatus of claim 16, wherein the controller includes an alignment processing unit, the alignment processing unit provides a drive signal to the wafer transfer unit, the wafer transfer unit places the wafer on the carrier based on the drive signal, the first vision device provides captured images of the carrier and the wafer to the alignment processing unit, and the alignment processing unit provides the drive signal to the wafer transfer unit again based on the captured images to align the wafer with the carrier in real time.

18. The apparatus of claim 1, wherein, In a plan view, the carrier has a quadrilateral shape, and the wafer has a circular shape.

19. A method of manufacturing a display device, the method comprising: performing a primary alignment process including aligning a wafer with a reference point of a carrier; performing a wafer primary pressing process including pressing the wafer; performing a primary deformation inspection process including measuring a first degree of deformation of the wafer and the carrier; performing a separation process including separating the wafer from the carrier; performing a secondary alignment process including aligning the wafer with the carrier; performing a wafer secondary pressing process including pressing the wafer; and performing a secondary deformation inspection process including measuring a second degree of deformation of the wafer and the carrier, wherein the performing of the secondary alignment process includes aligning the wafer by offsetting a correction value from the reference point by using the first degree of deformation measured in the primary deformation inspection process as the correction value. when, in the secondary deformation inspection process, the second degree of deformation is less than or equal to a threshold value, the method ends.

20. The method of claim 19, wherein, when, in the secondary deformation inspection process, the second degree of deformation exceeds a threshold value, the method further includes performing a correction value recalculation and wafer realignment process including recalculating the correction value and realigning the wafer.

21. The method of claim 19, wherein, the performing of the correction value recalculation and wafer realignment process includes:

22. The method of claim 21, wherein, performing a correction value recalculation process including recalculating the correction value; performing a wafer realignment process including realigning the wafer; ​ performing a process comprising re-pressing the wafer; and performing a deformation recheck process comprising measuring a third degree of deformation of the wafer and the carrier.

23. The method of claim 22, wherein, The performing of the correction value recalculation process comprises calculating correction values for a current wafer using correction values of a previous wafer.

24. The method of claim 23, wherein, When, in the deformation recheck process, the third degree of deformation is less than or equal to a threshold value, the method ends.

25. The method of claim 23, wherein, When, in the deformation recheck process, the third degree of deformation exceeds a threshold value, the method further comprises performing the correction value recalculation and wafer realignment processes again.

26. The method of claim 25, wherein, each of the correction values of the previous wafer comprises at least one sub-correction value, and the number of sub-correction values in the correction values of the previous wafer is equal to the number of repetitions of the performing of the correction value recalculation process.

27. The method of claim 26, wherein, a final sub-correction value among the sub-correction values of each of the correction values of the previous wafer is a correction value of the previous wafer.

28. The method of claim 19, wherein, In each of the performing of the wafer first-pressing process and the performing of the wafer second-pressing process, a pressing force applied when the carrier and the wafer are combined is corrected in real time based on a pressing force measured by a pressure sensor.

29. The method of claim 19, wherein, In the performing of the separation process comprising separating the wafer from the carrier, a pressing force applied when the wafer is separated from the carrier is corrected in real time based on a pressing force measured by a pressure sensor.

30. An electronic device comprising a head-mounted display device manufactured by the apparatus according to any one of claims 1 to 18, wherein, the head-mounted display device comprises at least one display device, a display device housing configured to accommodate the at least one display device, and an optical member configured to magnify a display image of the at least one display device or change an optical path, and wherein the at least one display device comprises a semiconductor substrate, a plurality of conductive layers sequentially stacked on the semiconductor substrate, and a plurality of light emitting elements on the plurality of conductive layers.

31. An electronic device comprising a head-mounted display device manufactured by the method according to any one of claims 19 to 29, wherein the head-mounted display device comprises at least one display device, a display device housing configured to accommodate the at least one display device, and an optical member configured to magnify a display image of the at least one display device or change an optical path, and wherein the at least one display device comprises a semiconductor substrate, a plurality of conductive layers sequentially stacked on the semiconductor substrate, and a plurality of light emitting elements on the plurality of conductive layers.

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