Display panel, manufacturing method of display panel and electronic equipment

Abstract

The invention provides a display panel, a manufacturing method of the display panel, electronic equipment and an array substrate. The first electrode is positioned on one side of the array substrate; the insulating layer is located on the side, away from the array substrate, of the first electrode, the insulating layer comprises a first opening, the central area of the first electrode is exposed out of the first opening, and the edge area of the first electrode is covered with the insulating layer; and the thickness of the insulating layer is greater than or equal to that of the first electrode. The thickness of the insulating layer is set to be larger than the thickness of the first electrode, the fracture risk of the insulating layer can be reduced, the first electrode is prevented from being damaged by etching liquid in the subsequent patterning etching process of other film layers, and the yield of the display panel is guaranteed.

Description

[0001] This application claims priority to the Chinese patent application No. 2024104771416, filed on April 19, 2024, entitled “Display panel, manufacturing method of display panel and electronic device”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel, a manufacturing method of display panel and an electronic device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) and flat display devices based on Light Emitting Diode (LED) technology have been widely used in mobile phones, televisions, notebook computers, desktop computers and other consumer electronic products due to their high image quality, power saving, thin body and wide application range, and have become the mainstream of display devices.

[0004] However, the process performance of the current OLED display product needs to be improved. SUMMARY

[0005] In order to overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a display panel, which comprises:

[0006] An array substrate;

[0007] An insulating layer located on one side of the array substrate, the insulating layer comprising a plurality of first openings;

[0008] A plurality of first electrodes located on one side of the array substrate and arranged at intervals, the first electrodes comprising a portion exposed from the first openings, and the side surface of the first electrodes being covered by the insulating layer, the thickness of the insulating layer being greater than or equal to the thickness of the first electrodes;

[0009] A light emitting unit located on the side of the first electrode away from the array substrate.

[0010] In some possible implementations, the insulating layer comprises a first insulating portion covering the first electrodes and a second insulating portion not covering the first electrodes, the ratio of the thickness of the first insulating portion to the thickness of the first electrodes being greater than or equal to 1;

[0011] Preferably, the thickness of the insulating layer is greater than or equal to 1000 angstroms;

[0012] Preferably, the thickness of the insulating layer ranges from 2000 to 4000 angstroms;

[0013] Preferably, the distance from the side of the first insulating portion away from the array substrate to the array substrate is greater than the distance from the side of the first electrode away from the array substrate to the array substrate.

[0014] In some possible implementation manners, the first electrode comprises a first surface away from the side of the array substrate and a second surface close to the side of the array substrate.

[0015] The orthographic projection of the second surface on the array substrate is located within the orthographic projection of the first surface on the array substrate, or the orthographic projection of the first surface on the array substrate is located within the orthographic projection of the second surface on the array substrate.

[0016] In some possible implementation manners, the material of the insulating layer is inorganic material.

[0017] Preferably, the insulating layer comprises a first sub-layer and a second sub-layer arranged in a direction away from the array substrate, and the content of silicon in the first sub-layer is different from the content of silicon in the second sub-layer.

[0018] The content of nitrogen and silicon in the first sub-layer is a first ratio, and the content of nitrogen and silicon in the second sub-layer is a second ratio, and the first ratio is different from the second ratio.

[0019] Preferably, the material of the first sub-layer comprises silicon nitride, and the material of the second sub-layer comprises silicon nitride or silicon oxide.

[0020] In some possible implementation manners, the first ratio is X, and the second ratio is Y, wherein 0X<3 / 4, 0Y<3 / 4, and X>Y.

[0021] Preferably, when Y=0, the thickness of the second sub-layer is less than the thickness of the first sub-layer; and when Y≠0, the thickness of the second sub-layer is greater than the thickness of the first sub-layer.

[0022] In some possible implementation manners, the thickness of the first sub-layer ranges from 0 to 3000 angstroms, and the thickness of the second sub-layer ranges from 0 to 4000 angstroms.

[0023] In some possible implementation manners, the first electrode comprises a first conductive layer, a second conductive layer and a third conductive layer arranged in a direction away from the array substrate, and the etching rate of the second conductive layer is different from the etching rate of the first conductive layer and the third conductive layer.

[0024] Preferably, the orthographic projection of the second conductive layer on the array substrate is located within the orthographic projection of the first conductive layer and the third conductive layer on the array substrate.

[0025] Preferably, the material of the first conductive layer and the third conductive layer comprises at least one of indium tin oxide, indium zinc oxide, indium gallium oxide, and the material of the second conductive layer comprises silver.

[0026] In some possible implementation manners, the display panel further comprises:

[0027] An isolation structure located on a side of the insulating layer away from the array substrate, the isolation structure comprising an isolation opening, a projection of the first opening on the array substrate being located within a projection of the isolation opening on the array substrate;

[0028] Preferably, the isolation structure comprises a support portion and a barrier portion which are stacked on a side away from the array substrate, a projection of the support portion on the array substrate being located within a projection of the barrier portion on the array substrate.

[0029] In some possible implementation manners, at least part of the first electrode has a projection on the array substrate which at least partially overlaps with a projection of the isolation structure on the array substrate.

[0030] Preferably, a side surface of the first electrode has a projection on the array substrate which is located within a projection of the isolation structure on the array substrate.

[0031] In some possible implementation manners, the support portion comprises a first metal layer and a second metal layer which are stacked on a side away from the array substrate, and the barrier portion comprises a third metal layer.

[0032] Preferably, the material of the first metal layer comprises molybdenum, the material of the second metal layer comprises aluminum, and the material of the third metal layer comprises titanium.

[0033] In some possible implementation manners, the display panel further comprises a second electrode which is at least partially located in the isolation opening, at least part of the second electrode is located on a side of the light emitting unit away from the array substrate and in electrical contact with the light emitting unit, and another at least part of the second electrode is located on a side of the insulating layer away from the array substrate and in electrical contact with the isolation structure.

[0034] In some possible implementation manners, the display panel further comprises a first encapsulation layer which is located on a side of the second electrode away from the array substrate and at least partially located in the first opening.

[0035] Preferably, at least part of the first encapsulation layer is located on a side of the isolation structure away from the array substrate.

[0036] Preferably, the first encapsulation layer corresponding to the first opening is arranged in a spaced manner, and the spaced fracture is located on a side of the isolation structure away from the array substrate.

[0037] Preferably, the display panel further comprises a second encapsulation layer and a third encapsulation layer arranged in a stacked manner away from the array substrate on a side of the first encapsulation layer away from the array substrate.

[0038] Preferably, the material of the first encapsulation layer and the third encapsulation layer comprises inorganic material, and the material of the second encapsulation layer comprises organic material.

[0039] In some possible implementation manners, the isolation opening comprises a first isolation opening and a second isolation opening, the light emitting unit comprises first light emitting units and second light emitting units different in light emitting color, at least part of the first light emitting units is located in the first isolation opening, and at least part of the second light emitting units is located in the second isolation opening.

[0040] The insulating layer comprises a first limiting portion extending from the isolation structure corresponding to the first isolation opening and a second limiting portion extending from the isolation structure corresponding to the second isolation opening, a projection of the first limiting portion on the substrate is located in a projection of the first isolation opening on the substrate, and a projection of the second limiting portion on the substrate is located in a projection of the second isolation opening on the substrate.

[0041] Preferably, the thickness of the first limiting portion and the thickness of the second limiting portion are both greater than the thickness of the first electrode.

[0042] The thickness of the first limiting portion is greater than the thickness of the second limiting portion, or

[0043] The thickness of the first limiting portion is substantially equal to the thickness of the second limiting portion.

[0044] Preferably, the isolation opening further comprises a third isolation opening, and the light emitting unit further comprises third light emitting units different in light emitting color from the first light emitting units and the second light emitting units, at least part of the third light emitting units is located in the third isolation opening.

[0045] The insulating layer further comprises a third limiting portion extending from the isolation structure corresponding to the third isolation opening, and a projection of the third limiting portion on the substrate is located in a projection of the third isolation opening on the substrate.

[0046] Preferably, the thickness of the first limiting portion, the thickness of the second limiting portion and the thickness of the third limiting portion are all greater than the thickness of the first electrode.

[0047] The thickness of the second limiting portion is greater than the thickness of the third limiting portion, or

[0048] The thickness of the second limiting portion is substantially equal to the thickness of the second limiting portion.

[0049] In some possible implementation manners, the display panel includes a display area and a non-display area at least partially surrounding the display area; the first electrode is located in the display area, and the display panel further includes a signal trace which is disposed in the same layer as the first electrode and located in the non-display area; and the insulating layer continuously covers the side surface of the signal trace and the side of the signal trace away from the array substrate.

[0050] Preferably, the thickness of the insulating layer is greater than or equal to the thickness of the signal trace.

[0051] The present application also provides a display panel, which includes:

[0052] an array substrate;

[0053] an insulating layer located on one side of the array substrate, the insulating layer including a first opening;

[0054] a plurality of first electrodes located on one side of the array substrate and spaced apart; the first electrode includes a portion exposed from the first opening, the insulating layer includes a first insulating portion covering the first electrode and a second insulating portion disposed away from the first electrode, and the thickness of the insulating layer at the junction of the first insulating portion and the second insulating portion is greater than the thickness of the first electrode corresponding to the first insulating portion;

[0055] a light emitting unit located on the side of the first electrode away from the array substrate; and

[0056] a second electrode located on the side of the light emitting unit away from the array substrate.

[0057] In some possible implementation manners, the insulating layer covers the sidewall of the first electrode.

[0058] In some possible implementation manners, the insulating layer includes a pixel defining layer, and the material of the insulating layer is an inorganic material.

[0059] Preferably, the insulating layer includes a first sub-layer and a second sub-layer which are disposed in the direction away from the array substrate in a stacked manner, the content of nitrogen and silicon in the first sub-layer is a first ratio, the content of nitrogen and silicon in the second sub-layer is a second ratio, and the first ratio is different from the second ratio.

[0060] Preferably, the material of the first sub-layer includes silicon nitride, and the material of the second sub-layer includes silicon nitride or silicon oxide.

[0061] In some possible implementation manners, the first ratio is X and the second ratio is Y, where 0

[0062] Preferably, when Y=0, the second sub-layer thickness is less than the first sub-layer thickness; and when Y≠0, the second sub-layer thickness is greater than the first sub-layer thickness.

[0063] In some possible implementation manners, the thickness of the first sub-layer ranges from 0 to 3000 angstroms, and the thickness of the second sub-layer ranges from 0 to 4000 angstroms.

[0064] In some possible implementation manners, a projection of at least part of the first electrode on the array substrate at least partially overlaps with a projection of the isolation structure on the array substrate.

[0065] Preferably, a projection of a side surface of the first electrode on the array substrate is located within a projection of the isolation structure on the array substrate.

[0066] In some possible implementation manners, the display panel further includes:

[0067] An isolation structure located on a side of the insulating layer away from the array substrate, the isolation structure including an isolation opening, and a projection of the first opening on the array substrate being located within a projection of the isolation opening on the array substrate.

[0068] Preferably, the isolation structure includes a support portion and a blocking portion which are stacked on a side away from the array substrate, and a projection of the support portion on the array substrate is located within a projection of the blocking portion on the array substrate.

[0069] Another object of the present application is to provide a manufacturing method of a display panel, the method including:

[0070] Providing an array substrate;

[0071] Providing a first electrode on a side of the array substrate;

[0072] Providing an insulating layer on a side of the first electrode away from the array substrate, the insulating layer including a first opening, the first electrode including a portion exposed from the first opening, and a side surface of the first electrode being covered by the insulating layer; and a thickness of the insulating layer being greater than or equal to a thickness of the first electrode.

[0073] Forming a light-emitting unit on a side of the first electrode away from the array substrate.

[0074] In some possible implementation manners, the step of disposing the insulating layer on the side of the first electrode away from the array substrate comprises:

[0075] The insulating layer has a thickness greater than or equal to 1000 angstroms on the side of the first electrode away from the array substrate.

[0076] In some possible implementation manners, the method further comprises:

[0077] disposing an isolation layer on the side of the insulating layer away from the array substrate;

[0078] performing etching on the isolation layer to form an isolation structure having an isolation opening;

[0079] performing etching on the insulating layer from the isolation opening to form a first opening, the first opening exposing at least part of the first electrode.

[0080] In some possible implementation manners, the step of disposing the insulating layer on the side of the first electrode away from the array substrate comprises:

[0081] forming a first sub-layer of the insulating layer on the side of the first electrode away from the array substrate by using a material having a first ratio of nitrogen content to silicon content;

[0082] forming a second sub-layer of the insulating layer on the side of the first sub-layer away from the array substrate by using a material having a second ratio of nitrogen content to silicon content, the first ratio being different from the second ratio.

[0083] Another purpose of the present application is to provide an electronic device comprising the display panel provided by the present application or comprising the manufacturing method of the display panel provided by the present application.

[0084] Compared with the prior art, the present application has the following beneficial effects:

[0085] The present application provides a display panel, a manufacturing method of a display panel, and an electronic device. By setting the thickness of the insulating layer to be greater than the thickness of the first electrode, the risk of a break in the insulating layer at the position covering the first electrode can be reduced, and the first electrode can be prevented from being damaged by etching liquid in the subsequent patterning and etching process of other film layers, thereby ensuring the yield of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0086] Figure 1 FIG. 1 is a structural schematic diagram of a display panel provided by the present embodiment;

[0087] Figure 2 FIG. 2 is another structural schematic diagram of a display panel provided by the present embodiment;

[0088] Figure 3 Figure 3C is a schematic diagram of a structure of a display panel according to an embodiment of the present application;

[0089] Figure 4 Figure 4C is a schematic diagram of a structure of a display panel according to an embodiment of the present application;

[0090] Figure 5 Figure 5C is a schematic diagram of a structure of a display panel according to an embodiment of the present application;

[0091] Figure 6 Figure 6C is a schematic diagram of a structure of a display panel according to an embodiment of the present application;

[0092] Figure 7 Figure 7C is a schematic diagram of a structure of a display panel according to an embodiment of the present application;

[0093] Figure 8 Figure 8C is a schematic diagram of an isolation structure according to an embodiment of the present application;

[0094] Figure 9 Figure 9C is a schematic diagram of a structure of a display panel according to an embodiment of the present application;

[0095] Figure 10 Figure 10C is a schematic diagram of a structure of a display panel according to an embodiment of the present application;

[0096] Figure 11 Figure 11C is a schematic diagram of a manufacturing method of a display panel according to an embodiment of the present application;

[0097] Figure 12 Figure 12C is a schematic diagram of a manufacturing process of a display panel according to an embodiment of the present application;

[0098] Figure 13 Figure 13C is a schematic diagram of a manufacturing process of a display panel according to an embodiment of the present application.

[0099] Icon: 110 - array substrate; 120 - first electrode; 121 - first conductive layer; 122 - second conductive layer; 123 - third conductive layer; 1201 - first surface; 1202 - second surface; 130 - insulating layer; 131 - first sub-layer; 132 - second sub-layer; 1301 - first insulating part; 1302 - second insulating part; P - junction; 1305 - first limiting part; 1306 - second limiting part; 1307 - third limiting part; 140 - isolation structure; 141 - support part; 142 - blocking part; 911 - first isolation opening; 912 - second isolation opening; 913 - third isolation opening; 150 - light emitting unit; 151 - first light emitting unit; 152 - second light emitting unit; 153 - third light emitting unit; 160 - second electrode; 170 - first encapsulation layer; 180 - second encapsulation layer; 301 - undercut structure; 302 - fracture; 1190 - third encapsulation layer; 1401 - isolation layer; 1411 - first metal layer; 1412 - second metal layer; 1421 - third metal layer; 810 - first opening. DETAILED DESCRIPTION

[0100] The following detailed description of embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the application as claimed, but merely represents selected embodiments of the application.

[0101] It should be noted that similar reference numbers and letters in the following drawings represent similar items, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings.

[0102] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed during use, and are merely for the convenience of describing the application and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application. In addition, the terms "first", "second", "third", and the like are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0103] It should be noted that the different features in the embodiments of the application can be combined with each other without conflict.

[0104] The inventors have found that in a conventional OLED display panel, the display panel usually includes an array substrate, a first electrode (e.g., an anode) located on one side of the array substrate, and an insulating layer (e.g., a pixel defining layer) located on a side of the first electrode away from the array substrate. The insulating layer usually needs to cover at least part of the first electrode (e.g., the edge of the first electrode). In this case, if the thickness of the first electrode and the insulating layer is not properly set, the first electrode may be damaged in subsequent etching of other film layers, affecting the yield of the display panel.

[0105] Therefore, the present embodiment provides a solution to reduce the risk of damage to the first electrode. The solution provided by the present embodiment is described in detail below.

[0106] Please refer to Figure 1 and Figure 2 , Figure 1 and Figure 2 A display panel provided by the present embodiment can include an array substrate 110, a first electrode 120, an insulating layer 130, and a light emitting unit 150.

[0107] In the present embodiment, the array substrate 110 can include a plurality of film layer structures, such as a substrate, a buffer layer, an active layer, a plurality of metal layers, a plurality of insulating layers, and a planarization layer. The plurality of film layer structures of the array substrate 110 can form a plurality of thin film transistors (TFTs) at different positions of the array substrate 110. The thin film transistors can cooperate with each other to form a plurality of pixel driving units or driving circuits.

[0108] The insulating layer 130 is located on a side of the first electrode 120 away from the array substrate 110, and the insulating layer 130 includes a first opening 810.

[0109] A plurality of first electrodes 120 are located on a side of the array substrate 110, and the plurality of first electrodes 120 are arranged at intervals. The first electrode 120 includes a portion exposed from the first opening 810, and a side surface of the first electrode 120 is covered by the insulating layer 130. For example, the first opening 810 exposes a central region of the first electrode 120, and an edge region of the first electrode 120 is covered by the insulating layer 130. That is, the insulating layer 130 extends along the side surface of the first electrode 120 to a side of the first electrode 120 away from the array substrate 110, and covers at least part of the side of the first electrode 120 away from the array substrate 110.

[0110] In the embodiment, the thickness H1 of the insulating layer 130 is greater than or equal to the thickness H2 of the first electrode 120. The thickness of the insulating layer 130 refers to the minimum distance from the side of the insulating layer 130 away from the array substrate 110 to the side of the insulating layer 130 close to the array substrate 110 in the direction perpendicular to the array substrate 110. Due to process errors, process design, subsequent process effects, etc., the thickness of the insulating layer at the edge position may be thinned, uneven, etc. Therefore, the thickness of the insulating layer in the present application refers to the thickness of the uniform part of the electrode layer.

[0111] The light emitting unit 150 is at least partially located in the first opening 810 and on the side of the first electrode 120 away from the array substrate 110. The light emitting unit 150 can include a hole injection layer, a hole transport layer, an electron blocking layer, etc.

[0112] Optionally, the display panel provided in the embodiment can further include a second electrode 160 located on the side of the light emitting unit 150 away from the array substrate 110.

[0113] Based on the above design, in the embodiment, by setting the thickness of the insulating layer 130 to be greater than the thickness of the first electrode 120, the risk of a break in the insulating layer 130 covering the edge of the first electrode 120 can be reduced, and the etching liquid can be prevented from invading the first electrode 120 from the break in the insulating layer 130 in the subsequent process of patterning and etching other film layers, thereby protecting the first electrode 120 and ensuring the yield of the display panel.

[0114] In some possible implementation manners, referring to Figure 3 The insulating layer 130 includes a first insulating part 1301 covering the first electrode 120 and a second insulating part 1302 not covering the first electrode 120. That is, the orthographic projection of the first insulating part 1301 on the array substrate 110 overlaps the orthographic projection of the first electrode 120 on the array substrate, and the orthographic projection of the second insulating part on the array substrate does not overlap the orthographic projection of the first electrode 120 on the substrate. The ratio of the thickness of the first insulating part 1301 to the thickness of the first electrode 120 is greater than or equal to 1.

[0115] In some possible implementation manners, the thickness of the first electrode 120 is about 1000 angstroms. Therefore, the thickness of the insulating layer 130 is greater than or equal to 1000 angstroms.

[0116] Optionally, the thickness of the insulating layer 130 ranges from 2000 to 4000 angstroms. In this way, it can be ensured that the insulating layer 130 can better cover the edge of the first electrode 120, and the risk of a break in the insulating layer 130 can be reduced.

[0117] In some possible implementation manners, referring to Figure 4The first electrode 120 includes a first surface 1201 away from the side of the array substrate 110 and a second surface 1202 close to the side of the array substrate 110.

[0118] Optionally, the orthographic projection of the first surface 1201 on the array substrate 110 is located within the orthographic projection of the second surface 1202 on the array substrate 110.

[0119] For example, in the present embodiment, the cross-sectional shape of the first electrode 120 in a cross section perpendicular to the array substrate 110 can be rectangular. In this case, the first insulating portion 1301 is the portion of the insulating layer 130 covering the surface of the first electrode 120 away from the array substrate 110.

[0120] For another example, in the present embodiment, the cross-sectional shape of the first electrode 120 in a cross section perpendicular to the array substrate 110 can be trapezoidal, and the longer base of the trapezoid is located on the side close to the array substrate 110. In this case, the first insulating portion 1301 is the portion of the insulating layer 130 covering the surface of the first electrode 120 away from the array substrate 110 and the side surface of the first electrode 120.

[0121] Alternatively, please refer to Figure 5 Optionally, the orthographic projection of the second surface 1202 on the array substrate 110 is located within the orthographic projection of the first surface 1201 on the array substrate 110.

[0122] For example, in the present embodiment, the cross-sectional shape of the first electrode 120 in a cross section perpendicular to the array substrate 110 can be trapezoidal, and the longer base of the trapezoid is located on the side away from the array substrate 110. In this case, the first insulating portion 1301 is the portion of the insulating layer 130 covering the surface of the first electrode 120 away from the array substrate 110.

[0123] It should be noted that, in the case where the first electrode 120 has multiple film layers, the cross-sectional shape of the first electrode 120 can be trapezoidal as a whole, but the side surface of the first electrode 120 can form a stepped or jagged structure due to etching process or different etching resistance of different film layers. Due to process errors, process design, subsequent process effects, etc., the thickness of the first electrode 120 at the edge position can be thinned, uneven, etc., and therefore, the thickness of the first electrode 120 in the present application refers to the thickness of the uniform portion of the electrode layer.

[0124] In some possible implementation manners, the insulating layer 130 can be a pixel defining layer, the first opening 810 can be a pixel opening, and the material of the insulating layer 130 can be an inorganic material.

[0125] In some possible implementation manners, please refer to Figure 6The insulating layer 130 includes a first sub-layer 131 and a second sub-layer 132 stacked in a direction away from the array substrate 110, and the contents of silicon in the first sub-layer 131 and the second sub-layer 132 are different.

[0126] Optionally, the contents of nitrogen and silicon in the first sub-layer 131 are in a first ratio, and the contents of nitrogen and silicon in the second sub-layer 132 are in a second ratio, and the first ratio is different from the second ratio.

[0127] In some possible implementation manners, the materials of the first sub-layer 131 and the second sub-layer 132 can both be silicon nitride, but the first ratio is different from the second ratio.

[0128] For example, in the forming process of the first sub-layer 131 and the second sub-layer 132, different power bombardments can be adopted to form silicon targets in an environment containing nitrogen.

[0129] In other possible implementation manners, the material of the first sub-layer 131 can be silicon nitride, and the material of the second sub-layer 132 can be silicon oxide.

[0130] In some possible implementation manners, the first ratio is X, and the second ratio is Y, where 0 < X < 3 / 4, and 0 ≤ Y < 3 / 4, and X > Y.

[0131] On this basis, optionally, when Y = 0, the thickness H4 of the second sub-layer 132 is less than the thickness H3 of the first sub-layer 131; and when Y ≠ 0, the thickness H4 of the second sub-layer 132 is greater than the thickness H3 of the first sub-layer 131.

[0132] Optionally, the thickness H3 of the first sub-layer 131 ranges from 0 to 3000 angstroms, and the thickness H4 of the second sub-layer 132 ranges from 0 to 4000 angstroms.

[0133] In some possible implementation manners, please refer to Figure 1 and Figure 2 The first electrode 120 includes a first conductive layer 121, a second conductive layer 122, and a third conductive layer 123 stacked in a direction away from the array substrate 110, and the etching rate of the second conductive layer 122 is different from the etching rates of the first conductive layer 121 and the third conductive layer 123.

[0134] Optionally, please refer to Figure 7The orthogonal projection of the second conductive layer 122 on the array substrate 110 is located in the orthogonal projection of the first conductive layer 121 and the third conductive layer 123 on the array substrate 110. That is, on the side of the first electrode 120, compared with the first conductive layer 121 and the third conductive layer 123, the second conductive layer 122 makes the cross-sectional shape of the first electrode 120 as a whole in the shape of an I-beam. In this case, the first insulating part 1301 is a part of the insulating layer 130 covering the side of the first electrode 120 away from the array substrate 110.

[0135] For example, the material of the first conductive layer 121 and the third conductive layer 123 includes at least one of indium tin oxide, indium zinc oxide, and indium gallium oxide, and the material of the second conductive layer 122 includes silver. Among them, the material of the second conductive layer 122 adopts silver, which can ensure that the first electrode 120 has smaller resistance and ensure conductivity; the first conductive layer 121 and the third conductive layer 123 adopt at least one of indium tin oxide, indium zinc oxide, and indium gallium oxide, which can protect the second conductive layer 122 between the first conductive layer 121 and the third conductive layer 123 and reduce the risk of oxidation of the second conductive layer 122.

[0136] In some possible implementations, referring again to Figure 1 and Figure 2 The display panel provided in the embodiment can further include an isolation structure 140.

[0137] The isolation structure 140 is located on the side of the insulating layer 130 away from the array substrate 110, and the isolation structure 140 includes an isolation opening. The orthogonal projection of the first opening 810 on the array substrate 110 is located in the orthogonal projection of the isolation opening on the array substrate 110. The isolation opening is in communication with the first opening 810 and exposes at least part of the first electrode 120 together.

[0138] The isolation structure 140 can be used to disconnect the light emitting units 150 and the second electrodes 160 between adjacent pixels when the light emitting units 150 and the second electrodes 160 are subsequently formed by evaporation, so that different colors of light emitting units 150 can be arranged in different first openings 810 by using the method of whole-layer evaporation and etching.

[0139] Among them, the patent applications PCT / CN2023 / 134518, 202310759370.2, 202310740412.8, 202310707209.0, and 202311346196.5 disclose related technical solutions of the isolation structure 140, the contents of which are incorporated by reference in this application for reference.

[0140] Further, in some possible implementation manners, the material of the insulating layer 130 is an inorganic material. In this way, the insulating layer 130 is made of the inorganic material with weak water absorption, so as to ensure the stability of the insulating layer 130 in the subsequent wet process of the light emitting unit 150 and the second electrode 160.

[0141] In some possible implementation manners, referring to Figure 8 The isolation structure 140 includes a support portion 141 and a barrier portion 142 which are arranged in a stack away from the array substrate 110, and a projection of the support portion 141 on the array substrate 110 is located within a projection of the barrier portion 142 on the array substrate 110. That is, the side surface of the isolation structure 140 forms an undercut structure. In this way, when other organic material layers are formed by subsequent evaporation, these organic material layers can be disconnected.

[0142] In some possible implementation manners, the support portion 141 includes a first metal layer 1411 and a second metal layer 1412 which are arranged in a stack away from the array substrate 110, and the barrier portion 142 includes a third metal layer 1421.

[0143] Optionally, the material of the first metal layer 1411 includes molybdenum, the material of the second metal layer 1412 includes aluminum, and the material of the third metal layer 1421 includes titanium.

[0144] In some possible implementation manners, at least part of the isolation structure 140 is electrically conductive, referring to Figure 2 At least part of the second electrode 160 is located on the side of the light emitting unit 150 away from the array substrate 110 and is in electrical contact with the light emitting unit 150, and the second electrode 160 is additionally in electrical contact with the isolation structure 140 on the side of the insulating layer 130 away from the array substrate 110, for example, the second electrode 160 extends from the first opening 810 to the side of the insulating layer 130 away from the array substrate 110 and is in electrical contact with the isolation structure 140.

[0145] The first electrode 120 can be connected with a pixel driving circuit in the array substrate 110, and the second electrode 160 can be connected with a common voltage providing circuit through the isolation structure 140. When there is a potential difference between the first electrode 120 and the second electrode 160, the light emitting unit 150 located between the first electrode 120 and the second electrode 160 is driven to emit light.

[0146] In some possible implementation manners, referring again to Figure 1 A projection of the first electrode 120 on the array substrate 110 at least partially overlaps with a projection of the isolation structure 140 on the array substrate 110, for example, a projection of the side surface of the first electrode 120 on the array substrate 110 is located within a projection of the isolation structure 140 on the array substrate 110.

[0147] That is, at least part of the first electrode 120 extends below the isolation structure 140. A parasitic capacitance can be formed between the first electrode 120 having electrical conductivity and the isolation structure 140 having electrical conductivity, resulting in a parasitic capacitance between the second electrode 160 electrically connected to the isolation structure 140 and the first electrode 120, which affects the reset effectiveness of the light emitting device at the time of reset.

[0148] In this case, the display panel provided by the embodiment can increase the distance H0 between the isolation structure 140 and the first electrode 120 by increasing the thickness of the insulating layer 130, thereby reducing the parasitic capacitance between the first electrode 120 and the second electrode 160, and ensuring the reset effectiveness of the light emitting device at the time of reset.

[0149] In some possible implementation manners, referring to Figure 9 The display panel provided by the embodiment can further include a first encapsulation layer 170.

[0150] Optionally, the first encapsulation layer 170 can extend from the first opening 810 to a side of the isolation structure 140 away from the array substrate 110. The first encapsulation layer 170 corresponding to adjacent first openings 810 can be disconnected at the side of the isolation structure 140 away from the array substrate 110.

[0151] Further, in some possible implementation manners, the display panel provided by the embodiment further includes a second encapsulation layer 180 and a third encapsulation layer 190 which are arranged in a stack at a side of the first encapsulation layer 170 away from the array substrate 110.

[0152] Optionally, the material of the first encapsulation layer 170 and the third encapsulation layer 190 includes an inorganic material, and the material of the second encapsulation layer 180 includes an organic material. For example, the first encapsulation layer 170 and the third encapsulation layer 190 can be formed in a chemical vapor deposition (CVD) manner, and the second encapsulation layer 180 can be formed in an ink-jet printing (IJP) manner.

[0153] Optionally, a gap can be formed between the part of the first encapsulation layer 170 located at the side of the isolation structure 140 away from the array substrate 110 and the isolation structure 140. The second encapsulation layer 180 can fill the gap.

[0154] In some possible implementation manners, referring to Figure 10The isolation openings include a first isolation opening 911 and a second isolation opening 912, and the light emitting unit 150 includes a first light emitting unit 151 and a second light emitting unit 152 having different light emitting colors, at least part of the first light emitting unit 151 is located within the first isolation opening 911, and at least part of the second light emitting unit 152 is located within the second isolation opening 912.

[0155] The insulating layer 130 includes a first limited part 1305 extending from the isolation structure 140 corresponding to the first isolation opening 911, and a second limited part 1306 extending from the isolation structure 140 corresponding to the second isolation opening 912, the orthographic projection of the first limited part 1305 on the substrate 111 is located within the orthographic projection of the first isolation opening 911 on the substrate 111, that is, the first isolation opening 911 exposes the first limited part 1305 of the insulating layer 130. The orthographic projection of the second limited part 1306 on the substrate 111 is located within the orthographic projection of the second isolation opening 912 on the substrate 111, that is, the second isolation opening 912 exposes the second limited part 1306 of the insulating layer 130.

[0156] For example, near the first isolation opening 911, the insulating layer 130 extends from the part of the isolation structure 140 (i.e., not covered by the isolation structure 140) close to one side of the substrate 110 as the first limited part 1305, and the first limited part 1305 exposes at least part of the first isolation opening 911.

[0157] Near the second isolation opening 912, the insulating layer 130 extends from the part of the isolation structure 140 (i.e., not covered by the isolation structure 140) close to one side of the substrate 110 as the second limited part 1306, and the second limited part 1306 exposes at least part of the second isolation opening 912.

[0158] The thickness H21 of the first limited part 1305 and the thickness H22 of the second limited part 1306 are both greater than the thickness of the first electrode 120.

[0159] Optionally, in some possible implementation manners, the thickness H21 of the first limited part 1305 is substantially equal to the thickness H22 of the second limited part 1306.

[0160] Optionally, in another possible implementation manner, the thickness H21 of the first limited part 1305 is greater than the thickness H22 of the second limited part 1306.

[0161] For example, the first light emitting unit 151 can be fabricated prior to the second light emitting unit 152. During the patterning etching process of the first light emitting unit 151, the second defined portion 1306 of the insulating layer 130 located in the second isolation opening 911 and not covered by the isolation structure 140 can be etched and thinned, so that the thickness H21 of the first defined portion 1305 of the insulating layer 130 located in the first isolation opening 911 is greater than the thickness H22 of the second defined portion 1306 located in the second isolation opening 912.

[0162] Optionally, the isolation opening further comprises a third isolation opening 913, and the light emitting unit 150 further comprises a third light emitting unit 153 having a light emitting color different from those of the first light emitting unit 151 and the second light emitting unit 152, at least part of the third light emitting unit 153 is located in the third isolation opening 913. For example, the light emitting colors of the first light emitting unit 151, the second light emitting unit 152 and the third light emitting unit 153 can be one of red, green and blue respectively.

[0163] The insulating layer 130 further comprises a third defined portion 1307 of the isolation structure 140 corresponding to the third isolation opening 913, and the orthographic projection of the third defined portion 1307 on the substrate 111 is located in the orthographic projection of the third isolation opening 913 on the substrate 111, that is, the third isolation opening 913 exposes the third defined portion 1307 of the insulating layer 130.

[0164] For example, near the third isolation opening 913, the portion of the insulating layer 130 protruding from the isolation structure 140 (i.e., not covered by the isolation structure 140) near the side of the substrate 110 is the third defined portion 1307, and the third defined portion 1307 exposes at least part of the third isolation opening 913.

[0165] In some possible implementations, the thickness H21 of the first defined portion 1305, the thickness H22 of the second defined portion 1306 and the thickness H23 of the third defined portion 1307 are all greater than the thickness of the first electrode 120.

[0166] Optionally, in some possible implementations, the thickness H22 of the second defined portion 1306 and the thickness H23 of the third defined portion 1307 are substantially equal, that is, the thickness H21 of the first defined portion 1305, the thickness H22 of the second defined portion 1306 and the thickness H23 of the third defined portion 1307 are substantially equal.

[0167] Optionally, in another possible implementation, the thickness H22 of the second defined portion 1306 is greater than the thickness H23 of the third defined portion 1307. That is, the thickness H21 of the first defined portion 1305, the thickness H22 of the second defined portion 1306 and the thickness H23 of the third defined portion 1307 decrease in turn.

[0168] For example, the first light emitting unit 151 can be fabricated prior to the second light emitting unit 152, and the second light emitting unit 152 can be fabricated prior to the third light emitting unit 153. During the patterning etching process of the first light emitting unit 151, the third limiting portion 1307 of the insulating layer 130 located in the third isolation opening 913 and not covered by the isolation structure 140 can be thinned by the etching, and the thickness H21 of the first limiting portion 1305 of the insulating layer 130 located in the first isolation opening 911 is greater than the thickness H23 of the third limiting portion 1307 located in the third isolation opening 913. Then, during the patterning etching process of the second light emitting unit 152, the third limiting portion 1307 of the insulating layer 130 located in the third isolation opening 913 and not covered by the isolation structure 140 is thinned again by the etching, so that the thickness H22 of the second limiting portion 1306 of the insulating layer 130 located in the second isolation opening 912 is greater than the thickness H23 of the third limiting portion 1307 located in the third isolation opening 913.

[0169] In some possible implementation manners, in the region where the insulating layer 130 covers the first electrode 120, the ratio of the thickness of the insulating layer 130 to the thickness of the first electrode 120 is greater than or equal to 1. For example, referring to FIG. 1, the ratio of the thickness H1 of the insulating layer 130 to the thickness H2 of the first electrode 120 is greater than or equal to 1. Figure 2 The insulating layer 130 includes a first insulating portion 1301 and a second insulating portion 1302, the orthographic projection of the first insulating portion 1301 on the array substrate 110 overlaps the orthographic projection of the first electrode 120 on the array substrate 110, and the orthographic projection of the second insulating portion 1302 on the array substrate 110 is offset from the orthographic projection of the first electrode 120 on the array substrate 110. That is, in the insulating layer 130, the portion covering the first electrode 120 is the first insulating portion 1301, and the portion not covering the first electrode 120 is the second insulating portion 1302.

[0170] The distance H5 from the side of the first insulating portion 1301 away from the array substrate 110 to the array substrate 110 is greater than the distance H6 from the side of the first electrode 120 away from the array substrate 110 to the array substrate 110. That is, at least part of the insulating layer 130 covers the side of the first electrode 120 away from the array substrate 110.

[0171] In some possible implementation manners, the display panel provided by the embodiment can further include a touch function layer, which can be located on the side of the third encapsulation layer 190 away from the array substrate 110. The touch function layer can include a touch electrode for performing touch detection. Optionally, the touch electrode can be arranged in a self-capacitance detection mode and / or a mutual-capacitance detection mode, which is not limited in the embodiment.

[0172] In some possible implementations, the display panel provided in this embodiment may further include a polarizing layer, which may be located on a side of the third encapsulation layer 190 away from the array substrate 110. The polarizer can reduce the reflection of external light by the display panel, thereby ensuring the display effect of the display panel.

[0173] In some possible implementations, the display panel provided in this embodiment may further include a cover plate for protecting the display panel. The cover plate may be located on a side of the film layer farthest from the array substrate 110 and away from the array substrate 110 .

[0174] Please see again Figure 2 The insulating layer 130 is located on a side of the first electrode 120 away from the array substrate 110. The insulating layer 130 includes a first opening 810. The first electrode 120 includes a portion exposed from the first opening 810. For example, the first opening 810 exposes a central region of the first electrode 120, and an edge region of the first electrode 120 is covered by the insulating layer 130.

[0175] The insulating layer 130 includes a first insulating portion 1301 covering the first electrode 120 and a second insulating portion 1302 staggered from the first bottom electrode 120. Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 or Figure 7 The insulating layer 130 is located at the junction P between the first insulating portion 1301 and the second insulating portion 1302, close to the end of the first electrode 120. Figure 3 The thickness H7 of the insulating layer 130 at the junction P between the first insulating portion 1301 and the second insulating portion 1302 is greater than the thickness H8 of the first electrode 120 corresponding to the first insulating portion 1301 .

[0176] The thickness H7 of the insulating layer 130 at the junction P between the first insulating portion 1301 and the second insulating portion 1302 refers to the thickness at this position in a direction perpendicular to the array substrate 110 .

[0177] The light emitting unit 150 is at least partially located in the first opening 810 and located on a side of the first electrode 120 away from the array substrate 110. The material of the light emitting unit 150 includes an electroluminescent material.

[0178] In some possible implementations, the side surface of the first electrode 120 is covered by the insulating layer 130. That is, the insulating layer 130 extends along the side surface of the first electrode 120 to a side of the first electrode 120 away from the array substrate 110, and covers at least part of the side of the first electrode 120 away from the array substrate 110. In some possible implementations, the insulating layer 130 can be a pixel boundary layer, the first opening 810 can be a pixel opening, and the material of the insulating layer 130 can be an inorganic material.

[0179] In some possible implementations, referring to Figure 6 , the insulating layer 130 includes a first sub-layer 131 and a second sub-layer 132 which are stacked in a direction away from the array substrate 110, and a first ratio of nitrogen and silicon content in the first sub-layer 131 is different from a second ratio of nitrogen and silicon content in the second sub-layer 132.

[0180] In some possible implementations, the materials of the first sub-layer 131 and the second sub-layer 132 can both be silicon nitride, but the first ratio of nitrogen and silicon content in the first sub-layer 131 is different from the second ratio of nitrogen and silicon content in the second sub-layer 132.

[0181] In some other possible implementations, the material of the first sub-layer 131 can be silicon nitride, and the material of the second sub-layer 132 can be silicon oxide.

[0182] In some possible implementations, the first ratio of nitrogen and silicon content in the first sub-layer 131 is X, and the second ratio of nitrogen and silicon content in the second sub-layer 132 is Y, where 0 < X < 3 / 4 and 0 ≤ Y < 3 / 4, and X > Y.

[0183] On this basis, optionally, when Y = 0, the thickness H4 of the second sub-layer 132 is less than the thickness H3 of the first sub-layer 131; and when Y ≠ 0, the thickness H4 of the second sub-layer 132 is greater than the thickness H3 of the first sub-layer 131.

[0184] Optionally, the thickness H3 of the first sub-layer 131 ranges from 0 to 3000 angstroms, and the thickness H4 of the second sub-layer 132 ranges from 0 to 4000 angstroms.

[0185] In some possible implementations, referring again to Figure 1 , the orthographic projection of the first electrode 120 on the array substrate 110 at least partially overlaps the orthographic projection of the isolation structure 140 on the array substrate 110, for example, the orthographic projection of the side surface of the first electrode 120 on the array substrate 110 is located within the orthographic projection of the isolation structure 140 on the array substrate 110.

[0186] In some possible implementations, referring again to Figure 1 and Figure 2The display panel provided by the embodiment can further include an isolation structure 140.

[0187] The isolation structure 140 is located on the side of the insulating layer 130 away from the array substrate 110, and includes an isolation opening. The orthographic projection of the first opening 810 on the array substrate 110 is located within the orthographic projection of the isolation opening on the array substrate 110. The isolation opening and the first opening 810 are in communication, and together expose at least part of the first electrode 120.

[0188] In some possible implementation manners, referring to Figure 8 The isolation structure 140 includes a support part 141 and a blocking part 142 which are stacked on the side away from the array substrate 110. The orthographic projection of the support part 141 on the array substrate 110 is located within the orthographic projection of the blocking part 142 on the array substrate 110. That is, the side of the isolation structure 140 forms an undercut structure.

[0189] In some possible implementation manners, the display panel includes a display area and a non-display area (such as a frame area) at least partially surrounding the display area.

[0190] The first electrode 120 is located in the display area, and the display panel further includes a signal trace which is provided in the same layer as the first electrode 120 and is located in the non-display area. The insulating layer 130 covers the side surface of the signal trace and the side of the signal trace away from the array substrate 110.

[0191] For example, in the display area, the insulating layer 130 covers the edge region of the first electrode 120 and exposes the central region of the first electrode. In the non-display area, the insulating layer 130 completely covers the signal trace which is provided in the same layer as the first electrode 120.

[0192] In this case, the thickness of the insulating layer 130 can be greater than or equal to the thickness of the signal trace. In this way, it can be ensured that the signal trace in the non-display area will be damaged by the etching solution in the patterning and etching operation of the isolation structure 140.

[0193] Referring to Figure 11 The embodiment further provides a manufacturing method of a display panel, which can include the following steps.

[0194] In step S110, an array substrate 110 is provided.

[0195] In step S120, a first electrode 120 is provided on one side of the array substrate 110.

[0196] Step S130, an insulating layer 130 is disposed on the side of the first electrode 120 away from the array substrate 110, the insulating layer 130 comprises a first opening 810, the first electrode 120 comprises a portion exposed from the first opening 810, and the side surface of the first electrode 120 is covered by the insulating layer 130. The thickness H1 of the insulating layer 130 is greater than or equal to the thickness H2 of the first electrode 120.

[0197] Step S140, a light emitting unit 150 is formed at least partially in the first opening 810 and on the side of the first electrode 120 away from the array substrate 110.

[0198] In some possible implementation manners, in step S130, the insulating layer 130 with a thickness greater than or equal to 1000 angstroms can be disposed on the side of the first electrode 120 away from the array substrate 110.

[0199] In some possible implementation manners, after step S130, the method further comprises the following steps.

[0200] Step S210, a separation layer 1401 is disposed on the side of the insulating layer 130 away from the array substrate 110.

[0201] For example, referring to FIG. 2, the separation layer 1401 can be formed on the side of the insulating layer 130 away from the array substrate 110. Figure 12 In this embodiment, the separation layer 1401 can be formed in an integral layer.

[0202] Step S220, the separation layer 1401 is etched to form a separation structure 140 with a separation opening.

[0203] For example, referring to FIG. 2, the separation layer 1401 can be formed on the side of the insulating layer 130 away from the array substrate 110. Figure 13 In this embodiment, the separation layer 1401 can be patterned by etching, so as to form the separation structure 140 with the separation opening.

[0204] In the foregoing steps, the risk of the insulating layer 130 having a breakage is reduced, and in the process of patterning and etching the separation layer 1401 in step S150, the wind direction of the etching liquid invading the first electrode 120 from the breakage of the insulating layer 130 can be reduced, so as to avoid damaging the first electrode 120.

[0205] Step S230, the insulating layer 130 is etched from the separation opening to form a first opening 810, and the first opening 810 exposes at least part of the first electrode 120.

[0206] After the separation opening is etched, the insulating layer 130 can be further etched to form a structure as shown in FIG. 1. Figure 1

[0207] ​In some possible implementation manners, in step S130, a material with a first ratio of nitrogen and silicon content can be used to form the first sub-layer 121 of the insulating layer 130 on the side of the first electrode 120 away from the array substrate 110, and then a material with a second ratio of nitrogen and silicon content can be used to form the second sub-layer 122 of the insulating layer 130 on the side of the first sub-layer 121 away from the array substrate 110.

[0208] The first ratio is different from the second ratio.

[0209] In some possible implementation manners, in step S140, the etching method can be used to form the light-emitting unit 150, the second electrode 160 and the encapsulation unit 170, which are at least partially located in the isolation opening and are stacked away from the array substrate 110.

[0210] The present application also provides an electronic device including the display panel provided by the present application or the display panel manufactured by the manufacturing method of the display panel provided by the present application. The electronic device can include a mobile phone, a tablet computer, a smart wearable device, a television, a notebook computer, a display, and the like.

[0211] To sum up, the present application provides a display panel, a manufacturing method of a display panel and an electronic device. By setting the thickness of the insulating layer to be greater than the thickness of the first electrode, the risk of a break in the insulating layer at the position covering the first electrode can be reduced, and the first electrode can be prevented from being damaged by the etching liquid in the subsequent patterning and etching process of other film layers, thereby ensuring the yield of the display panel.

[0212] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described, however, as long as the combinations of the technical features do not contradict each other, they should be considered within the scope of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: an array substrate; an insulating layer located on one side of the array substrate, the insulating layer comprising a plurality of first openings; a plurality of first electrodes located on one side of the array substrate and arranged at intervals, the first electrodes comprising portions exposed from the first openings, and the side surfaces of the first electrodes being covered by the insulating layer, the thickness of the insulating layer being greater than or equal to the thickness of the first electrodes; a light-emitting unit located on the side of the first electrodes away from the array substrate.

2. The display panel of claim 1, wherein, The insulating layer comprises a first insulating portion covering the first electrodes and a second insulating portion not covering the first electrodes, the ratio of the thickness of the first insulating portion to the thickness of the first electrodes being greater than or equal to 1; Preferably, the thickness of the insulating layer is greater than or equal to 1000 angstroms; Preferably, the thickness of the insulating layer ranges from 2000 to 4000 angstroms; Preferably, the distance from the side of the first insulating portion away from the array substrate to the array substrate is greater than the distance from the side of the first electrodes away from the array substrate to the array substrate.

3. The display panel of claim 1, wherein, The first electrodes comprise a first surface on the side away from the array substrate and a second surface on the side close to the array substrate; The orthographic projection of the second surface on the array substrate is located within the orthographic projection of the first surface on the array substrate, or the orthographic projection of the first surface on the array substrate is located within the orthographic projection of the second surface on the array substrate.

4. The display panel of claim 1, wherein, The material of the insulating layer is an inorganic material; Preferably, the insulating layer comprises a first sub-layer and a second sub-layer arranged in layers in the direction away from the array substrate, the content of silicon in the first sub-layer being different from the content of silicon in the second sub-layer; The content of nitrogen and silicon in the first sub-layer is a first ratio, and the content of nitrogen and silicon in the second sub-layer is a second ratio, the first ratio being different from the second ratio; Preferably, the material of the first sub-layer comprises silicon nitride, and the material of the second sub-layer comprises silicon nitride or silicon oxide.

5. The display panel of claim 4, wherein, The first ratio is X, and the second ratio is Y, wherein 0X<3 / 4, 0Y<3 / 4, and X>Y; Preferably, when Y=0, the thickness of the second sub-layer is less than the thickness of the first sub-layer; when Y≠0, the thickness of the second sub-layer is greater than the thickness of the first sub-layer.

6. The display panel of claim 4, wherein, The thickness of the first sub-layer ranges from 0 to 3000 angstroms, and the thickness of the second sub-layer ranges from 0 to 4000 angstroms.

7. The display panel of claim 1, wherein, The first electrodes comprise a first conductive layer, a second conductive layer, and a third conductive layer arranged in layers in the direction away from the array substrate, the etching rate of the second conductive layer being different from the etching rates of the first conductive layer and the third conductive layer; Preferably, the orthographic projection of the second conductive layer on the array substrate is located within the orthographic projections of the first conductive layer and the third conductive layer on the array substrate; Preferably, the materials of the first conductive layer and the third conductive layer comprise at least one of indium tin oxide, indium zinc oxide, and indium gallium oxide, and the material of the second conductive layer comprises silver.

8. The display panel of claim 1, wherein, The display panel further comprises: An isolation structure located on a side of the insulating layer distal to the array substrate, the isolation structure comprising an isolation opening, a projection of the first opening on the array substrate being located within a projection of the isolation opening on the array substrate; Preferably, the isolation structure comprises a support portion and a barrier portion which are stacked on a side distal to the array substrate, a projection of the support portion on the array substrate being located within a projection of the barrier portion on the array substrate.

9. The display panel of claim 8, wherein, At least part of the first electrode has a projection on the array substrate which at least partially overlaps a projection of the isolation structure on the array substrate; Preferably, a side surface of the first electrode has a projection on the array substrate which is located within a projection of the isolation structure on the array substrate.

10. The display panel of claim 9, wherein, The support portion comprises a first metal layer and a second metal layer which are stacked on a side distal to the array substrate, and the barrier portion comprises a third metal layer; Preferably, the first metal layer comprises molybdenum, the second metal layer comprises aluminum, and the third metal layer comprises titanium.

11. The display panel of claim 9, wherein, The display panel further comprises a second electrode at least partially located within the isolation opening, at least part of the second electrode being located on a side of the light emitting unit distal to the array substrate and in electrical contact with the light emitting unit, and another at least part of the second electrode being located on a side of the insulating layer distal to the array substrate and in electrical contact with the isolation structure.

12. The display panel of claim 11, wherein, The display panel further comprises a first encapsulation layer on a side of the second electrode distal to the array substrate and at least partially located within the first opening; Preferably, at least part of the first encapsulation layer is located on a side of the isolation structure distal to the array substrate; Preferably, the first encapsulation layers corresponding to adjacent first openings are spaced apart, and a spaced-apart breakage is located on a side of the isolation structure distal to the array substrate; Preferably, the display panel further comprises a second encapsulation layer and a third encapsulation layer which are stacked on a side of the first encapsulation layer distal to the array substrate; Preferably, the first encapsulation layer and the third encapsulation layer comprise inorganic materials, and the second encapsulation layer comprises an organic material.

13. The display panel of claim 8, wherein, The isolation opening comprises a first isolation opening and a second isolation opening, the light emitting unit comprises first light emitting units and second light emitting units which differ in light emitting color, at least part of the first light emitting units being located within the first isolation opening, and at least part of the second light emitting units being located within the second isolation opening; The insulating layer comprises a first limiting portion of the isolation structure corresponding to the first isolation opening and a second limiting portion of the isolation structure corresponding to the second isolation opening, a projection of the first limiting portion on the substrate being located within a projection of the first isolation opening on the substrate, and a projection of the second limiting portion on the substrate being located within a projection of the second isolation opening on the substrate; Preferably, the thickness of the first limiting portion and the thickness of the second limiting portion are both greater than the thickness of the first electrode. The thickness of the first limiting part is greater than the thickness of the second limiting part, or The thickness of the first limiting part is substantially equal to the thickness of the second limiting part. Preferably, the isolation opening further comprises a third isolation opening, the light-emitting unit further comprises a third light-emitting unit with a light-emitting color different from the light-emitting colors of the first and second light-emitting units, at least part of the third light-emitting unit is located in the third isolation opening. The insulating layer further comprises a third limiting part of the isolation structure corresponding to the third isolation opening, the orthographic projection of the third limiting part on the substrate is located in the orthographic projection of the third isolation opening on the substrate. Preferably, the thicknesses of the first, second and third limiting parts are all greater than the thickness of the first electrode. The thickness of the second limiting part is greater than the thickness of the third limiting part, or The thickness of the second limiting part is substantially equal to the thickness of the second limiting part.

14. The display panel of claim 1, wherein, The display panel comprises a display area and a non-display area at least partially surrounding the display area; the first electrode is located in the display area, and the display panel further comprises a signal trace provided in the same layer as the first electrode and located in the non-display area; and the insulating layer continuously covers the side surface of the signal trace and the side of the signal trace away from the array substrate. Preferably, the thickness of the insulating layer is greater than or equal to the thickness of the signal trace.

15. A display panel, characterized by The display panel comprises: an array substrate; an insulating layer located on one side of the array substrate, the insulating layer comprising a first opening; a plurality of first electrodes located on one side of the array substrate and spaced apart; the first electrode comprises a portion exposed from the first opening, the insulating layer comprises a first insulating portion covering the first electrode and a second insulating portion provided away from the first electrode, and the thickness of the insulating layer at the junction of the first and second insulating portions is greater than the thickness of the first electrode corresponding to the first insulating portion; a light-emitting unit located on the side of the first electrode away from the array substrate; and a second electrode located on the side of the light-emitting unit away from the array substrate.

16. The display panel of claim 15, wherein, The insulating layer covers the sidewall of the first electrode.

17. The display panel of claim 15, wherein, The material of the insulating layer is inorganic material. Preferably, the insulating layer comprises a first sub-layer and a second sub-layer stacked in a direction away from the array substrate, the nitrogen and silicon contents in the first sub-layer are in a first ratio, the nitrogen and silicon contents in the second sub-layer are in a second ratio, and the first ratio is different from the second ratio. Preferably, the material of the first sub-layer comprises silicon nitride, and the material of the second sub-layer comprises silicon nitride or silicon oxide.

18. The display panel of claim 17, wherein, The first ratio is X, and the second ratio is Y, wherein 0X<3 / 4, 0Y<3 / 4, and X>Y. Preferably, when Y=0, the thickness of the second sub-layer is less than the thickness of the first sub-layer; and when Y≠0, the thickness of the second sub-layer is greater than the thickness of the first sub-layer.

19. The display panel of claim 17, wherein, The thickness of the first sub-layer ranges from 0 to 3000 angstroms, and the thickness of the second sub-layer ranges from 0 to 4000 angstroms.

20. The display panel of claim 15, wherein, A projection of at least part of the first electrode on the array substrate at least partially overlaps a projection of the isolation structure on the array substrate. Preferably, a projection of a side surface of the first electrode on the array substrate is located within a projection of the isolation structure on the array substrate.

21. The display panel of claim 15, wherein, The display panel further comprises: An isolation structure on a side of the insulating layer away from the array substrate, the isolation structure comprising an isolation opening, a projection of the first opening on the array substrate being located within a projection of the isolation opening on the array substrate. Preferably, the isolation structure comprises a support portion and a blocking portion stacked on a side away from the array substrate, a projection of the support portion on the array substrate being located within a projection of the blocking portion on the array substrate.

22. A method of manufacturing a display panel, characterized by, The method comprises: Providing an array substrate; Providing a first electrode on a side of the array substrate; Providing an insulating layer on a side of the first electrode away from the array substrate, the insulating layer comprising a first opening, the first electrode comprising a portion exposed from the first opening, a side surface of the first electrode being covered by the insulating layer, a thickness of the insulating layer being greater than or equal to a thickness of the first electrode; Forming a light emitting unit on a side of the first electrode away from the array substrate.

23. The method of claim 22, wherein, The step of providing an insulating layer on a side of the first electrode away from the array substrate comprises: Providing an insulating layer with a thickness greater than or equal to 1000 angstroms on a side of the first electrode away from the array substrate.

24. The method of claim 22, wherein, The method further comprises: Providing an isolation layer on a side of the insulating layer away from the array substrate; Etching the isolation layer to form an isolation structure with an isolation opening; Etching the insulating layer from the isolation opening to form a first opening, the first opening exposing at least part of the first electrode.

25. The method of claim 22, wherein, The step of providing an insulating layer on a side of the first electrode away from the array substrate comprises: Using a material with a first ratio of nitrogen to silicon to form a first sub-layer of the insulating layer on a side of the first electrode away from the array substrate; Using a material with a second ratio of nitrogen to silicon to form a second sub-layer of the insulating layer on a side of the first sub-layer away from the array substrate, the first ratio being different from the second ratio.

26. An electronic device, comprising: The electronic device comprises the display panel of any one of claims 1-21 or the display panel manufactured by the display panel manufacturing method of any one of claims 22-25.

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