High-linearity digital time converter circuit
By employing a dual-stage discharge mechanism and an adaptive full-scale adjustment high-linearity digital time converter circuit, the shortcomings of traditional digital time converters in terms of linearity and accuracy are overcome, achieving high linearity and robust digital time conversion, suitable for various high-speed systems.
Patent Information
- Application Number
- CN202510979597.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-16
- Publication Date
- 2025-10-28
AI Technical Summary
Existing digital time converter circuits suffer from insufficient linearity and accuracy in demanding applications, especially when clearing jitter in fractional phase-locked loops, where the nonlinearity of traditional architectures is quite significant.
A high linearity digital time converter circuit is adopted, which uses a two-stage discharge mechanism, including a variable slope stage and a constant slope stage, combined with adaptive full-scale adjustment, to ensure the linear relationship between time delay and control code. Furthermore, the sensitivity to parasitic capacitance and process, voltage, and temperature changes is reduced through analog integrated circuit design.
It achieves high linearity digital time conversion, adapts to full-scale variations in different application scenarios, improves system robustness and conversion accuracy, reduces sensitivity to parasitic capacitance and PVT variations, and simplifies circuit structure and power consumption.
Smart Images
Figure CN120848145A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design and relates to a high linearity digital time converter circuit. Background Technology
[0002] Time converter (DTC) circuits are commonly used in various SOC or monolithic integrated circuit systems, most commonly in PLLs, SerDes, and PET. In these systems, the performance of the time converter (DTC) directly affects the overall performance of the circuit system. For example, in fractional-N PLLs, the time converter (DTC) is typically used to implement jitter removal; therefore, its linearity directly affects the jitter removal effect, and consequently, the quality of the PLL output clock. Currently, common DTC architectures fall into two categories, as follows: Figure 1 He Ru Figure 2 , Figure 1 It is a variable slope digital time converter architecture. Because the slope of the charging curve corresponding to different DTC codes is inconsistent at the decision comparison point VB, the DTC has a large nonlinearity. Figure 2 For constant slope digital-to-time converter architecture, such as Figure 2 It is known that the slope of the charging curve is constant at the decision comparison point VB. Therefore, theoretically, the linearity of the DTC is good. However, in practice, since the charging starting point usually uses a capacitor-type DAC, the DTC is susceptible to parasitic effects of capacitors and has low accuracy, resulting in nonlinearity. Therefore, in some demanding applications, such as fractional phase-locked loop jitter clearing, there are high requirements for the linearity and full-scale error of the DTC, necessitating a DTC architecture with higher linearity. Summary of the Invention
[0003] In view of this, the purpose of the present invention is to provide a high linearity digital time converter circuit, which is suitable for PLL, SerDes, PET and other systems, can realize high linearity digital time conversion function, and can simplify the circuit structure of related systems.
[0004] To achieve the above objectives, the present invention provides the following technical solution:
[0005] A high linearity digital time converter circuit includes a DTC current source 200, a decision comparator circuit 100, a reset circuit 300, and a first inverter INV1. The first input terminal of the decision comparator circuit is connected to a threshold voltage VB, and the second input terminal is connected to the DTC current source and the first output terminal of the reset circuit (denoted as point A). The output terminal of the decision comparator circuit is connected to the input terminal of the first inverter INV1 and the second output terminal of the reset circuit (denoted as point B). The output terminal of the first inverter INV1 outputs a signal.
[0006] Preferably, the decision comparison circuit 100 includes an amplifier, a current source, a resistor, a first NMOS transistor M1, and a third NMOS transistor M3; the positive input terminal of the amplifier is connected to the comparison signal VB, the negative input terminal of the amplifier is connected to one end of the resistor and the source of the third NMOS transistor M3, and the output terminal of the amplifier is connected to the gate of the third NMOS transistor M3 and the gate of the first NMOS transistor M1; the other end of the resistor is grounded; the drain of the third NMOS transistor M3 is connected to the current source; the source of the first NMOS transistor M1 is connected to the DTC current source and the first output terminal of the reset circuit 300, and the drain of the first NMOS transistor M1 is connected to the input terminal of the first inverter INV1 and the second output terminal of the reset circuit.
[0007] Preferably, the reset circuit includes a PMOS transistor M0, a buffer BUF, a second inverter INV2, a second NMOS transistor M2, and a capacitor C. hold The drain of PMOS transistor M0 is connected to the drain of the first NMOS transistor M1 in the decision comparator circuit. The source of PMOS transistor M0 is connected to the operating voltage VS, and the gate of PMOS transistor M0 is connected to the output of buffer BUF. The input of buffer BUF is connected to the input of the second inverter INV2 and receives the CKEN signal. The output of the second inverter INV2 is connected to the gate of the second NMOS transistor M2. The drain of the second NMOS transistor M2 is connected to the operating voltage VS, and the source of the second NMOS transistor M2 is connected to capacitor C. hold One end of the circuit is connected to the source of the first NMOS transistor M1 in the decision comparator circuit and the DTC current source 200; capacitor C hold The other end is grounded.
[0008] Preferably, the DTC current source 200 is composed of multiple digitally controlled current sources connected in parallel, and each digitally controlled current source is composed of a switch connected in series with the current source.
[0009] Preferably, the output current magnitude and conduction time of the DTC current source 200 are determined by the clock signal CK. DTC1 Clock signal CK DTC2 and control code DTC code control.
[0010] Preferably, the voltage signal at the positive input terminal of the amplifier in the decision comparator circuit is converted into the gate voltage of the first NMOS transistor M1, thereby forming a stable threshold voltage for the decision comparator circuit. The decision comparator circuit compares the potential at point A with the threshold voltage VB. When the potential at point A is less than the threshold voltage, the potential at point B, i.e., the input voltage at the first inverter INV1, changes from high to low, and the total output of the circuit changes from low to high. This process completes the delay of the rising edge of the clock signal. The DTC current source is connected to the capacitor C of the reset circuit. hold The discharge process determines the rise time of the signal.
[0011] Preferably, the capacitor C of the DTC current source in the reset circuit hold The discharge process is divided into a variable slope stage and a constant slope stage in sequence.
[0012] Preferably, the time delay from the input signal CKIN of the DTC current source 200 to the input signal CKOUT of the reset circuit 300 is determined by the control code DTC. code control.
[0013] The beneficial effects of this invention are as follows:
[0014] (1) High linearity conversion: The circuit of this invention achieves high linearity digital time conversion. By using constant current discharge (constant slope stage) at the signal inversion point (threshold voltage), the time delay and control code DTC are effectively guaranteed. code The linear relationship between them. The entire conversion process is insensitive to circuit parasitic capacitance, further reducing nonlinear factors.
[0015] (2) Adaptive full-scale adjustment and wide applicability: The duration of the first stage (variable slope stage) of the discharge process (i.e., the DTC full-scale time) can be adaptively adjusted. This allows the circuit to adapt to application scenarios where the full-scale time changes during operation (such as the periodic fluctuation of the voltage-controlled oscillator caused by PVT), and it is particularly suitable for systems that require dynamic adjustment, such as Fractional-N PLL jitter correction.
[0016] The circuit design of this invention is applicable to a variety of high-speed systems, such as PLL (phase-locked loop), SerDes (serializer / deserializer), PET (phase error tracker), etc.
[0017] (3) Strong robustness and stable performance:
[0018] Insensitive to PVT (process, voltage, temperature) variations: The adaptive full-scale adjustment mechanism (the first-stage discharge time Tosc automatically adapts to the input signal period) effectively offsets the impact of PVT variations on the core time delay accuracy, improving system robustness.
[0019] Insensitive to parasitic capacitance: The circuit design and operating principle make its performance less susceptible to the influence of parasitic capacitance, ensuring conversion accuracy and stability.
[0020] (4) Simple circuit structure and easy integration: Implemented using analog integrated circuits, the overall circuit structure is simple. It is easy to integrate into more complex SoC designs. Compared with traditional solutions, it helps to simplify the circuit structure of related application systems (such as PLL, SerDes).
[0021] (5) High power efficiency: As an analog circuit implementation, it usually has the characteristic of low power consumption.
[0022] In summary, this invention provides a simple and easy-to-integrate analog DTC circuit solution. Its unique two-stage discharge mechanism (adaptive variable slope stage + constant current constant slope stage) cleverly combines adaptive full-scale adjustment and constant flip-point current to ensure high linearity and robustness to PVT variations throughout the conversion range, while maintaining the advantages of insensitivity to parasitic effects and low power consumption. This makes it very suitable for precise timing control applications in high-performance clock systems (such as PLLs and SerDes).
[0023] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description
[0024] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:
[0025] Figure 1 Schematic diagram and characteristic curves of a variable slope digital time converter;
[0026] Figure 2 Schematic diagram and characteristic curves of a constant slope digital time converter;
[0027] Figure 3 This is a circuit diagram of the high linearity digital time conversion circuit of the present invention;
[0028] Figure 4 This is a timing diagram of the high linearity digital-to-time conversion circuit of the present invention;
[0029] Figure 5 This is a characteristic curve of the high linearity digital time conversion circuit (point A) of the present invention;
[0030] Figure reference numerals: 100 - decision comparator circuit, 200 - DTC current source, 300 - reset circuit. Detailed Implementation
[0031] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0032] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.
[0033] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.
[0034] Please see Figure 3 This invention provides a high linearity digital time converter (DTC) circuit. The circuit structure includes: a DTC current source 200, a decision comparator circuit 100, a reset circuit 300, and an inverter INV1. The left input terminal of the decision comparator circuit 100 is connected to a threshold voltage VB, and the right input terminal is connected to the lower output terminal of the DTC current source 200 and the reset circuit 300 (denoted as point A). The output terminal of the decision comparator circuit is connected to the input terminal of INV1 and the upper output terminal of the reset circuit (denoted as point B). The output terminal of the inverter INV1 outputs a signal.
[0035] Example 1:
[0036] In this embodiment of the invention, the decision comparison circuit 100 includes an amplifier, a current source, a resistor, and two NMOS transistors (M1 and M3). The positive input terminal of the amplifier is connected to the comparison voltage signal VB, the negative input terminal of the amplifier is connected to one end of the resistor and the source of M3, and the output terminal of the amplifier is connected to the gate of M3 and the gate of M1, respectively. The other end of the resistor is grounded. The drain of M3 is connected to the current source. The source of M1 is connected to the DTC current source and one end of the reset circuit, and the drain of M1 is connected to the input terminal of the inverter INV1 and the other end of the reset circuit, respectively.
[0037] Example 2:
[0038] In this embodiment of the invention, the reset circuit 300 includes a PMOS transistor M0, two inverters (INV0, INV2), an NMOS transistor M2, and a capacitor C. hold The drain of M0 is connected to the drain of M1 in the decision comparator circuit 100, the source of M0 is connected to the operating voltage, and the gate of M0 is connected to the output of the buffer BUF. The input of the buffer BUF is connected to the input of the inverter INV2 and receives the CKEN signal. The output of the buffer BUF is connected to the gate of M2. The drain of M2 is connected to the operating voltage, and the source of M2 is connected to capacitor C. hold One end of the capacitor is connected to the source of M1 in the decision comparator circuit and the DTC current source; capacitor C hold The other end is grounded.
[0039] Example 3:
[0040] In an embodiment of the present invention, the DTC current source 200 is composed of multiple digitally controlled current sources connected in parallel. Each digitally controlled current source consists of a switch connected in series with a current source. The output current magnitude and conduction time of the DTC current source are determined by the signal CK. DTC1 CK DTC2 DTC code control.
[0041] The working principle of the circuit of this invention is as follows:
[0042] Figure 3 In the circuit structure shown, the threshold voltage generation circuit in the decision comparator circuit 100 consists of an amplifier, an NMOS transistor M3, a resistor, and a current source. The various parts of the threshold voltage generation circuit form a negative feedback circuit, converting the voltage signal VB at the positive input of the amplifier into the gate voltage of the NMOS transistor M1, thereby forming a stable threshold voltage for the decision comparator circuit. Figure 5 The voltage VB is shown. The NMOS transistor M2 in the reset circuit 300 is related to the capacitor C in the reset circuit. hold The charging process and the effect of the DTC current source on capacitor C holdThe discharge process causes a potential change at point A. The decision comparator circuit compares the potential at point A with the threshold voltage. When the potential at point A is less than the threshold voltage, the potential at point B, i.e., the voltage at the input of inverter INV1, changes from high to low. The overall output of the circuit then changes from low to high. This process completes the delay of the rising edge of the clock signal. The DTC current source is connected to C... hold The discharge process determines the signal rise time delay. The DTC current source of this invention affects C. hold The discharge process is divided into a variable slope stage and a constant slope stage in sequence.
[0043] like Figure 5 As shown, 0~T osc The time period is for DTC current source 200 pairs of capacitors C hold The variable slope phase of the discharge process. Combined with, for example... Figure 4 The circuit timing diagram shows that when CKEN is low, the output of the CKEN signal through the buffer BUF is low. At this time, M0 is turned on, and the potential at point B (the drain of M1 and the input of inverter INV1) is high. The total output of the circuit is CK. out The voltage level is low; simultaneously, the CKEN signal outputs a high level via inverter INV2, at which point M2 is turned on, and the potential at point A is... Figure 5 As shown in the diagram, VS completes the reset. When CKEN changes from low to high, upon detecting the rising edge of CKIN, CK... DTC1 When the voltage level changes from low to high, during the duration of the high-level transition, the current source array (i.e., DTC current source 200) will affect C. hold Discharge occurs, and the discharge rate depends on the DTC control code. code ,like Figure 5 As shown, different voltage change slopes in this stage represent different DTC control codes. The discharge time in the first stage of this invention is CK. DTC1 The duration of the high-level signal can be adaptively adjusted. Taking a Fractional-NPLL as an example, due to the influence of PVT factors, the period of the signal output by the voltage-controlled oscillator will fluctuate. This invention can adaptively control the discharge time to one cycle of the voltage-controlled oscillator (i.e., T) to accommodate such fluctuations. osc ).
[0044] In T osc The time period from the start of time until the potential at point A is less than VB is the period of time for the DTC current source to C. hold The constant slope phase of the discharge process. At this time, CK... DTC1 CK becomes low level DTC2 When the voltage level goes high, the current source array turns on all current sources, affecting C. holdA second discharge is initiated, with a constant current during this discharge period, until the potential at point A is less than VB. At this point, transistor M1 conducts, discharging to point B. The potential at point B decreases, and CKOUT goes high. This completes the rising edge delay process.
[0045] Through the above process, this invention achieves a time delay from CKIN to CKOUT, the magnitude of which depends on the DTC code. Throughout the entire operation, it is insensitive to the circuit's parasitic capacitance, and the discharge current remains constant at the switching point. Therefore, the DTC exhibits excellent linearity during the conversion process.
[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A high linearity digital time converter circuit, characterized in that, The circuit includes a DTC current source, a decision comparator circuit, a reset circuit, and a first inverter INV1; The first input terminal of the decision comparison circuit is connected to the threshold voltage VB, the second input terminal is connected to the DTC current source and the first output terminal of the reset circuit, and the output terminal of the decision comparison circuit is connected to the input terminal of the first inverter INV1 and the second output terminal of the reset circuit. The output terminal of the first inverter INV1 outputs a signal.
2. The high linearity digital time converter circuit according to claim 1, characterized in that, The decision comparison circuit includes an amplifier, a current source, a resistor, a first NMOS transistor M1, and a third NMOS transistor M3. The positive input terminal of the amplifier is connected to the comparison signal VB, the negative input terminal of the amplifier is connected to one end of the resistor and the source of the third NMOS transistor M3, and the output terminal of the amplifier is connected to the gate of the third NMOS transistor M3 and the gate of the first NMOS transistor M1. The other end of the resistor is grounded. The drain of the third NMOS transistor M3 is connected to the current source. The source of the first NMOS transistor M1 is connected to the DTC current source and the first output terminal of the reset circuit, and the drain of the first NMOS transistor M1 is connected to the input terminal of the first inverter INV1 and the second output terminal of the reset circuit.
3. The high linearity digital time converter circuit according to claim 1, characterized in that, The reset circuit includes a PMOS transistor M0, a buffer BUF, a second inverter INV2, a second NMOS transistor M2, and a capacitor C. hold The drain of PMOS transistor M0 is connected to the drain of the first NMOS transistor M1 in the decision comparator circuit. The source of PMOS transistor M0 is connected to the operating voltage VS, and the gate of PMOS transistor M0 is connected to the output of buffer BUF. The input of buffer BUF is connected to the input of the second inverter INV2 and receives the CKEN signal. The output of the second inverter INV2 is connected to the gate of the second NMOS transistor M2. The drain of the second NMOS transistor M2 is connected to the operating voltage VS, and the source of the second NMOS transistor M2 is connected to capacitor C. hold One end of the capacitor is connected to the source of the first NMOS transistor M1 in the decision comparator circuit and the DTC current source; capacitor C hold The other end is grounded.
4. The high linearity digital time converter circuit according to claim 1, characterized in that, The DTC current source is composed of multiple numerically controlled current sources connected in parallel, and each numerically controlled current source is composed of a switch and a current source connected in series.
5. The high linearity digital time converter circuit according to claim 4, characterized in that, The magnitude of the output current of the DTC current source is determined by the clock signal CK. DTC1 Clock signal CK DTC2 and control code DTC code control.
6. The high linearity digital time converter circuit according to claim 2, characterized in that, The first and second output terminals of the reset circuit are denoted as points A and B, respectively. The voltage signal at the positive input terminal of the amplifier in the decision comparator circuit is converted into the gate voltage of the first NMOS transistor M1, thereby forming a stable threshold voltage VB for the decision comparator circuit. The decision comparator circuit compares the potential at point A with the threshold voltage. When the potential at point A is less than the threshold voltage, the potential at point B, i.e., the input voltage at the first inverter INV1, changes from high to low, and the total output terminal of the circuit changes from low to high. This process completes the time delay of the rising edge of the clock signal. The DTC current source is connected to the capacitor C of the reset circuit. hold The discharge process determines the rise time of the signal.
7. The high linearity digital time converter circuit according to claim 6, characterized in that, The capacitor C of the DTC current source in the reset circuit hold The discharge process is divided into a variable slope stage and a constant slope stage in sequence.
8. The high linearity digital time converter circuit according to claim 1, characterized in that, The time delay from the input signal CKIN of the DTC current source to the input signal CKOUT of the reset circuit is determined by the control code DTC. code control.