Distributed FPGA cooperative control device based on time-sensitive network

Abstract

The invention provides a distributed FPGA (Field Programmable Gate Array) cooperative control device based on a time-sensitive network, which comprises a main board body and a connecting port, and is characterized in that the left end of the front side of the main board body is provided with a group of side fixed embedding ports used for keeping the position of the main board body. An IEEE 802.1 Qbv protocol dispatches a PLL unit of an FPGA flicker control module, a programmable counter of the PLL unit can accurately adjust an LED indication signal, meanwhile, an HBM power supply combination continuously provides stable bandwidth for an external storage interface, meanwhile, turbine fan blades cooperate with semiconductor cooling fins to maintain the temperature of a chip stable, and when network parameters need to be adjusted, the chip temperature is controlled to be stable. A hardware module can be updated online through cooperation of a USB expansion port and a partial reconfiguration technology, collaborative optimization of control and calculation is realized through a heterogeneous calculation architecture (ARM processor + FPGA), a complex scheduling algorithm can be executed, and nanosecond hardware acceleration response can be provided.

Description

Technical Field

[0001] This invention is a distributed FPGA collaborative control device based on time-sensitive networks, belonging to the field of FPGA control equipment technology. Background Technology

[0002] In Time-Sensitive Networking (TSN) environments, the real-time reliability of distributed FPGA collaborative control devices faces several challenges. When handling distributed tasks, FPGA devices require precise time synchronization and data consistency. While TSN standards provide time synchronization mechanisms, such as IEEE 802.1AS, these mechanisms may suffer from insufficient synchronization accuracy in practical applications due to network latency, jitter, and clock skew between devices. The configuration and reconfiguration process of FPGAs can be time-consuming, affecting the system's real-time responsiveness. Data transmission reliability in the network is also an issue. Although TSN defines various flow scheduling and priority control mechanisms, network congestion and packet loss can still occur, especially under high load conditions, directly impacting the reliability of collaborative control between FPGA devices.

[0003] Conventional solutions include employing more advanced synchronization protocols, adding redundant paths, and implementing packet retransmission strategies. However, these methods also have drawbacks. For example, while more advanced synchronization protocols can improve time synchronization accuracy, they increase system complexity and configuration difficulty. Adding redundant paths can improve data transmission reliability, but it consumes more network resources and may exacerbate network congestion. While packet retransmission strategies can compensate for data loss, they introduce additional latency, affecting the system's real-time performance. Therefore, there is an urgent need for a distributed FPGA collaborative control device based on time-sensitive networking to address these issues. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a distributed FPGA collaborative control device based on time-sensitive networks, comprising: a motherboard, a distributed FPGA core, and connection ports, in order to solve the problems mentioned in the background art.

[0005] The technical solution of the present invention is implemented as follows: A distributed FPGA collaborative control device based on time-sensitive network includes: a motherboard, a distributed FPGA core and a connection port. The front left end of the motherboard is provided with a set of side positioning slots for maintaining the position of the motherboard. The side positioning slots are fitted together with the external device body connection positioning end. The front cross-section of the motherboard is a rectangular structure, and each of its four sets of external corners is provided with a set of positioning pins for positioning and fitting the motherboard. The lower end of the positioning pin has two sets of fixing connectors for support and fixed by bolts. The upper left side of the front side of the main board has an upper air guide cavity for maintaining airflow inside. Inside the upper air guide cavity is a dust-blocking mesh to block dust from the air. To the right of the upper air guide cavity is a control core for controlling the collaborative operation of several distributed FPGA cores. The control core is a core processor. To the right of the control core are several distributed FPGA cores for FPGA collaborative control. These distributed FPGA cores are arranged in a linear structure and are all embedded inside the main board. During use, the device physically docks with the external equipment body through the side mounting port, ensuring that the positioning pins are fully engaged with the corresponding slots inside the chassis. The lower fixing connector is then secured to the frame using the matching bolts, completing the mechanical fixation of the motherboard. Before starting, the dustproof mesh of the upper air duct must be checked to ensure that the heat dissipation airflow is unobstructed. After power-on, the control core will automatically initialize each distributed FPGA core and establish hardware-level synchronous communication through the built-in TSN (Time Sensitive Network) protocol stack. Users can load preset collaborative control algorithms through the connection port. The control core will dynamically allocate computing tasks to the linearly arranged FPGA array and monitor the working status and clock synchronization deviation of each unit in real time.

[0006] In a preferred embodiment, the right side of the motherboard body has several sets of internal mounting cavities for mounting distributed FPGA cores. The interior of each internal mounting cavity is a rectangular hollow structure. Each set of internal mounting cavities has an internal vent plate at its upper end for allowing external air to circulate. The internal vent plate has several sets of diamond-shaped ventilation holes. At the same time, a cooling silicone grease coating and an insulating coating are provided between the internal vent plate and the distributed FPGA cores. On the left side of the middle position of the distributed FPGA cores, there is an internal positioning slot for connecting and positioning external devices. The inner side of the internal positioning slot has a sealing ring for preventing dust accumulation. The right side of the motherboard body has a set of rear connection ports for external data expansion connections corresponding to each set of internal mounting cavities.

[0007] In a preferred embodiment, the distributed FPGA core includes a distributed core body, a power supply module, an FPGA flashing control module, and a semiconductor heat sink. The lower end of the distributed core body is provided with a set of load boards for connection and operation. Each set of load boards is soldered onto a corresponding distributed core body. Several sets of load boards are arranged in parallel. The rear right side of each load board is provided with a power supply module for providing individual power control. The power supply module includes a VCCINT power rail, a user I / O power supply, and an HBM power supply combination for powering high-bandwidth memory and analog-to-digital conversion modules. To the right of the power supply module is a set of FPGA flashing control modules for clock generation and management.

[0008] In a preferred embodiment, the FPGA blinking control module includes a PLL (Phase-Locked Loop), a CMT (Clock Management Unit), a timing logic control component, an LED blinking component, and an output driver module. The timing logic control component consists of a counter and a flip-flop. The counter is used to measure time by accumulating clock cycles and can also program parameters to change the blinking frequency. The output driver module consists of IOBs (Programmable I / O Units) and directly drives the LED blinking component for blinking indication. It also adjusts the user I / O power supply and adapts to the power supply requirements of the LED blinking component. The right side of the FPGA blinking control module has a buffer for caching distributed data processing on the FPGA. The front of the buffer has an external storage interface for connecting to external storage devices. The left side of the external storage interface has a connection for connecting to external devices. The load board has a set of USB expansion interfaces on the left side for external USB data expansion. In actual use, the physical connection of all load boards is completed through the plug-in ports to ensure the electrical isolation of the parallel structure. Before powering on, the voltage matching of each power rail (VCCINT, user I / O, HBM combination) of the power supply module needs to be checked. After connecting the adapter power supply through the external power socket, the FPGA blinking control module will automatically start the PLL and CMT for clock synchronization. At this time, the LED blinking component will trigger a periodic light signal to indicate the initialization state through the counter. During operation, configuration parameters can be loaded through the USB expansion port. The external storage interface can be connected to a high-speed memory to expand the buffer capacity. The timing logic control component will dynamically adjust the I / O power output according to the preset algorithm. At the same time, the turbine fan blades and semiconductor heat sink work together to form forced convection heat dissipation through the main exhaust shell.

[0009] In a preferred embodiment, the USB expansion interface has a set of external power interfaces for connecting to external devices on its rear side. The lower end of the distribution core body has a set of semiconductor heat sinks for rapid heat dissipation. The outer side of the semiconductor heat sink has a set of main heat dissipation plates for providing heat conduction. The main heat dissipation plates are made of silicone grease and are located in the middle of the connection between the heating end of the semiconductor heat sink and the thermally conductive copper plate. The lower rear side of the main heat dissipation plates has a set of thermally conductive copper plates for conducting heat from the semiconductor heat sink. The thermally conductive copper plates are a right-angled arc structure and are in contact with the main air intake shell.

[0010] In a preferred embodiment, the main exhaust casing has a rectangular cross-section when viewed from above. Inside the main exhaust casing is a set of turbine blades for guiding and exchanging heat from the first and second heat-conducting copper plates. A set of air inlets is located behind the turbine blades to introduce heat-exchange air, and a set of air outlets is located on the left side of the turbine blades to exhaust the heat-exchange air. Both the air inlets and outlets have several sets of rectangular strip-shaped airflow channels, and the interiors of the air inlets and outlets are interconnected with the interiors of the turbine blades. On the upper left side of the main exhaust casing is a set of second heat-conducting copper plates for conducting heat from the second semiconductor heat sink. The first and second heat-conducting copper plates have the same specifications, and the lower right front side of the second heat-conducting copper plate is connected to the semiconductor heat sink. The heat sink 2 is connected to the heat-generating end. The first and second thermally conductive copper sheets are of the same specification and are both made of metallic copper. The first and second thermally conductive copper sheets are embedded inside the main air intake shell and form an integrated structure with the turbine fan blades. First, the silicone grease filling state of the main heat sink end plate is ensured to ensure that there are no gaps between the semiconductor heat sink and the thermally conductive copper sheets. Before powering on, it is necessary to confirm that the polarity of the external power interface is matched. After starting, the semiconductor heat sink will start working immediately. At this time, the turbine fan blades in the main air intake shell will automatically adjust the speed according to the temperature sensor signal. During operation, heat is quickly conducted to the air duct through the right-angle arc-shaped thermally conductive copper sheets 1 / 2. The airflow generated by the turbine fan blades is drawn in from the rectangular strip air inlet, and after heat exchange on the surface of the copper sheet, it is discharged from the air outlet, forming a closed-loop heat dissipation path.

[0011] In a preferred embodiment, the distributed FPGA core also includes a Time-Sensitive Network (TSN) module. As a core extension of the IEEE 802.1 standard family, the TSN achieves deterministic latency transmission through three mechanisms: time synchronization, traffic scheduling, and resource management. Its core protocols include the IEEE 802.1AS-Rev time synchronization protocol, the IEEE 802.1Qbv time-aware shaping protocol, and the IEEE 802.1CB frame duplication elimination protocol. The distributed FPGA core achieves coordinated control and computation through a heterogeneous architecture of a hard-core processor system (HPS) and programmable logic (PL). This includes Xilinx Zynq UltraScale+ MPSoC series devices integrating a quad-core ARM Cortex-A53 processing system and programmable logic units, supporting hardware acceleration modules with nanosecond-level response at the PL end. It uses the AXI-Stream interface for high-speed data stream transmission, constructs a data path from the physical layer to the application layer through a DMA controller, and utilizes partial reconfiguration technology to dynamically load hardware modules.

[0012] In a preferred embodiment, the inner mounting cavity of the motherboard carries multiple distributed FPGA cores through a rectangular hollow structure. Its parallel load board layout provides a physical basis for the time-sensitive transmission of TSN. The turbine fan blades embedded in the main exhaust shell maintain the stable operation of semiconductor heat sink one and semiconductor heat sink two, ensuring that the FPGA core maintains sub-microsecond clock accuracy when implementing the IEEE802.1AS-Rev synchronization protocol. The diamond-shaped ventilation holes of the inner partition plate, combined with the cooling silicone grease coating, enable multiple Kintex-7 FPGAs to keep the core temperature within ±2℃ under 20% load fluctuation, meeting the heat dissipation requirements of 1μs clock deviation in TSN switch interconnection scenarios. The heat conduction path is formed by thermally conductive copper sheet one, thermally conductive copper sheet two, and heat sink end plate. The control core, protected by a sealed ring within the internal positioning port, drives the quad-core ARM Cortex-A53 processing system to perform global scheduling. The power supply module for the distributed FPGA core uses an HBM power supply combination, providing 3.2Gbps data transmission bandwidth for the external storage interface. It connects to a buffer via an AXI-Stream interface to achieve hardware-level filtering for the preprocessing module. The PLL unit of the FPGA blink control module directly drives the timing logic control component. Its programmable counter, under the TSN's IEEE 802.1Qbv scheduling mechanism, compresses the LED blinking frequency error to ±0.05%. Simultaneously, the USB expansion port, in conjunction with the DMA controller, constructs a data path between the physical and application layers. In actual use, the physical connection of each module is completed through the AXI-Stream interface, ensuring the smooth operation of the data path constructed by the DMA controller. Upon startup, the quad-core ARM Cortex-A53 processing system automatically synchronizes the clocks of each node via the IEEE 802.1AS-Rev protocol. The hardware acceleration module on the PL end is dynamically loaded according to TSN requirements. During device operation, IEEE... The 802.1Qbv protocol schedules the PLL unit of the FPGA blink control module, whose programmable counter precisely adjusts the LED indicator signal. Simultaneously, the HBM power supply continuously provides stable bandwidth to the external storage interface, while the turbine fan blades and semiconductor heatsink maintain stable chip temperature. When network parameters need adjustment, the hardware module can be updated online via the USB expansion port with partial reconfiguration technology. Through a heterogeneous computing architecture (ARM processor + FPGA), it achieves coordinated optimization of control and computation, enabling the execution of complex scheduling algorithms and providing nanosecond-level hardware acceleration response, while integrating IEEE 802.1... The TSN protocol stack (including time synchronization, traffic shaping, and frame duplication elimination mechanisms) ensures sub-microsecond clock accuracy and deterministic latency in network transmission, meeting the real-time requirements of industrial automation and other scenarios. It guarantees long-term stable operation under high loads. The high-speed data path built with the AXI-Stream interface and DMA controller, combined with HBM power supply and partial reconfiguration technology, meets the dynamic update capabilities of different data transmission bandwidths and hardware modules. The modular design, through parallel load boards and standardized interfaces, expands the system scale and simplifies the maintenance process. The overall solution performs excellently in terms of real-time performance, reliability, and scalability.

[0013] After adopting the above technical solution, the beneficial effects of the present invention are as follows: Physical docking with the external device body through the side fixed socket ensures that the positioning pin is fully engaged with the corresponding slot in the chassis. The lower fixed connector is fastened to the frame with matching bolts to complete the mechanical fixation of the motherboard. Before starting, it is necessary to check whether the dustproof patch of the upper air guide cavity is clean to ensure that the heat dissipation air duct is unobstructed. After powering on, the control core will automatically initialize each distributed FPGA core and establish hardware-level synchronous communication through the built-in TSN (Time Sensitive Network) protocol stack. Users can load preset collaborative control algorithms through the connection port. The control core will dynamically allocate computing tasks to the linearly arranged FPGA array and monitor the working status and clock synchronization deviation of each unit in real time. The physical connection of all load boards is completed through the plug-in port to ensure the electrical isolation of the parallel structure. Before powering on, the voltage matching of each power rail (VCCINT, user I / O, HBM combination) of the power supply module needs to be checked. After connecting the adapter power supply through the external power plug, the FPGA blinking control module will automatically start the PLL and CMT for clock synchronization. At this time, the LED blinking component will trigger periodic light signals through the counter to indicate the initialization state. During operation, configuration parameters can be loaded through the USB expansion port. The external storage interface can be connected to a high-speed memory to expand the buffer capacity. The timing logic control component will dynamically adjust the I / O power output according to the preset algorithm. At the same time, the turbine fan blades and semiconductor heat sink work together to form forced convection heat dissipation through the main air intake shell. During device operation, the IEEE 802.1Qbv protocol schedules the PLL unit of the FPGA blinking control module. Its programmable counter precisely adjusts the LED indicator signal. Simultaneously, the HBM power supply continuously provides stable bandwidth to the external storage interface, while the turbine fan blades and semiconductor heatsink maintain stable chip temperature. When network parameters need adjustment, the hardware module can be updated online via the USB expansion port using partial reconfiguration technology. Through a heterogeneous computing architecture (ARM processor + FPGA), it achieves coordinated optimization of control and computation, enabling the execution of complex scheduling algorithms and providing nanosecond-level hardware acceleration response. It integrates IEEE 802.1... The TSN protocol stack (including time synchronization, traffic shaping, and frame duplication elimination mechanisms) ensures sub-microsecond clock accuracy and deterministic latency in network transmission, meeting the real-time requirements of industrial automation and other scenarios. It guarantees long-term stable operation under high loads. The high-speed data path built with the AXI-Stream interface and DMA controller, combined with HBM power supply and partial reconfiguration technology, meets the dynamic update capabilities of different data transmission bandwidths and hardware modules. The modular design, through parallel load boards and standardized interfaces, expands the system scale and simplifies the maintenance process. The overall solution performs excellently in terms of real-time performance, reliability, and scalability. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of a distributed FPGA collaborative control device based on a time-sensitive network according to the present invention. Figure 2 This is a right oblique side view of the structure of a distributed FPGA collaborative control device based on a time-sensitive network according to the present invention. Figure 3 This is a front top view of the internal structure of the distributed FPGA core in a distributed FPGA collaborative control device based on a time-sensitive network according to the present invention. Figure 4 This is a front top view of the related structures of thermally conductive copper sheet one and thermally conductive copper sheet two in a distributed FPGA collaborative control device based on time-sensitive network according to the present invention. Figure 5 This is a bottom view of the distribution positions of semiconductor heat sink one and semiconductor heat sink two in a distributed FPGA collaborative control device based on time-sensitive network according to the present invention. Figure 6 This is a system flowchart of the distributed FPGA collaborative control device based on time-sensitive network according to the present invention. In the diagram: 1-Main board body, 2-Side positioning port, 3-Positioning pin, 4-Fixed connector, 5-Upper air guide chamber, 6-Control core, 7-Distributed FPGA core, 8-Inner positioning port, 9-Rear connection port; 71-Core Main Body of the Division, 72-Power Supply Module, 73-Power Flicker Module, 74-Buffer, 75-External Storage Interface, 76-Plug-in Port, 77-USB Expansion Port, 78-External Power Supply Socket, 79-Connection Interface, 701-Load Board, 702-Main Heatsink, 703-Heat Conducting Copper Sheet 1, 704-Main Airflow Sheet, 705-Air Outlet, 706-Air Inlet, 707-Wheel Drive Fan Blade, 708-Side Heatsink, 709-Heat Conducting Copper Sheet 2, 710-Semiconductor Heatsink 1, 711-Semiconductor Heatsink 2. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Please see Figure 1-Figure 2 As the first embodiment of the present invention: a distributed FPGA collaborative control device based on time-sensitive network, including: a main board body 1, a distributed FPGA core 7 and a connection port 9. The front left end of the main board body 1 is provided with a set of side fixing slots 2 for maintaining the position of the main board body 1. The side fixing slots 2 are fitted together with the external device main body connection positioning end. The front cross-section of the main board body 1 is a rectangular structure, and the inner side of its four sets of external corners is provided with a set of positioning pins 3 for positioning and fitting the main board body 1. The lower end positioning pin 3 has two sets of fixing connectors 4 for support and fixed by bolts. The upper left side of the front side of the main board 1 has an upper air guide cavity 5 for maintaining airflow inside. Inside the upper air guide cavity 5 is a dust-blocking mesh to block dust from entering the air. To the right of the upper air guide cavity 5 is a control core 6 for controlling the collaborative operation of several distributed FPGA cores 7. The control core 6 is a core processor. To the right of the control core 6 are several distributed FPGA cores 7 for FPGA collaborative control. The distributed FPGA cores 7 are arranged in a linear structure and are all embedded inside the main board 1. In actual use, through… The side mounting port 2 is physically connected to the external device body to ensure that the positioning pin 3 is fully engaged with the corresponding slot in the chassis. The lower fixing connector 4 is fastened to the frame with matching bolts to complete the mechanical fixation of the motherboard body 1. Before starting, it is necessary to check whether the dustproof patch of the upper air duct 5 is clean to ensure that the heat dissipation air duct is unobstructed. After power-on, the control core 6 will automatically initialize each distributed FPGA core 7 and establish hardware-level synchronous communication through the built-in TSN (Time Sensitive Network) protocol stack. Users can load preset collaborative control algorithms through the connection port 9. The control core 6 will dynamically allocate computing tasks to the linearly arranged FPGA array and monitor the working status and clock synchronization deviation of each unit in real time.

[0018] The right side of the motherboard body 1 has several sets of internal mounting cavities for mounting distributed FPGA cores 7. The interior of each internal mounting cavity is a rectangular hollow structure. Each set of internal mounting cavities has an internal diaphragm plate at the top for external air exchange and ventilation. The internal diaphragm plate has several sets of diamond-shaped ventilation holes. At the same time, there is a cooling silicone grease coating and an insulating coating between the internal diaphragm plate and the distributed FPGA cores 7. On the left side of the middle position of the distributed FPGA cores 7, there is an internal positioning slot 8 for connecting and positioning external devices. The inner side of the internal positioning slot 8 has a sealing ring to prevent dust accumulation. On the right side of the motherboard body 1, corresponding to each set of internal mounting cavities, there is a set of rear connection ports 9 for external data expansion connections.

[0019] Please see Figure 1-Figure 5 As a second embodiment of the present invention: based on the description in Embodiment 1, the distributed FPGA core 7 further includes a distributed core body 71, a power supply module 72, an FPGA flashing control module 73, and a semiconductor heat sink 711. The lower end of the distributed core body 71 is provided with a set of load boards 701 for connecting to and supporting its operation. Each set of load boards 701 is welded and installed corresponding to a set of distributed core bodies 71. Several sets of load boards 701 are arranged in parallel. The rear right side of the load board 701 is provided with a set of power supply modules 72 for providing individual power control. The power supply module 72 includes a set of VCCINT power rails, user I / O power supplies, and an HBM power supply combination for providing power to high-bandwidth memory and analog-to-digital conversion modules. The right side of the power supply module 72 is provided with a set of FPGA flashing control modules 73 for clock generation and management.

[0020] The FPGA blinking control module 73 includes a PLL (Phase-Locked Loop), a CMT (Clock Management Unit), a timing logic control component, an LED blinking component, and an output driver module. The timing logic control component consists of a counter and flip-flops. The counter is used to measure time by accumulating clock cycles and can also program parameters to change the blinking frequency. The output driver module consists of IOBs (Programmable I / O Units) and directly drives the LED blinking component for blinking indication. It also adjusts the user I / O power supply and adapts to the power supply requirements of the LED blinking component. The right side of the FPGA blinking control module 73 has a buffer 74 for caching distributed data processing on the FPGA. The front of the buffer 74 has an external storage interface 75 for providing a connection interface 79 to an external storage device. The left side of the external storage interface 75 has a plug-in port 76 for connecting to external devices. The load board 701... On the left side, there is a set of USB expansion interfaces for external USB data expansion. In actual use, the physical connection of all load boards 701 is completed through the plug-in port 76 to ensure the electrical isolation of the parallel structure. Before powering on, the voltage matching of each power rail (VCCINT, user I / O, HBM combination) of the power supply module 72 needs to be checked. After connecting the adapter power supply through the external power plug 78, the FPGA blinking control module 73 will automatically start the PLL and CMT for clock synchronization. At this time, the LED blinking component will trigger a periodic light signal to indicate the initialization state through the counter. During operation, configuration parameters can be loaded through the USB expansion port 77. The external storage interface 75 can be connected to a high-speed memory to expand the capacity of the buffer 74. The timing logic control component will dynamically adjust the I / O power output according to the preset algorithm. At the same time, the turbine fan blades 707 and the semiconductor heat sink work together to form forced convection heat dissipation through the main air intake shell 704.

[0021] The USB expansion interface has an external power interface for connecting to external devices. The lower end of the core body 71 has a semiconductor heat sink 710 for rapid heat dissipation. The outer side of the semiconductor heat sink 710 has a main heat dissipation end plate 702 for heat conduction. The main heat dissipation end plate 702 is made of silicone grease and is located in the middle of the connection between the heating end of the semiconductor heat sink and the thermally conductive copper plate 703. The lower rear side of the main heat dissipation end plate 702 has a set of thermally conductive copper plates 703 for conducting heat from the semiconductor heat sink 710. The thermally conductive copper plate 703 has a right-angle arc structure and is in contact with the main air intake shell 704.

[0022] Please see Figure 1-Figure 5As a third embodiment of the present invention: based on the description in Embodiment 2, further, the main exhaust housing 704 has a rectangular cross-section when viewed from above. Inside the main exhaust housing 704 is a set of turbine fan blades 707 for guiding and exchanging heat from the first heat-conducting copper sheet 703 and the second heat-conducting copper sheet 709. Behind the turbine fan blades 707 is a set of air inlets 706 for introducing the heat-exchange air. To the left of the turbine fan blades 707 is a set of air outlets 705 for expelling the air after heat exchange. Both the air inlets 706 and the air outlets 705 have several sets of rectangular strip-shaped air guiding channels. The interiors of the air inlets 706 and the air outlets 705 are uniformly connected to the interiors of the turbine fan blades 707. On the upper left side of the main exhaust housing 704 is a set of second heat-conducting copper sheets 709 for conducting heat from the second semiconductor heat sink 711. The first heat-conducting copper sheet 703 and the second heat-conducting copper sheet 709 have the same specifications. The lower right front side of 709 is connected to the heating end of semiconductor heat sink 711. The thermally conductive copper sheet 703 and thermally conductive copper sheet 709 have the same specifications and are both made of metallic copper. Both thermally conductive copper sheet 703 and thermally conductive copper sheet 709 are embedded inside the main air intake shell 704 and form an integrated structure with the turbine fan blade 707. First, the silicone grease filling state of the main heat sink 702 ensures that there are no gaps between the semiconductor heat sink and the thermally conductive copper sheet. Before powering on, it is necessary to confirm that the polarity of the external power interface is matched. After starting, the semiconductor heat sink will start working immediately. At this time, the turbine fan blade 707 in the main air intake shell 704 will automatically adjust the speed according to the temperature sensor signal. During operation, heat is quickly conducted to the air duct through the right-angle arc-shaped thermally conductive copper sheet 703 / 2. The airflow generated by the turbine fan blade 707 is drawn in from the rectangular strip air inlet 706, and after heat exchange on the surface of the copper sheet, it is discharged from the air outlet 705, forming a closed-loop heat dissipation path.

[0023] Please see Figure 6As a fourth embodiment of the present invention, the distributed FPGA core 7 also includes a Time-Sensitive Network (TSN) module. The TSN, as a core extension of the IEEE 802.1 standard family, achieves deterministic latency transmission through three mechanisms: time synchronization, traffic scheduling, and resource management. Its core protocols include the IEEE 802.1AS-Rev time synchronization protocol, the IEEE 802.1Qbv time-aware shaping protocol, and the IEEE 802.1CB frame duplication elimination protocol. The distributed FPGA core 7 achieves collaborative control and computation through a heterogeneous architecture of a hard-core processor system (HPS) and programmable logic (PL). This includes Xilinx Zynq UltraScale+ MPSoC series devices integrating a quad-core ARM Cortex-A53 processing system and programmable logic units, supporting hardware acceleration modules with nanosecond-level response at the PL end, using the AXI-Stream interface for high-speed data stream transmission, constructing a data path from the physical layer to the application layer through a DMA controller, and utilizing partial reconfiguration technology to dynamically load hardware modules.

[0024] The inner mounting cavity of the mainboard 1 carries multiple distributed FPGA cores 7 through a rectangular hollow structure. Its parallel load board 701 layout provides the physical basis for TSN time-sensitive transmission. The turbine fan blades 707 embedded in the main exhaust shell 704 maintain the stable operation of semiconductor heat sink 710 and semiconductor heat sink 711, ensuring that the FPGA core maintains sub-microsecond clock accuracy when implementing the IEEE 802.1AS-Rev synchronization protocol. The diamond-shaped ventilation holes of the inner partition plate, combined with the cooling silicone grease coating, enable multiple Kintex-7 FPGAs to keep the core temperature within ±2℃ under 20% load fluctuation, meeting the heat dissipation requirements of 1μs clock deviation in TSN switch interconnection scenarios. The heat conduction path is formed by the thermal conductive copper sheet 703 and the thermal conductive copper sheet 709 and the heat sink end plate. The control core 6, protected by a sealed ring on the inner positioning port 8, drives the quad-core ARM Cortex-A53 processing system to perform global scheduling. The power supply module 72 of the distributed FPGA core 7 uses an HBM power supply combination to provide 3.2Gbps data transmission bandwidth for the external storage interface 75. It connects to the buffer 74 via an AXI-Stream interface to achieve hardware-level filtering for the preprocessing module. The PLL unit of the FPGA blink control module 73 directly drives the timing logic control component. Its programmable counter, under the IEEE 802.1Qbv scheduling mechanism of TSN, compresses the LED blinking frequency error to ±0.05%. Simultaneously, the USB expansion port 77, in conjunction with the DMA controller, constructs a data path between the physical layer and the application layer. In actual use, the physical connection of each module is completed through the AXI-Stream interface, ensuring the smooth operation of the data path constructed by the DMA controller. Upon startup, the quad-core ARM Cortex-A53 processing system automatically synchronizes the clocks of each node via the IEEE 802.1AS-Rev protocol. The hardware acceleration module on the PL end is dynamically loaded according to TSN requirements. During device operation, IEEE... The 802.1Qbv protocol schedules the PLL unit of the FPGA blink control module 73, whose programmable counter precisely adjusts the LED indicator signal. Simultaneously, the HBM power supply continuously provides stable bandwidth to the external storage interface 75, while the turbine fan blades 707, along with the semiconductor heatsink, maintain stable chip temperature. When network parameters need adjustment, the hardware module can be updated online via the USB expansion port 77 using partial reconfiguration technology. Through a heterogeneous computing architecture (ARM processor + FPGA), it achieves coordinated optimization of control and computation, enabling the execution of complex scheduling algorithms and providing nanosecond-level hardware acceleration response, while integrating IEEE 802.1... The TSN protocol stack (including time synchronization, traffic shaping, and frame duplication elimination mechanisms) ensures sub-microsecond clock accuracy and deterministic latency in network transmission, meeting the real-time requirements of industrial automation and other scenarios. It guarantees long-term stable operation under high loads. The high-speed data path built with the AXI-Stream interface and DMA controller, combined with HBM power supply and partial reconfiguration technology, meets the dynamic update capabilities of different data transmission bandwidths and hardware modules. The modular design, through parallel load boards 701 and standardized interfaces, expands the system scale and simplifies the maintenance process. The overall solution performs excellently in terms of real-time performance, reliability, and scalability.

[0025] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A distributed FPGA collaborative control device based on time-sensitive networking, comprising: The motherboard body (1) has an FPGA core (7) and a connection port (9). The front left side of the motherboard body (1) has a set of side positioning slots (2) for maintaining the position of the motherboard body (1). The side positioning slots (2) are fitted together with the external device body connection positioning end. The front cross-section of the motherboard body (1) is a rectangular structure. The four sets of external corners are respectively provided with a set of positioning pins (3) for positioning and fitting the motherboard body (1). The lower end of the positioning pin (3) is provided with two sets of fixing connectors (4) for supporting it and fixed by bolts. The upper left end of the front side of the main body (1) is provided with an upper air guide cavity (5) for keeping the air inside it circulating. The upper air guide cavity (5) is provided with a set of dustproof patch mesh for blocking dust inside the air. The upper air guide cavity (5) is provided with a set of control cores (6) for controlling the collaborative operation of several sets of distributed FPGA cores (7) on the right side. The control core (6) is a core processor. The control core (6) is provided with several sets of distributed FPGA cores (7) for FPGA collaborative control on the right side. The distributed FPGA cores (7) are arranged in a straight line and are all embedded in the main body (1).

2. The distributed FPGA collaborative control device based on time-sensitive network according to claim 1, characterized in that: The motherboard body (1) has several sets of internal mounting cavities on the right side for placing distributed FPGA cores (7) for corresponding installation. The internal mounting cavity has a rectangular hollow structure. Each set of internal mounting cavities has an internal diaphragm plate at the top for allowing external air to circulate. The internal diaphragm plate has several sets of rhomboid ventilation holes. At the same time, the internal diaphragm plate and the distributed FPGA cores (7) are provided with a cooling silicone grease coating and an insulating coating. The middle left side of the distributed FPGA cores (7) has an internal positioning slot (8) for connecting and positioning external devices. The inner side of the internal positioning slot (8) has a sealing ring for preventing dust accumulation. The right side of the motherboard body (1) has a set of rear connection ports (9) for external data expansion connections in each set of internal mounting cavities.

3. The distributed FPGA collaborative control device based on time-sensitive network according to claim 2, characterized in that: The distributed FPGA core (7) includes a distributed core body (71), a power supply module (72), an FPGA flashing control module (73), and a semiconductor heat sink (711). The lower end of the distributed core body (71) is provided with a set of load boards (701) for connection and operation. Each set of load boards (701) corresponds to a set of distributed core bodies (71) for welding and installation. Several sets of load boards (701) are arranged in parallel. The rear right side of the load board (701) is provided with a set of power supply modules (72) for providing individual power control. The power supply module (72) includes a set of VCCINT power rails, user I / O power supply, and HBM power supply combination for providing power to high bandwidth memory and analog-to-digital conversion modules. The right side of the power supply module (72) is provided with a set of FPGA flashing control modules (73) for clock generation and management.

4. A distributed FPGA collaborative control device based on a time-sensitive network according to claim 3, characterized in that: The FPGA blinking control module (73) includes a PLL (phase-locked loop), a CMT (clock management unit), a timing logic control component, an LED blinking component, and an output driver module. The timing logic control component consists of a counter and a trigger. The counter is used to measure time by accumulating clock cycles and can also program parameters to change the blinking frequency. The output driver module consists of an IOB (programmable I / O unit) and directly drives the LED blinking component to blink. It also adjusts the user I / O power supply and adapts to the power supply requirements of the LED blinking component. The FPGA blinking control module (73) has a set of buffers (74) on the right side for caching distributed data processing on the FPGA. The buffers (74) have a set of external storage interfaces (75) on the front side for providing a connection interface (79) with external storage devices. The external storage interfaces (75) have a set of plug-in ports (76) on the left side for connecting with external devices. The load board (701) has a set of USB expansion interfaces on the left side for external USB data expansion.

5. A distributed FPGA collaborative control device based on a time-sensitive network according to claim 4, characterized in that: The USB expansion interface is provided with a set of external power interfaces for connecting to external devices. The lower end of the distribution core body (71) is provided with a set of semiconductor heat sinks (710) for rapid heat dissipation. The outer side of the semiconductor heat sink (710) is provided with a set of main heat dissipation end plates (702) for providing heat conduction. The main heat dissipation end plates (702) are made of silicone grease material and are located in the middle of the connection between the heating end of the semiconductor heat sink and the thermally conductive copper plate (703). The lower rear side of the main heat dissipation end plate (702) is provided with a set of thermally conductive copper plates (703) for conducting heat from the semiconductor heat sink (710). The thermally conductive copper plate (703) is a right-angle arc structure and is in contact with the main air intake shell (704).

6. A distributed FPGA collaborative control device based on a time-sensitive network according to claim 5, characterized in that: The main air intake casing (704) has a rectangular cross-section when viewed from above. Inside the main air intake casing (704) is a set of turbine fan blades (707) for guiding and exchanging heat between the first heat-conducting copper plate (703) and the second heat-conducting copper plate (709). A set of air inlets (706) for introducing heat-exchange air is provided on the rear side of the turbine fan blades (707), and a set of air outlets (705) for expelling the heat-exchange air is provided on the left side of the turbine fan blades (707). Both the air inlets (706) and the air outlets (705) are provided with several sets of rectangular strip-shaped air guiding channels. The interiors of the air inlets (706) and the air outlets (705) are uniformly integrated with the turbine fan blades. (707) The interior is interconnected. The upper left side of the main air intake shell (704) is provided with a set of thermally conductive copper sheets (709) for conducting heat from the semiconductor heat sink (711). The thermally conductive copper sheet (703) and the thermally conductive copper sheet (709) have the same specifications. The lower right front side of the thermally conductive copper sheet (709) is connected to the heating end of the semiconductor heat sink (711). The thermally conductive copper sheet (703) and the thermally conductive copper sheet (709) have the same specifications and are both made of metallic copper. The thermally conductive copper sheet (703) and the thermally conductive copper sheet (709) are both embedded inside the main air intake shell (704) and form an integrated structure with the turbine fan blade (707).

7. A distributed FPGA collaborative control device based on time-sensitive networks according to claim 3, characterized in that: The distributed FPGA core (7) also includes a Time-Sensitive Network (TSN) module. As a core extension of the IEEE 802.1 standard family, the TSN module achieves deterministic delay transmission through three major mechanisms: time synchronization, traffic scheduling, and resource management. The core protocols include the IEEE 802.1AS-Rev time synchronization protocol, the IEEE 802.1Qbv time-aware shaping protocol, and the IEEE 802.1CB frame duplication elimination protocol. The distributed FPGA core (7) achieves coordination of control and computation through the heterogeneous architecture of the hard processor system (HPS) and programmable logic (PL). This includes the Xilinx Zynq UltraScale+MPSoC series devices integrating a quad-core ARM Cortex-A53 processing system and programmable logic units, supporting hardware acceleration modules with nanosecond-level response at the PL end, using the AXI-Stream interface to achieve high-speed data stream transmission, constructing a data path from the physical layer to the application layer through a DMA controller, and using partial reconfiguration technology to achieve dynamic loading of hardware modules.

8. A distributed FPGA collaborative control device based on a time-sensitive network according to claim 2, characterized in that: The inner mounting cavity of the main board (1) carries multiple distributed FPGA cores (7) through a rectangular hollow structure. Its parallel load board (701) layout provides a physical basis for the time-sensitive transmission of TSN. The turbine fan blades (707) embedded in the main exhaust shell (704) maintain the stable operation of semiconductor heat sink one (710) and semiconductor heat sink two (711), ensuring that the FPGA core maintains sub-microsecond clock accuracy when implementing the IEEE 802.1AS-Rev synchronization protocol. The diamond-shaped ventilation holes of the inner partition plate, combined with the cooling silicone grease coating, enable multiple Kintex-7 FPGAs to keep the core temperature within ±2℃ under 20% load fluctuation, meeting the heat dissipation requirements of 1μs clock deviation in the TSN switch interconnection scenario. The heat conduction path is formed by the heat conduction copper sheet one (703) and the heat conduction copper sheet two (709) and the heat dissipation end plate. The control core (6) is protected by the sealing ring of the inner positioning socket (8) and drives the quad-core ARM Cortex-A53 processing system to perform global scheduling. The power supply module (72) of the distributed FPGA core (7) adopts the HBM power supply combination to provide 3.2Gbps data transmission bandwidth for the external storage interface (75) and connects to the buffer (74) through the AXI-Stream interface to realize hardware-level filtering of the preprocessing module. The PLL unit of the FPGA blink control module (73) directly drives the timing logic control component. Its programmable counter compresses the LED blinking frequency error to ±0.05% under the IEEE 802.1Qbv scheduling mechanism of TSN. At the same time, the USB expansion port (77) cooperates with the DMA controller to build a data path between the physical layer and the application layer.

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