Infrared image data correction method and device and storage medium

Abstract

The invention discloses an infrared image data correction method and device and a storage medium, and the method comprises the steps: carrying out the blind pixel correction of infrared image data when a field programmable gate array receives the infrared image data collected by an infrared detector; writing the multi-frame infrared image data into a memory through a PCIe interface, and transmitting a first interrupt signal to a system-on-chip through the PCIe interface; the system-on-chip reads the multi-frame infrared image data from the memory, calculates a first correction matrix of two-point correction according to the multi-frame infrared image data, writes the first correction matrix into the memory, and transmits a second interrupt signal to the field programmable gate array through the PCIe interface; and the field programmable gate array reads the first correction matrix from the memory through the PCIe interface, and performs two-point correction on the infrared image data according to the first correction matrix. According to the embodiment, the delay is low, the development difficulty of the correction algorithm is reduced, the cost is low, and the development period is short.

Description

Technical Field

[0001] This invention relates to the field of industrial control technology, and in particular to a method, device and storage medium for correcting infrared image data. Background Technology

[0002] Infrared detectors can acquire information such as surface thermal radiation and internal heat dissipation of objects to provide thermal images of the target object and background, thus becoming a means for people to observe and perceive the objective world, and have wide applications in security and other scenarios.

[0003] Currently, FPGAs (Field Programmable Gate Arrays) are often deployed in industrial control equipment to control the equipment. Therefore, FPGAs are responsible for correcting infrared images.

[0004] However, FPGA design is geared towards the low level of hardware, and the hardware description language has a low level of abstraction. It describes the structure and behavior of hardware circuits, while infrared image correction is an algorithmic process with high accuracy requirements and a complex design process. This makes the debugging and analysis process of FPGA for infrared image correction difficult and inefficient. Summary of the Invention

[0005] In view of this, the present invention provides a method, device and storage medium for correcting infrared image data, so as to improve the efficiency of correcting infrared image data.

[0006] A first aspect of the present invention provides a method for correcting infrared image data, wherein a field-programmable gate array (FPGA) is configured with a PCIe interface of conformal block design, a system-on-a-chip (SoC) is connected to the PCIe interface, and the SoC is configured with memory; the method includes:

[0007] When the field-programmable gate array receives infrared image data collected by the infrared detector, it performs blind element correction on the infrared image data;

[0008] When the field-programmable gate array completes blind element correction, it writes multiple frames of infrared image data into the memory through the PCIe interface and transmits a first interrupt signal to the system-on-a-chip through the PCIe interface.

[0009] In response to the first interrupt signal, the system-on-a-chip reads multiple frames of infrared image data from the memory, calculates a first correction matrix for two-point correction based on the multiple frames of infrared image data, writes the first correction matrix into the memory, and transmits a second interrupt signal to the field-programmable gate array through the PCIe interface.

[0010] In response to the second interrupt signal, the field-programmable gate array reads the first correction matrix from the memory through the PCIe interface and performs two-point correction on the infrared image data based on the first correction matrix.

[0011] A second aspect of the present invention provides an infrared image data correction device, the device comprising a field-programmable gate array (FPGA) and a system-on-a-chip (SoC), wherein the FPGA is configured with a block-designed PCIe interface, the SoC is connected to the PCIe interface, and the SoC is configured with memory.

[0012] The field-programmable gate array is used to perform blind element correction on the infrared image data when it receives infrared image data acquired by the infrared detector;

[0013] The field-programmable gate array is also used to write multiple frames of infrared image data into the memory through the PCIe interface when blind pixel correction is completed, and to transmit a first interrupt signal to the system-on-a-chip through the PCIe interface.

[0014] The system-on-a-chip is configured to, in response to the first interrupt signal, read multiple frames of infrared image data from the memory, calculate a first correction matrix for two-point correction based on the multiple frames of infrared image data, write the first correction matrix into the memory, and transmit a second interrupt signal to the field programmable gate array through the PCIe interface.

[0015] The field-programmable gate array is also configured to, in response to the second interrupt signal, read the first correction matrix from the memory through the PCIe interface, and perform two-point correction on the infrared image data based on the first correction matrix.

[0016] A third aspect of the present invention provides an electronic device, the electronic device comprising:

[0017] At least one processor; and

[0018] A memory communicatively connected to the at least one processor; wherein,

[0019] The memory stores a computer program that can be executed by the at least one processor to enable the at least one processor to perform the infrared image data correction method as described in the first aspect above.

[0020] A fourth aspect of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the infrared image data correction method as described in the first aspect above.

[0021] A fifth aspect of the present invention provides a computer program product comprising a computer program that, when executed by a processor, implements the infrared image data correction method as described in the first aspect above.

[0022] In this embodiment, when the field-programmable gate array (FPGA) receives infrared image data acquired by the infrared detector, it performs blind pixel correction on the infrared image data. Upon completion of blind pixel correction, it writes multiple frames of infrared image data into memory via the PCIe interface and transmits a first interrupt signal to the system-on-a-chip (SoC) via the PCIe interface. In response to the first interrupt signal, the SoC reads multiple frames of infrared image data from memory, calculates a first correction matrix for two-point correction based on the multiple frames of infrared image data, writes the first correction matrix into memory, and transmits a second interrupt signal to the FPGA via the PCIe interface. In response to the second interrupt signal, the FPGA reads the first correction matrix from memory via the PCIe interface and performs two-point correction on the infrared image data based on the first correction matrix. In this embodiment, all corrections are calculated in real time, and the output of infrared image data can be achieved without delay. The low latency of PCIe interface communication ensures low latency throughout the correction process. The correction parameter calculation involves multiple reads and writes with a large amount of data. The SoC's memory read and write operations are simple, and the flexibility of SoC-based development greatly reduces the difficulty of developing correction algorithms. The connection between FPGA and SoC is simple, requiring minimal modification to the FPGA, resulting in low hardware costs, maintaining system stability, and the SoC's wide range of applications and mature technology, which reduces the difficulty of software and hardware development and shortens the development cycle.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart of an infrared image data correction method provided in Embodiment 1 of the present invention.

[0026] Figure 2 This is a schematic diagram of the interaction between an FPGA and a SoC provided in Embodiment 1 of the present invention.

[0027] Figure 3This is an example diagram of storing infrared image data for two-point correction provided in Embodiment 1 of the present invention.

[0028] Figure 4 This is a flowchart of an infrared image data correction method provided in Embodiment 2 of the present invention.

[0029] Figure 5 This is an example diagram of storing infrared image data for single-point correction, provided in Embodiment 2 of the present invention.

[0030] Figure 6 This is a flowchart of FPGA parameter reading provided in Embodiment 2 of the present invention.

[0031] Figure 7 This is a schematic diagram of the structure of an infrared image data correction device provided in Embodiment 3 of the present invention.

[0032] Figure 8 This is a schematic diagram of the structure of an electronic device provided in Embodiment 4 of the present invention. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be used interchangeably where appropriate so that the embodiments of the invention described herein can cover implementations in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] Example 1

[0036] See Figure 1The diagram shows a flowchart of an infrared image data correction method provided in Embodiment 1 of the present invention. This embodiment is applicable to the case where FPGA is equipped with SoC (System on Chip) to process infrared image data. The method can be executed by an infrared image data correction device, which can be implemented in hardware and / or software and can be configured in an electronic device.

[0037] like Figure 2 As shown, the electronic device includes a field-programmable gate array (FPGA) and a system-on-a-chip (SoC).

[0038] Among them, the field-programmable gate array (FPGA) is configured with a block-design compliant PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard) interface, which can convert the PCIe interface into a standard AXI (Advanced eXtensible Interface) interface, reducing the development difficulty of the FPGA, improving the ease of operation of the FPGA, and effectively shortening the development time.

[0039] The performance of a System-on-a-Chip (SoC) is stronger than that of a Field-Programmable Gate Array (FPGA). It has powerful video encoding and decoding capabilities, self-developed Image Signal Processing (ISP), and Artificial Intelligence (AI) functions. In addition to assisting the FPGA in preprocessing infrared image data, it can also provide other functions, which can facilitate subsequent development.

[0040] Taking the RK3588 as an example, the RK3588 uses an 8nm process and integrates a quad-core Cortex-A76 and a quad-core Cortex-A55 architecture. It is also equipped with a Mali-G610 GPU (graphics processor) and an NPU (neural processing unit), which has powerful computing and graphics processing capabilities and supports 8K video encoding and decoding.

[0041] The system-on-a-chip (SoC) is connected to the PCIe interface, allowing the SoC to directly call the PCIe interface. The SoC is equipped with external memory (such as DDR4). The external memory of the SoC has the characteristics of large capacity and fast read and write speed, which facilitates the implementation of algorithms for processing infrared image data (such as two-point correction and single-point correction).

[0042] The PCIe interface consists of two parts: a high-speed (AXI) interface and a low-speed (AXI-LITE) interface. The high-speed interface is used to transmit large amounts of data (i.e., infrared image data), while the low-speed interface is used to transmit configuration information (such as thresholds) and control commands (such as interrupt signals). The FPGA or SoC responds to configuration information and control commands in real time.

[0043] In addition, the system-on-a-chip (SoC) includes multiple GPIO (General-purpose input / output) interfaces for directly transmitting and receiving interrupt signals. At the same time, PCIe can also support the transmission of interrupt signals. The FPGA and SoC work together to perform different preprocessing of infrared image data based on different interfaces or interrupt signals.

[0044] like Figure 1 As shown, the method includes:

[0045] Step 101: When the field programmable gate array receives infrared image data collected by the infrared detector, it performs blind element correction on the infrared image data.

[0046] like Figure 2 As shown, the FPGA can be connected to the infrared detector via wired or wireless means. The infrared detector is deployed in the factory's production workshop and other locations according to business requirements, continuously collecting infrared image data from the target object, and continuously transmitting the infrared image data to the FPGA.

[0047] Due to defects in manufacturing processes and materials, infrared detectors may experience complete or severe failure of array elements, causing their response to infrared radiation to deviate significantly from the normal value. Therefore, when the FPGA receives infrared image data collected by the infrared detector, it can perform blind element correction on the infrared image data, that is, detect blind elements and correct blind elements.

[0048] In the specific implementation, each infrared detector is configured with a variety of different information. The configuration information is stored in the SoC, that is, all information that may need to be changed is stored in the SoC. The FPGA does not make any modifications. The system-on-a-chip reads the blind element correction threshold from the configuration information of each infrared detector and transmits the threshold to the field programmable gate array through the PCIe interface.

[0049] Generally, the average grayscale value of each pixel in an infrared image data frame is calculated, and the threshold is determined based on the average value. For example, if the bit width of the infrared image data output by the infrared detector is 14 bits and the full scale is 16383, then one-tenth of the maximum value can be set as the threshold. The threshold is configured after the electronic device is powered on, and the threshold can be modified in the middle or written directly, and the FPGA reads it in real time.

[0050] In the FPGA, the average gray value of each pixel in the infrared image data is calculated to obtain the baseline value. Then, each pixel in the infrared image data is traversed, and the absolute value of the difference between the gray value of the current pixel and the baseline value is taken to obtain the gray value deviation value. The gray value deviation value of the current pixel is compared with the threshold. When the gray value deviation value is greater than or equal to the threshold, the pixel is determined to be a blind pixel, and the blind pixel is then filtered.

[0051] Let I in(x,y) θ represents the grayscale value of pixel (x,y) in the infrared image data, M represents the total number of rows in the infrared image data, N represents the total number of columns in the infrared image data, and θ represents the threshold.

[0052] Therefore, the baseline value is: The criteria for determining blind cells are: |I in(x,y) -μ∣≥θ.

[0053] Taking mean filtering as an example of filtering processing, mean filtering is an image spatial domain filtering technique that suppresses noise or smooths details by averaging local pixels.

[0054] Specifically, for a blind pixel in infrared image data, the arithmetic mean of the gray values ​​of all pixels in its neighborhood window is taken as the output value, replacing the gray value of the blind pixel itself.

[0055] Let I in(x,y) Let N be the grayscale value of the blind pixel (x,y) in the infrared image data, N be the number of pixels in the window, (2k+1)×(2k+1) be the size of the window, and I be the grayscale value of the blind pixel (x,y). in(x+i,y+j) This represents the grayscale value of other pixels surrounding the blind pixel.

[0056] Therefore, the output value of the mean filter is:

[0057] For example, using a 3x3 window, the FPGA internally calls three RAMs (Random Access Memory) with a depth of 2048 and a bit width of 16 bits according to the resolution of the infrared image data. The output infrared image data is sequentially written into the three RAMs for buffering. When the third line of infrared image data is input, the first two lines of infrared image data are read out at the same time. The gray values ​​of three adjacent pixels are buffered in the register, and the average value is calculated after summing. The average value is used to replace the gray value of the blind pixel coordinates according to the coordinates of the blind pixel.

[0058] Step 102: When the field-programmable gate array completes blind element correction, it writes multiple frames of infrared image data into memory through the PCIe interface and transmits the first interrupt signal to the system-on-a-chip through the PCIe interface.

[0059] Infrared detectors are composed of a large number of photosensitive units (pixels). Due to manufacturing limitations, even under the same temperature and lighting conditions, the output signals of each pixel will differ (manifested as some pixels being brighter and others being darker). This phenomenon is called non-uniformity. Non-uniformity can cause noise such as fixed stripes and spots in infrared image data, affecting the accuracy of temperature measurement and visual effect.

[0060] Therefore, as Figure 2 As shown, during blind pixel correction, the FPGA and SoC work together to correct the infrared image data, improving the uniformity and accuracy of the infrared image.

[0061] One type of correction is two-point correction, which involves acquiring infrared image data from two reference points at different temperatures (such as a low-temperature blackbody and a high-temperature blackbody) and calculating the reference slope (gain, i.e., response factor) and offset (i.e. intercept factor) of each pixel to eliminate non-uniformity between pixels (mainly to solve the problem of inconsistent gain).

[0062] Specifically, such as Figure 3 As shown, during the two-point calibration process, the surface temperature of the blackbody can be adjusted. The FPGA acquires multiple frames (usually 10 frames) of low-temperature infrared image data and multiple frames (usually 10 frames) of high-temperature infrared image data respectively. Using DMA (Direct Memory Access) technology, all infrared image data used for two-point calibration is directly written into the memory of the SoC through the PCIe interface.

[0063] Based on the BlockDesign design, the FPGA and SoC can pre-agree on the memory allocation for storing the infrared image data in the two-point correction, as well as the interrupt signal (i.e., the first interrupt signal) for calculating the first correction matrix of the two-point correction.

[0064] To accommodate the calibration requirements of infrared image data at different resolutions and to ensure 4K alignment of storage space, the SoC sets the first address allocated in its memory for storing infrared image data in two-point calibration to 4096*2048*16bit. This can be achieved by making a single code modification for infrared image data of different resolutions, making it easy to port to different projects.

[0065] Therefore, the FPGA can query the SoC's memory locally to find the first address allocated for storing infrared image data in two-point correction, and write multiple frames of infrared image data into the first address of the SoC's memory through the PCIe interface.

[0066] When all infrared image data buffered for two-point correction is complete, the first interrupt signal is transmitted to the SoC via the PCIe interface.

[0067] Step 103: In response to the first interrupt signal, the system-on-a-chip reads multiple frames of infrared image data from memory, calculates the first correction matrix for two-point correction based on the multiple frames of infrared image data, writes the first correction matrix into memory, and transmits the second interrupt signal to the field programmable gate array through the PCIe interface.

[0068] like Figure 2 As shown, when the SoC receives the first interrupt signal, it can read the multi-frame infrared image data cached by the FPGA for two-point correction from the memory.

[0069] like Figure 3 As shown, in a specific implementation, the SoC can query the first address allocated in its memory for storing infrared image data in two-point calibration, and read multiple frames of infrared image data from the first address in its memory.

[0070] Since the infrared image data is directly written from the FPGA to the SoC's external memory, the FPGA does not cache the infrared image data in its memory. The output has no delay or the delay can be calculated. After writing, an interrupt is sent to notify the SoC to read the infrared image data for processing, which reduces the SoC's resource consumption and reduces the SoC's processing time. This is because if the SoC receives the infrared image data first and stores it in its memory, there is a minimum delay of one frame, and the delay is not easy to calculate accurately.

[0071] Furthermore, FPGAs are equipped with multiple interfaces to output infrared image data, so the infrared image data is mainly calibrated in the FPGA, which facilitates the connection to subsequent outputs and reduces modification costs. In contrast, SoCs do not have these interfaces, and if the connection to the operation is to be achieved, it will cause great damage to the hardware, which is not only costly but also easily brings uncertain risks to the entire system.

[0072] like Figure 2 As shown, when the SoC reads multiple frames of infrared image data, it can calculate the first correction matrix for two-point correction based on the multiple frames of infrared image data. The first correction matrix includes a response rate factor and an intercept factor.

[0073] In the specific implementation, let I... in(x,y) I represents the grayscale value of pixel (x,y) in the input infrared image data. out(x,y) I represents the grayscale value of pixel (x,y) in the output infrared image data. H For high-temperature infrared image data, I L For low-temperature infrared image data, The average value of infrared image data at high temperature, These are the average values ​​of infrared image data at low temperatures. The average value of all pixels in high-temperature infrared image data. K is the average value of all pixels in low-temperature infrared image data. (x,y) B is the response rate factor. (x,y) is the intercept factor.

[0074] Therefore, the function for two-point correction is: I out(x,y) =K (x,y) ×I in(x,y) +B (x,y) .

[0075] n is the number of high-temperature infrared image data, I Hi For the infrared image data of the i-th frame at high temperature, I Li This is the low-temperature infrared image data of the i-th frame.

[0076] for The grayscale value of the middle pixel (x, y). for The grayscale value of a pixel (x, y), where M is the number of rows and N is the number of columns.

[0077] Will Substitute the two-point correction function:

[0078] Will Substitute the two-point correction function:

[0079] Solving for:

[0080] Furthermore, the high-temperature and low-temperature infrared image data of the SoC are processed in the same way: each row of pixels in multiple frames of infrared image data is read sequentially, and the average value of each pixel in each row is calculated to obtain the average frame rate of all pixels. The data is stored in memory, and the sum of all pixels is calculated. This sum is then divided by the total number of pixels in the multi-frame infrared image data (n*M*N, where n is the number of infrared image data points) to obtain the average number of pixels across the multi-frame infrared image data.

[0081] Based on the calculation of the response rate factor K (x,y) The formula first calculates the difference between the average value of high temperature and the average value of low temperature, caches it in an internal register, and then reads the average frames of high temperature and low temperature sequentially from memory, calculates the difference between the average frames, and stores it in memory.

[0082] The system sequentially reads the difference between average frames from memory, divides the difference between average frames by the difference between average frames to calculate the response rate factor, and writes the response rate factor into its memory.

[0083] Based on the calculation of the intercept factor B (x,y) The formula, while simultaneously reading the response rate factor results and the average frame rate at high temperatures from memory. Calculate the product between the two, and subtract the product from the average temperature of the internal register cache to calculate the intercept factor.

[0084] When the SoC completes the calculation of the first correction matrix for two-point correction, it can write the first correction matrix into its memory.

[0085] Based on the BlockDesign design, the FPGA and SoC can pre-agree on the memory allocation of the second address (response rate factor has an independent second address, intercept factor has an independent second address) for storing the first correction matrix in the two-point correction, as well as the interrupt signal for performing the two-point correction (i.e., the second interrupt signal).

[0086] Then, the SoC can query its memory locally for the second address allocated to store the first correction matrix in the two-point correction, and write the first correction matrix into the second address in its memory.

[0087] When the first correction matrix buffer used for two-point correction is completed, the SoC transmits a second interrupt signal to the FPGA via the PCIe interface.

[0088] Step 104: In response to the second interrupt signal, the field-programmable gate array reads the first correction matrix from memory through the PCIe interface and performs two-point correction on the infrared image data based on the first correction matrix.

[0089] like Figure 2 As shown, when the FPGA receives the second interrupt signal, it can use DMA technology to read the first correction matrix from the SoC's memory through the PCIe interface.

[0090] Based on the BlockDesign design, the FPGA and SoC can pre-agree on the memory to be allocated as the second address for storing the first correction matrix in the two-point correction.

[0091] Therefore, the FPGA can query the SoC's memory locally for the second address allocated to store the first correction matrix in the two-point correction, and read the first correction matrix from the second address in the SoC's memory through the PCIe interface.

[0092] When the FPGA acquires the first correction matrix, it can perform two-point correction on the infrared image data based on the first correction matrix.

[0093] Furthermore, the first correction matrix includes a response rate factor and an intercept factor. Then, the FPGA can add the intercept factor to the product between the infrared image data and the response rate factor to obtain new infrared image data, thus completing the two-point correction.

[0094] In this embodiment, when the field-programmable gate array (FPGA) receives infrared image data acquired by the infrared detector, it performs blind pixel correction on the infrared image data. Upon completion of blind pixel correction, it writes multiple frames of infrared image data into memory via the PCIe interface and transmits a first interrupt signal to the system-on-a-chip (SoC) via the PCIe interface. In response to the first interrupt signal, the SoC reads multiple frames of infrared image data from memory, calculates a first correction matrix for two-point correction based on the multiple frames of infrared image data, writes the first correction matrix into memory, and transmits a second interrupt signal to the FPGA via the PCIe interface. In response to the second interrupt signal, the FPGA reads the first correction matrix from memory via the PCIe interface and performs two-point correction on the infrared image data based on the first correction matrix. In this embodiment, all corrections are calculated in real time, and the output of infrared image data can be achieved without delay. The low latency of PCIe interface communication ensures low latency throughout the correction process. The correction parameter calculation involves multiple reads and writes with a large amount of data. The SoC's memory read and write operations are simple, and the flexibility of SoC-based development greatly reduces the difficulty of developing correction algorithms. The connection between FPGA and SoC is simple, requiring minimal modification to the FPGA, resulting in low hardware costs, maintaining system stability, and the SoC's wide range of applications and mature technology, which reduces the difficulty of software and hardware development and shortens the development cycle.

[0095] Example 2

[0096] See Figure 4 The diagram illustrates a flowchart of an infrared image data correction method provided in Embodiment 2 of the present invention. This embodiment adds single-point correction and histogram equalization to the aforementioned embodiments. Figure 4 As shown, the method includes:

[0097] Step 401: When the field programmable gate array receives infrared image data collected by the infrared detector, it performs blind element correction on the infrared image data.

[0098] Step 402: When the field-programmable gate array completes blind element correction, it writes multiple frames of infrared image data into memory through the PCIe interface and transmits the first interrupt signal to the system-on-a-chip through the PCIe interface.

[0099] Step 403: In response to the first interrupt signal, the system-on-a-chip reads multiple frames of infrared image data from memory, calculates the first correction matrix for two-point correction based on the multiple frames of infrared image data, writes the first correction matrix into memory, and transmits the second interrupt signal to the field programmable gate array through the PCIe interface.

[0100] Step 404: In response to the second interrupt signal, the field-programmable gate array reads the first correction matrix from memory through the PCIe interface and performs two-point correction on the infrared image data based on the first correction matrix.

[0101] Step 405: When the field-programmable gate array completes the two-point calibration, it writes multiple frames of infrared image data into memory through the PCIe interface and transmits the third interrupt signal to the system-on-a-chip through the PCIe interface.

[0102] like Figure 2 As shown, in the correction of infrared image data, two-point correction establishes the basic model of pixel response and determines the reference slope and offset of pixel response. Single-point correction supplements and corrects the offset based on the current environment (such as equipment temperature changes and instantaneous noise) without affecting the determined gain characteristics, ensuring that the correction is more in line with the real-time scene.

[0103] When the FPGA completes the two-point calibration, it closes the shutter every certain time interval (e.g., 10 seconds). When the shutter is closed, the device acquires multiple frames (usually 10 frames) of infrared image data and uses DMA technology to write the multiple frames of infrared image data directly into the SoC's memory through the PCIe interface.

[0104] Based on the BlockDesign design, the FPGA and SoC can pre-agree on the memory allocation for storing the infrared image data in single-point correction, as well as the interrupt signal (i.e., the third interrupt signal) for calculating the second correction matrix of single-point correction.

[0105] To accommodate the calibration requirements of infrared image data at different resolutions and to ensure 4K alignment of storage space, the SoC allocates a third address of 4096*2048*16bit in its memory for storing infrared image data in single-point calibration. This can be achieved by making a single code modification for infrared image data of different resolutions, making it easy to port to different projects.

[0106] So, if Figure 5 As shown, the FPGA can locally query the SoC's memory to allocate the third address for storing infrared image data in single-point correction, and write multiple frames of infrared image data into the SoC's memory at the third address via the PCIe interface.

[0107] When all infrared image data buffered for single-point correction is complete, a third interrupt signal is transmitted to the SoC via the PCIe interface.

[0108] Step 406: In response to the third interrupt signal, the system-on-a-chip reads multiple frames of infrared image data from memory, calculates the second correction matrix for single-point correction based on the multiple frames of infrared image data, writes the second correction matrix into memory, and transmits the fourth interrupt signal to the field programmable gate array through the PCIe interface.

[0109] like Figure 2 As shown, when the SoC receives the third interrupt signal, it can read the multi-frame infrared image data cached by the FPGA for single-point correction from the memory.

[0110] In specific implementations, such as Figure 5 As shown, the SoC can locally query the third address allocated by its memory for storing infrared image data in single-point calibration, and read multiple frames of infrared image data from the third address in its memory.

[0111] Since the infrared image data is directly written from the FPGA to the SoC's external memory, the FPGA does not cache the infrared image data in its memory. The output has no delay or the delay can be calculated. After writing, an interrupt is sent to notify the SoC to read the infrared image data for processing, which reduces the SoC's resource consumption and reduces the SoC's processing time. This is because if the SoC receives the infrared image data first and stores it in its memory, there is a minimum delay of one frame, and the delay is not easy to calculate accurately.

[0112] Furthermore, FPGAs are equipped with multiple interfaces to output infrared image data, so the infrared image data is mainly calibrated in the FPGA, which facilitates the connection to subsequent outputs and reduces modification costs. In contrast, SoCs do not have these interfaces, and if the connection to the operation is to be achieved, it will cause great damage to the hardware, which is not only costly but also easily brings uncertain risks to the entire system.

[0113] like Figure 2 As shown, when the SoC reads multiple frames of infrared image data, it can calculate the second correction matrix for single-point correction based on the multiple frames of infrared image data.

[0114] In the specific implementation, let This is the average value of multiple frames of infrared image data. for The average value of all pixels in A (x,y) This is the second correction matrix.

[0115] So, n represents the number of infrared image data.

[0116] for The grayscale value of a pixel (x, y), where M is the number of rows and N is the number of columns.

[0117] I(x,y) This represents the grayscale value of a pixel (x, y) in the infrared image data.

[0118] Furthermore, the SoC sequentially reads the pixels of each row of infrared image data for each frame, calculates the average value of each pixel in each row, and obtains the average frame value of all pixels. Average frames The data is stored in memory, and the sum of all pixels is calculated. This sum is then divided by the total number of pixels in the multi-frame infrared image data (n*M*N, where n is the number of infrared image data points) to obtain the average number of pixels across the multi-frame infrared image data. The average frame stored in memory Read them sequentially and subtract them from the average of all pixels to obtain the second correction matrix A for single-point correction. (x,y) .

[0119] When the SoC completes the calculation of the second correction matrix for single-point correction, it can write the second correction matrix into its memory.

[0120] Based on the BlockDesign design, the FPGA and SoC can pre-agree on the memory allocation for the fourth address of the second correction matrix in the single-point correction, as well as the interrupt signal for performing the single-point correction (i.e., the fourth interrupt signal).

[0121] Then, the SoC can query its memory locally to find the fourth address allocated for storing the correction parameters in the single-point correction, and write the second correction matrix into the fourth address of its memory.

[0122] When the second correction matrix buffer used for single-point correction is completed, the SoC transmits a fourth interrupt signal to the FPGA via the PCIe interface.

[0123] Step 407: In response to the fourth interrupt signal, the field-programmable gate array reads the second correction matrix from memory through the PCIe interface and performs single-point correction on the infrared image data based on the second correction matrix.

[0124] like Figure 2 As shown, when the FPGA receives the fourth interrupt signal, it can use DMA technology to read the second correction matrix from the SoC's memory via the PCIe interface.

[0125] Based on the BlockDesign design, the FPGA and SoC can pre-agree on the memory allocation for the fourth address in storing the second correction matrix in single-point correction.

[0126] Therefore, the FPGA can query the SoC's memory locally to find the fourth address allocated for storing the correction parameters in the single-point correction, and read the second correction matrix from the fourth address of the SoC's memory through the PCIe interface.

[0127] When acquiring the second correction matrix, the FPGA can perform single-point correction on the infrared image data based on the second correction matrix.

[0128] I in(x,y) I represents the grayscale value of pixel (x,y) in the input infrared image data. out(x,y) A represents the grayscale value of pixel (x,y) in the output infrared image data. (x,y) This is the second correction matrix.

[0129] Therefore, the function for single-point correction is: I out(x,y) =I in(x,y) +A (x,y) .

[0130] Step 408: When the field-programmable gate array completes single-point correction, it performs histogram equalization on the infrared image data.

[0131] Infrared image data has low contrast, and the target cannot even be directly observed with the naked eye. Therefore, when performing single-point correction, the FPGA performs histogram equalization on the infrared image data to increase the contrast of the infrared image data and make the target easier to observe.

[0132] Histogram equalization distributes a small number of concentrated gray levels in infrared image data evenly across the entire gray range. It does this by non-linearly stretching the infrared image data and adjusting the corresponding output values ​​according to the gray probability distribution of the infrared image data. Gray levels that occur more frequently are assigned a larger gray value range, while gray levels that occur less frequently are compressed, so that the number of pixels in each gray range is roughly the same.

[0133] After using the native histogram equalization algorithm to perform histogram equalization on infrared image data, distortion may occur due to local areas being too bright or too dark.

[0134] In this embodiment, the original histogram algorithm is modified to separately count overly bright or dark areas. If the number of pixels in such areas is small, they are discarded during normalization, thereby enhancing contrast while preventing distortion of the infrared image data.

[0135] In practice, multiple preset gray levels can be determined.

[0136] For each gray level, count the number of pixels in the infrared image data at that gray level.

[0137] For one or more gray levels with the highest sorting, if the number of sub-levels is less than or equal to a preset first threshold, it indicates that the local area is too bright, and the pixels of the gray level and the infrared image data of the gray value in that gray level are discarded.

[0138] For one or more gray levels with the lowest sorting, if the number of sub-levels is less than or equal to a preset second threshold, it indicates that the local area is too dark, and the pixels of the gray level and the infrared image data of the gray value in the gray level are discarded.

[0139] Histogram equalization is performed on the remaining pixels in the infrared image data based on the remaining gray levels.

[0140] Let I r For grayscale levels, S i P represents the number of pixels in the infrared image data for each gray level, where N is the total number of pixels in the infrared image data, and P is the number of pixels in the infrared image data. (Si) H represents the probability of grayscale values. (k) Let I be the cumulative probability of grayscale. out For the new grayscale level.

[0141] So, P (Si) =S i / N, I out =H (k) ×I r .

[0142] The FPGA is equipped with RAM, and histogram equalization is implemented independently by the FPGA. The FPGA counts the number of sub-pixels and the total number of pixels by calling the RAM. When a frame of infrared image data is received, the counted number of sub-pixels and the total number of pixels are read out, and the grayscale probability, the cumulative grayscale probability, and the new grayscale level are calculated. The new grayscale level is then stored in RAM. When the FPGA receives new infrared image data, it uses the grayscale value of the current pixel as the address, reads the mapped new grayscale value from the new grayscale level in RAM, and replaces the current grayscale value with the new grayscale value.

[0143] Step 409: When the field-programmable gate array completes histogram equalization, it outputs infrared image data.

[0144] like Figure 2 As shown, when the FPGA completes histogram equalization, it can output infrared image data to other devices through other interfaces for further post-processing or display.

[0145] like Figure 6The diagram illustrates the operation flow of FPGA reading parameters (first correction matrix, second correction matrix) in this embodiment. VIDEO_IN_VS represents the field signal input for the current frame, indicating that one frame of infrared image data input is valid. VIDEO_IN_DS indicates that the current frame of infrared image data is valid. To ensure that the parameters are ready when the first line of data arrives, a memory request data, RD_DDR4_REQ, is generated during VIDEO_IN_VS. Upon receiving the request, data is read from memory and written to local RAM, i.e., WR_RAM_EN is valid. When infrared image data arrives, i.e., VIDEO_IN_DS is valid, the parameters are read from RAM, i.e., RD_RAM_EN.

[0146] Specifically, when each frame of infrared image data is input, a line of parameters is read from the SoC's memory and stored in the internal RAM on the rising edge of the frame synchronization signal. Then, another line of parameters is read from the SoC's memory and stored in the RAM on the rising edge of each line synchronization signal. This operation ensures that a line of parameters is always prepared in advance in the RAM. When the line synchronization signal is valid, the parameters in the RAM are read for two-point correction and single-point correction. Two-point correction involves multiplying the infrared image data by the response rate factor and adding the intercept factor. Single-point correction involves adding the infrared image data to the second correction matrix.

[0147] Example 3

[0148] See Figure 7 The diagram illustrates a structural schematic of an infrared image data correction device provided in Embodiment 3 of the present invention. Figure 7 As shown, the device includes a field-programmable gate array 710 and a system-on-a-chip 720. The field-programmable gate array 710 is configured with a block-compliant PCIe interface, and the system-on-a-chip 720 is connected to the PCIe interface. The system-on-a-chip 720 is configured with memory.

[0149] The field-programmable gate array 710 is used to perform blind pixel correction on the infrared image data when it receives infrared image data collected by the infrared detector.

[0150] The field-programmable gate array 710 is also used to write multiple frames of infrared image data into the memory through the PCIe interface when blind pixel correction is completed, and to transmit a first interrupt signal to the system-on-a-chip through the PCIe interface;

[0151] The system-on-a-chip 720 is used to respond to the first interrupt signal by reading multiple frames of infrared image data from the memory, calculating a first correction matrix for two-point correction based on the multiple frames of infrared image data, writing the first correction matrix into the memory, and transmitting a second interrupt signal to the field programmable gate array through the PCIe interface.

[0152] The field-programmable gate array 710 is also configured to, in response to the second interrupt signal, read the first correction matrix from the memory through the PCIe interface, and perform two-point correction on the infrared image data based on the first correction matrix.

[0153] In one embodiment of the present invention, the system-on-a-chip 720 is further configured to read the threshold for blind element correction from the configuration information of the infrared detector and transmit the threshold to the field-programmable gate array via the PCIe interface;

[0154] The field-programmable gate array 710 is also used for:

[0155] The baseline value is obtained by calculating the average grayscale value of each pixel in the infrared image data.

[0156] The grayscale deviation value is obtained by taking the absolute value of the difference between the grayscale value of the pixel and the baseline value.

[0157] When the grayscale deviation value is greater than or equal to the threshold, the pixel is determined to be a blind pixel, and the blind pixel is subjected to filtering processing.

[0158] In one embodiment of the present invention, the field-programmable gate array 710 is further configured to:

[0159] The memory address is found to be the first address allocated for storing infrared image data in two-point calibration.

[0160] Multiple frames of infrared image data are written into the first address of the memory via the PCIe interface;

[0161] The system-on-chip 720 is also used for:

[0162] The memory address is found to be the first address allocated for storing infrared image data in two-point calibration.

[0163] Multiple frames of infrared image data are read from the first address of the memory.

[0164] In one embodiment of the present invention, the system-on-a-chip 720 is further configured to:

[0165] The memory address is found to be the second address allocated for storing the first correction matrix in the two-point correction.

[0166] Write the first correction matrix into the second address of the memory;

[0167] The field-programmable gate array 710 is also used for:

[0168] The memory address is found to be the second address allocated for storing the first correction matrix in the two-point correction.

[0169] The first correction matrix is ​​read from the second address of the memory via the PCIe interface.

[0170] In one embodiment of the present invention, the field-programmable gate array 710 is further configured to write multiple frames of infrared image data into the memory through the PCIe interface when completing two-point correction, and transmit a third interrupt signal to the system-on-a-chip through the PCIe interface;

[0171] The system-on-a-chip 720 is also used to respond to the third interrupt signal by reading multiple frames of infrared image data from the memory, calculating a second correction matrix for single-point correction based on the multiple frames of infrared image data, writing the second correction matrix into the memory, and transmitting a fourth interrupt signal to the field programmable gate array through the PCIe interface.

[0172] The field-programmable gate array 710 is also configured to, in response to the fourth interrupt signal, read the second correction matrix from the memory through the PCIe interface, and perform single-point correction on the infrared image data based on the second correction matrix;

[0173] The field-programmable gate array 710 is also used to perform histogram equalization on the infrared image data when single-point correction is completed;

[0174] The field-programmable gate array 710 is also used to output the infrared image data when performing histogram equalization.

[0175] In one embodiment of the present invention, the field-programmable gate array 710 is further configured to:

[0176] The memory address is found to be the third address allocated for storing infrared image data in single-point calibration.

[0177] Multiple frames of infrared image data are written into the third address of the memory via the PCIe interface;

[0178] The system-on-chip 720 is also used for:

[0179] The memory address is found to be the third address allocated for storing infrared image data in single-point calibration.

[0180] Multiple frames of infrared image data are read from the third address of the memory.

[0181] In one embodiment of the present invention, the system-on-a-chip 720 is further configured to:

[0182] The memory address in question is the fourth address allocated for storing the calibration parameters in the single-point calibration.

[0183] Write the second correction matrix into the fourth address of the memory;

[0184] The field-programmable gate array 710 is also used for:

[0185] The memory address in question is the fourth address allocated for storing the calibration parameters in the single-point calibration.

[0186] The second correction matrix is ​​read from the fourth address of the memory via the PCIe interface.

[0187] In one embodiment of the present invention, the field-programmable gate array 710 is further configured to:

[0188] Define multiple preset gray levels;

[0189] For each gray level, count the number of pixels in the infrared image data at that gray level;

[0190] For one or more of the highest-ranked gray levels, if the number of sub-levels is less than or equal to a preset first threshold, then the gray level and the pixels of the infrared image data in the gray level are discarded.

[0191] For one or more of the lowest sorted gray levels, if the number of sub-levels is less than or equal to a preset second threshold, then the gray level and the pixels of the infrared image data in the gray level are discarded.

[0192] Histogram equalization is performed on the remaining pixels in the infrared image data based on the remaining gray levels.

[0193] The infrared image data correction device provided in the embodiments of the present invention can execute the infrared image data correction method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the infrared image data correction method.

[0194] Example 4

[0195] See Figure 8This diagram illustrates a structural schematic of an electronic device according to an embodiment of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, blade servers, mainframe computers, and other suitable computers. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0196] like Figure 8 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0197] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0198] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as methods for correcting infrared image data.

[0199] In some embodiments, the infrared image data correction method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the infrared image data correction method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the infrared image data correction method by any other suitable means (e.g., by means of firmware).

[0200] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0201] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0202] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0203] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0204] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0205] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0206] Example 5

[0207] This invention also provides a computer program product, which includes a computer program that, when executed by a processor, implements the infrared image data correction method provided in any embodiment of this invention.

[0208] In implementing the computer program product, computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0209] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0210] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for correcting infrared image data, characterized in that, The field-programmable gate array (FPGA) is configured with a block-compliant PCIe interface, a system-on-a-chip (SoC) is connected to the PCIe interface, and the SoC includes memory. The method includes: When the field-programmable gate array receives infrared image data collected by the infrared detector, it performs blind element correction on the infrared image data; When the field-programmable gate array completes blind element correction, it writes multiple frames of infrared image data into the memory through the PCIe interface and transmits a first interrupt signal to the system-on-a-chip through the PCIe interface. In response to the first interrupt signal, the system-on-a-chip reads multiple frames of infrared image data from the memory, calculates a first correction matrix for two-point correction based on the multiple frames of infrared image data, writes the first correction matrix into the memory, and transmits a second interrupt signal to the field-programmable gate array through the PCIe interface. In response to the second interrupt signal, the field-programmable gate array reads the first correction matrix from the memory through the PCIe interface and performs two-point correction on the infrared image data based on the first correction matrix.

2. The method according to claim 1, characterized in that, Also includes: The system-on-a-chip reads the blind pixel correction threshold from the configuration information of the infrared detector and transmits the threshold to the field-programmable gate array via the PCIe interface; The step of performing blind pixel correction on the infrared image data includes: The baseline value is obtained by calculating the average grayscale value of each pixel in the infrared image data. The grayscale deviation value is obtained by taking the absolute value of the difference between the grayscale value of the pixel and the baseline value. When the grayscale deviation value is greater than or equal to the threshold, the pixel is determined to be a blind pixel, and the blind pixel is subjected to filtering processing.

3. The method according to claim 1, characterized in that, The step of writing multiple frames of infrared image data into the memory via the PCIe interface includes: The memory address is found to be the first address allocated for storing infrared image data in two-point calibration. Multiple frames of infrared image data are written into the first address of the memory via the PCIe interface; The step of reading multiple frames of infrared image data from the memory includes: The memory address is found to be the first address allocated for storing infrared image data in two-point calibration. Multiple frames of infrared image data are read from the first address of the memory.

4. The method according to claim 1, characterized in that, The step of writing the first correction matrix into the memory includes: The memory address is found to be the second address allocated for storing the first correction matrix in the two-point correction. Write the first correction matrix into the second address of the memory; The step of reading the first correction matrix from the memory via the PCIe interface includes: The memory address is found to be the second address allocated for storing the first correction matrix in the two-point correction. The first correction matrix is ​​read from the second address of the memory via the PCIe interface.

5. The method according to any one of claims 1-4, characterized in that, Also includes: When the field-programmable gate array completes two-point correction, it writes multiple frames of infrared image data into the memory through the PCIe interface and transmits a third interrupt signal to the system-on-a-chip through the PCIe interface. In response to the third interrupt signal, the system-on-a-chip reads multiple frames of infrared image data from the memory, calculates a second correction matrix for single-point correction based on the multiple frames of infrared image data, writes the second correction matrix into the memory, and transmits a fourth interrupt signal to the field-programmable gate array through the PCIe interface; In response to the fourth interrupt signal, the field-programmable gate array reads the second correction matrix from the memory through the PCIe interface and performs single-point correction on the infrared image data based on the second correction matrix; When performing single-point correction, the field-programmable gate array performs histogram equalization on the infrared image data; The field-programmable gate array outputs the infrared image data when performing histogram equalization.

6. The method according to claim 5, characterized in that, The step of writing multiple frames of infrared image data into the memory via the PCIe interface includes: The memory address is found to be the third address allocated for storing infrared image data in single-point calibration. Multiple frames of infrared image data are written into the third address of the memory via the PCIe interface; The step of reading multiple frames of infrared image data from the memory includes: The memory address is found to be the third address allocated for storing infrared image data in single-point calibration. Multiple frames of infrared image data are read from the third address of the memory.

7. The method according to claim 5, characterized in that, The step of writing the second correction matrix into the memory includes: The memory address in question is the fourth address allocated for storing the calibration parameters in the single-point calibration. Write the second correction matrix into the fourth address of the memory; The step of reading the second correction matrix from the memory via the PCIe interface includes: The memory address in question is the fourth address allocated for storing the calibration parameters in the single-point calibration. The second correction matrix is ​​read from the fourth address of the memory via the PCIe interface.

8. The method according to claim 5, characterized in that, The histogram equalization of the infrared image data includes: Define multiple preset gray levels; For each gray level, count the number of pixels in the infrared image data at that gray level; For one or more of the highest-ranked gray levels, if the number of sub-levels is less than or equal to a preset first threshold, then the gray level and the pixels of the infrared image data in the gray level are discarded. For one or more of the lowest sorted gray levels, if the number of sub-levels is less than or equal to a preset second threshold, then the gray level and the pixels of the infrared image data in the gray level are discarded. Histogram equalization is performed on the remaining pixels in the infrared image data based on the remaining gray levels.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor to enable the at least one processor to perform the correction method for infrared image data as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method for correcting infrared image data as described in any one of claims 1-8.

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