Memory device, operating method thereof, and memory system

Abstract

The embodiment of the invention provides a memory device, an operation method thereof and a memory system. The memory device includes: a first memory bank and a second memory bank; the redundancy analysis circuit is coupled with the first memory bank and the second memory bank; the redundancy analysis circuit comprises a redundancy circuit which stores failure address information in a first memory bank and a second memory bank; the first memory bank is connected with the second memory bank and is configured to output a fail address signal according to an enable signal of the first memory bank or the second memory bank, and the fail address signal comprises fail address information of the first memory bank or the second memory bank; and the matching circuit is coupled with the redundant circuit, and is configured to receive the to-be-activated address signal and the failure address signal, match the to-be-activated address information in the to-be-activated address signal with the failure address information in the failure address signal, and output a matched address signal.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a memory device and its operation method, and a memory system. Background Technology

[0002] Memory devices and systems are storage devices used to preserve information in modern information technology. As people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and systems. Summary of the Invention

[0003] In view of the above, embodiments of this application provide a memory device and its operation method, as well as a memory system.

[0004] In a first aspect, embodiments of this application provide a memory device, the memory device comprising: a first memory bank and a second memory bank; and a redundancy analysis circuit coupled to both the first memory bank and the second memory bank; wherein the redundancy analysis circuit comprises: a redundancy circuit, storing failure address information in the first memory bank and the second memory bank; and configured to output a failure address signal based on an enable signal of the first memory bank or the second memory bank, the failure address signal containing failure address information of the first memory bank or the second memory bank; and a matching circuit, coupled to the redundancy circuit, and configured to receive an activation address signal and a failure address signal, and match the activation address information in the activation address signal with the failure address information in the failure address signal, and output a matching address signal.

[0005] In some embodiments, the memory device further includes a decoding circuit, a first register, and a second register; the decoding circuit includes a first decoding circuit; wherein the first decoding circuit is coupled to a redundancy analysis circuit and configured to receive an address signal to be activated and a matching address signal, and generate a first decoding signal based on the address signal to be activated and the matching address signal; the first decoding signal includes normal address information to be activated in the first memory bank / second memory bank, and / or redundant address information to be activated; the first register is coupled to the first decoding circuit and configured to store the first decoding signal in response to an enable signal of the first memory bank being in an enabled state; the second register is coupled to the first decoding circuit and configured to store the first decoding signal in response to an enable signal of the second memory bank being in an enabled state.

[0006] In some embodiments, the first storage is configured to be activated after the second register has finished storing the first decoded signal; or, the second storage is configured to be activated after the first register has finished storing the first decoded signal.

[0007] In some embodiments, the address signal to be activated includes a first signal or a second signal, the first signal including address information to be activated in a first memory, and the second signal including address information to be activated in a second memory; the first decoding signal includes a third signal or a fourth signal, the third signal including normal address information to be activated and / or redundant address information to be activated in the first memory, and the fourth signal including normal address information to be activated and / or redundant address information to be activated in the second memory; the redundancy analysis circuit is configured to receive and store the first signal, and in response to the first register completing the storage of the third signal, the first decoding circuit is configured to generate the fourth signal / third signal the next time the second signal / first signal is received and stored; or, the redundancy analysis circuit is configured to receive and store the second signal, and in response to the second register completing the storage of the fourth signal, the first decoding circuit is configured to receive and store the first signal / second signal, and generate the third signal / fourth signal.

[0008] In some embodiments, the memory device further includes a decoding circuit; the decoder circuit includes a second decoding circuit and a third decoding circuit; wherein the second decoding circuit is coupled to a redundancy analysis circuit and is configured to, in response to an enable signal of the first memory bank being enabled, receive an address signal to be activated and a matching address signal, and generate a second decoding signal based on the address signal to be activated and the matching address signal; the second decoding signal includes normal address information to be activated in the first memory bank and / or redundant address information to be activated; the third decoding circuit is coupled to the redundancy analysis circuit and is configured to, in response to an enable signal of the second memory bank being enabled, receive an address signal to be activated and a matching address signal, and generate a third decoding signal based on the address signal to be activated and the matching address signal; the third decoding signal includes normal address information to be activated in the second memory bank and / or redundant address information to be activated.

[0009] In some embodiments, the redundancy analysis circuit includes a row redundancy analysis circuit, which includes a row redundancy circuit and a row matching circuit. The row redundancy circuit is configured to: store corresponding failed row address information in the first and second memory banks respectively, and output a failed row address signal, the failed row address signal containing the failed row address information corresponding to one of the memory banks to be activated in the first and second memory banks; the row matching circuit is configured to: receive the row address signal to be activated, match the row address information to be activated in the row address signal with the failed row address information in the failed row address signal, and output a matched row signal; the decoding circuit includes a row decoding circuit, which is configured to: receive the row address signal to be activated and the matched row signal, and generate a first row decoding signal / a second row decoding signal / a third row decoding signal based on the row address signal to be activated and the matched row signal; the first row decoding signal / a second row decoding signal / a third row decoding signal includes the row address information to be activated in the first / second memory bank, and / or the redundant row address information to be activated.

[0010] In some embodiments, the row redundancy circuit includes a first latch circuit and a second latch circuit; the row matching circuit includes a comparator circuit; the first latch circuit stores a first failed row address signal and is configured to output the stored first failed row address signal in response to an enabled state of a first read signal; or, the second latch circuit stores a second failed row address signal and is configured to output the stored second failed row address signal in response to an enabled state of a second read signal; the comparator circuit is configured to receive a row address signal to be activated and the first failed row address signal / second failed row address signal, and generate a matching row signal.

[0011] In some embodiments, the first latch circuit is further configured to store the first failed row address signal to be stored in response to the enable state of the first write signal; or, the second latch circuit is further configured to store the second failed row address signal to be stored in response to the enable state of the second write signal.

[0012] In some embodiments, the memory device further includes a control circuit; the control circuit is configured to generate a first read signal in response to an enable signal of a first memory bank, or to generate a second read signal in response to an enable signal of a second memory bank.

[0013] In some embodiments, the control circuit is further configured to generate a first failed row address signal and a first write signal corresponding to the failed row of the first memory bank in response to the occurrence of a failed row in a normal row of the first memory bank, or to generate a second failed row address signal and a second write signal corresponding to the failed row of the second memory bank in response to the occurrence of a failed row in a normal row of the second memory bank.

[0014] In some embodiments, the first latch circuit includes a first gating circuit, a first latch, and a second gating circuit; the second latch circuit includes a third gating circuit, a second latch, and a fourth gating circuit; the first gating circuit is configured to receive a first failed row address signal to be stored and a first write signal, and in response to the enable state of the first write signal, transmit the first failed row address signal to be stored to the first latch; the first latch is configured to receive and store the first failed row address signal to be stored / output the stored first failed row address signal; the second gating circuit is configured to receive the first failed row address signal stored in the first latch and a first read signal, and in response to the first read signal... In the enabled state, the first failed row address signal stored in the first latch is transmitted to the comparator circuit; or, the third gating circuit is configured to receive the second failed row address signal to be stored and the second write signal, and in response to the enabled state of the second write signal, transmit the second failed row address signal to be stored to the second latch; the second latch is configured to receive and store the second failed row address signal to be stored / output the stored second failed row address signal; the fourth gating circuit is configured to receive the second failed row address signal stored in the second latch and the second read signal, and in response to the enabled state of the second read signal, transmit the second failed row address signal stored in the second latch to the comparator circuit.

[0015] In some embodiments, the comparison circuit includes a transmission gate and a fifth gating circuit; the transmission gate is configured to receive a row address signal to be activated and a first failed row address signal / second failed row address signal, and generate a first state of a matching signal in response to the enabled state of the first failed row address signal / second failed row address signal; the first state of the matching signal represents a failed row address in the row address to be activated that matches the first failed row address / second failed row address; the fifth gating circuit is configured to receive an inverted signal of the row address signal to be activated and the first failed row address signal / second failed row address signal, and generate a matching signal in a second state in response to the enabled state of the inverted signal of the first failed row address signal / second failed row address signal; the second state of the matching signal represents a failed row address in the row address to be activated that does not match the first failed row address / second failed row address.

[0016] In some embodiments, the memory device further includes a first word line driver, a second word line driver, a third word line driver, and a fourth word line driver; the first word line driver is configured to receive an output signal from a decoding circuit and generate a first drive signal; the first drive signal is used to drive normal rows in the first memory bank; and / or, the second word line driver is configured to receive an output signal from the decoding circuit and generate a second drive signal; the second drive signal is used to drive redundant rows in the first memory bank; the third word line driver is configured to receive an output signal from the decoding circuit and generate a third drive signal; the third drive signal is used to drive normal rows in the second memory bank; and / or, the fourth word line driver is configured to receive an output signal from the decoding circuit and generate a fourth drive signal; the fourth drive signal is used to drive redundant rows in the second memory bank.

[0017] Secondly, embodiments of this application provide a memory device, the memory device comprising: a first memory bank and a second memory bank disposed adjacent to each other; and a redundancy analysis circuit located between the first memory bank and the second memory bank and coupled to both the first memory bank and the second memory bank; wherein the redundancy analysis circuit comprises: a redundancy circuit, storing failure address information in the first memory bank and the second memory bank; and configured to output a failure address signal according to an enable signal of the first memory bank or the second memory bank, the failure address signal containing failure address information of the first memory bank or the second memory bank; and a matching circuit, coupled to the redundancy circuit, and configured to receive an activation address signal and a failure address signal, and match the activation address information in the activation address signal with the failure address information in the failure address signal, and output a matching address signal.

[0018] In some embodiments, the memory device further includes a decoding circuit, a first register, and a second register; the decoding circuit includes a first decoding circuit; wherein the first decoding circuit is located between the first memory bank and the second memory bank and coupled to the redundancy analysis circuit, and is configured to receive an address signal to be activated and a matching address signal, and generate a first decoding signal based on the address signal to be activated and the matching address signal; the first decoding signal includes normal address information to be activated in the first memory bank / second memory bank, and / or redundant address information to be activated; the first register is located between the redundancy analysis circuit, the first decoding circuit, and the first memory bank and coupled to the first decoding circuit, and is configured to store the first decoding signal in response to an enable signal of the first memory bank being in an enabled state; the second register is located between the redundancy analysis circuit, the first decoding circuit, and the second memory bank and coupled to the first decoding circuit, and is configured to store the first decoding signal in response to an enable signal of the second memory bank being in an enabled state.

[0019] In some embodiments, the memory device further includes a first word line driver and a second word line driver located between a first register and a first memory bank, and a third word line driver and a fourth word line driver located between a second register and a second memory bank; the first word line driver is configured to receive an output signal from a decoding circuit and generate a first drive signal; the first drive signal is used to drive normal rows in the first memory bank; and / or, the second word line driver is configured to receive an output signal from a decoding circuit and generate a second drive signal; the second drive signal is used to drive redundant rows in the first memory bank; the third word line driver is configured to receive an output signal from a decoding circuit and generate a third drive signal; the third drive signal is used to drive normal rows in the second memory bank; and / or, the fourth word line driver is configured to receive an output signal from a decoding circuit and generate a fourth drive signal; the fourth drive signal is used to drive redundant rows in the second memory bank.

[0020] In some embodiments, the memory device further includes a decoding circuit; the decoding circuit includes a second decoding circuit and a third decoding circuit; wherein, the second decoding circuit is located between the first memory bank and the second memory bank and coupled to the redundancy analysis circuit, and is configured to receive an address signal to be activated and a matching address signal in response to an enable signal of the first memory bank being enabled, and generate a second decoding signal based on the address signal to be activated and the matching address signal; the second decoding signal includes normal address information to be activated in the first memory bank and / or redundant address information to be activated; the third decoding circuit is located between the first memory bank and the second memory bank and coupled to the redundancy analysis circuit, and is configured to receive an address signal to be activated and a matching address signal in response to an enable signal of the second memory bank being enabled, and generate a third decoding signal based on the address signal to be activated and the matching address signal; the third decoding signal includes normal address information to be activated in the second memory bank and / or redundant address information to be activated.

[0021] In some embodiments, the memory device further includes a first word line driver and a second word line driver located between the redundancy analysis circuit, the second decoding circuit, and the first memory bank; and a third word line driver and a fourth word line driver located between the redundancy analysis circuit, the third decoding circuit, and the second memory bank; the first word line driver is configured to receive an output signal from the decoding circuit and generate a first drive signal; the first drive signal is used to drive normal rows in the first memory bank; and / or, the second word line driver is configured to receive an output signal from the decoding circuit and generate a second drive signal; the second drive signal is used to drive redundant rows in the first memory bank; the third word line driver is configured to receive an output signal from the decoding circuit and generate a third drive signal; the third drive signal is used to drive normal rows in the second memory bank; and / or, the fourth word line driver is configured to receive an output signal from the decoding circuit and generate a fourth drive signal; the fourth drive signal is used to drive redundant rows in the second memory bank.

[0022] Thirdly, embodiments of this application provide a memory system comprising: one or more memory devices as provided in the first aspect; and a memory controller coupled to and controlling the memory devices.

[0023] Fourthly, embodiments of this application provide an operation method for a memory device, the memory device including a first memory bank and a second memory bank, and a redundancy analysis circuit coupled to both the first memory bank and the second memory bank; the operation method includes: a redundancy circuit of the redundancy analysis circuit storing failure address information in the first memory bank and the second memory bank; outputting a failure address signal according to an enable signal of the first memory bank or the second memory bank, the failure address signal containing failure address information of the first memory bank or the second memory bank; and a matching circuit of the redundancy analysis circuit coupled to the redundancy circuit receiving an activation address signal and a failure address signal, matching the activation address information in the activation address signal with the failure address information in the failure address signal, and outputting a matching address signal.

[0024] In some embodiments, the operation method further includes: a first decoding circuit coupled to a redundancy analysis circuit receiving an address signal to be activated and a matching address signal, and generating a first decoding signal based on the address signal to be activated and the matching address signal; the first decoding signal includes normal address information to be activated in a first memory bank / second memory bank, and / or redundant address information to be activated; in response to an enable signal of the first memory bank, a first register coupled to the first decoding circuit stores the first decoding signal; in response to an enable signal of the second memory bank, a second register coupled to the first decoding circuit stores the first decoding signal.

[0025] In some embodiments, the operation method includes: activating a first storage bank in response to the second register completing the storage of the first decoded signal; or activating a second storage bank in response to the first register completing the storage of the first decoded signal.

[0026] In some embodiments, the operation method further includes: a redundancy analysis circuit receiving and storing a first signal; in response to the first register completing the storage of a third signal, the first decoding circuit receiving and storing a second signal / first signal again, and generating a fourth signal / third signal; or, a redundancy analysis circuit receiving and storing a second signal; in response to the second register completing the storage of a fourth signal, the first decoding circuit receiving and storing a first signal / second signal, and generating a third signal / fourth signal; wherein, the address signal to be activated includes either the first signal or the second signal, the first signal including address information to be activated in the first memory, and the second signal including address information to be activated in the second memory; the first decoding signal includes either the third signal or the fourth signal, the third signal including normal address information to be activated and / or redundant address information to be activated in the first memory, and the fourth signal including normal address information to be activated and / or redundant address information to be activated in the second memory.

[0027] In some embodiments, the operation method further includes: in response to the enable signal of the first memory being enabled, a second decoding circuit coupled to the redundancy analysis circuit receives an address signal to be activated and a matching address signal, and generates a second decoding signal based on the address signal to be activated and the matching address signal; the second decoding signal includes normal address information to be activated in the first memory and / or redundant address information to be activated; in response to the enable signal of the second memory being enabled, a third decoding circuit coupled to the redundancy analysis circuit receives the address signal to be activated and the matching address signal, and generates a third decoding signal based on the address signal to be activated and the matching address signal; the third decoding signal includes normal address information to be activated in the second memory and / or redundant address information to be activated.

[0028] In some embodiments, the operation method includes: a row redundancy circuit storing corresponding failed row address information in a first memory bank and a second memory bank respectively, and outputting a failed row address signal, wherein the failed row address signal includes the failed row address information corresponding to one of the first and second memory banks to be activated; a row matching circuit receiving the row address signal to be activated, matching the row address information to be activated in the row address signal with the failed row address information in the failed row address signal, and outputting a matched row signal; a row decoding circuit receiving the row address signal to be activated and the matched row signal, and generating a first row decoding signal / a second row decoding signal / a third row decoding signal according to the row address signal to be activated and the matched row signal; the first row decoding signal / a second row decoding signal / a third row decoding signal includes the row address information to be activated in the first memory bank / the second memory bank, and / or the redundant row address information to be activated; wherein, the redundancy analysis circuit includes a row redundancy analysis circuit, the row redundancy analysis circuit includes a row redundancy circuit and a row matching circuit, and the decoding circuit includes a row decoding circuit.

[0029] In some embodiments, the operation method includes: in response to an enabled state of a first read signal, storing a first failed row address signal stored by a first latch circuit outputting a first failed row address signal; or, in response to an enabled state of a second read signal, storing a second failed row address signal stored by a second latch circuit outputting a second failed row address signal; a comparison circuit receives a row address signal to be activated and the first failed row address signal / second failed row address signal, and generates a matching signal; wherein the row redundancy circuit includes a first latch circuit and a second latch circuit; and the row matching circuit includes a comparison circuit.

[0030] In some embodiments, the operation method includes: in response to the enabled state of a first write signal, a first latch circuit stores a first failed row address signal to be stored; or, in response to the enabled state of a second write signal, a second latch circuit stores a second failed row address signal to be stored.

[0031] In some embodiments, the operation method further includes: in response to an enable signal of a first memory bank, the control circuit generates a first read signal, or in response to an enable signal of a second memory bank, the control circuit generates a second read signal; wherein the memory device includes a control circuit.

[0032] In some embodiments, the operation method further includes: in response to a failed row appearing in a normal row in a first memory bank, the control circuit generates a first failed row address signal and a first write signal corresponding to the failed row in the first memory bank; or, in response to a failed row appearing in a normal row in a second memory bank, the control circuit generates a second failed row address signal and a second write signal corresponding to the failed row in the second memory bank.

[0033] In some embodiments, the first latch circuit includes a first gating circuit, a first latch, and a second gating circuit; the second latch circuit includes a third gating circuit, a second latch, and a fourth gating circuit; the operation method further includes: the first gating circuit receiving a first failed row address signal to be stored and a first write signal, and in response to the enabled state of the first write signal, transmitting the first failed row address signal to be stored to the first latch; the first latch receiving and storing the first failed row address signal to be stored / outputting the stored first failed row address signal; the second gating circuit receiving the first failed row address signal stored in the first latch and a first read signal, and in response to the first write signal's enable state, transmitting the first failed row address signal to be stored to the first latch; the first latch receiving and storing the first failed row address signal to be stored / outputting the stored first failed row address signal; the second gating circuit receiving the first failed row address signal stored in the first latch and a first read signal, and in response to the first write signal's enable state, transmitting the first failed row address signal to be stored to the first latch; the second latch receiving and storing the first failed row address signal to be stored ... to the first latch; the second gating circuit receiving the first failed row address signal stored in the first latch and a first read signal, and in response to the first write signal's enable state, transmitting the first failed row address signal to be stored to the first latch; the second latch receiving and storing the first failed row address signal to be stored to the first latch; the second latch receiving and storing the first failed row address signal to be stored to When the read signal is enabled, the first failed row address signal stored in the first latch is transmitted to the comparator circuit; or, the third gating circuit receives the second failed row address signal to be stored and the second write signal, and in response to the enable state of the second write signal, transmits the second failed row address signal to be stored to the second latch; the second latch receives and stores the second failed row address signal to be stored / outputs the stored second failed row address signal; the fourth gating circuit receives the second failed row address signal stored in the second latch and the second read signal, and in response to the enable state of the second read signal, transmits the second failed row address signal stored in the second latch to the comparator circuit.

[0034] In some embodiments, the comparison circuit includes a transmission gate and a fifth gate circuit; the operation method further includes: the transmission gate receiving a row address signal to be activated and a first failed row address signal / second failed row address signal, and generating a first state of a matching signal in response to the enabled state of the first failed row address signal / second failed row address signal; the first state of the matching signal represents a failed row address in the row address to be activated that matches the first failed row address / second failed row address; the fifth gate circuit receiving the inverted signal of the row address signal to be activated and the first failed row address signal / second failed row address signal, and generating a matching signal in a second state in response to the enabled state of the inverted signal of the first failed row address signal / second failed row address signal; the second state of the matching signal represents a failed row address in the row address to be activated that does not match the first failed row address / second failed row address.

[0035] In some embodiments, the memory device further includes a first word line driver, a second word line driver, a third word line driver, and a fourth word line driver; the operation method further includes: the first word line driver receiving an output signal from a decoding circuit and generating a first driving signal; the first driving signal being used to drive normal rows in a first memory bank; and / or, the second word line driver receiving an output signal from a decoding circuit and generating a second driving signal; the second driving signal being used to drive redundant rows in the first memory bank; the third word line driver receiving an output signal from a decoding circuit and generating a third driving signal; the third driving signal being used to drive normal rows in a second memory bank; and / or, the fourth word line driver receiving an output signal from a decoding circuit and generating a fourth driving signal; the fourth driving signal being used to drive redundant rows in the second memory bank.

[0036] In the embodiments of this application, under the premise of ensuring that the redundancy analysis function is normal, the first and second memory banks of the memory device share the redundancy analysis circuit. Due to circuit reuse, area can be saved, the size of the memory device can be improved, and the integration of the memory device can be increased. Moreover, reducing a part of the circuit will reduce the total power consumption and static leakage current of the memory device. Attached Figure Description

[0037] Figure 1 One of the schematic diagrams of a redundancy analysis circuit for a memory device provided in an embodiment of this application;

[0038] Figure 2 for Figure 1 A schematic diagram of part of the circuit;

[0039] Figure 3 One of the schematic diagrams of a planar layout of a memory device provided in an embodiment of this application;

[0040] Figure 4 A second schematic diagram of a planar layout of a memory device provided in an embodiment of this application;

[0041] Figure 5 A third schematic diagram of a planar layout of a memory device provided in an embodiment of this application;

[0042] Figure 6 Fourth schematic diagram of a planar layout of a memory device provided for an embodiment of this application;

[0043] Figure 7 One of the schematic diagrams of a redundant circuit and a matching circuit for another memory device provided in an embodiment of this application;

[0044] Figure 8 A second schematic diagram of a redundant circuit and a matching circuit for another memory device provided in an embodiment of this application;

[0045] Figure 9 A third schematic diagram of a redundant circuit and a matching circuit for another memory device provided in an embodiment of this application;

[0046] Figure 10 A fourth schematic diagram of a redundant circuit and a matching circuit for another memory device provided in an embodiment of this application;

[0047] Figure 11 Fifth schematic diagram of a redundant circuit and matching circuit of another memory device provided in an embodiment of this application;

[0048] Figure 12 A schematic diagram of a redundancy analysis circuit for another memory device provided in an embodiment of this application;

[0049] Figure 13 A schematic diagram of a redundancy circuit and a matching circuit for another memory device provided in an embodiment of this application;

[0050] Figure 14 One of the schematic diagrams of a planar layout of another memory device provided in an embodiment of this application;

[0051] Figure 15 A second schematic diagram of another planar layout of a memory device provided in an embodiment of this application;

[0052] Figure 16 This is a schematic diagram of the composition structure of an exemplary dynamic random access memory according to an embodiment of this application;

[0053] Figure 17 This is a schematic diagram of a memory system provided in an embodiment of this application. Detailed Implementation

[0054] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0055] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0056] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0057] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0058] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0060] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0061] Memory devices, such as Dynamic Random Access Memory (DRAM), include normal memory arrays and redundant memory arrays. DRAM is equipped with a redundancy-related circuit system that can use redundant cells in the redundant memory array to replace faulty cells in the normal memory array, thereby improving yield.

[0062] refer to Figure 1 The signal path traversed by the activation address signal 10a input to the memory device (e.g., DRAM) each time: Taking the activation address signal 10a sent to the first memory bank 110-0 as an example, when the activation address signal 10a is input, the first redundancy circuit 102-0 of the first redundancy analysis circuit 100-0 of the first memory bank 110-0 outputs a failure address signal 12a; the first matching circuit 104-0 of the first redundancy analysis circuit 100-0 receives the activation address signal 10a and the failure address signal 12a and outputs a matching address signal 14a; the second decoding circuit 106-1 of the first memory bank 110-0 receives the activation address signal 10a and the matching address signal 14a and outputs a decoding signal 16a; the first word line driving circuit 108-0 of the first memory bank 110-0 enables the normal word line nwl and / or the redundant word line rwl corresponding to the activation address signal 10a according to the received decoding signal 16a, so as to drive the normal cells and / or redundant cells in the first memory bank 110-0. Here, the first redundant circuit 102-0 of the first memory bank 110-0 is used to store the address information (failure address information) of the faulty unit of the first memory bank 110-0; the failure address signal 12a includes the failure address information in the first memory bank 110-0.

[0063] Here, each memory bank has an independent redundancy circuit and a matching circuit. Specifically, the first redundancy circuit 102-0 of the first redundancy analysis circuit 100-0 of the first memory bank 110-0 outputs a failure address signal 12a, which includes the failure address information of the faulty unit in the first memory bank 110-0. The second redundancy circuit 102-1 of the second redundancy analysis circuit 100-1 of the second memory bank 110-1 outputs a failure address signal 12a, which includes the failure address information of the faulty unit in the second memory bank 110-1.

[0064] The signal path traversed by the activation address signal 10a sent to the second memory bank 110-1 can be understood by referring to the specific situation of the signal path traversed by the activation address signal 10a sent to the first memory bank 110-0. The circuits traversed by the signal path corresponding to the second memory bank 110-1, such as the second redundancy circuit 102-1 of the second redundancy analysis circuit 100-1, the second matching circuit 104-1 of the second redundancy analysis circuit 100-1, the third decoding circuit 106-2, and the second word line driving circuit 108-1, can be understood by referring to the first redundancy circuit 102-0 of the first redundancy analysis circuit 100-0, the first matching circuit 104-0 of the first redundancy analysis circuit 100-0, the second decoding circuit 106-1, and the first word line driving circuit 108-0, respectively.

[0065] refer to Figure 2 The DRAM is equipped with a redundancy-related circuit system, and the address signal path through which the failure address signal 12a passes is as follows: Taking the activation address signal 10a sent to the first memory bank 110-0, and the first redundancy circuit 102-0 storing the failure address information of the faulty cell in the first memory bank 110-0 and outputting the failure address signal 12a as an example, the first matching circuit 104-0 of the first redundancy analysis circuit 100-0 of the first memory bank 110-0 receives the activation address signal 10a and the failure address signal 12a, and outputs the matching address signal 14a; the second decoding circuit 106-1 of the first memory bank 110-0 receives the matching address signal 14a and outputs the decoding signal 16a; the first word line driving circuit 108-0 of the first memory bank 110-0 enables the redundant word line rwl corresponding to the activation address signal 10a according to the received decoding signal 16a, so as to drive the redundant cells in the first memory bank 110-0.

[0066] It should be noted that the components / circuits / devices / signals identified by the same reference numerals in the memory devices of various embodiments of this application shall be understood as the same or similar components / circuits / devices / signals. For example, the first memory bank 110-0 and the second memory bank 110-1, the first word line driving circuit 108-0 and the second word line driving circuit 108-1 in each schematic diagram.

[0067] It should be noted that if the input address to be activated has a failed address (or faulty address), the failed address needs to be replaced with a redundant address. When accessing the failed unit (or faulty unit), it will automatically switch to accessing the redundant unit corresponding to the faulty unit to replace the faulty unit.

[0068] Figure 3This is a schematic diagram of the XY plane layout of the memory device provided in the embodiments of this application. Herein and hereinafter, for ease of description of the embodiments of this application, the first direction and the second direction are represented as two orthogonal directions parallel to the top surface of the memory device; the third direction is the thickness direction of the memory device, perpendicular to the top surface of the memory device. The first direction can be represented as the X direction in the figures; the second direction can be represented as the Y direction in the figures; and the third direction can be represented as the Z direction in the figures.

[0069] refer to Figure 3 The memory device includes a first memory bank 110-0, a first decoding circuit xdec-0 coupled to the first memory bank 110-0, a second memory bank 110-1, and a second decoding circuit xdec-1 coupled to the second memory bank 110-1; the first decoding circuit xdec-0 and the second decoding circuit xdec-1 are both located between the first memory bank 110-0 and the second memory bank 110-1; wherein, the first decoding circuit xdec-0 includes a first redundancy analysis circuit 100-0, a second decoding circuit 106-1, and a first word line driving circuit 108-0, and the second decoding circuit xdec-1 includes a second redundancy analysis circuit 100-1, a third decoding circuit 106-2, and a second word line driving circuit 108-1.

[0070] The connection relationship and signal flow path of the first redundancy analysis circuit 100-0, the second decoding circuit 106-1, the first word line driving circuit 108-0, and the first memory bank 110-0 can be referred to Figure 1 The connection relationship and signal flow path between the first redundancy analysis circuit 100-0, the second decoding circuit 106-1, the first word line driving circuit 108-0, and the first memory bank 110-0 can be understood. Correspondingly, the connection relationship and signal flow path between the second memory bank 110-1 and the second decoding circuit xdec-1 can be understood by referring to the connection relationship and signal flow path between the first memory bank 110-0 and the first decoding circuit xdec-0.

[0071] Each time the memory device inputs an address to be activated, it needs to compare it with the failed address information stored in the redundancy analysis circuit to determine whether the input address to be activated is a failed address. Based on this, it determines whether redundancy replacement is needed, that is, replacing the failed address with a redundant address. When accessing a faulty unit based on the address to be activated signal, it will automatically switch to accessing the redundant unit corresponding to the faulty unit used to replace the faulty unit. However, the storage and comparison circuits in the redundancy analysis circuit occupy a considerable portion of the total area of ​​the decoding circuit. For example, the area of ​​the first redundancy analysis circuit 100-0 occupies about 1 / 4 of the area of ​​the first decoding circuit xdec-0.

[0072] refer to Figure 3 and Figure 4 The first memory bank 110-0 and the second memory bank 110-1 each have their own independent decoding circuits. The decoding circuits located between the first memory bank 110-0 and the second memory bank 110-1 (such as the first redundancy analysis circuit 100-0 and the second redundancy analysis circuit 100-1) occupy a considerable portion of the area, resulting in a large first distance D1 between the first memory bank 110-0 and the second memory bank 110-1, which in turn hinders the improvement of the memory device size.

[0073] refer to Figure 5 In some embodiments, the first memory bank 110-0 and the second memory bank 110-1 may reuse the decoding circuitry (e.g., reuse the first redundancy analysis circuit 100-0 and the second redundancy analysis circuit 100-1). This reduces the area of ​​redundant circuitry, saving memory device area and reducing static leakage current; however, the number of redundant word lines rwl in each memory bank (one of the first memory bank 110-0 and the second memory bank 110-1) may need to be increased, and the area of ​​the memory array of the memory banks may increase. For example, compared to Figure 4 The number of redundant word lines rwl in the first memory bank 110-0 (including redundant word lines rwl_0, rwl_1, and rwl_2). Figure 5 The number of redundant word lines rwl (including redundant word lines rwl_0, rwl_1, rwl_2, rwl_3, rwl_4, and rwl_5) in the first memory bank 110-0 has increased.

[0074] refer to Figure 6 In some embodiments, the first memory bank 110-0 and the second memory bank 110-1 can share a decoding circuit (e.g., share a first redundancy analysis circuit 100-0). This reduces the area of ​​redundant circuitry, thereby saving memory device area and reducing static leakage current. However, when the first redundancy analysis circuit 100-0 is used to replace a word line in the first memory bank 110-0 with a redundant word line, the word line wl in the second memory bank 110-1 will also be replaced with a redundant word line simultaneously. The first redundancy analysis circuit 100-0 limits the flexibility of separately performing redundancy replacement on the first memory bank 110-0 and the second memory bank 110-1. For example, if the first memory bank 110-0 and the second memory bank 110-1 share the first redundancy analysis circuit 100-0, and the first redundancy analysis circuit 100-0 is used to replace a word line wl in the first memory bank 110-0... <64> Replace with a redundant word line rwl <0> Then the word line wl in the second memory bank 110-1 <64> It will also be replaced with redundant word lines rwl <0> .

[0075] Therefore, circuit reuse is required without affecting the independent replacement of faulty memory cells, thereby saving area, improving the size of the memory device, and increasing the integration of the memory device.

[0076] In view of the above, embodiments of this application provide a memory device and its operation method, as well as a memory system.

[0077] In a first aspect, embodiments of this application provide a memory device, with reference to Figure 7 The memory device 10 includes: a first memory bank 110-0 and a second memory bank 110-1; and a redundancy analysis circuit 101 coupled to both the first memory bank 110-0 and the second memory bank 110-1; wherein the redundancy analysis circuit 101 includes: a redundancy circuit 103, which stores failure address information in the first memory bank 110-0 and the second memory bank 110-1; and is configured to output a failure address signal 12a based on the enable signal ACT_BK0 / ACT_BK1 of the first memory bank 110-0 or the second memory bank 110-1, the failure address signal 12a containing the failure address information of the first memory bank 110-0 or the second memory bank 110-1; and a matching circuit 104, coupled to the redundancy circuit 103, and configured to receive an activation address signal 10a and a failure address signal 12a, and match the activation address information in the activation address signal 10a with the failure address information in the failure address signal 12a, and output a matching address signal 14a.

[0078] The memory device 10, such as DRAM, may include multiple memory banks (including a first memory bank 110-0 and a second memory bank 110-1), for example, eight memory banks. The number of memory banks may also be less than eight or greater than eight. Each memory bank may include multiple memory arrays, for example, four memory arrays. The number of memory arrays may also be less than four or greater than four. For example, a DRAM with four memory arrays per memory bank may be represented as X4 DRAM.

[0079] A storage array may include a normal storage array and a redundant storage array. A portion of the storage array may be a normal storage array, and the remainder may be a redundant storage array. Redundant cells in the redundant storage array may be used to replace faulty cells in the normal storage array. Normal cells in the normal storage array can be characterized as accessible storage cells. The memory device may be configured such that, when redundancy is enabled, accessing a faulty cell in the normal storage array based on an active address signal will automatically switch to accessing a redundant cell in the redundant storage array used to replace the faulty cell. In other words, when redundancy is enabled, access to faulty cells is prohibited.

[0080] Redundancy analysis circuit 101 includes content addressable memory (CAM).

[0081] The redundant circuit 103 includes an internal register for storing address information of faulty units; for example, storing the failure address information of faulty units in the first memory bank 110-0 and the second memory bank 110-1.

[0082] The matching circuit 104 includes a comparison circuit for comparing the input activation address signal 10a with the failure address information 12a stored in the first memory bank 110-0 or the second memory bank 110-1 in the redundancy analysis circuit, and outputting a matching address signal 14a. The matching address signal 14a in a first state indicates that the input activation address has a failure address and needs to be replaced with a redundant address. When redundancy is enabled, accessing a failure unit based on the activation address signal will automatically switch to accessing the redundant unit corresponding to the failure unit used to replace it. In other words, when redundancy is enabled, access to the failure unit is prohibited. The matching address signal 14a in a second state indicates that the input activation address does not have a failure address and does not require redundancy replacement.

[0083] Here, the failure address signal 12a includes the failure address information of the faulty cell in the first memory bank 110-0 or the second memory bank 110-1.

[0084] Compared to each memory bank having independent redundant circuitry and matching circuitry (see reference) Figure 1 In the embodiments of this application, reference is made to... Figure 7 The first memory bank 110-0 and the second memory bank 110-1 can share the redundant circuit 103, which is used to store the failure address information in the first memory bank 110-0 and the second memory bank 110-1. The first memory bank 110-0 and the second memory bank 110-1 can share the matching circuit 104, which is used to compare the input activation address signal with the failure address information stored in the first memory bank 110-0 or the second memory bank 110-1 in the redundancy analysis circuit, and output the matching address signal.

[0085] For example, the redundancy circuit 103 outputs a failure address signal 12a based on the enable signal ACT_BK0 of the first memory bank 110-0. The failure address signal 12a contains the failure address information of the first memory bank 110-0. The matching circuit 104 receives the activation address signal 10a and the failure address signal 12a, and matches the activation address information in the activation address signal 10a with the failure address information in the failure address signal 12a, outputting a matching address signal 14a. The matching address signal 14a indicates whether the input activation address 10a has a failure address and is used to determine whether the failure address needs to be replaced with a redundant address. The matching address signal 14a and the activation address signal 10a are then processed by a decoding circuit (see reference). Figure 8 After decoding, it can be used to drive normal and / or redundant units in the first memory bank 110-0.

[0086] In this embodiment, the first and second memory banks of the memory device share a redundancy analysis circuit. For example, the first and second memory banks share a single redundancy analysis circuit. Due to circuit reuse, area can be saved, the size of the memory device can be improved, and the integration of the memory device can be increased. Furthermore, reducing a portion of the circuit will reduce the total power consumption and static leakage current of the memory device.

[0087] refer to Figure 8 In some embodiments, the memory device 10 further includes a decoding circuit, a first register 112-0, and a second register 112-1; the decoding circuit includes a first decoding circuit 106-0; wherein the first decoding circuit 106-0 is coupled to the redundancy analysis circuit 101 and is configured to receive an activation address signal 10a and a matching address signal 14a, and generate a first decoding signal 16a based on the activation address signal 10a and the matching address signal 14a; the first decoding signal 16a includes the first memory bank 110-0 / the second memory bank. The first register 110-1 contains normal address information to be activated and / or redundant address information to be activated; the second register 112-0 is coupled to the first decoding circuit 106-0 and is configured to store the first decoding signal 16a in response to the enable signal ACT_BK0 of the first storage bank 110-0 being in an enabled state; the third register 112-1 is coupled to the first decoding circuit 106-0 and is configured to store the first decoding signal 16a in response to the enable signal ACT_BK1 of the second storage bank 110-1 being in an enabled state.

[0088] The first decoding circuit 106-0 includes a row decoder for connection to a memory array of a memory device via word lines (including normal word lines nwl and / or redundant word lines rwl); the row decoder can select one of the word lines based on an address.

[0089] For example, the redundancy circuit 103 outputs a failure address signal 12a according to the enable signal ACT_BK0 of the first memory bank 110-0. The failure address signal 12a contains the failure address information of the first memory bank 110-0. The matching circuit 104 receives the activation address signal 10a and the failure address signal 12a, and matches the activation address information in the activation address signal 10a with the failure address information in the failure address signal 12a, and outputs a matching address signal 14a. The first decoding circuit 106-0 receives the activation address signal 10a and the matching address signal 14a, and generates a first decoding signal 16a according to the activation address signal 10a and the matching address signal 14a. The first register 112-0 is in an enabled state in response to the enable signal ACT_BK0 of the first memory bank 110-0, and stores the first decoding signal 16a. The first decoding signal 16a is used to drive the normal cells and / or redundant cells in the first memory bank 110-0.

[0090] In this embodiment, the redundancy analysis circuit and the decoding circuit can be shared by two memory banks (a first memory bank and a second memory bank). Since the two memory banks share one redundancy analysis circuit and decoding circuit, the circuit size is reduced and area is saved. When one of the memory banks (e.g., the first memory bank) is activated, the corresponding first register will store the first decoding signal output from the shared decoding circuit. Then, based on the first decoding signal, specific normal word lines and / or redundant word lines in the first memory bank are selected to drive the corresponding normal units and / or redundant units. The second register corresponding to the other inactive memory bank (e.g., the second memory bank) will not latch the first decoding signal output by the decoding circuit. This avoids or reduces the limitation on the flexibility of the first redundancy analysis circuit to perform redundancy replacement on the first memory bank and the second memory bank respectively, and can maintain the flexibility of the redundancy analysis circuit for redundancy replacement.

[0091] refer to Figure 8 In some embodiments, the first storage bank 110-0 is configured to be activated after the second register 112-1 has finished storing the first decoded signal 16a; or, the second storage bank 110-1 is configured to be activated after the first register 112-0 has finished storing the first decoded signal 16a.

[0092] In this embodiment, when one active memory bank (e.g., the first memory bank) uses the redundancy analysis circuit and the decoding circuit, another memory bank (e.g., the second memory bank) can use the redundancy analysis circuit and the decoding circuit after the first decoding signal output by the decoding circuit is latched by a register (e.g., the first register). This maintains the flexibility of the redundancy analysis circuit for redundancy replacement without incurring additional physical costs by reducing a portion of the circuitry.

[0093] refer to Figure 8 In some embodiments, the address signal to be activated 10a includes a first signal or a second signal. The first signal includes the address information to be activated in the first memory bank 110-0, and the second signal includes the address information to be activated in the second memory bank 110-1. The first decoding signal 16a includes a third signal or a fourth signal. The third signal includes the normal address information to be activated and / or the redundant address information to be activated in the first memory bank 110-1, and the fourth signal includes the normal address information to be activated and / or the redundant address information to be activated in the second memory bank 110-1. The redundancy analysis circuit 101 is configured to receive and store the first signal. In response to the first register 112-0 completing the storage of the third signal, the first decoding circuit 106-0 is configured to receive and store the second signal / first signal the next time. Alternatively, the redundancy analysis circuit 101 is configured to receive and store the second signal. In response to the second register 112-1 completing the storage of the fourth signal, the first decoding circuit 106-0 is configured to receive and store the first signal / second signal.

[0094] For example, the redundancy analysis circuit 101 receives and stores a first signal, and the first decoding circuit 106-0 generates a third signal; in response to the first register 112-0 completing the storage of the third signal, the redundancy analysis circuit 101 receives and stores a second signal in the next instance, and the first decoding circuit 106-0 generates a fourth signal, or the redundancy analysis circuit 101 still receives and stores the first signal in the next instance, and the first decoding circuit 106-0 generates a third signal.

[0095] In this embodiment, once the first decoding signal output by the decoding circuit is latched by any register, such as the first register, the redundancy analysis circuit and the decoding circuit can be released for decoding another activation command, such as for activating a second memory bank. This maintains the flexibility of the redundancy analysis circuit for redundancy replacement without incurring additional physical costs by reducing a portion of the circuitry.

[0096] refer to Figure 9In some embodiments, the memory device 10 further includes a decoding circuit; the decoding circuit includes a second decoding circuit 106-1 and a third decoding circuit 106-2; wherein the second decoding circuit 106-1 is coupled to the redundancy analysis circuit 101 and configured to, in response to the enable signal ACT_BK0 of the first memory bank 110-0 being enabled, receive an address signal 10a to be activated and a matching address signal 14a, and generate a second decoding signal 17a based on the address signal 10a to be activated and the matching address signal 14a; the second decoding signal 17a includes the first memory bank 110-0. The normal address information to be activated in 0-0, and / or the redundant address information to be activated; the third decoding circuit 106-2 is coupled to the redundancy analysis circuit 101 and is configured to receive the address signal to be activated 10a and the matching address signal 14a in response to the enable signal ACT_BK1 of the second memory bank 110-1 being in an enabled state, and generate the third decoding signal 19a according to the address to be activated 10a and the matching address signal 14a; the third decoding signal 19a includes the normal address information to be activated in the second memory bank 110-1, and / or the redundant address information to be activated.

[0097] The second decoding circuit 106-1 includes a row decoder for connection to the first memory bank 110-0 via word lines (including normal word lines nwl and / or redundant word lines rwl); the second decoding circuit 106-1 can select one of the word lines wl based on an address. The third decoding circuit 106-2 includes a row decoder for connection to the second memory bank 110-1 via word lines (including normal word lines nwl and / or redundant word lines rwl); the third decoding circuit 106-2 can select one of the word lines wl based on an address.

[0098] For example, the redundancy circuit 103 outputs a failure address signal 12a based on the enable signal ACT_BK0 of the first memory bank 110-0. The failure address signal 12a contains the failure address information of the first memory bank 110-0. The matching circuit 104 receives the activation address signal 10a and the failure address signal 12a, and matches the activation address information in the activation address signal 10a with the failure address information in the failure address signal 12a, and outputs a matching address signal 14a. The second decoding circuit 106-1 receives the activation address signal 10a and the matching address signal 14a based on the first memory bank 110-0 being in an enabled state according to the enable signal ACT_BK0, and generates a second decoding signal 17a based on the activation address signal 10a and the matching address signal 14a. The second decoding signal 17a is used to drive the normal cells and / or redundant cells in the first memory bank 110-0.

[0099] In this embodiment, the redundancy analysis circuit can be shared by two memory banks (a first memory bank and a second memory bank). Since the two memory banks share one redundancy analysis circuit, the circuit size is reduced, saving area. When a memory bank (e.g., the first memory bank) is activated, the corresponding second decoding circuit generates a second decoding signal based on the address signal to be activated and the matching address signal. Then, based on the second decoding signal, it selects specific normal word lines and / or redundant word lines in the first memory bank to drive the corresponding normal cells and / or redundant cells. The third decoding circuit corresponding to the other inactive memory bank (e.g., the second memory bank) does not receive the address signal to be activated and the matching address signal, and will not generate a third decoding signal for driving the normal cells and / or redundant cells of the second memory bank. This maintains the flexibility of the redundancy analysis circuit for redundancy replacement.

[0100] refer to Figure 10 and Figure 11 In some embodiments, the redundancy analysis circuit includes a row redundancy analysis circuit, which in turn includes a row redundancy circuit and a row matching circuit. The row redundancy circuit is configured to: store the corresponding failed row address information in the first memory bank 110-0 and the second memory bank 110-1, respectively, and output a failed row address signal `row_latch`, where `row_latch` contains the failed row address information corresponding to the memory bank to be activated in the first and second memory banks. The row matching circuit is configured to: receive the row address signal `row_address` to be activated, match the row address information in `row_address` with the failed row address information in `row_latch`, and output a matched row signal `row_red_code`. Decoding... The circuit includes a row decoding circuit, which is configured to receive a row address signal to be activated (row_address) and a matching row signal (row_red_code), and generate a first row decoding signal (row_predec_code), a second row decoding signal (row_predec_code0), and a third row decoding signal (row_predec_code1) based on the row address signal to be activated (row_address) and the matching row signal (row_red_code). The first row decoding signal (row_predec_code), the second row decoding signal (row_predec_code0), and the third row decoding signal (row_predec_code1) include the row address information to be activated in the first memory bank / the second memory bank, and / or the redundant row address information to be activated.

[0101] Here, for reference Figure 10 The decoding circuit includes a first decoding circuit, and the first decoding circuit 106-0 may include a first row decoding circuit; Reference Figure 11The decoding circuit includes a second decoding circuit and a third decoding circuit. The second decoding circuit 106-1 may include a second row decoding circuit, and the third decoding circuit 106-2 may include a third row decoding circuit.

[0102] refer to Figure 10 The row redundancy circuit, which stores the corresponding failed row address information in the first and second memory banks, is enabled according to the enable signal ACT_BK0 of the first memory bank 110-0 and outputs a failed row address signal row_latch, which contains the failed row address information corresponding to the first memory bank. The row matching circuit matches the activated row address information in the activated row address signal row_address with the failed row address information in the failed row address signal row_latch and outputs a matched row signal row_red_code. The first decoding circuit 106-0 (including the first row decoding circuit) receives the activated row address signal row_address and the matched row signal row_red_code and generates a first row decoding signal row_predec_code. The first row decoding signal row_predec_code includes the row address information to be activated in the first memory bank and / or the redundant row address information to be activated.

[0103] For example, the memory device generates an activation address signal row_address<14:0> based on the command address signal CA<7:0> sent to the first memory bank. The row redundancy circuit outputs a failure row address signal row_latch<14:0>. The row matching circuit receives the activation address signal row_address<14:0> and the failure row address signal row_latch<14:0> and outputs a matching row signal row_red_code<255:0>. The decoding circuit receives the activation address signal row_address<14:0> and the matching row signal row_red_code<255:0> and outputs a first row decoding signal row_predec_code<32768:0>. The first row decoding signal row_predec_code<32768:0> includes signals for driving the normal word line nwl<32768:0> and the redundant word line rwl<511:0> of the first memory bank.

[0104] It should be noted that the first line of decoding signal row_predec_code<32768:0> is used to automatically switch to accessing the redundant unit corresponding to the faulty unit when accessing the faulty unit based on the row address signal row_address<14:0> when redundancy is enabled. In other words, when redundancy is enabled, accessing the faulty unit is prohibited, and instead, the redundant unit corresponding to the faulty unit is accessed.

[0105] refer to Figure 10 and Figure 12 ,or Figure 11 and Figure 12 In some embodiments, the row redundancy circuit 103 includes a first latch circuit 1032 and a second latch circuit 1034; the row matching circuit 104 includes a comparator circuit 1042; the first latch circuit 1032 stores a first failed row address signal and is configured to output the stored first failed row address signal row_latch0 in response to the enable state of the first read signal rd_0; or, the second latch circuit 1034 stores a second failed row address signal and is configured to output the stored second failed row address signal row_latch1 in response to the enable state of the second read signal rd_1; the comparator circuit 1042 is configured to receive the row address signal to be activated row_address and the first failed row address signal row_latch0 / second failed row address signal row_latch1, and generate a matching row signal row_red_code.

[0106] refer to Figure 12 In some embodiments, the first latch circuit 1032 is further configured to store the first failed row address signal to be stored in response to the enable state of the first write signal wr_0; or, the second latch circuit 1034 is further configured to store the second failed row address signal to be stored in response to the enable state of the second write signal wr_0.

[0107] refer to Figure 10 and Figure 12 ,or Figure 11 and Figure 12 In some embodiments, the memory device 10 further includes a control circuit. Figure 10 , Figure 11 and Figure 12 (Not shown); The control circuit is configured to generate a first read signal rd_0 in response to the enable signal ACT_BK0 of the first memory bank, or to generate a second read signal rd_1 in response to the enable signal ACT_BK1 of the second memory bank.

[0108] refer to Figure 10 and Figure 12 ,or Figure 11 and Figure 12In some embodiments, the control circuit is further configured to generate a first failed row address signal row_latch0 and a first write signal wr_0 corresponding to the failed row in the first memory bank in response to the occurrence of a failed row (or faulty row) in the normal rows of the first memory bank; or, in response to the occurrence of a failed row in the normal rows of the second memory bank, generate a second failed row address signal row_latch1 and a second write signal wr_1 corresponding to the failed row in the second memory bank.

[0109] For example, when a faulty row (or malfunctioning row) appears in a normal row of the first memory bank, the memory device generates a first faulty row / malfunctioning row address signal row_address_bad0 (see reference). Figure 12 The first latch circuit 1032, in response to the enabled state of the first write signal wr_0, receives the first failed row / faulty row address signal row_address_bad0 and stores the first failed row address signal row_latch0. When a failed row (or faulty row) appears in a normal row in the second memory bank, the memory device generates a second failed row / faulty row address signal row_address_bad1 and a second write signal wr_1. The second latch circuit 1034, in response to the enabled state of the second write signal wr_1, receives the second failed row / faulty row address signal row_address_bad1 and stores the second failed row address signal row_latch1.

[0110] refer to Figure 13In some embodiments, the first latch circuit 1032 includes a first gate circuit G1, a first latch L1, and a second gate circuit G2; the second latch circuit 1034 includes a third gate circuit G3, a second latch L2, and a fourth gate circuit G4; the first gate circuit G1 is configured to receive a first failed row address signal to be stored and a first write signal wr_0, and in response to the enable state of the first write signal wr_0, transmit the first failed row address signal to be stored to the first latch L1; the first latch L1 is configured to receive and store the first failed row address signal to be stored / output the stored first failed row address signal row_latch0; the second gate circuit G2 is configured to receive the first failed row address signal row_latch0 stored by the first latch L1 and a first read signal rd_0, and in response to the enable state of the first read signal rd_0, transmit the first failed row address signal to be stored to the first latch L1. In the enable state, the first failed row address signal row_latch0 stored in the first latch L1 is transmitted to the comparator circuit 1042; or, the third gate circuit G3 is configured to receive the second failed row address signal to be stored and the second write signal wr_1, and in response to the enable state of the second write signal wr_1, transmit the second failed row address signal to be stored to the second latch L2; the second latch L2 is configured to receive and store the second failed row address signal to be stored / output the stored second failed row address signal row_latch1; the fourth gate circuit G4 is configured to receive the second failed row address signal stored in the second latch L2 and the second read signal rd_1, and in response to the enable state of the second read signal rd_1, transmit the second failed row address signal row_latch1 stored in the second latch L2 to the comparator circuit 1042.

[0111] The first gating circuit G1 includes an inverter. Its input receives the inverted signal (or the first failed row address signal row_latch0) of the row address signal to be activated (which contains the first failed row address information). Its control terminal receives a first write signal wr_0. In response to the enable state of the first write signal wr_0, its output terminal outputs the first failed row address signal row_latch0. The first latch L1 includes a cross-coupled inverter. Its input is connected to the output of the first gating circuit G1, and its output terminal is connected to the input of the second gating circuit G2. It is used to latch the first failed row address signal row_latch0. The second gating circuit G2 includes an inverter. Its input receives the first failed row address signal row_latch0 latched by the first latch L1. Its control terminal receives a first read signal rd_0. In response to the enable state of the first read signal rd_0, its output terminal outputs the first failed row address signal row_latch0.

[0112] The third gate circuit G3, the second latch L2, and the fourth gate circuit G4 of the second latch circuit can be referenced from the description of the specific settings of the first gate circuit G1, the first latch L1, and the second gate circuit G2.

[0113] refer to Figure 13 In some embodiments, the comparison circuit 1042 includes a transmission gate G6 and a fifth gate circuit G5; the transmission gate G6 is configured to receive the inverted signal of the row address to be activated signal row_address and the first failed row address signal row_latch0 / second failed row address signal row_latch1, and in response to the enabled state of the first failed row address signal row_latch0 / second failed row address signal row_latch1, generate a first state of the matching signal row_red_code; the first state of the matching signal row_red_code represents the match between the row address to be activated and the first failed row address. The failed row address that matches the first failed row address / the second failed row address; the fifth gate circuit G5 is configured to receive the inverted signal of the row address to be activated signal row_address and the inverted signal of the first failed row address signal / the second failed row address signal, and in response to the enabled state of the inverted signal of the first failed row address signal row_latch0 / the second failed row address signal row_latch1, the generated matching signal row_red_code is in the second state; the second state of the matching signal row_red_code represents the failed row address that does not match the first failed row address / the second failed row address among the row addresses to be activated.

[0114] Transmission gate G6 includes a PMOS transistor and an NMOS transistor connected in parallel. The input terminals of the PMOS transistor and the NMOS transistor receive the inverted signal of the row address signal to be activated, row_address. The control terminal of the PMOS transistor receives the inverted signals of the first failed row address signal, row_latch0, and the second failed row address signal, row_latch1. The control terminal of the NMOS transistor also receives the first failed row address signal, row_latch0, and the second failed row address signal, row_latch1. In response to the enabled state of the first failed row address signal, row_latch0, and the second failed row address signal, row_latch1, the output terminals of the PMOS transistor and the NMOS transistor output the row address signal to be activated, row_address, i.e., the matching signal, row_red_code, is in the first state.

[0115] The fifth gate circuit G5 includes an inverter. Its input receives the inverted signal of the row address signal to be activated, row_address. Its control terminal receives the inverted signals of the first failed row address signal, row_latch0, and the second failed row address signal, row_latch1. In response to the enabled state of the inverted signals of the first failed row address signal, row_latch0, and the second failed row address signal, row_latch1, its output terminal outputs the inverted signal of the row address signal to be activated, row_address. That is, the matching signal row_red_code is in the second state.

[0116] In some embodiments, the active row address signal `row_address` and the matching signal `row_red_code` have the same number of bits. For example, the redundancy analysis circuit 101 receives an n-bit active row address signal `row_address`. <n>Output n-bit matching signal row_red_code <n>, where n is a natural number.

[0117] In other embodiments, the comparison circuit includes a comparator ( Figure 13 A comparator (not shown) is configured to receive the row address signal to be activated (row_address) and the first failed row address signal (row_latch0) / the second failed row address signal (row_latch1), compare the row address signal to be activated (row_address) and the first failed row address signal (row_latch0) / the second failed row address signal (row_latch1), and output a matching signal (row_red_code); wherein, the first state representation of the matching signal (row_red_code) includes the failed row address in the row address to be activated that matches the first failed row address / the second failed row address, and the second state representation of the matching signal (row_red_code) includes the failed row address in the row address to be activated that does not match the first failed row address / the second failed row address.

[0118] For example, reference can be made to Figure 13 The comparison circuit 1042 in the text can be replaced with a comparator. The first input of the comparator receives the inverted signal of the row address signal to be activated, row_address, and the second input receives the first failed row address signal, row_latch0, and the second failed row address signal, row_latch1. The inverted signal of the row address signal to be activated, row_address, is compared with the first failed row address signal, row_latch0, and the second failed row address signal, row_latch1, and the matching signal, row_red_code, is output.

[0119] refer to Figure 10 and Figure 11 In some embodiments, the memory device further includes a first word line driver, a second word line driver, a third word line driver, and a fourth word line driver; the first word line driver is configured to receive an output signal from a decoding circuit and generate a first drive signal; the first drive signal is used to drive normal rows in the first memory bank; and / or, the second word line driver is configured to receive an output signal from a decoding circuit and generate a second drive signal; the second drive signal is used to drive redundant rows in the first memory bank; the third word line driver is configured to receive an output signal from a decoding circuit and generate a third drive signal; the third drive signal is used to drive normal rows in the second memory bank; and / or, the fourth word line driver is configured to receive an output signal from a decoding circuit and generate a fourth drive signal; the fourth drive signal is used to drive redundant rows in the second memory bank.

[0120] The first word line driving circuit 108-0 for driving the normal rows and / or redundant rows in the first memory bank includes a first word line driver and a second word line driver for controlling the voltage of selected word lines w1 connected to the normal rows and / or redundant rows in the first memory bank. The second word line driving circuit 108-1 for driving the normal rows and / or redundant rows in the second memory bank includes a third word line driver and a fourth word line driver for controlling the voltage of selected word lines w1 connected to the normal rows and / or redundant rows in the second memory bank.

[0121] Secondly, embodiments of this application provide a memory device, with reference to... Figure 14 and Figure 8 The memory device 10 includes: a first memory bank 110-0 and a second memory bank 110-1 disposed adjacent to each other; and a redundancy analysis circuit 101 located between the first memory bank 110-0 and the second memory bank 110-1 and coupled to both the first memory bank 110-0 and the second memory bank 110-1; wherein the redundancy analysis circuit 101 includes: a redundancy circuit 103, which stores failure address information in the first memory bank 110-0 and the second memory bank 110-1; and is configured to, based on the first memory bank 110-0 or the second memory bank 110-1, perform a redundancy analysis on the failure address information. The enable signal ACT_BK0 / ACT_BK1 of memory bank 110-1 outputs a failure address signal 12a, which contains failure address information of the first memory bank 110-0 or the second memory bank 110-1. The matching circuit 104 is coupled to the redundancy circuit 103 and is configured to receive the activation address signal 10a and the failure address signal 12a, match the activation address information in the activation address signal 10a with the failure address information in the failure address signal 12a, and output a matching address signal 14a.

[0122] refer to Figure 14 and Figure 8 In some embodiments, the memory device 10 further includes a decoding circuit, a first register 112-0, and a second register 112-1; the decoding circuit includes a first decoding circuit 106-0; wherein the first decoding circuit 106-0 is located between the first memory bank 110-0 and the second memory bank 110-1 and coupled to the redundancy analysis circuit 101, and is configured to receive an address signal to be activated 10a and a matching address signal 14a, and generate a first decoding signal 16a based on the address signal to be activated 10a and the matching address signal 14a; the first decoding signal 16a includes normal address information to be activated in the first memory bank 110-0 / second memory bank 110-1, and / or address information to be activated. Activated redundant address information; a first register 112-0, located between and coupled to the first decoding circuit 106-0 and the first storage bank 110-0, and configured to store the first decoding signal 16a in response to the enable signal ACT_BK0 of the first storage bank 110-0 being in an enabled state; a second register 112-1, located between and coupled to the first decoding circuit 106-0 and the first storage bank 110-0, and configured to store the first decoding signal 16a in response to the enable signal ACT_BK1 of the second storage bank being in an enabled state.

[0123] refer to Figure 3 The first memory bank 110-0 and the second memory bank 110-1 each have their own independent decoding circuits. The decoding circuit located between the first memory bank 110-0 and the second memory bank 110-1 (such as the first redundancy analysis circuit 100-0 and the second redundancy analysis circuit 100-1) occupies a considerable portion of the area. The first distance D1 between the first memory bank 110-0 and the second memory bank 110-1 is large, which hinders the improvement of the size of the memory device.

[0124] refer to Figure 14 The first memory bank 110-0 and the second memory bank 110-1 can share the redundancy analysis circuit 101 and the first decoding circuit 106-0. The area occupied by the redundancy analysis circuit 101 and the first decoding circuit 106-0 located between the first memory bank 110-0 and the second memory bank 110-1 is reduced. The second distance D2 between the first memory bank 110-0 and the second memory bank 110-1 is smaller than the first distance D1 (for comparison). Figure 3 This improves the size of memory devices.

[0125] Compared to reference Figure 4 The memory device shown in this application embodiment has a redundancy analysis circuit and a decoding circuit that can be shared by two memory banks (a first memory bank and a second memory bank). Since the two memory banks share a redundancy analysis circuit and a decoding circuit, the distance between the memory banks is reduced.

[0126] refer to Figure 14 and Figure 8 In some embodiments, the memory device 10 further includes a first word line driver and a second word line driver located between the first register 112-0 and the first memory bank 110-0, and a third word line driver and a fourth word line driver located between the second register 112-1 and the second memory bank 110-1; the first word line driver is configured to receive an output signal from the decoding circuit and generate a first drive signal; the first drive signal is used to drive normal rows in the first memory bank; and / or, the second word line driver is configured to receive an output signal from the decoding circuit and generate a second drive signal; the second drive signal is used to drive redundant rows in the first memory bank; the third word line driver is configured to receive an output signal from the decoding circuit and generate a third drive signal; the third drive signal is used to drive normal rows in the second memory bank; and / or, the fourth word line driver is configured to receive an output signal from the decoding circuit and generate a fourth drive signal; the fourth drive signal is used to drive redundant rows in the second memory bank.

[0127] refer to Figure 15 and Figure 9 In some embodiments, the memory device 10 further includes a decoding circuit; the decoding circuit includes a second decoding circuit 106-1 and a third decoding circuit 106-2; wherein, the second decoding circuit 106-1 is located between the first memory bank 110-0 and the second memory bank 110-1 and coupled to the redundancy analysis circuit 101, and is configured to receive a target address signal 10a and a matching address signal 14a in response to the enable signal ACT_BK0 of the first memory bank 110-0 being enabled, and generate a second decoding signal 17a based on the target address signal 10a and the matching address signal 14a; the second decoding signal 17a includes the first memory bank 110-0. The normal address information to be activated in 0-0, and / or the redundant address information to be activated; the third decoding circuit 106-2, located between the first memory bank 110-0 and the second memory bank 110-1 and coupled to the redundancy analysis circuit 101, is configured to receive the address signal to be activated 10a and the matching address signal 14a in response to the enable signal ACT_BK1 of the second memory bank 110-1 being enabled, and generate the third decoding signal 19a according to the address to be activated 10a and the matching address signal 14a; the third decoding signal 19a includes the normal address information to be activated in the second memory bank 110-1 and / or the redundant address information to be activated.

[0128] refer to Figure 15 The first memory bank 110-0 and the second memory bank 110-1 can share the redundancy analysis circuit 101. The area occupied by the redundancy analysis circuit 101, the second decoding circuit 106-1, and the third decoding circuit 106-2 located between the first memory bank 110-0 and the second memory bank 110-1 is reduced. The third distance D3 between the first memory bank 110-0 and the second memory bank 110-1 is smaller than the first distance D1 (for comparison). Figure 3 This improves the size of memory devices.

[0129] Compared to reference Figure 3 The redundancy analysis circuit of the memory device shown in the embodiment of this application can be shared by two memory banks (a first memory bank and a second memory bank). Since the two memory banks share a redundancy analysis circuit, the distance between the memory banks is reduced.

[0130] refer to Figure 15 and Figure 9 In some embodiments, the memory device 10 further includes a first word line driver and a second word line driver located between the redundancy analysis circuit 101, the second decoding circuit 106-1, and the first memory bank 110-0; and a third word line driver and a fourth word line driver located between the redundancy analysis circuit 101, the third decoding circuit 106-2, and the second memory bank 110-1; the first word line driver is configured to receive the output signal of the decoding circuit and generate a first drive signal; the first drive signal is used to drive normal rows in the first memory bank; and / or, the second word line driver is configured to receive the output signal of the decoding circuit and generate a second drive signal; the second drive signal is used to drive redundant rows in the first memory bank; the third word line driver is configured to receive the output signal of the decoding circuit and generate a third drive signal; the third drive signal is used to drive normal rows in the second memory bank; and / or, the fourth word line driver is configured to receive the output signal of the decoding circuit and generate a fourth drive signal; the fourth drive signal is used to drive redundant rows in the second memory bank.

[0131] In this embodiment, under the premise of ensuring the redundancy analysis function is normal, the first and second memory banks of the memory device share the redundancy analysis circuit. Due to circuit reuse, area can be saved, the distance between memory banks can be reduced, thereby improving the size of the memory device and increasing the integration of the memory device. Furthermore, reducing a portion of the circuit will reduce the total power consumption and static leakage current of the memory device.

[0132] In the embodiments of this application, when one of the two memory banks (e.g., the first memory bank) is activated, the corresponding first register will store the first decoding signal output from the shared decoding circuit. Then, based on the first decoding signal, specific normal word lines and / or redundant word lines in the first memory bank are selected to drive the corresponding normal units and / or redundant units. The second register corresponding to the other inactive memory bank (e.g., the second memory bank) will not latch the first decoding signal output from the decoding circuit. This avoids or reduces the limitation on the flexibility of the first redundancy analysis circuit 100-0 to perform redundancy replacement on the first memory bank 110-0 and the second memory bank 110-1, respectively, and can maintain the flexibility of the redundancy analysis circuit for redundancy replacement.

[0133] In some embodiments, the memory device of any of the above embodiments includes dynamic random access memory.

[0134] Figure 16 This is a schematic diagram of the composition structure of an exemplary dynamic random access memory according to an embodiment of this application. Figure 16 The right side shows the circuitry of a memory cell in a DRAM. A DRAM comprises at least one DRAM die, and each DRAM die includes a memory cell array. The memory cell array contains multiple memory cells 201 arranged in an array. Each memory cell 201 includes a transistor T and a capacitor C. The primary function of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cell array uses row and column addresses to specify addresses. By specifying the intersection of the row and column (by specifying the row and column addresses of the DRAM), the memory controller can independently access each memory cell in the DRAM chip and perform read, write, or refresh operations on the stored data.

[0135] Figure 16 The left side shows the memory cell array and some peripheral circuitry in a DRAM. It's important to note that the row decoding circuit, in response to an address input to it, selects a word line to choose the row of the memory cell to access. The row decoding circuit decodes the input address and enables (activates) the word line corresponding to the decoded address. The column decoding circuit selects one or more bit lines to input our output data into a portion of the row of the memory cell corresponding to the selected word line.

[0136] Thirdly, embodiments of this application provide a memory system, with reference to Figure 17 The memory system 30 includes: one or more memory devices 10 as provided in the first aspect; and a memory controller 20 coupled to and controlling the memory devices 10.

[0137] In some embodiments, the memory device 10 includes DRAM, Synchronous Dynamic Random-Access Memory (SDRAM), or Double-Data-Rate Fourth Generation Synchronous Dynamic Random-Access Memory (DDR4 SDRAM). In some embodiments, the memory device 10 may further include Static Random-Access Memory (SRAM).

[0138] In some embodiments, the memory controller 20 may control the overall operation of the memory system 30, such as write operations, read operations, and refresh operations. In some specific embodiments, the memory controller 20 is configured to store data in the memory device 10, or to read data stored in the memory device 10.

[0139] In some embodiments, the memory controller 20 is also configured to store various information required for the operation of the memory system 30 (e.g., metadata information and mapping tables) into the memory device 10, and to access the non-volatile memory device based on the information stored in the memory device 10.

[0140] Fourthly, embodiments of this application provide an operation method for a memory device, the memory device including a first memory bank and a second memory bank, and a redundancy analysis circuit coupled to both the first memory bank and the second memory bank; the operation method includes: a redundancy circuit of the redundancy analysis circuit storing failure address information in the first memory bank and the second memory bank; outputting a failure address signal according to an enable signal of the first memory bank or the second memory bank, the failure address signal containing failure address information of the first memory bank or the second memory bank; and a matching circuit of the redundancy analysis circuit coupled to the redundancy circuit receiving an activation address signal and a failure address signal, matching the activation address information in the activation address signal with the failure address information in the failure address signal, and outputting a matching address signal.

[0141] In some embodiments, the operation method further includes: a first decoding circuit coupled to a redundancy analysis circuit receiving an address signal to be activated and a matching address signal, and generating a first decoding signal based on the address signal to be activated and the matching address signal; the first decoding signal includes normal address information to be activated in a first memory bank / second memory bank, and / or redundant address information to be activated; in response to an enable signal of the first memory bank, a first register coupled to the first decoding circuit stores the first decoding signal; in response to an enable signal of the second memory bank, a second register coupled to the first decoding circuit stores the first decoding signal.

[0142] In some embodiments, the operation method includes: activating a first storage bank in response to the second register completing the storage of the first decoded signal; or activating a second storage bank in response to the first register completing the storage of the first decoded signal.

[0143] In some embodiments, the operation method further includes: a redundancy analysis circuit receiving and storing a first signal; in response to the first register completing the storage of a third signal, the next time a second signal / first signal is received and stored, the decoding circuit generates a fourth signal / third signal; or, a redundancy analysis circuit receiving and storing a second signal; in response to the second register completing the storage of a fourth signal, the first signal / second signal being received and stored, the decoding circuit generating a third signal / fourth signal; wherein, the address signal to be activated includes either the first signal or the second signal, the first signal including address information to be activated in the first memory, and the second signal including address information to be activated in the second memory; the first decoding signal includes either the third signal or the fourth signal, the third signal including normal address information to be activated and / or redundant address information to be activated in the first memory, and the fourth signal including normal address information to be activated and / or redundant address information to be activated in the second memory.

[0144] In some embodiments, the operation method further includes: in response to the enable signal of the first memory being enabled, a second decoding circuit coupled to the redundancy analysis circuit receives an address signal to be activated and a matching address signal, and generates a second decoding signal based on the address signal to be activated and the matching address signal; the second decoding signal includes normal address information to be activated in the first memory and / or redundant address information to be activated; in response to the enable signal of the second memory being enabled, a third decoding circuit coupled to the redundancy analysis circuit receives the address signal to be activated and the matching address signal, and generates a third decoding signal based on the address signal to be activated and the matching address signal; the third decoding signal includes normal address information to be activated in the second memory and / or redundant address information to be activated.

[0145] In some embodiments, the operation method includes: a row redundancy circuit storing corresponding failed row address information in a first memory bank and a second memory bank respectively, and outputting a failed row address signal, wherein the failed row address signal includes the failed row address information corresponding to one of the first and second memory banks to be activated; a row matching circuit receiving the row address signal to be activated, matching the row address information to be activated in the row address signal with the failed row address information in the failed row address signal, and outputting a matched row signal; a row decoding circuit receiving the row address signal to be activated and the matched row signal, and generating a first row decoding signal / a second row decoding signal / a third row decoding signal according to the row address signal to be activated and the matched row signal; the first row decoding signal / a second row decoding signal / a third row decoding signal includes the row address information to be activated in the first memory bank / the second memory bank, and / or the redundant row address information to be activated; wherein, the redundancy analysis circuit includes a row redundancy analysis circuit, the row redundancy analysis circuit includes a row redundancy circuit and a row matching circuit, and the decoding circuit includes a row decoding circuit.

[0146] In some embodiments, the operation method includes: in response to an enabled state of a first read signal, storing a first failed row address signal stored by a first latch circuit outputting a first failed row address signal; or, in response to an enabled state of a second read signal, storing a second failed row address signal stored by a second latch circuit outputting a second failed row address signal; a comparison circuit receives a row address signal to be activated and the first failed row address signal / second failed row address signal, and generates a matching signal; wherein the row redundancy circuit includes a first latch circuit and a second latch circuit; and the row matching circuit includes a comparison circuit.

[0147] In some embodiments, the operation method includes: in response to the enabled state of a first write signal, a first latch circuit stores a first failed row address signal to be stored; or, in response to the enabled state of a second write signal, a second latch circuit stores a second failed row address signal to be stored.

[0148] In some embodiments, the operation method further includes: in response to an enable signal of a first memory bank, the control circuit generates a first read signal, or in response to an enable signal of a second memory bank, the control circuit generates a second read signal; wherein the memory device includes a control circuit.

[0149] In some embodiments, the operation method further includes: in response to a failed row appearing in a normal row in a first memory bank, the control circuit generates a first failed row address signal and a first write signal corresponding to the failed row in the first memory bank; or, in response to a failed row appearing in a normal row in a second memory bank, the control circuit generates a second failed row address signal and a second write signal corresponding to the failed row in the second memory bank.

[0150] In some embodiments, the first latch circuit includes a first gating circuit, a first latch, and a second gating circuit; the second latch circuit includes a third gating circuit, a second latch, and a fourth gating circuit; the operation method further includes: the first gating circuit receiving a first failed row address signal to be stored and a first write signal, and in response to the enabled state of the first write signal, transmitting the first failed row address signal to be stored to the first latch; the first latch receiving and storing the first failed row address signal to be stored / outputting the stored first failed row address signal; the second gating circuit receiving the first failed row address signal stored in the first latch and a first read signal, and in response to the first write signal's enable state, transmitting the first failed row address signal to be stored to the first latch; the first latch receiving and storing the first failed row address signal to be stored / outputting the stored first failed row address signal; the second gating circuit receiving the first failed row address signal stored in the first latch and a first read signal, and in response to the first write signal's enable state, transmitting the first failed row address signal to be stored to the first latch; the second latch receiving and storing the first failed row address signal to be stored ... to the first latch; the second gating circuit receiving the first failed row address signal stored in the first latch and a first read signal, and in response to the first write signal's enable state, transmitting the first failed row address signal to be stored to the first latch; the second latch receiving and storing the first failed row address signal to be stored to the first latch; the second latch receiving and storing the first failed row address signal to be stored to When the read signal is enabled, the first failed row address signal stored in the first latch is transmitted to the comparator circuit; or, the third gating circuit receives the second failed row address signal to be stored and the second write signal, and in response to the enable state of the second write signal, transmits the second failed row address signal to be stored to the second latch; the second latch receives and stores the second failed row address signal to be stored / outputs the stored second failed row address signal; the fourth gating circuit receives the second failed row address signal stored in the second latch and the second read signal, and in response to the enable state of the second read signal, transmits the second failed row address signal stored in the second latch to the comparator circuit.

[0151] In some embodiments, the comparison circuit includes a transmission gate and a fifth gating circuit; the operation method further includes: the transmission gate receiving the inverted signal of the row address signal to be activated and the first failed row address signal / second failed row address signal, and generating a first state of the matching signal in response to the enabled state of the first failed row address signal / second failed row address signal; the first state of the matching signal represents the failed row address in the row address to be activated that matches the first failed row address / second failed row address; the fifth gating circuit receiving the inverted signal of the row address signal to be activated and the inverted signal of the first failed row address signal / second failed row address signal, and generating a matching signal in a second state in response to the enabled state of the inverted signal of the first failed row address signal / second failed row address signal; the second state of the matching signal represents the failed row address in the row address to be activated that does not match the first failed row address / second failed row address.

[0152] In some embodiments, the memory device further includes a first word line driver, a second word line driver, a third word line driver, and a fourth word line driver; the operation method further includes: the first word line driver receiving an output signal from a decoding circuit and generating a first driving signal; the first driving signal being used to drive normal rows in a first memory bank; and / or, the second word line driver receiving an output signal from a decoding circuit and generating a second driving signal; the second driving signal being used to drive redundant rows in the first memory bank; the third word line driver receiving an output signal from a decoding circuit and generating a third driving signal; the third driving signal being used to drive normal rows in a second memory bank; and / or, the fourth word line driver receiving an output signal from a decoding circuit and generating a fourth driving signal; the fourth driving signal being used to drive redundant rows in the second memory bank.

[0153] The memory devices used in the operation methods of the memory devices provided in the embodiments of the fourth aspect of this application are the same as or similar to the memory devices in the embodiments of the first aspect described above. For technical features not disclosed in detail in the embodiments of this application, please refer to the memory devices in the embodiments of the first aspect described above for understanding, and they will not be repeated here.

[0154] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0155] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.< / n> < / n>

Claims

1. A memory device, characterized in that, include: First storage and second storage; as well as, A redundancy analysis circuit coupled to both the first memory bank and the second memory bank; wherein the redundancy analysis circuit includes: A redundant circuit stores failure address information in the first memory bank and the second memory bank; and is configured to output a failure address signal based on an enable signal of the first memory bank or the second memory bank, the failure address signal containing failure address information of the first memory bank or the second memory bank. A matching circuit, coupled to the redundant circuit, is configured to receive an activation address signal and a failure address signal, match the activation address information in the activation address signal with the failure address information in the failure address signal, and output a matching address signal.

2. The memory device according to claim 1, characterized in that, The memory device further includes a decoding circuit, a first register, and a second register; the decoding circuit includes a first decoding circuit; wherein... The first decoding circuit is coupled to the redundancy analysis circuit and is configured to receive the address signal to be activated and the matching address signal, and generate a first decoding signal based on the address signal to be activated and the matching address signal; the first decoding signal includes normal address information to be activated in the first memory bank / second memory bank, and / or redundant address information to be activated. The first register is coupled to the first decoding circuit and is configured to store the first decoding signal in response to an enable signal of the first memory bank. The second register, coupled to the first decoding circuit, is configured to store the first decoding signal in response to an enable signal of the second memory bank.

3. The memory device according to claim 2, characterized in that, The first storage bank is configured to be activated in response to the second register completing the storage of the first decoded signal; or, the second storage bank is configured to be activated in response to the first register completing the storage of the first decoded signal.

4. The memory device according to claim 3, characterized in that, The address signal to be activated includes a first signal or a second signal, wherein the first signal includes address information to be activated in the first memory, and the second signal includes address information to be activated in the second memory; the first decoding signal includes a third signal or a fourth signal, wherein the third signal includes normal address information to be activated and / or redundant address information to be activated in the first memory, and the fourth signal includes normal address information to be activated and / or redundant address information to be activated in the second memory; The redundancy analysis circuit is configured to receive and store the first signal, and in response to the first register completing the storage of the third signal, to receive and store the second signal / first signal again, and the first decoding circuit is configured to generate the fourth signal / third signal; or, the redundancy analysis circuit is configured to receive and store the second signal, and in response to the second register completing the storage of the fourth signal, to receive and store the first signal / second signal, and the first decoding circuit is configured to generate the third signal / fourth signal.

5. The memory device according to claim 1, characterized in that, The memory device further includes a decoding circuit; the decoder circuit includes a second decoding circuit and a third decoding circuit; wherein... The second decoding circuit is coupled to the redundancy analysis circuit and is configured to receive the address signal to be activated and the matching address signal in response to the enable signal of the first memory bank being enabled, and generate a second decoding signal based on the address signal to be activated and the matching address signal; the second decoding signal includes normal address information to be activated in the first memory bank and / or redundant address information to be activated. The third decoding circuit is coupled to the redundancy analysis circuit and is configured to receive the address signal to be activated and the matching address signal in response to the enable signal of the second memory bank being in an enabled state, and generate a third decoding signal based on the address signal to be activated and the matching address signal; the third decoding signal includes normal address information to be activated in the second memory bank and / or redundant address information to be activated.

6. The memory device according to claim 2 or 5, characterized in that, The redundancy analysis circuit includes a row redundancy analysis circuit, which further includes a row redundancy circuit and a row matching circuit; wherein... The row redundancy circuit is configured to store the corresponding failed row address information in the first memory bank and the second memory bank respectively, and output a failed row address signal, wherein the failed row address signal contains the failed row address information corresponding to one of the memory banks to be activated in the first memory bank and the second memory bank; The row matching circuit is configured to receive the row address signal to be activated, match the row address information to be activated in the row address signal with the invalid row address information in the invalid row address signal, and output a matching row signal; The decoding circuit includes a row decoding circuit, which is configured to receive the row address signal to be activated and the matching row signal, and generate a first row decoding signal, a second row decoding signal, and a third row decoding signal based on the row address signal to be activated and the matching row signal. The first row decoding signal, the second row decoding signal, and the third row decoding signal include the row address information to be activated in the first memory bank, the second memory bank, and / or the redundant row address information to be activated.

7. The memory device according to claim 6, characterized in that, The row redundancy circuit includes a first latch circuit and a second latch circuit; the row matching circuit includes a comparison circuit. The first latch circuit stores a first failed row address signal and is configured to output the stored first failed row address signal in response to the enable state of the first read signal; or, the second latch circuit stores a second failed row address signal and is configured to output the stored second failed row address signal in response to the enable state of the second read signal. The comparison circuit is configured to receive the row address signal to be activated and the first failed row address signal / second failed row address signal, and generate the matching row signal.

8. The memory device according to claim 7, characterized in that, The first latch circuit is further configured to store the first failed row address signal to be stored in response to the enable state of the first write signal; or, the second latch circuit is further configured to store the second failed row address signal to be stored in response to the enable state of the second write signal.

9. The memory device according to claim 8, characterized in that, The memory device also includes a control circuit; The control circuit is configured to generate the first read signal in response to an enable signal of the first memory bank, or to generate the second read signal in response to an enable signal of the second memory bank.

10. The memory device according to claim 9, characterized in that, The control circuit is further configured to, in response to the occurrence of a failed row in a normal row in the first memory bank, generate a first failed row address signal and a first write signal corresponding to the failed row in the first memory bank, or, in response to the occurrence of a failed row in a normal row in the second memory bank, generate a second failed row address signal and a second write signal corresponding to the failed row in the second memory bank.

11. The memory device according to claim 10, characterized in that, The first latch circuit includes a first gate circuit, a first latch, and a second gate circuit; the second latch circuit includes a third gate circuit, a second latch, and a fourth gate circuit. The first gating circuit is configured to receive the first failed row address signal to be stored and the first write signal, and in response to the enabled state of the first write signal, transmit the first failed row address signal to be stored to the first latch. The first latch is configured to receive and store the first failed row address signal to be stored / output the stored first failed row address signal; the second gating circuit is configured to receive the first failed row address signal stored in the first latch and the first read signal, and in response to the enable state of the first read signal, transmit the first failed row address signal stored in the first latch to the comparison circuit. or, The third gating circuit is configured to receive the second failed row address signal to be stored and the second write signal, and in response to the enabled state of the second write signal, transmit the second failed row address signal to be stored to the second latch; the second latch is configured to receive and store the second failed row address signal to be stored / output the stored second failed row address signal; the fourth gating circuit is configured to receive the second failed row address signal stored in the second latch and the second read signal, and in response to the enabled state of the second read signal, transmit the second failed row address signal stored in the second latch to the comparison circuit.

12. The memory device according to claim 10, characterized in that, The comparison circuit includes a transmission gate and a fifth gate control circuit; The transmission gate is configured to receive the inverse signal of the row address signal to be activated and the first failed row address signal / second failed row address signal, and generate a first state of the matching signal in response to the enable state of the first failed row address signal / second failed row address signal; the first state of the matching signal represents the failed row address in the row address to be activated that matches the first failed row address / second failed row address. The fifth gating circuit is configured to receive the inverted signal of the row address signal to be activated and the inverted signal of the first failed row address signal / the second failed row address signal, and in response to the enabled state of the inverted signal of the first failed row address signal / the second failed row address signal, the generated matching signal is in a second state; the second state of the matching signal represents the failed row address in the row address to be activated that does not match the first failed row address / the second failed row address.

13. The memory device according to claim 2 or 5, characterized in that, The memory device further includes a first word line driver, a second word line driver, a third word line driver, and a fourth word line driver; The first word line driver is configured to receive the output signal of the decoding circuit and generate a first drive signal; The first drive signal is used to drive the normal row in the first memory bank; and / or, the second word line driver is configured to receive the output signal of the decoding circuit and generate the second drive signal; The second drive signal is used to drive the redundant rows in the first memory bank; The third word line driver is configured to receive the output signal of the decoding circuit and generate a third driving signal; The third drive signal is used to drive the normal row in the second memory bank; and / or, the fourth word line driver is configured to receive the output signal of the decoding circuit and generate the fourth drive signal; The fourth drive signal is used to drive the redundant rows in the second memory bank.

14. A memory device, characterized in that, include: The first and second storage units are arranged adjacent to each other; as well as, A redundancy analysis circuit located between and coupled to both the first and second memory banks; wherein the redundancy analysis circuit includes: A redundant circuit stores failure address information in the first memory bank and the second memory bank; and is configured to output a failure address signal based on an enable signal of the first memory bank or the second memory bank, the failure address signal containing failure address information of the first memory bank or the second memory bank. A matching circuit, coupled to the redundant circuit, is configured to receive an activation address signal and a failure address signal, match the activation address information in the activation address signal with the failure address information in the failure address signal, and output a matching address signal.

15. The memory device according to claim 14, characterized in that, The memory device further includes a decoding circuit, a first register, and a second register; the decoding circuit includes a first decoding circuit; wherein... The first decoding circuit is located between the first memory bank and the second memory bank and coupled to the redundancy analysis circuit, and is configured to receive the address signal to be activated and the matching address signal, and generate a first decoding signal based on the address signal to be activated and the matching address signal; the first decoding signal includes normal address information to be activated in the first memory bank / second memory bank, and / or redundant address information to be activated. The first register is located between and coupled to the first decoding circuit and the first memory bank, and is configured to store the first decoding signal in response to an enable signal of the first memory bank being in an enabled state. The second register is located between the redundancy analysis circuit, the first decoding circuit and the second memory bank and is coupled to the first decoding circuit, and is configured to store the first decoding signal in response to the enable signal of the second memory bank being in an enabled state.

16. The memory device according to claim 15, characterized in that, The memory device further includes a first word line driver and a second word line driver located between the first register and the first memory bank, and a third word line driver and a fourth word line driver located between the second register and the second memory bank. The first word line driver is configured to receive the output signal of the decoding circuit and generate a first drive signal; The first drive signal is used to drive the normal row in the first memory bank; and / or, the second word line driver is configured to receive the output signal of the decoding circuit and generate the second drive signal; The second drive signal is used to drive the redundant rows in the first memory bank; The third word line driver is configured to receive the output signal of the decoding circuit and generate a third driving signal; The third drive signal is used to drive the normal row in the second memory bank; and / or, the fourth word line driver is configured to receive the output signal of the decoding circuit and generate the fourth drive signal; The fourth drive signal is used to drive the redundant rows in the second memory bank.

17. The memory device according to claim 14, characterized in that, The memory device further includes a decoding circuit; the decoding circuit includes a second decoding circuit and a third decoding circuit; wherein... The second decoding circuit is located between the first memory bank and the second memory bank and coupled to the redundancy analysis circuit. It is configured to receive the address signal to be activated and the matching address signal in response to the enable signal of the first memory bank being enabled, and generate a second decoding signal based on the address signal to be activated and the matching address signal. The second decoding signal includes normal address information to be activated in the first memory bank and / or redundant address information to be activated. The third decoding circuit is located between the first memory bank and the second memory bank and coupled to the redundancy analysis circuit. It is configured to receive the address signal to be activated and the matching address signal in response to the enable signal of the second memory bank being enabled, and generate a third decoding signal based on the address signal to be activated and the matching address signal. The third decoding signal includes normal address information to be activated in the second memory bank and / or redundant address information to be activated.

18. The memory device according to claim 17, characterized in that, The memory device further includes a first word line driver and a second word line driver located between the redundancy analysis circuit, the second decoding circuit and the first memory bank, as well as a third word line driver and a fourth word line driver located between the redundancy analysis circuit, the third decoding circuit and the second memory bank. The first word line driver is configured to receive the output signal of the decoding circuit and generate a first drive signal; The first drive signal is used to drive the normal row in the first memory bank; and / or, the second word line driver is configured to receive the output signal of the decoding circuit and generate the second drive signal; The second drive signal is used to drive the redundant rows in the first memory bank; The third word line driver is configured to receive the output signal of the decoding circuit and generate a third driving signal; The third drive signal is used to drive the normal row in the second memory bank; and / or, the fourth word line driver is configured to receive the output signal of the decoding circuit and generate the fourth drive signal; The fourth drive signal is used to drive the redundant rows in the second memory bank.

19. A memory system, characterized in that, include: One or more memory devices as described in any one of claims 1 to 13; as well as A memory controller, which is coupled to and controls the memory device.

20. A method of operating a memory device, characterized in that, The memory device includes a first memory bank and a second memory bank, and a redundancy analysis circuit coupled to both the first memory bank and the second memory bank; the operation method includes: The redundancy analysis circuit stores the failure address information in the first memory bank and the second memory bank; according to the enable signal of the first memory bank or the second memory bank, it outputs a failure address signal, the failure address signal containing the failure address information of the first memory bank or the second memory bank; The matching circuit of the redundancy analysis circuit coupled to the redundancy circuit receives the address signal to be activated and the address signal to fail, and matches the address information to be activated in the address signal to be activated with the address information to fail in the address signal to fail, and outputs the matching address signal.

21. The operating method according to claim 20, characterized in that, The operation method further includes: The first decoding circuit coupled to the redundancy analysis circuit receives the address signal to be activated and the matching address signal, and generates a first decoding signal based on the address signal to be activated and the matching address signal; the first decoding signal includes normal address information to be activated in the first memory bank / second memory bank, and / or redundant address information to be activated. In response to the enable signal of the first memory, the first register coupled to the first decoding circuit stores the first decoding signal; In response to the enable signal of the second memory, the second register coupled to the first decoding circuit stores the first decoding signal.

22. The operating method according to claim 21, characterized in that, The operation method includes: The first storage is activated in response to the second register completing the storage of the first decoded signal; or, the second storage is activated in response to the first register completing the storage of the first decoded signal.

23. The operating method according to claim 21, characterized in that, The operation method further includes: The redundancy analysis circuit receives and stores a first signal. In response to the first register completing the storage of a third signal, the first decoding circuit receives and stores a second signal / first signal for the next time. Alternatively, the redundancy analysis circuit receives and stores a second signal. In response to the second register completing the storage of the fourth signal, the first decoding circuit receives and stores the first signal / second signal. Wherein, the address signal to be activated includes either the first signal or the second signal, the first signal including address information to be activated in the first memory, and the second signal including address information to be activated in the second memory; the first decoding signal includes either the third signal or the fourth signal, the third signal including normal address information to be activated and / or redundant address information to be activated in the first memory, and the fourth signal including normal address information to be activated and / or redundant address information to be activated in the second memory.

24. The operating method according to claim 20, characterized in that, The operation method further includes: In response to the enable signal of the first memory bank being enabled, the second decoding circuit of the decoding circuit coupled to the redundancy analysis circuit receives the address signal to be activated and the matching address signal, and generates a second decoding signal based on the address signal to be activated and the matching address signal; the second decoding signal includes the normal address information to be activated in the first memory bank, and / or the redundant address information to be activated. In response to the enable signal of the second memory bank being enabled, the third decoding circuit of the decoding circuit coupled to the redundancy analysis circuit receives the address signal to be activated and the matching address signal, and generates a third decoding signal based on the address signal to be activated and the matching address signal; the third decoding signal includes the normal address information to be activated in the second memory bank and / or the redundant address information to be activated.

25. The operating method according to claim 21 or 24, characterized in that, The operation method includes: The row redundancy circuit stores the corresponding failed row address information in the first memory bank and the second memory bank respectively, and outputs the failed row address signal. The failed row address signal contains the failed row address information corresponding to one of the memory banks to be activated in the first memory bank and the second memory bank. The row matching circuit receives the row address signal to be activated, matches the row address information to be activated in the row address signal with the invalid row address information in the invalid row address signal, and outputs the matching row signal; The row decoding circuit receives the row address signal to be activated and the matching row signal, and generates a first row decoding signal, a second row decoding signal, and a third row decoding signal based on the row address signal to be activated and the matching row signal. The first row decoding signal, the second row decoding signal, and the third row decoding signal include the row address information to be activated in the first memory bank, the second memory bank, and / or the redundant row address information to be activated. The redundancy analysis circuit includes a row redundancy analysis circuit, which in turn includes a row redundancy circuit and a row matching circuit. The decoding circuit includes the row decoding circuit.

26. The operating method according to claim 25, characterized in that, The operation method includes: In response to the enable state of the first read signal, the first latch circuit outputs and stores the first failed row address signal, which includes the first failed row address signal; or, in response to the enable state of the second read signal, the second latch circuit outputs and stores the second failed row address signal, which includes the second failed row address signal. The comparator circuit receives the row address signal to be activated and the first failed row address signal / second failed row address signal, and generates the matching signal; The row redundancy circuit includes the first latch circuit and the second latch circuit; the row matching circuit includes the comparison circuit.

27. The operating method according to claim 26, characterized in that, The operation method includes: In response to the enable state of the first write signal, the first latch circuit stores the first failed row address signal to be stored; or, in response to the enable state of the second write signal, the second latch circuit stores the second failed row address signal to be stored.

28. The operating method according to claim 27, characterized in that, The operation method further includes: In response to the enable signal of the first memory cell, the control circuit generates the first read signal; or, in response to the enable signal of the second memory cell, the control circuit generates the second read signal. The memory device includes the control circuit.

29. The operating method according to claim 28, characterized in that, The operation method further includes: In response to a failed row appearing in a normal row in the first memory bank, the control circuit generates a first failed row address signal and a first write signal corresponding to the failed row in the first memory bank; or, in response to a failed row appearing in a normal row in the second memory bank, the control circuit generates a second failed row address signal and a second write signal corresponding to the failed row in the second memory bank.

30. The operating method according to claim 29, characterized in that, The first latch circuit includes a first gating circuit, a first latch, and a second gating circuit; the second latch circuit includes a third gating circuit, a second latch, and a fourth gating circuit; the operation method further includes: The first gating circuit receives the first failed row address signal to be stored and the first write signal. In response to the enabled state of the first write signal, it transmits the first failed row address signal to be stored to the first latch. The first latch receives and stores the first failed row address signal to be stored and outputs the stored first failed row address signal. The second gating circuit receives the first failed row address signal stored in the first latch and the first read signal. In response to the enabled state of the first read signal, it transmits the first failed row address signal stored in the first latch to the comparison circuit. or, The third gating circuit receives the second failed row address signal to be stored and the second write signal. In response to the enabled state of the second write signal, it transmits the second failed row address signal to be stored to the second latch. The second latch receives and stores the second failed row address signal to be stored and outputs the stored second failed row address signal. The fourth gating circuit receives the second failed row address signal stored in the second latch and the second read signal. In response to the enabled state of the second read signal, it transmits the second failed row address signal stored in the second latch to the comparison circuit.

31. The operating method according to claim 29, characterized in that, The comparison circuit includes a transmission gate and a fifth gate control circuit; the operation method further includes: The transmission gate receives the inverse signal of the row address signal to be activated and the first failed row address signal / second failed row address signal, and generates a first state of the matching signal in response to the enable state of the first failed row address signal / second failed row address signal; the first state of the matching signal represents the failed row address in the row address to be activated that matches the first failed row address / second failed row address. The fifth gating circuit receives the inverted signal of the row address signal to be activated and the inverted signal of the first failed row address signal / the second failed row address signal. In response to the enabled state of the inverted signal of the first failed row address signal / the second failed row address signal, the generated matching signal is in a second state. The second state of the matching signal represents the failed row address in the row address to be activated that does not match the first failed row address / the second failed row address.

32. The operating method according to claim 21 or 24, characterized in that, The memory device further includes a first word line driver, a second word line driver, a third word line driver, and a fourth word line driver; The operation method further includes: The first word line driver receives the output signal of the decoding circuit and generates a first driving signal; the first driving signal is used to drive the normal rows in the first memory bank; and / or, the second word line driver receives the output signal of the decoding circuit and generates a second driving signal; the second driving signal is used to drive the redundant rows in the first memory bank; The third word line driver receives the output signal of the decoding circuit and generates a third driving signal; the third driving signal is used to drive the normal rows in the second memory bank; and / or, the fourth word line driver receives the output signal of the decoding circuit and generates a fourth driving signal; the fourth driving signal is used to drive the redundant rows in the second memory bank.

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