Online wake-up recovery circuit for improving durability of ferroelectric storage unit

Abstract

The invention belongs to the technical field of ferroelectric memories, and particularly discloses an online wake-up recovery circuit for improving durability of a ferroelectric memory unit, which comprises a configurable cascade delay control circuit and a controllable booster circuit which are connected with each other, the configurable cascade delay control circuit is used for generating a plurality of delay pulse signals with different pulse widths, and the controllable booster circuit is used for generating a plurality of delay pulse signals with different pulse widths. And the controllable boost circuit is used for controlling the charging time according to each delay pulse signal, performing adjustable boost, outputting the boosted voltage to the ferroelectric storage unit, and performing wake-up operation on the ferroelectric storage unit. Based on the configurable delay control circuit and the controllable booster circuit, a higher write-in voltage is applied after the ferroelectric memory reaches a certain number of read-write times, and the polarization state of a ferroelectric capacitor in the ferroelectric memory unit is recovered, so that the durability of the ferroelectric memory unit is remarkably improved, the service life of the ferroelectric memory unit is prolonged, and the performance of the ferroelectric memory unit is improved. And the circuit design has the characteristics of high area efficiency, high flexibility and easiness in integration, and is suitable for a large-scale ferroelectric memory array.

Description

Technical Field

[0001] This invention belongs to the field of ferroelectric memory technology, specifically relating to an online wake-up recovery circuit for improving the durability of ferroelectric memory cells. Background Art

[0002] Ferroelectric RAM (FeRAM) is a type of random access memory based on ferroelectric materials. It combines the fast read / write capabilities of dynamic random access memory (DRAM) with the data retention characteristics of non-volatile memory. Ferroelectric RAM retains data even after power is off, giving it significant advantages in low power consumption and fast storage. However, the ferroelectric capacitors in the ferroelectric RAM cells experience fatigue with increasing write cycles, which can lead to data read errors. After fatigue, the ferroelectric capacitors can be restored to normal operation by increasing the write voltage. After this fatigue, the ferroelectric RAM cell maintains normal function within a certain number of write cycles. This process of restoring the ferroelectric RAM cell to normal function is called a wake-up operation.

[0003] Existing ferroelectric memory cell wake-up recovery methods rely on ECC-assisted write drivers. This approach applies a high refresh voltage to restore the polarization state of the ferroelectric memory cell when an ECC (Error Correction Code) flag error is detected. However, this method catches both read / write errors caused by ferroelectric capacitor fatigue and those caused by other logic circuits. Ferroelectric capacitor fatigue occurs when the maximum number of erase / write cycles is reached, while logic circuit errors occur randomly during any read operation. This means logic circuit errors may occur before ferroelectric capacitor fatigue. When a logic circuit error occurs before ferroelectric capacitor fatigue, the generated ECC will prematurely wake up the ferroelectric memory cell, causing the write voltage to be raised too early, thus reducing the overall durability of the ferroelectric memory cell. Therefore, a wake-up recovery method that can effectively guarantee the durability of ferroelectric memory cells is urgently needed. Summary of the Invention

[0004] The purpose of this invention is to provide an online wake-up recovery circuit that improves the durability of ferroelectric memory cells, thereby solving the aforementioned problems in the prior art.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] This invention provides an online wake-up and recovery circuit for improving the durability of ferroelectric memory cells. The circuit includes a configurable cascaded delay control circuit and a controllable boost circuit connected to each other. The configurable cascaded delay control circuit generates several delay pulse signals with different pulse widths upon receiving a trigger signal and transmits each delay pulse signal to the controllable boost circuit. The controllable boost circuit controls the charging time according to each delay pulse signal, performs adjustable voltage boosting, and outputs the boosted voltage to the ferroelectric memory cell to perform a wake-up operation on the ferroelectric memory cell.

[0007] In one possible design, the input of the configurable cascaded delay control circuit is connected to a logic control module. The logic control module is used to monitor the number of reads and writes of the ferroelectric memory cell and generate a trigger signal when the number of reads and writes of the ferroelectric memory cell reaches a set threshold. The trigger signal is then sent to the configurable cascaded delay control circuit.

[0008] In one possible design, the configurable cascaded delay control circuit is also used to output an enable signal to a controllable boost circuit, which is then reset upon receiving the enable signal.

[0009] In one possible design, the output of the controllable boost circuit is connected to the word line and bit line of the ferroelectric memory, and is used to output the boosted voltage to each ferroelectric memory cell connected to the word line and bit line of the ferroelectric memory. The ferroelectric memory includes word lines and bit lines, and several ferroelectric memory cells are connected to the word lines and bit lines.

[0010] In one possible design, the configurable cascaded delay control circuit includes a multiplexer and several delay lines, each delay line being connected in parallel between the input terminal and the multiplexer, and each delay line having a different number of delay units. The output terminal of the multiplexer is connected to a controllable boost circuit.

[0011] In one possible design, the delay unit employs an RC delay mechanism and a Schmitt trigger for stepless delay and pulse shaping to generate a pulse signal of the corresponding width.

[0012] In one possible design, the controllable boost circuit includes field-effect transistors M0, M1, M2, M3, M4, M5, M6, and M7, and a capacitor C1. The gates of field-effect transistors M0 and M1 are connected in parallel to the first control terminal. The source of field-effect transistor M0 is connected to the second control terminal. The source of field-effect transistor M1 is connected to the inter-source voltage VSS. The drain of field-effect transistor M0 and the drain of field-effect transistor M1 are connected to the source of field-effect transistor M2. The gate of field-effect transistor M2 is connected to the power supply voltage VDD. The drain of field-effect transistor M2 is connected to the gate of field-effect transistor M3. The source of field-effect transistor M3 is connected to the third control terminal. The drain of MOSFET M4 is connected to the output terminal, the gate of MOSFET M4 is connected to the first control terminal, the source of MOSFET M4 is connected to the source-to-source voltage VSS, the gate and source of MOSFET M5 are connected to the output terminal, the drain of MOSFET M5 is connected to the power supply voltage VDD, the drain of MOSFET M6 is connected to the output terminal, the gate of MOSFET M6 is connected to the fourth control terminal, the source of MOSFET M6 is connected to the gate of MOSFET M7, the source of MOSFET M7 is connected to the fifth control terminal, the drain of MOSFET M7 is connected to the negative terminal of capacitor C1, and the positive terminal of capacitor C1 is connected to the output terminal. The first, second, third, fourth, and fifth control terminals are used to connect to the respective delayed pulse signals.

[0013] In one possible design, the field-effect transistors M0, M1, M2, M3, M4, M5, M6, and M7 are all NMOS field-effect transistors, and the capacitor C1 is a ferroelectric capacitor.

[0014] Beneficial effects: Based on a configurable delay control circuit and a controllable boost circuit, this invention applies a higher write voltage after the ferroelectric memory has reached a certain number of read and write cycles, restoring the polarization state of the ferroelectric capacitors in the ferroelectric memory cell, thereby significantly improving the durability of the ferroelectric memory cell and extending its service life. Furthermore, the circuit design of this invention has the characteristics of high area efficiency, strong flexibility, and easy integration, and is suitable for large-scale ferroelectric memory arrays. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the wake-up recovery circuit in the embodiment;

[0017] Figure 2 This is a schematic diagram of the configurable cascaded delay control circuit in the embodiment;

[0018] Figure 3 This is a circuit diagram of the delay unit in the embodiment;

[0019] Figure 4 This is a circuit diagram of the controllable boost circuit in the embodiment;

[0020] Figure 5 This is a schematic diagram of the load connection of the controllable boost circuit in the embodiment. Detailed Implementation

[0021] It should be noted that the descriptions of these embodiments are intended to aid in understanding the invention and do not constitute a limitation thereof. The specific structural and functional details disclosed herein are merely for describing exemplary embodiments of the invention. However, the invention may be embodied in many alternative forms and should not be construed as being limited to the embodiments described herein.

[0022] It should be understood that, unless otherwise explicitly specified and limited, the corresponding terms should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be an electrical connection, a direct connection, or an indirect connection through an intermediate medium; it can also refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments according to the specific circumstances.

[0023] Specific details are provided in the following description to provide a complete understanding of the exemplary embodiments. However, those skilled in the art will understand that the exemplary embodiments can be implemented without these specific details. For example, the system may be shown in block diagrams to avoid obscuring the example with unnecessary details. In other embodiments, well-known processes, structures, and techniques may be shown without non-essential details to avoid obscuring the embodiments.

[0024] Example:

[0025] This embodiment provides an online wake-up recovery circuit to improve the durability of ferroelectric memory cells, such as... Figure 1As shown, the system includes a configurable cascaded delay control circuit and a controllable boost circuit connected to each other. The configurable cascaded delay control circuit generates several delay pulse signals with different pulse widths after receiving a trigger signal, and transmits each delay pulse signal to the controllable boost circuit. The controllable boost circuit controls the charging time according to each delay pulse signal, performs adjustable boosting, and outputs the boosted voltage to the ferroelectric memory cell to wake up the ferroelectric memory cell. The input terminal of the configurable cascaded delay control circuit is connected to a logic control module. The logic control module monitors the number of read / write operations of the ferroelectric memory cell and generates a trigger signal when the number of read / write operations reaches a set threshold, sending the trigger signal to the configurable cascaded delay control circuit. The configurable cascaded delay control circuit also outputs an enable signal to the controllable boost circuit, which is reset upon receiving the enable signal.

[0026] In practice, the logic control module records the number of reads and writes of the ferroelectric memory cell using a counter. When the number of reads and writes of the ferroelectric memory cell reaches a preset threshold (e.g., 10), the system will automatically control the read / write operation. 8 When the write voltage is increased (e.g., after a certain number of erase / write cycles), a wake-up recovery operation is triggered. The logic control module sends a trigger signal to the configurable cascaded delay control circuit. The configurable cascaded delay control circuit generates delay pulse signals with different pulse widths (including WLEN, CHARGE_PUMP, PUMP, DRIVE, GATE_VALUE) based on the input trigger signal, controlling the charging time of the controllable boost circuit. The controllable boost circuit receives each delay pulse signal and, through the charging and discharging process of the ferroelectric capacitor, boosts the output voltage to VDD+ΔV (e.g., word line voltage to 2.99V, bit line voltage to 2.3V). The boosted voltage is applied to the ferroelectric capacitor of the ferroelectric memory cell. By enhancing the electric field to compensate for the fatigue effect caused by oxygen vacancy migration and charge injection, the residual polarization intensity of the ferroelectric capacitor is restored, realizing the wake-up operation of the ferroelectric memory cell (electric field compensation mechanism; after the ferroelectric capacitor is fatigued, the ferroelectric capacitor can be restored to normal operation by increasing the write voltage (electric field compensation). After this, the ferroelectric memory cell function remains correct within a certain number of erase / write cycles, i.e., the wake-up operation). After the wake-up operation is completed, the configurable cascaded delay control circuit outputs an enable signal to the controllable boost circuit based on the trigger of the logic control module. The controllable boost circuit is used to receive the enable signal and then reset. The wake-up recovery circuit enters the standby state and waits for the next trigger.

[0027] Configurable cascaded delay control circuits use ferroelectric capacitors as the core delay element, achieving stepless delay and pulse shaping through RC delay mechanisms and Schmitt triggers to generate control pulses of varying widths, ensuring precise timing control of the boost circuit. For example... Figure 2As shown, the configurable cascaded delay control circuit includes a multiplexer and several delay lines. Each delay line is connected in parallel between the input terminal and the multiplexer. The output terminal of the multiplexer is connected to a controllable boost circuit. The multiplexer selects and outputs each delay pulse signal (controlled by S0 and S1). Each delay line has a different number of delay units DELAY. The delay units DELAY on each delay line generate different selectable delays for the multiplexer to select and output.

[0028] The delay unit employs an RC delay mechanism and a Schmitt trigger for stepless delay and pulse shaping, generating a pulse signal of the appropriate width. For example, the circuit structure of the delay unit is as follows: Figure 3 As shown, the RC (resistor-capacitor) delay mechanism achieves nanosecond-level delay by controlling the charging time. A Schmitt trigger (SMT) is used for pulse shaping to ensure steep output signal edges. When the edge of the input signal arrives, the capacitor begins to charge or discharge, causing a change in the output signal. The capacitor used is a ferroelectric capacitor (FeCAP). By controlling the charging and discharging process of the capacitor, the delay effect can be achieved. By changing the direction and intensity of the external electric field of the ferroelectric capacitor, the capacitance value of the ferroelectric capacitor can be adjusted. This allows the delay unit to achieve stepless adjustment of the delay. The width of the output pulse will be wider than the width of the input pulse, and the pulse amplitude will gradually change, with the rising and falling edges of the output pulse becoming smoother. The delay unit uses a ferroelectric capacitor. The high dielectric constant of the ferroelectric capacitor results in a small area, stable delay, and is unaffected by changes in polarization direction. Compared with traditional inverter chain delay circuits, it has less error accumulation and higher stability.

[0029] To obtain a sharp, clear pulse signal, a Schmitt trigger can be used for pulse shaping. This transforms the output waveform into a pulse waveform with steep edges. The pulse signal, after RC delay processing, is input to the Schmitt trigger. By specifying the upper threshold (Uth) and lower threshold (Lth) of the Schmitt trigger, the trigger outputs a high level when the amplitude of the input signal exceeds the upper threshold and a low level when the amplitude of the input signal is below the lower threshold. This results in a sharp, clean pulse signal as the output of the Schmitt trigger, thus completing the function of the pulse shaping circuit.

[0030] A controllable boost circuit can be based on a charge pump topology, using ferroelectric capacitors as boost elements. By controlling the charging time, the output voltage can be adjusted between VDD and VDD+ΔV to meet the different boost requirements of word lines (WL), bit lines (BL), and board lines (PL) in ferroelectric memory. For example... Figure 4As shown, the controllable boost circuit includes field-effect transistors M0, M1, M2, M3, M4, M5, M6, and M7, and capacitor C1. Field-effect transistors M0, M1, M2, M3, M4, M5, M6, and M7 are all NMOS field-effect transistors, and capacitor C1 is a ferroelectric capacitor. The gates of field-effect transistors M0 and M1 are connected in parallel to the first control terminal. The source of field-effect transistor M0 is connected to the second control terminal. The source of field-effect transistor M1 is connected to the inter-source voltage VSS. The drain of field-effect transistor M0 and the drain of field-effect transistor M1 are connected to the source of field-effect transistor M2. The gate of field-effect transistor M2 is connected to the power supply voltage VDD. The drain of field-effect transistor M2 is connected to the gate of field-effect transistor M3. The source of field-effect transistor M3 is connected to the third control terminal. The drain of field-effect transistor M3 is connected to the output terminal. The drain of field-effect transistor M4 is connected to the output terminal. The gate of field-effect transistor M4 is connected to the first control terminal. The source of field-effect transistor M4 is connected to the inter-source voltage VSS. The gate and source of transistor M5 are connected to the output terminal. The drain of transistor M5 is connected to the power supply voltage VDD. The drain of transistor M6 is connected to the output terminal. The gate of transistor M6 is connected to the fourth control terminal. The source of transistor M6 is connected to the gate of transistor M7. The source of transistor M7 is connected to the fifth control terminal. The drain of transistor M7 is connected to the negative terminal of capacitor C1. The positive terminal of capacitor C1 is connected to the output terminal. The first, second, third, fourth, and fifth control terminals are used to input various delayed pulse signals (WLEN, CHARGE_PUMP, PUMP, DRIVE, GATE_VALUE), respectively.

[0031] Field-effect transistors (FETs) M2 and M3 form a threshold-loss-free transmission structure, FET M5 is used to discharge excess charge, and FET M4 controls the standby and active states of the circuit. Circuit operation principle: The first stage consists of four FETs (FETs M0, M1, M2, and M3) that boost the processed voltage to the power supply voltage VDD. The second stage includes three FETs (FETs M4, M6, and M7) and a boost capacitor (capacitor C1). Capacitor C1 further pushes the voltage to above VDD+ΔV, and then FET M5 stabilizes the voltage at VDD+ΔV. The key parts of each stage use the M2+M3 and M6+M7 architecture for lossless data transmission. Only two NMOS transistors are needed to completely transmit the VDD voltage, avoiding threshold loss. For example, the field-effect transistor M2 will have some loss when transmitting VDD, causing the voltage between M2 and M3 to fall below the required level. When M3 is at a high level, it will gradually accumulate charge. When the PUMP signal switches from low to high level, the potential between M2 and M3 will be pulled up due to the presence of M3, exceeding the required VDD+ΔV. The discharge mechanism (through NMOS field-effect transistor M5) can stabilize the output voltage at VDD+ΔV, ensuring the accuracy and stability of the output voltage.

[0032] like Figure 5 As shown, the output of the controllable boost circuit can simultaneously connect to the word line (WL), bit line (BL), and board line (PL) of the ferroelectric memory to output the boosted voltage VDD+ΔV, suitable for integrated ferroelectric memory arrays. Each word line (WL) can connect 39 ferroelectric memory cells, and each bit line (BL) can connect 512 ferroelectric memory cells, ensuring that the controllable boost circuit completes charging within 320ns, meeting the operating frequency of the 25MHz SPI interface. When the load increases, the controllable boost circuit maintains a stable output voltage by extending the charging time (GATE_VALUE pulse width), and can support a maximum boost requirement of VDD+0.5V.

[0033] The wake-up recovery circuit of this embodiment has the following advantages in specific testing and application:

[0034] 1. Significantly improves the durability of ferroelectric memory cells: By restoring the polarization state of the ferroelectric capacitor through an electric field compensation mechanism, the number of erase / write cycles of the ferroelectric memory cell can be increased from 10... 9 The upgrade was increased to 3×10. 9 Secondly, durability is improved by 200%, effectively extending the service life of ferroelectric memory.

[0035] 2. High area efficiency: Using ferroelectric capacitors as boost and delay elements significantly reduces the circuit area (utilizing the high dielectric constant of ferroelectric capacitors to drastically reduce the circuit area, making the delay circuit only 15% of the traditional design and the boost capacitor area only 1μm). 2 It is suitable for large-scale integration.

[0036] 3. High flexibility of use: The configurable delay control circuit supports stepless delay, and the controllable boost circuit can achieve multiple voltage outputs by adjusting the charging time to adapt to the boost requirements of different ferroelectric storage units.

[0037] 4. Low power consumption: The circuit consumes very little power in standby mode, and the boost operation is only triggered when necessary, which meets the low power consumption requirements of embedded systems and IoT devices.

[0038] 5. Easy to integrate: The circuit design is highly compatible with CMOS technology and supports mainstream processes such as SMIC 153nm, making it easy to achieve mass production on existing production lines.

[0039] Finally, it should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An online wake-up recovery circuit for improving the durability of ferroelectric memory cells, characterized in that, The device includes a configurable cascaded delay control circuit and a controllable boost circuit that are interconnected. The configurable cascaded delay control circuit generates several delay pulse signals with different pulse widths after receiving a trigger signal and transmits each delay pulse signal to the controllable boost circuit. The controllable boost circuit controls the charging time according to each delay pulse signal, performs adjustable boosting, and outputs the boosted voltage to the ferroelectric memory cell to wake up the ferroelectric memory cell.

2. The online wake-up recovery circuit for improving the durability of ferroelectric memory cells according to claim 1, characterized in that, The input terminal of the configurable cascaded delay control circuit is connected to the logic control module. The logic control module is used to monitor the number of read and write operations of the ferroelectric memory cell and generate a trigger signal when the number of read and write operations of the ferroelectric memory cell reaches a set threshold. The trigger signal is then sent to the configurable cascaded delay control circuit.

3. The online wake-up recovery circuit for improving the durability of ferroelectric memory cells according to claim 1, characterized in that, The configurable cascaded delay control circuit is also used to output an enable signal to the controllable boost circuit, which is used to reset after receiving the enable signal.

4. The online wake-up recovery circuit for improving the durability of ferroelectric memory cells according to claim 1, characterized in that, The output terminal of the controllable boost circuit is connected to the word line and bit line of the ferroelectric memory, and is used to output the boosted voltage to each ferroelectric memory cell connected to the word line and bit line of the ferroelectric memory. The ferroelectric memory includes word line and bit line, and several ferroelectric memory cells are connected to the word line and bit line.

5. The online wake-up recovery circuit for improving the durability of ferroelectric memory cells according to claim 1, characterized in that, The configurable cascaded delay control circuit includes a multiplexer and several delay lines. Each delay line is connected in parallel between the input terminal and the multiplexer. Each delay line has a different number of delay units. The output terminal of the multiplexer is connected to a controllable boost circuit.

6. The online wake-up recovery circuit for improving the durability of ferroelectric memory cells according to claim 5, characterized in that, The delay unit uses an RC delay mechanism and a Schmitt trigger for stepless delay and pulse shaping to generate a pulse signal of the corresponding width.

7. The online wake-up recovery circuit for improving the durability of ferroelectric memory cells according to claim 1, characterized in that, The controllable boost circuit includes field-effect transistors M0, M1, M2, M3, M4, M5, M6, and M7, and capacitor C1. The gates of field-effect transistors M0 and M1 are connected in parallel to the first control terminal. The source of field-effect transistor M0 is connected to the second control terminal. The source of field-effect transistor M1 is connected to the inter-source voltage VSS. The drain of field-effect transistor M0 and the drain of field-effect transistor M1 are connected to the source of field-effect transistor M2. The gate of field-effect transistor M2 is connected to the power supply voltage VDD. The drain of field-effect transistor M2 is connected to the gate of field-effect transistor M3. The source of field-effect transistor M3 is connected to the third control terminal. The drain of field-effect transistor M3 is connected to the output terminal. The drain of MOSFET M4 is connected to the output terminal, the gate of MOSFET M4 is connected to the first control terminal, the source of MOSFET M4 is connected to the source-to-source voltage VSS, the gate and source of MOSFET M5 are connected to the output terminal, the drain of MOSFET M5 is connected to the power supply voltage VDD, the drain of MOSFET M6 is connected to the output terminal, the gate of MOSFET M6 is connected to the fourth control terminal, the source of MOSFET M6 is connected to the gate of MOSFET M7, the source of MOSFET M7 is connected to the fifth control terminal, the drain of MOSFET M7 is connected to the negative terminal of capacitor C1, and the positive terminal of capacitor C1 is connected to the output terminal. The first, second, third, fourth, and fifth control terminals are used to connect to the respective delayed pulse signals.

8. The online wake-up recovery circuit for improving the durability of ferroelectric memory cells according to claim 7, characterized in that, The field-effect transistors M0, M1, M2, M3, M4, M5, M6, and M7 are all NMOS field-effect transistors, and the capacitor C1 is a ferroelectric capacitor.

Images