Semiconductor device with DQS interval timer

Abstract

The invention relates to a semiconductor device with a DQS interval timer. An example apparatus includes a first circuit configured to activate a first control signal in response to a second control signal and to deactivate the first control signal in response to a third control signal; a second circuit coupled to the first circuit and configured to output a clock signal when a predetermined clock period has elapsed after the first control signal is activated; and a third circuit coupled to the second circuit and configured to count the clock signal. The third circuit is configured to activate the third control signal when a count value reaches a first value and activate a fourth control signal when a count value reaches a second value greater than the first value. A difference between the second value and the first value is the predetermined clock period or less.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device having a DQS interval timer. Background Technology

[0002] DDR5 DRAM includes a DQS interval timer, which measures the difference between the propagation time of the data signal in the DRAM and the propagation time of the data strobe signal. The operation of measuring this difference in propagation time using the DQS interval timer must be completed within a specified time period. Summary of the Invention

[0003] On one hand, this disclosure provides an apparatus comprising: a first circuit configured to activate a first control signal in response to a second control signal and deactivate the first control signal in response to a third control signal; a second circuit coupled to the first circuit and configured to output a clock signal after a predetermined clock cycle has elapsed since the first control signal was activated; and a third circuit coupled to the second circuit and configured to count the clock signal, wherein the third circuit is configured to activate the third control signal when the count value reaches a first value and to activate a fourth control signal when the count value reaches a second value greater than the first value, and wherein the difference between the second value and the first value is the predetermined clock cycle or less.

[0004] On the other hand, this disclosure provides an apparatus comprising: a control circuit configured to start generating a clock signal after N clock cycles have elapsed since a first signal is activated and to stop generating the clock signal after N clock cycles have elapsed since a second signal is activated; and a first counter circuit configured to count the clock signal, deactivate a third signal when the count value reaches M and activate the second signal when the count value reaches K, wherein K is less than M and equal to or greater than MN.

[0005] On the other hand, this disclosure provides an apparatus comprising: an enable control circuit configured to activate a first enable signal in response to a start signal and deactivate the first enable signal in response to an end signal; a plurality of cascaded trigger circuits configured to shift the first enable signal in response to a first clock signal to generate a second enable signal; a clock gate circuit configured to generate a second clock signal in response to the second enable signal; and a counter circuit configured to count the second clock signal, generate a third enable signal when the count value reaches a first value, and generate the end signal before the count value reaches the first value. Attached Figure Description

[0006] Figure 1This is a block diagram based on the present disclosure for explaining the configuration of a semiconductor memory device;

[0007] Figure 2 This is the circuit diagram of the data input circuit;

[0008] Figure 3 This is the circuit diagram of the DQS interval timer and the DQS interval oscillator;

[0009] Figure 4 This is the circuit diagram of a synchronizer;

[0010] Figure 5A This is the circuit diagram of an interval counter;

[0011] Figure 5B It is a truth table representing the operation of the adder circuit;

[0012] Figure 6 This is a timing diagram used to explain the operation of the DQS interval timer; and

[0013] Figure 7 This is a block diagram illustrating an example of the application of the technology according to this disclosure to a time delay shifter. Detailed Implementation

[0014] Various embodiments of this disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects of this disclosure and various embodiments by way of illustration. The detailed description provides sufficient detail to enable those skilled in the art to practice these embodiments of the disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0015] Figure 1 This is a block diagram based on the present disclosure used to explain the configuration of the semiconductor memory device 10. Figure 1 The semiconductor memory device 10 shown is a DDR5 DRAM and includes a memory cell array 11 comprising multiple memory cells, an access control circuit 12 for accessing the memory cell array 11, a command address terminal 21 to which a command address signal CA is input from the outside, and clock terminals 22 and 23 to which complementary external clock signals CKT and CKC are input from the outside, respectively. The access control circuit 12 includes a command decoder 31, a clock generator 32, and a mode register 33.

[0016] The command address signal CA is decoded by the command decoder 31, thereby generating various internal commands. For example, when the command address signal CA indicates a read command, the internal read command is generated by the command decoder 31, and the data stored in the designated memory cell in the memory cell array 11 is read. The read data DQ read from the memory cell array 11 is output to the outside via the data input / output terminal 24 through the data control circuit 13. When a read operation is performed, the complementary data strobe signals DQST and DQSC are output synchronously from the strobe terminals 25 and 26, respectively, along with the read data DQ. When the command address signal CA indicates a write command, the internal write command is generated by the command decoder 31, and the write data DQ input from the outside to the data input / output terminal 24 is written to the designated memory cell in the memory cell array 11 via the data control circuit 13. When a write operation is performed, the complementary data strobe signals DQST and DQSC are input to the strobe terminals 25 and 26, respectively, along with the write data DQ.

[0017] When the command address signal CA indicates a mode register setting command, the internal mode register setting command is generated by the command decoder 31, and various parameters set in the mode register 33 are overwritten. When the command address signal CA indicates a DQS interval oscillator start command, the internal command MPC_DQSOSCST is generated by the command decoder 31. The internal command MPC_DQSOSCST is supplied to the data control circuit 13.

[0018] External clock signals CKT and CKC are input to clock generator 32, which is included in access control circuit 12. Clock generator 32 generates internal clock signal ICLK based on external clock signals CKT and CKC. The operation of access control circuit 12 and data control circuit 13 is performed synchronously with internal clock signal ICLK.

[0019] The data control circuit 13 includes a data input circuit 100 and a DQS interval timer 200.

[0020] Figure 2 This is the circuit diagram of data input circuit 100. (For example...) Figure 2As shown, the data input circuit 100 includes an input buffer 101 that receives write data DQ from an external input via a data input / output terminal 24, and an input buffer 102 that receives complementary data strobe signals DQST and DQSC from an external input via strobe terminals 25 and 26, respectively. The output signal of the input buffer 101 is supplied to the data input node of the data latch circuit 105 via logic circuit 103. The output signal of the input buffer 102 is supplied to the clock input node of the data latch circuit 105 via logic circuit 104. With this configuration, the internal write data IDQ transmitted via the input buffer 101 and logic circuit 103 is synchronized with the strobe signal IDQS transmitted via the input buffer 102 and logic circuit 104 and latched on the data latch circuit 105. In DDR5 DRAM, the inherent delay tDelay_DQ of the input buffer 101 and logic circuit 103 and the inherent delay tDelay_DQS of the input buffer 102 and logic circuit 104 do not need to be matched with each other.

[0021] Figure 3 This is the circuit diagram of the DQS interval timer 200 and the DQS interval oscillator 290. (See diagram for example.) Figure 3 As shown, the DQS interval timer 200 includes an enable control circuit 210 that generates an enable signal EN. The enable control circuit 210 is set synchronously with the internal command MPC_DQSOSCST and reset synchronously with the stop signal OSCSTOP. During the period in which the enable control circuit 210 is set, the enable signal EN is activated. The enable signal EN is supplied to the synchronizer 220.

[0022] Figure 4 This is the circuit diagram of synchronizer 220. (For example...) Figure 4 As shown, synchronizer 220 consists of multiple cascaded flip-flop circuits. Figure 4 In the example shown, the synchronizer 220 consists of N latching circuits, which are formed from a first-stage flip-flop circuit 221 that receives the enable signal EN to a final-stage flip-flop circuit 22N that outputs the enable signal SYNCEN. These flip-flop circuits 221 to 22N are synchronized with the internal clock signal ICLK to perform latching operations. With this configuration, the enable signal SYNCEN output from the final-stage flip-flop circuit 22N is synchronized with the internal clock signal ICLK. The enable signal SYNCEN is supplied to... Figure 3 The clock gate circuit 230 is shown in the diagram. When the enable signal SYNCEN is activated, clock gate circuit 230 allows the internal clock signal ICLK to pass through, thereby outputting an internal clock signal SYNCCK that is synchronized with the internal clock signal ICLK. The internal clock signal SYNCCK is supplied to the interval counter 240. Figure 3As shown, the DQS interval timer 200 includes an enable control circuit 210, a synchronizer 220, a clock gate circuit 230, and an interval counter 240.

[0023] Figure 5A This is the circuit diagram for an interval counter 240. (For example...) Figure 5A As shown, the interval counter 240 includes multiple cascaded adder circuits 241 to 24X and decoders 251 and 252. Figure 5A In the example shown, X adder circuits, from the first-stage adder circuit 241 to the final-stage adder circuit 24X, are contained within an interval counter 240. Each of the adder circuits 241 to 24X includes an input node A, output nodes C and S, and a clock node. An internal clock signal SYNCCK is supplied to each clock node of the adder circuits 241 to 24X. The truth table representing the operation of the adder circuits 241 to 24X is as follows: Figure 5B The configuration is illustrated below. With this configuration, adder circuits 241 to 24X function as binary counters, performing counting operations synchronously with the internal clock signal SYNCCK. The count values ​​of adder circuits 241 to 24X are supplied to decoders 251 and 252. Decoder 251 activates the enable signal OSCEN when the count value of adder circuits 241 to 24X exceeds an initial value, and deactivates the enable signal OSCEN when the count value of adder circuits 241 to 24X reaches a set value M. The set value M is not a fixed value and can vary based on the parameter SET set in the mode register 33. Furthermore, decoder 252 activates the stop signal OSCSTOP when the count value of adder circuits 241 to 24X reaches a set value K. The set value K is a value less than M and equal to or greater than MN. As mentioned above, N is the number of trigger circuits 221 to 22N constituting synchronizer 220. Therefore, the set value K can also vary based on the parameter SET set in the mode register 33. The stop signal OSCSTOP generated by the interval counter 240 is supplied to the enable control circuit 210. The enable signal OSCEN generated by the interval counter 240 is supplied to the DQS oscillator 260.

[0024] During the period when the enable signal OSCEN is activated, the DQS oscillator 260 generates the oscillator signal OSC. The period of the oscillator signal OSC is designed to correspond to a reference. Figure 2 The inherent delay tDelay_DQ is matched with the inherent delay tDelay_DQS. The oscillator signal OSC is supplied to the DQS OSC counter 270. The DQS OSC counter 270 counts the oscillator signal OSC. Figure 3 As shown, the DQS interval oscillator 290 includes a DQS oscillator 260 and a DQS OSC counter 270.

[0025] Figure 6 This is a timing diagram used to explain the operation of DQS interval timer 200. Figure 6 The example shown illustrates a case where the set value M is 8 and the number N of the trigger circuits 221 to 22N constituting synchronizer 220 is 4. First, when the internal command MPC_DQSOSCST is activated at time t1, the enable control circuit 210 activates the enable signal EN. The activation timing of the enable signal EN is time t2. The enable signal EN is input to synchronizer 220, and the enable signal SYNCEN is activated at time t3, where the enable signal EN has passed through the trigger circuits 221 to 22N constituting synchronizer 220. Figure 6 In the example shown, since N is 4, the time interval between time t2 and time t3 is approximately 4 clock cycles.

[0026] When the enable signal SYNCEN is activated, clock gate 230 allows the enable clock signal ICLK to pass through, thereby starting the output of the internal clock signal SYNCCK. The internal clock signal SYNCCK is counted by the interval counter 240. Figure 6 In the example shown, the initial value of the interval counter 240 is -1, and the enable signal OSCEN is activated when the count value becomes 0 on the first count. The activation timing of the enable signal OSCEN is time t4. When the enable signal OSCEN is activated, the DQS oscillator 260 is activated and the oscillation of the oscillator signal OSC is started. The oscillator signal OSC is counted by the DQS OSC counter 270.

[0027] When the interval counter 240 continues counting and its count value reaches MN (=4) at time t5, the stop signal OSCSTOP is activated. In response, the enable control circuit 210 immediately deactivates the enable signal EN. The deactivation timing of the enable signal EN is immediately after time t5 at time t6. However, even when the enable signal EN is deactivated, the enable signal SYNCEN is not immediately deactivated, so that the timing of the internal clock signal SYNCCK continues and the interval counter 240 continues counting until the enable signal SYNCEN is deactivated. Subsequently, when the count value of the interval counter 240 reaches M (=8) at time t7, the enable signal OSCEN is deactivated. When the enable signal OSCEN is deactivated, the DQS oscillator 260 stops oscillating the oscillator signal OSC. This process ends the counting operation performed by the DQS OSC counter 270. Figure 6In the example shown, the count value of the DQS OSC counter 270 stops at 6. The count value of the DQS OSC counter 270 is transmitted to an external controller, which can detect the difference between the inherent delay tDelay_DQ and the inherent delay tDelay_DQS based on the count value of the DQS OSC counter 270. Therefore, based on the difference between the inherent delays in the DRAM described above, the timing of the write data DQ and the data strobe signals DQST and DQSC is adjusted at the controller side to cancel out the difference between the inherent delays in the DRAM and perform a smoothing operation.

[0028] As described above, because the semiconductor memory device according to this embodiment activates the stop signal OSCSTOP before the interval counter 240 deactivates the activation enable signal OSCEN, the enable control circuit 210 is quickly reset. Therefore, the period during which DQS interval monitor commands can be received externally is shortened. For example, in Figure 6 In the example shown, compared to the case where the stop signal OSCSTOP and the enable signal OSCEN are activated simultaneously, the period during which the DQS interval monitor command can be accepted is shortened by four clock cycles. Furthermore, during the period until the enable signal EN, which is deactivated by the stop signal OSCSTOP, passes through synchronizer 220, the enable signal SYNCEN is maintained in an activated state, allowing the interval counter 240 to perform its counting operation normally.

[0029] Figure 7 This is a block diagram illustrating an example of the application of the technology according to this disclosure to a time delay shifter. Figure 7 The circuit shown in the image has a time delay shifter 280 installed instead of... Figure 3 The configuration of the interval counter 240 is shown in the diagram. The delay shifter 280 generates the internal command CMDOUT by delaying the internal command CMDIN by a predetermined clock period in sync with the internal clock signal SYNCCK. Even with this circuit configuration, it is possible to shorten the period during which the internal command CMDSTART can be input to the enable control circuit 210 by generating a stop signal CMDSTOP before outputting the internal command CMDOUT.

[0030] Although various embodiments have been disclosed in the context of certain preferred embodiments and examples, those skilled in the art will understand that the scope of this disclosure extends beyond the explicitly disclosed embodiments to other alternative embodiments and / or uses of the embodiments, their obvious modifications, and equivalents. Furthermore, those skilled in the art will readily understand other modifications within the scope of this disclosure based on this disclosure. It is also conceivable that various combinations or sub-combinations of specific features and aspects of the embodiments may be made, and these still fall within the scope of this disclosure. It should be understood that various features and aspects of the disclosed embodiments may be combined or substituted with each other to form different modes of the disclosed embodiments. Therefore, it is intended that at least some of the scope of this disclosure should not be limited to the specific disclosed embodiments described above.

Claims

1. An apparatus comprising: A first circuit is configured to activate a first control signal in response to a second control signal and deactivate the first control signal in response to a third control signal. A second circuit is coupled to the first circuit and configured to output a clock signal after a predetermined clock cycle has elapsed following the activation of the first control signal. and A third circuit, coupled to the second circuit and configured to count the clock signal, is also included. The third circuit is configured to activate the third control signal when the count value reaches a first value and to activate the fourth control signal when the count value reaches a second value greater than the first value. The difference between the second value and the first value is the predetermined clock cycle or less.

2. The device according to claim 1, The second circuit includes multiple cascaded flip-flop circuits, and The difference between the second value and the first value is the number of the plurality of trigger circuits or fewer.

3. The device of claim 1, wherein the difference between the second value and the first value is the same as the predetermined clock period.

4. The device according to claim 3, The second circuit includes multiple cascaded flip-flop circuits, and The difference between the second value and the first value is the same as the number of the plurality of trigger circuits.

5. The device of claim 1, further comprising a fourth circuit coupled to the third circuit and configured to generate an oscillating signal until the count value reaches the second value.

6. The device of claim 5, further comprising a fifth circuit coupled to the fourth circuit and configured to count the oscillation signal.

7. The device of claim 6, further comprising a data input circuit, the data input circuit comprising: The first input circuit is configured to generate an internal data signal in response to an external data signal; The second input circuit is configured to generate an internal data strobe signal in response to an external data strobe signal; and A data latch circuit configured to latch the internal data signal in response to the internal data strobe signal. The difference between the delay time of the first input circuit and the delay time of the second input circuit is the same as the clock period of the oscillation signal.

8. The device of claim 1, further comprising a command decoder configured to activate the second control signal when a predetermined command is issued from an external source.

9. The device of claim 1, further comprising a mode register configured to specify the second value.

10. An apparatus comprising: A control circuit configured to start generating a clock signal after N clock cycles have elapsed since the first signal is activated, and to stop generating the clock signal after N clock cycles have elapsed since the second signal is activated. and A first counter circuit is configured to count the clock signal, deactivate the third signal when the count value reaches M, and activate the second signal when the count value reaches K. Where K is less than M and equal to or greater than MN.

11. The device according to claim 10, wherein K is MN.

12. The device of claim 10, further comprising an oscillation circuit configured to generate an oscillation signal until the count value reaches M.

13. The device of claim 12, further comprising a second counter circuit configured to count the oscillation signal.

14. The device of claim 13, further comprising a data input circuit, the data input circuit comprising: The first input circuit is configured to generate an internal data signal in response to an external data signal; The second input circuit is configured to generate an internal data strobe signal in response to an external data strobe signal; and A data latch circuit configured to latch the internal data signal in response to the internal data strobe signal. The difference between the delay time of the first input circuit and the delay time of the second input circuit is the same as the clock period of the oscillation signal.

15. The device of claim 10, further comprising a command decoder configured to activate the first signal when a predetermined command is issued from an external source.

16. The device of claim 10, further comprising a mode register configured to specify a value of M.

17. An apparatus comprising: An enable control circuit is configured to activate a first enable signal in response to a start signal and deactivate the first enable signal in response to an end signal. Multiple cascaded flip-flop circuits are configured to shift the first enable signal in response to a first clock signal to generate a second enable signal; A clock gate circuit configured to generate a second clock signal in response to the second enable signal; and A counter circuit configured to count the second clock signal, generate a third enable signal when the count value reaches a first value, and generate the end signal before the count value reaches the first value.

18. The device of claim 17, wherein the counter circuit is configured to generate the end signal when the count value reaches a second value.

19. The device of claim 18, wherein the difference between the first value and the second value is the number of the plurality of cascaded trigger circuits or less.

20. The device of claim 19, wherein the difference between the first value and the second value is the same as the number of the plurality of cascaded trigger circuits.

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