Memory device, power supply method, charge pump circuit and system

Abstract

The embodiment of the invention discloses a memory device, a power supply method, a charge pump circuit and a system. The memory device includes: a memory cell array; the memory cell array comprises a plurality of memory cell rows and word lines coupled to the memory cell rows; and a peripheral circuit coupled to a corresponding memory cell row via the word line, and including: a first power supply circuit configured to supply power to the memory cell row at a first time, and a second power supply circuit configured to supply power to the memory cell row at a second time, starting to output a first voltage to a substrate of a first transistor included in a first word line driving circuit coupled with the first unselected word line; the second power supply circuit is configured to start to output a second voltage to one end of the first transistor at a second moment; wherein the first moment is earlier than the second moment.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory technology, and in particular to a memory device, power supply method, charge pump circuit and system. Background Technology

[0002] Memory devices are widely used in various electronic devices such as computers, wireless communication devices, cameras, and digital displays to store relevant data, especially Dynamic Random Access Memory (DRAM). Currently, in DRAM, voltage overshoot can occur during power-on due to coupling effects. Summary of the Invention

[0003] In view of the above, embodiments of this application provide a memory device, a power supply method, a charge pump circuit, and a system.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] In a first aspect, embodiments of this application provide a memory device, comprising: a memory cell array; the memory cell array comprising: a plurality of memory cell rows and a word line coupled to each memory cell row; and peripheral circuitry, the peripheral circuitry being coupled to the corresponding memory cell row via the word line, and comprising: a first power supply circuit and a second power supply circuit, wherein the first power supply circuitry is configured to: at a first moment, begin outputting a first voltage to the substrate of a first transistor included in a first word line driving circuit coupled to a first unselected word line; the second power supply circuitry is configured to: at a second moment, begin outputting a second voltage to one end of the first transistor; wherein the first moment is earlier than the second moment.

[0006] In the above scheme, the first voltage and the second voltage are negative voltages.

[0007] In the above scheme, the second voltage is provided to the source terminal of the first transistor.

[0008] In the above scheme, the plurality of memory cell rows include a plurality of memory cells; the memory cell includes a second transistor and a capacitor; wherein, a first end of the second transistor is connected to one end of the capacitor, a second end of the second transistor is connected to its corresponding bit line, and a control end of the second transistor is connected to its corresponding word line; wherein, the first power supply circuit is further configured to provide the first voltage to the substrate of the second transistor.

[0009] In the above scheme, the first power supply circuit is further configured to: respond to the first enable signal at the first moment, start outputting the first voltage, and after a first duration, the voltage value of the first voltage reaches a preset voltage value; and after a second duration, the voltage value of the first voltage reaches a first target voltage value.

[0010] In the above scheme, the second power supply circuit is further configured to: respond to the second enable signal at the second moment, start outputting the second voltage, and after a third duration, the voltage value of the second voltage reaches the second target voltage value.

[0011] In the above scheme, the second moment corresponds to the moment when the voltage value of the first voltage rises to the preset voltage value.

[0012] In the above scheme, the preset voltage value accounts for 50% to 90% of the first target voltage value.

[0013] In the above scheme, the peripheral circuit further includes: a third power supply circuit; wherein, the first power supply circuit is further configured to: at the first moment, start outputting the first voltage to the substrate of the third transistor included in the second word line driving circuit coupled to the second unselected word line; the third power supply circuit is configured to: at the third moment, start outputting the third voltage to one end of the third transistor; wherein, the first moment is earlier than the third moment.

[0014] In the above scheme, the third voltage is provided to the source terminal of the third transistor.

[0015] In the above scheme, the storage cell array includes multiple storage blocks; each storage block includes the multiple storage cell rows and word lines coupled to each storage cell row; wherein, the second unselected word line includes word lines belonging to the same storage block as the selected word line.

[0016] In the above scheme, the second unselected word line also includes at least a portion of the word lines contained in the storage block adjacent to the storage block where the selected word line is located.

[0017] In the above scheme, the first unselected character line includes other unselected character lines besides the second unselected character line.

[0018] In the above scheme, the third voltage is a negative voltage, and the absolute value of the third target voltage value of the third voltage is greater than the second target voltage value of the second voltage.

[0019] In the above scheme, the first power supply circuit includes: a first comparator and a voltage generator, wherein the first comparator is configured to: compare a reference voltage and a first feedback voltage, and output a first control signal according to the comparison result; the first feedback voltage is obtained according to the first voltage output by the voltage generator; the voltage generator is configured to: output the first voltage according to the first control signal.

[0020] In the above scheme, the first power supply circuit further includes: a feedback generator configured to receive the first voltage and output the first feedback voltage according to the first voltage; and a reference generator configured to output the reference voltage.

[0021] In the above scheme, the feedback generator includes: a fourth transistor and a plurality of first resistors connected in series, wherein a first terminal of the fourth transistor is connected to the first voltage, and a second terminal of the fourth transistor is connected to a first terminal of the plurality of first resistors; the second terminals of the plurality of first resistors are connected to a first initial voltage.

[0022] At a first moment, the control terminal of the fourth transistor is connected to a first enable signal, and the feedback generator outputs the first feedback voltage; the first feedback voltage is the voltage between two of the plurality of first resistors.

[0023] In the above scheme, the feedback generator further includes a fifth transistor and a sixth transistor, wherein the first terminal of the fifth transistor is connected to a first sub-voltage value included in the first initial voltage, and the second terminal is connected to the second terminal of the plurality of first resistors; the first terminal of the sixth transistor is connected to a second sub-voltage value included in the first initial voltage, and the second terminal is connected to the second terminal of the plurality of first resistors; wherein a second control signal is connected to the control terminal of the fifth transistor, and the first power supply circuit operates in a first mode; a third control signal is connected to the control terminal of the sixth transistor, and the first power supply circuit operates in a second mode.

[0024] In the above scheme, the reference generator includes: a plurality of second resistors connected in series; wherein, a first end of the plurality of second resistors is connected to the first initial voltage; and the other end of the plurality of second resistors is grounded, wherein the reference voltage is the voltage between two of the plurality of second resistors.

[0025] In the above scheme, the voltage generator includes: a clock driving sub-circuit and a negative charge pump sub-circuit, wherein: the clock driving sub-circuit is configured to: receive the first control signal and generate a fourth control signal according to the first control signal; the negative charge pump sub-circuit is coupled to the clock driving sub-circuit and is configured to: receive the fourth control signal and output the first voltage according to the fourth control signal.

[0026] In the above scheme, the negative charge pump circuit includes at least two negative charge pumps, wherein two adjacent negative charge pumps are connected in series or in parallel.

[0027] In the above scheme, the first power supply circuit further includes a voltage regulator configured to receive an adjustment control signal and, in response to the adjustment control signal, adjust the first voltage to a set target voltage value.

[0028] In the above scheme, the adjustment control signal includes at least one sub-control signal; the set target voltage value includes at least one sub-target voltage value; the voltage regulator includes: at least one group of P-type transistors and N-type transistors; in each group, the first terminal of the P-type transistor is connected to a second initial voltage, and its second terminal is connected to the first terminal of the N-type transistor; the second terminal of the N-type transistor is connected to the first voltage; wherein, in each group, the control terminal of the P-type transistor is connected to a third enable signal and the control terminal of the N-type transistor is connected to a corresponding sub-control signal, thereby adjusting the first voltage to the corresponding sub-target voltage value of the corresponding group.

[0029] In the above scheme, the first power supply circuit further includes: at least one second comparator; each second comparator is configured to: compare a reference voltage and a corresponding second feedback voltage, and output a corresponding sub-control signal; the second feedback voltage is the voltage between two of the series-connected first resistors, and is different from the first feedback voltage.

[0030] In the above scheme, the peripheral circuit is further configured as: a third comparator, configured to: compare the reference voltage and the third feedback voltage, and output a second enable signal according to the comparison result, and output the second enable signal to the second power supply circuit; wherein, the third feedback voltage is obtained when the voltage value of the first voltage reaches a preset voltage value.

[0031] In the above scheme, the absolute value of the first target voltage of the first voltage is greater than the absolute value of the second target voltage of the second voltage.

[0032] In the above scheme, the peripheral circuit further includes: a fourth power supply circuit, configured to: generate a bit line voltage that reaches a fourth target voltage value before the first moment, and provide the bit line voltage to the corresponding bit line.

[0033] Secondly, embodiments of this application provide a power supply method for a memory device, comprising: at a first moment, starting to generate a first voltage and providing the first voltage to the substrate of a first transistor included in a first word line driving circuit coupled to a first unselected word line; at a second moment, starting to generate a second voltage and providing the second voltage to one end of the first transistor; wherein the first moment is earlier than the second moment.

[0034] In the above scheme, the second voltage is provided to the source terminal of the first transistor.

[0035] In the above scheme, the method further includes: responding to a first enable signal at a first moment, starting to generate the first voltage, and after a first duration, the voltage value of the first voltage reaches a preset voltage value; after a second duration, the voltage value of the first voltage reaches a first target voltage value; wherein the preset voltage value accounts for 50% to 90% of the first target voltage value.

[0036] In the above scheme, the method further includes: in response to a second enable signal at the second moment, starting to generate the second voltage, and after a third duration, the voltage value of the second voltage reaches a second target voltage value; wherein, the second moment corresponds to the moment when the voltage value of the first voltage rises to the preset voltage value.

[0037] In the above scheme, the method further includes: providing the first voltage to the substrate of the second transistor contained in the memory cell of the memory device.

[0038] In the above scheme, the first voltage and the second voltage are negative voltages, and the absolute value of the first target voltage value of the first voltage is greater than the absolute value of the second target voltage value of the second voltage.

[0039] In the above scheme, the method further includes: at a first moment, providing the first voltage to the substrate of the third transistor included in the second word line driving circuit coupled to the second unselected word line; at a third moment, starting to generate a third voltage and providing the third voltage to the source terminal of the third transistor; the first moment is earlier than the third moment; wherein the third voltage is a negative voltage, and the absolute value of the third voltage value is greater than the second voltage value of the second voltage value.

[0040] In the above scheme, the memory device includes a plurality of memory blocks; each memory block includes a plurality of memory cell rows and word lines coupled to each memory cell row; wherein, the second unselected word line includes word lines belonging to the same memory block as the selected word line.

[0041] In the above scheme, the second unselected word line also includes at least a portion of the word lines contained in the storage block adjacent to the storage block where the selected word line is located.

[0042] In the above scheme, the first unselected character line includes other unselected character lines besides the second unselected character line.

[0043] In the above scheme, generating the first voltage includes: comparing a reference voltage and a first feedback voltage, and generating a first control signal based on the comparison result; and generating the first voltage based on the first control signal; the first feedback voltage is a feedback voltage obtained based on the first voltage.

[0044] In the above scheme, the method further includes: receiving an adjustment control signal; and adjusting the first voltage to a set target voltage value in response to the adjustment control signal; wherein the adjustment control signal is obtained based on a comparison result between a reference voltage and a second feedback voltage; the second feedback voltage is obtained based on the first voltage and is different from the first feedback voltage.

[0045] In the above scheme, the method further includes: comparing a reference voltage and a third feedback voltage, and outputting a second enable signal according to the comparison result; wherein, the third feedback voltage is obtained when the voltage value of the first voltage reaches the preset voltage value.

[0046] In the above scheme, the method further includes: before the first moment, generating a bit line voltage that reaches the fourth target voltage value, and providing the bit line voltage to the corresponding bit line.

[0047] Thirdly, embodiments of this application also provide a charge pump circuit for a memory device, comprising: a feedback generator, a reference generator, a first comparator, and a voltage generator, wherein the feedback generator is connected between a first node and the output terminal of the voltage generator, and has an input terminal that receives a first enable signal, and one of its output terminals is connected to a first input terminal of the first comparator; the reference generator is connected between the first node and ground, and its output terminal is connected to a second input terminal of the first comparator; the output terminal of the first comparator is connected to the input terminal of the voltage generator; and the output terminal of the voltage generator outputs a negative voltage.

[0048] In the above scheme, the feedback generator includes: a fourth transistor and a plurality of first resistors connected in series, wherein a first terminal of the fourth transistor is connected to the output terminal of the voltage generator, and a second terminal is connected to a first terminal of the plurality of first resistors connected in series; the second transistor also has a control terminal that receives the first enable signal; the second terminal of the plurality of first resistors connected in series is connected to the first node; and the output terminal led out between two of the plurality of first resistors connected in series is connected to the first input terminal of the first comparator.

[0049] In the above scheme, the feedback generator further includes a fifth transistor and a sixth transistor, wherein the first terminal of the fifth transistor is connected to the first node, and its second terminal is connected to the second terminal of the series-connected plurality of first resistors; the fifth transistor also has a control terminal for receiving a second control signal; the first terminal of the sixth transistor is connected to the second node, and its second terminal is connected to the second terminal of the series-connected plurality of first resistors; the sixth transistor also has a control terminal for receiving a third control signal.

[0050] In the above scheme, the reference generator includes: a plurality of second resistors connected in series; wherein, the first end of the plurality of second resistors is connected to the second end of the fifth transistor and the second end of the sixth transistor; the second end of the plurality of second resistors is grounded; and the output terminal led out between two of the plurality of second resistors is connected to the second input terminal of the first comparator.

[0051] The above scheme also includes: a voltage regulator; the voltage regulator includes: at least one set of P-type transistors and N-type transistors; in each set, the first terminal of the P-type transistor is connected to a third node, and its second terminal is connected to the first terminal of the N-type transistor; the P-type transistor also has a control terminal that receives a third enable signal; the second terminal of the N-type transistor is connected to the output terminal of the voltage generator; the N-type transistor also has a control terminal that receives a corresponding sub-control signal.

[0052] The above scheme further includes: at least one second comparator; the first input terminal of each second comparator is connected to a certain output terminal of the feedback generator, and the second input terminal is connected to the output terminal of the reference generator; the output terminal of each second comparator is connected to the control terminal of the corresponding group of N-type transistors.

[0053] The above scheme further includes: a third comparator, the first input terminal of which is connected to the first output terminal of the feedback generator; the second input terminal of which is connected to the output terminal of the reference generator; the output terminal of the second comparator outputs a second enable signal; wherein the voltage value output by the first output terminal is a preset voltage value; the second enable signal is used to enable other charge pump circuits.

[0054] In the above scheme, the voltage generator includes: a clock driving sub-circuit and a negative charge pump sub-circuit, wherein: the input terminal of the clock driving sub-circuit is connected to the output terminal of the first comparator; the output terminal of the clock driving sub-circuit is coupled to the input terminal of the negative charge pump sub-circuit; and the output terminal of the negative charge pump sub-circuit outputs the negative voltage.

[0055] In the above scheme, the negative charge pump circuit includes at least two negative charge pumps, wherein two adjacent negative charge pumps are connected in series or in parallel.

[0056] Fourthly, embodiments of this application also provide a memory system, including: at least one of the memory devices and a memory controller, which is coupled to the memory device and controls the memory device.

[0057] Fifthly, embodiments of this application also provide a computer system including the aforementioned memory system and an image processor, which is coupled to and controls the memory system.

[0058] This application provides a memory device, a power supply method, a charge pump circuit, and a system. The memory device includes: a memory cell array; the memory cell array includes: a plurality of memory cell rows and word lines coupled to each memory cell row; and peripheral circuitry, the peripheral circuitry being coupled to the corresponding memory cell rows via the word lines, and including: a first power supply circuit and a second power supply circuit, wherein the first power supply circuit is configured to: at a first moment, begin outputting a first voltage to the substrate of a first transistor included in a first word line driving circuit coupled to a first unselected word line; the second power supply circuit is configured to: at a second moment, begin outputting a second voltage to one end of the first transistor; wherein the first moment is earlier than the second moment. The memory device provided by this application reduces the coupling effect generated during the power-on process by providing voltages to the substrate and one end of the transistor included in the word line driving circuit at different times, thereby effectively suppressing overshoot generated during the power-on process. Attached Figure Description

[0059] In accompanying drawings that are not necessarily drawn to scale, the same reference numerals can describe similar components in different views. The same numbers with different letter suffixes can represent different instances of similar components. The accompanying drawings generally illustrate the various embodiments discussed in this document by way of example, not limitation.

[0060] Figure 1 This is a schematic diagram illustrating the composition principle of the memory device provided in the embodiments of this application;

[0061] Figure 2 Schematic diagram of the distribution of the memory cell array and peripheral circuits provided in the embodiments of this application. Figure 1 ;

[0062] Figure 3 Top view of the distribution of the memory cell array and peripheral circuits provided in the embodiments of this application. Figure 1 ;

[0063] Figure 4 Schematic diagram of the distribution of the memory cell array and peripheral circuits provided in the embodiments of this application. Figure 2 ;

[0064] Figure 5 Top view of the distribution of the memory cell array and peripheral circuits provided in the embodiments of this application. Figure 2 ;

[0065] Figure 6 Schematic diagram of the structure of the memory device provided in the embodiments of this application Figure 1 ;

[0066] Figure 7 A schematic diagram illustrating the connection relationship between the memory unit and the word line driving circuit provided in an embodiment of this application;

[0067] Figure 8 Timing diagrams between the first voltage, the second voltage, and the third voltage provided in embodiments of this application;

[0068] Figure 9 Schematic diagram of the structure of the memory device provided in the embodiments of this application Figure 2 ;

[0069] Figure 10 A schematic diagram illustrating the distribution of blocks in a bank, provided for an embodiment of this application;

[0070] Figure 11 Schematic diagram of the structure of the first power supply circuit provided in the embodiments of this application Figure 1 ;

[0071] Figure 12 This is a schematic diagram of a voltage generator provided in an embodiment of this application;

[0072] Figure 13 An exemplary schematic diagram illustrating the control of the negative charge pumps provided in an embodiment of this application;

[0073] Figure 14 Schematic diagram of the structure of the first power supply circuit provided in the embodiments of this application Figure 2 ;

[0074] Figure 15 A schematic diagram of a voltage regulator comprising three sets of P-type transistors and N-type transistors provided in an embodiment of this application;

[0075] Figure 16 A schematic diagram of a voltage regulator comprising a set of P-type transistors and N-type transistors provided for embodiments of this application;

[0076] Figure 17 A schematic diagram of the structure of a set of second comparators provided in an embodiment of this application;

[0077] Figure 18 A schematic diagram of the structure of a third comparator provided in an embodiment of this application;

[0078] Figure 19 Schematic diagram of the structure of the memory device provided in the embodiments of this application Figure 3 ;

[0079] Figure 20 A schematic flowchart illustrating a power supply method for a memory device provided in an embodiment of this application;

[0080] Figure 21 A schematic diagram of an exemplary structure of a charge pump circuit provided in an embodiment of this application;

[0081] Figure 22 This is a schematic block diagram illustrating the composition of an electronic device provided in an embodiment of this application.

[0082] Figure 23 This is a schematic block diagram illustrating an exemplary solid-state drive (SSD) or a storage device via flash memory (UFS) according to an embodiment of this application.

[0083] Figure 24 A schematic block diagram illustrating the composition of an exemplary memory provided in the embodiments of this application.

[0084] Figure 25 This is an exemplary schematic diagram of a computer system provided in an embodiment of this application. Detailed Implementation

[0085] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0086] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0087] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0088] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0089] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0090] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0091] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0092] DRAM is a semiconductor memory device that uses an array of memory cells, each consisting of a capacitor and a transistor. It primarily uses the amount of charge stored in the capacitor to represent a binary bit (1 or 0). The term "dynamic" is relative to the static nature of SRAM. In DRAM, due to capacitor leakage, charge is lost over time, leading to insufficient potential and data loss. Therefore, frequent charging to maintain the potential is necessary; this charging process is called self-refresh. This refresh operation continues until the data changes or power is lost. Therefore, DRAM is volatile when power is off.

[0093] Specifically, regarding the understanding of DRAM, such as... Figure 1 The diagram shown illustrates an exemplary memory device DRAM according to an embodiment of this application. Figure 1The right side shows the circuitry of a memory cell in a DRAM. Each DRAM chip 104 (Die) includes a memory cell array, which contains multiple memory cells 101 arranged in an array. Each memory cell 101 includes a transistor T and a capacitor C. The main working principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array, which can be viewed as a typical mesh structure. The memory cell array uses rows and columns to specify addresses. By specifying the intersection of the rows and columns (by specifying the row address and column address of the DRAM), the memory controller (such as those shown later)... Figure 22 The memory controller can independently access each memory cell in the DRAM chip and perform read or write operations on the data stored therein.

[0094] In some embodiments, the memory device may include a memory cell array and peripheral circuitry. The memory cell array may include multiple banks, each bank being divided into multiple blocks or memory banks. Each block includes multiple rows and columns of memory cells. Each row of memory cells is coupled to a corresponding word line, and each column of memory cells is coupled to a corresponding bit line. The peripheral circuitry may include a series of complementary metal-oxide-semiconductor (CMOS) control circuitry. For example, this series of CMOS control circuitry includes: control circuitry corresponding to each memory block, such as a sensing amplifier (SA) and a word-line driver (WLD); control circuitry corresponding to each memory cell, such as a row decoder and a column decoder; and control circuitry corresponding to all memory cells, such as a command buffer, a command decoder, an address buffer, a data buffer, and a mode register.

[0095] In practical applications, the layout between the memory cell array and peripheral circuitry is important. In some embodiments, the memory cell array and peripheral circuitry are arranged side-by-side on the same substrate. An example is... Figure 2 The diagram shows the distribution of the memory cell array and peripheral circuitry in the exemplary memory. Figure 1 ; Figure 3 Top view of the distribution of the memory cell array and peripheral circuitry in the exemplary memory shown. Figure 1 .like Figure 2As shown, the storage cell array 201 and the peripheral circuit 202 are arranged side by side. More specifically, the storage cell array includes M banks, each bank includes N blocks, each block has a control circuit on at least one side, and each bank has a control circuit on at least one side. Every K banks in the M banks form a bank row, and the M banks form M / K bank rows. Peripheral circuits corresponding to all banks are arranged between the two middle bank rows. It should be noted that M, N, and K are all positive integers, and M is an integer multiple of K.

[0096] For example, such as Figure 3 As shown, the storage cell array 201 includes 16 banks 201-1, each bank comprising multiple blocks. Each block has corresponding SA and WLD arrays arranged around its perimeter. Each bank has a corresponding column decoder 304 and row decoder 306 on its sides. Every four banks form a bank row, and the 16 banks form four bank rows. A control circuit 302 is located between the two middle bank rows. It should be noted that... Figure 3 The number of repositories in the example is for illustrative purposes only and is not intended to limit the number of repositories in the storage device in this application.

[0097] In some embodiments, the memory cell array 201 and the peripheral circuitry 202 may also be disposed on two substrates. An exemplary memory, such as... Figure 4 As shown, it includes: a first substrate 100, which includes at least a memory cell array 201; a second substrate 200, which includes at least a peripheral circuit 202; the first substrate 100 and the second substrate 200 are stacked and connected by bonding.

[0098] Here, the first substrate 100 may include, but is not limited to, a silicon substrate. The first substrate 100 may at least include a memory cell array 201. Later, the first substrate 100 may also include a dummy memory cell array. The memory cell array 201 may include multiple banks arranged in an array. Each bank includes multiple blocks, also called memory cells, arranged in an array. Each block includes multiple rows and columns of memory cells. Each row and column of memory cells includes multiple memory cells. The memory cell array 201 may also include multiple word lines and multiple bit lines. Each row of memory cells is coupled to a corresponding word line, and each column of memory cells is coupled to a corresponding bit line.

[0099] Here, the second substrate 200 is a different substrate from the first substrate 100, and the second substrate 200 includes, but is not limited to, a silicon substrate. In the following text, the second substrate 200 may include peripheral circuitry 202; said peripheral circuitry 202 may include control circuitry corresponding to memory blocks and / or control circuitry corresponding to memory repositories. Here, peripheral circuitry 202 also includes control circuitry corresponding to all memory repositories, such as command registers, command decoders, address registers, data registers, mode registers, etc.

[0100] In some embodiments, such as Figure 4 The memory shown may further include: a bonding interface located between the first substrate and the second substrate; a first interconnect layer located between the first substrate and the bonding interface; a second interconnect layer located between the second substrate and the bonding interface; the first substrate and the second substrate are connected through the first interconnect layer, the bonding interface, and the second interconnect layer.

[0101] Here, the memory device may further include a bonding interface, a first interconnect layer, and a second interconnect layer. Both the first and second interconnect layers may include multiple bonding contacts and a dielectric material electrically isolating the bonding contacts. In some embodiments, the bonding contacts may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof; the dielectric material may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics (dielectric constant less than 3.9), or any combination thereof. In some embodiments, the first interconnect layer is formed on a first substrate; the second interconnect layer is formed on a second substrate; then, the memory cell array contained in the first substrate and the peripheral circuitry contained in the second substrate are bonded at the bonding interface, and the bonding contacts and the surrounding dielectric material may be connected using hybrid bonding. That is, in some embodiments, the bonding interface is formed perpendicularly between the first and second interconnect layers. In some embodiments, the memory cell array in the first substrate and the peripheral circuit in the second substrate are bonded at the bonding interface through bonding contacts included in the first interconnect layer and bonding contacts included in the second interconnect layer, so as to realize the connection between the memory cell array and the peripheral circuit.

[0102] For example, Figure 5 As shown, it is a top view illustrating the distribution of the memory cell array and peripheral circuitry in the memory. Figure 2 It should be noted that, Figure 5 The first substrate 100 is located above the second substrate 200, and Figure 5 The solid lines correspond to the structures located in the first substrate 100, and the dashed lines correspond to the structures located in the second substrate 200. For ease of understanding, the structures in the second substrate 200 are shown in perspective.

[0103] For example, such as Figure 5 As shown, the storage unit array 201 includes 16 banks 201-1, each bank including multiple blocks. Directly below each block are a first SA and a second SA arranged opposite each other along a first direction, and a first WLD and a second WLD arranged opposite each other along a second direction. Below each bank on both sides are column decoders 304 and row decoders 306 corresponding to the bank. Every four banks form a bank row, and the 16 banks form four bank rows. A control circuit 302 is arranged below the middle two bank rows.

[0104] It should be noted that, Figure 5 The number of memory repositories is for illustrative purposes only and is not intended to limit the number of memory repositories in this application. The space originally used to house the control circuitry corresponding to each memory block in the first substrate can be left free, thereby providing more space for the arrangement of memory cells, word lines, and bit lines.

[0105] It should be noted that, Figure 5 The size relationship between a memory block and the surrounding SA and word line drivers shown is for illustrative purposes only and is not intended to limit the size relationship between a memory block and a programming logic subunit and the surrounding SA and word line drivers in the memory of this application.

[0106] It should be noted that the above are only two exemplary layouts of the memory cell array and peripheral circuits. Other layouts are also possible in practice. This application does not focus on the layout of the memory cell array and peripheral circuits, and will not elaborate on more layouts here. The operation method provided in the embodiments of this application is applicable to memory cell arrays and peripheral circuits with various layouts.

[0107] In practical applications, during the power-on process of reading, writing, and refreshing memory devices as described above, a large voltage overshoot phenomenon may occur between word lines and bit lines coupled to unselected memory cells, and between the substrate and source terminals of transistors included in word line drive circuits, due to the coupling effect.

[0108] To solve one or more of the above technical problems, such as Figure 6 As shown, this application embodiment provides a memory device 600, which may include:

[0109] Storage cell array 601; the storage cell array 601 includes: a plurality of storage cell rows and word lines coupled to each storage cell row; and

[0110] The peripheral circuit 602 is row-coupled to the corresponding memory cell via the word line, and includes: a first power supply circuit 6011 and a second power supply circuit 6012, wherein...

[0111] The first power supply circuit 6011 can be configured to: at a first moment, start outputting a first voltage to the substrate of the first transistor included in the first word line driving circuit coupled to the first unselected word line;

[0112] The second power supply circuit 6012 can be configured to: start outputting a second voltage to one end of the first transistor at a second time; wherein the first time is earlier than the second time.

[0113] Wherein, the first voltage and the second voltage are negative voltages.

[0114] The second voltage is provided to the source terminal of the first transistor.

[0115] It should be noted that the memory cell array 601 and peripheral circuit 602 mentioned here can be referred to in the previous section. Figures 1 to 5 The described structure is understood. In this embodiment, adjustments are made to some circuits in the peripheral circuitry; these adjustments will be described in detail below with reference to the accompanying drawings.

[0116] Specifically, the peripheral circuit 602 includes a first power supply circuit 6011 and a second power supply circuit 6012. Here, the first and second power supply circuits can be negative charge pump circuits, the specific structure of which will be described in detail below. The first word line driving circuit can be a driving circuit that drives the first unselected word line, and the first power supply circuit provides voltage to the substrate of the first transistor included in the first word line driving circuit, while the second power supply circuit provides voltage to one end (such as the source terminal) of the first transistor. The first unselected word line mentioned here is the word line coupled to an unselected memory cell; this is only one example. Unless otherwise specified, the operation of other unselected word lines can be referred to the operation of the first unselected word line. An unselected memory cell can refer to a memory cell that is prohibited from being operated on, such as a memory cell that is prohibited from being written to, read from, or refreshed. That is, during read, write, and refresh operations of the memory device, the substrate and one end (such as the source terminal) of the transistor in the driving circuit corresponding to the unselected word line coupled to the unselected memory cell in the memory cell array are provided with a negative voltage to prevent operation.

[0117] To reduce the coupling response between the substrate and source terminals of the relevant transistors, this application embodiment provides that, at a first moment, a first voltage (i.e., a negative voltage) is output to the substrate of the first transistor, namely VBB; then, at a second moment, a second voltage (also a negative voltage) is output to the source terminal of the first transistor, namely VWLN. Here, the first moment can be earlier than the second moment, and the voltage values ​​of both the first voltage and the second voltage increase over time until they reach the corresponding target voltage values.

[0118] In some embodiments, the plurality of memory cell rows may include a plurality of memory cells; the memory cell includes: a second transistor and a capacitor; wherein a first end of the second transistor is connected to one end of the capacitor, a second end of the second transistor is connected to its corresponding bit line, and a control end of the second transistor is connected to its corresponding word line; wherein the first power supply circuit may also be configured to: provide the first voltage to the substrate of the second transistor.

[0119] It should be noted that if Figure 1 As shown, a memory cell includes a transistor and a capacitor, which are arranged in an array. In some embodiments, the substrate of the second transistor included in the memory cell is the same substrate as the substrate of the first transistor included in the word line driving circuit. In other embodiments, the substrate of the second transistor included in the memory cell and the substrate of the first transistor included in the word line driving circuit are connected to the same voltage source. Regardless of the above, that is, in the embodiments of this application, the first voltage provided by the first power supply circuit can also be provided to the substrate of the second transistor included in the memory cell.

[0120] To understand the above scheme, such as Figure 7 The diagram illustrates the circuit connection structure between the word line driver circuit and the memory cell provided in this embodiment. XPP_INV is a power supply circuit for the word line driver circuit, and its output terminal xpp_1 or xpp_0 is connected to the XPP terminal of the word line driver circuit WL_DRV. The word line driver circuit WL_DRV includes two first transistors T1. CELL refers to the memory cell. Figure 7The memory cell type is a capacitor-type memory cell, which includes a second transistor T2 and a capacitor, i.e., 1T1C. In actual use, node XPP is connected to xpp_1 or xpp_0 of the power supply circuit XPP_INV. When the power supply circuit XPP_INV and WL_DRV are working, when each enable signal xpp_b_1 or xpp_b_0 is in an active state (low level), XPP_INV_en is in an active state (high level), MWL_b is in an active state (low level), and WLD is in an inactive state (low level), the word line WL is pulled up to Vpp. The above process is the driving flow for the selected word line. This application focuses on the driving of the unselected word line. Unless otherwise specified below, the driving process and voltage application operations described are all related to the circuit of the unselected word line.

[0121] Based on this, Figure 7 Under the structure shown, the solution provided by this application embodiment is as follows: At a first moment, the first power supply circuit starts to output a first voltage to the substrates of the first transistor and the second transistor, that is, to provide a negative voltage VBB to the substrates of the first transistor and the second transistor; then, at a second moment, the second power supply circuit starts to output a second voltage to the source terminal of the first transistor, that is, to provide a negative voltage VWLN to the source terminal of the first transistor. Furthermore, the first voltage and the second voltage can be voltage signals that increase in the negative direction from zero. As described above, this is a suppression operation (or disable operation) for memory cells coupled to unselected word lines, that is, first making the voltage value of VBB rise in the negative direction (ramping), and then making the voltage value of VWLN rise in the negative direction (ramping). This design weakens the coupling effect caused by the simultaneous ramping of the two, effectively suppressing the voltage overshoot phenomenon on the substrate and source terminal of the transistor during the rising process. Furthermore, when a negative voltage is applied to the substrate and source terminal of the first transistor of the first word line driving circuit, and the power supply circuit XPP_INV of the first word line driving circuit is not working, the word line voltage of the memory cell coupled to the first unselected word line is negative, thereby suppressing the operation of the memory cell.

[0122] In some embodiments, the first power supply circuit may be further configured to: respond to a first enable signal at a first moment, start outputting the first voltage, and after a first duration, the voltage value of the first voltage reaches a preset voltage value; and after a second duration, the voltage value of the first voltage reaches a first target voltage value.

[0123] In some embodiments, the second power supply circuit may also be configured to: in response to a second enable signal at a second time moment, start outputting the second voltage, and after a third time period, the voltage value of the second voltage reaches a second target voltage value.

[0124] It should be noted that the first and second voltages mentioned above can be voltages that ramp from zero to the negative over time. Based on this, for the first voltage, after a first time interval starting from a first moment, its voltage value reaches a preset voltage value, and after a second time interval, its voltage value reaches a first target voltage. For the second voltage, after a third time interval starting from a second moment, its voltage value reaches a second target voltage value. The first, second, and third time intervals are determined by the preset voltage value, the first target voltage value, and the second target voltage value, respectively, and are not limited here.

[0125] The second moment corresponds to the moment when the voltage value of the first voltage rises to the preset voltage value.

[0126] In some embodiments, the preset voltage value accounts for 50% to 90% of the first target voltage value.

[0127] It should be noted that the second moment can correspond to the moment when the voltage value of the first voltage rises to a preset voltage value, wherein the preset voltage value accounts for 50% to 90% of the first target voltage value of the first voltage. In some embodiments, the preset voltage value can account for 50% of the first target voltage value. In other embodiments, the preset voltage value can account for 90% of the first target voltage value. That is, the range of this proportion includes both endpoint values.

[0128] For example, Figure 8 As shown, it illustrates a timing diagram of a first voltage, a second voltage, and a third voltage, which will be described later. Figure 8 As shown, for the first voltage, at time t1, the first power supply circuit begins to output the first voltage. After a first time interval, i.e., at time t2, its voltage value reaches the preset voltage value, which is 70% of the first target voltage value. After a second time interval, i.e., at time t3, the first voltage value reaches the first target voltage value. It should be understood that, as described above, the first voltage is a negative voltage; therefore, the voltage value mentioned here refers only to its magnitude and is not used to indicate direction. Similarly, for the second voltage, the second power supply circuit begins to output the second voltage at time t2, and after a third time interval, i.e., at time t4, its voltage value reaches the second target voltage value.

[0129] In some embodiments, such as Figure 9As shown, the peripheral circuit may further include: a third power supply circuit 6013; wherein,

[0130] The first power supply circuit 6011 can also be configured to: at the first moment, start outputting the first voltage to the substrate of the third transistor included in the second word line driving circuit coupled to the second unselected word line;

[0131] The third power supply circuit 6013 can be configured to: start outputting a third voltage to one end of the third transistor at a third time; wherein the first time is earlier than the third time.

[0132] The third voltage is provided to the source terminal of the third transistor.

[0133] Wherein, the third voltage is a negative voltage, and the absolute value of the third target voltage value of the third voltage is greater than the second target voltage value of the second voltage.

[0134] In practical applications, because the unselected memory cell rows at different distances from the selected word line have varying degrees of influence on the operation of the selected memory cell, the closer the unselected memory cell row is to the selected memory cell row, the greater its influence; conversely, the farther the unselected memory cell row is from the selected memory cell row, the smaller its influence. Therefore, different negative voltages can be applied to unselected word lines at different distances from the selected word line, and the closer the unselected word line is to the selected word line, the larger the negative voltage applied. This effectively reduces the influence of these unselected word lines on the operation of the selected memory cell coupled to the selected word line. Based on this, in this embodiment, at a first moment, a first voltage is output to the substrate of the third transistor contained in the second unselected word line via a first power supply circuit; at a third moment, a third voltage is output to the source terminal of the third transistor via a third power supply circuit, and the first moment is earlier than the third moment. The third target voltage value of the third voltage is greater than the second target voltage value of the second voltage.

[0135] In some embodiments, the third moment may be the same as the aforementioned second moment.

[0136] In some embodiments, the third moment may not be the same as the aforementioned second moment. For example, since the third target voltage value of the third voltage is greater than the second target voltage value of the second voltage, the third moment may be earlier than the second moment in order not to increase the overall operating time.

[0137] In practical applications, the third time point can also be later than the second time point, as long as the time difference between the third and second time points has little impact on the overall operation time. Specifically, the relationship between the third and second time points can be determined based on the actual situation, and no restrictions are imposed here.

[0138] In this embodiment, the power supply voltages for generating the second and third voltages are provided by two different power supply circuits: a second power supply circuit and a third power supply circuit. In practical applications, where power supply technology allows, the second and third voltages can be obtained separately by controlling the ramp time; that is, the second and third power supply circuits can also be the same power supply circuit. The relationship between the second and third power supply circuits can also be selected according to the actual situation and is not limited.

[0139] Based on this, such as Figure 8 As shown, it provides a timing diagram of the second and third voltages when the second and third times are the same. The change of the second voltage over time has been described above. For the third voltage, the third power supply circuit starts outputting the third voltage at time t2, and after a fourth time interval, that is, at time t5, its voltage value reaches the third target voltage value.

[0140] As described above, the source terminals of the transistors contained in the unselected word lines can be applied with different voltages. In some embodiments, the memory cell array may include multiple memory blocks; each memory block includes the multiple memory cell rows and word lines coupled to each memory cell row; wherein the second unselected word line includes word lines belonging to the same memory block as the selected word line.

[0141] In some embodiments, the second unselected word line also includes at least a portion of the word lines contained in a storage block adjacent to the storage block where the selected word line is located.

[0142] In some embodiments, the first unselected character line includes other unselected character lines besides the second unselected character line.

[0143] To illustrate the above situation, for example, such as Figure 3 or Figure 5 The diagram illustrates an exemplary structure of a storage cell array. The storage cell array includes multiple banks, and each bank includes multiple storage blocks. Here, as... Figure 10 The diagram illustrates the structure of a storage block in a column of a Bank according to an embodiment of this application. In Block 0, sel WLn is the selected word line. WLn-1, WLn-2, ​​WLn+1, etc., in Block 0 are all unselected word lines, and the word lines in the remaining Blocks are also unselected word lines. Based on... Figure 10In the storage cell array shown in this embodiment, the second unselected word line may include word lines such as WLn-1, WLn-2, ​​and WLn+1 in Block 0. The second unselected word line may also include at least a portion of Block 1 and Block 1'; for example, this at least a portion may be all of them; or the at least a portion may be half of the word lines in Block 1 and Block 1' that are closer to the selected word line. The so-called first unselected word line may be any other unselected word line besides the second unselected word line, for example, all word lines from Block 1 and Block 1' up to Block n and Block n'.

[0144] In some embodiments, as Figure 11 As shown, the first power supply circuit 110 may include a first comparator 1101 and a voltage generator 1102, wherein the first comparator 1101 may be configured to compare a reference voltage and a first feedback voltage, and output a first control signal according to the comparison result; the first feedback voltage is obtained according to the first voltage output by the voltage generator.

[0145] The voltage generator 1102 can be configured to output the first voltage according to the first control signal.

[0146] It should be noted that, as mentioned earlier, the first power supply circuit can be a negative charge pump circuit, the specific circuit... Figure 11 As shown, it includes a first comparator 1101 and a voltage generator 1102. The first comparator 1101 receives a reference voltage and a first feedback voltage, compares the reference voltage and the first feedback voltage to obtain a comparison result, generates a first control signal based on the comparison result, and transmits the first control signal to the voltage generator. Then, the voltage generator 1102 receives the first control signal and outputs a first voltage based on the first control signal.

[0147] Wherein, the first feedback voltage is the feedback voltage of the first voltage output by the voltage generator. In some embodiments, such as Figure 11 As shown, the first power supply circuit 110 may further include a feedback generator 1103, which can be configured to receive the first voltage and output the first feedback voltage according to the first voltage.

[0148] The reference generator 1104 can be configured to output the reference voltage.

[0149] That is, the first power supply circuit may further include a feedback generator that generates a first feedback voltage. Specifically, the feedback generator receives a first voltage and outputs a first feedback voltage based on the first voltage. For the feedback generator 1103, in some embodiments, the feedback generator 1103 may include: a fourth transistor and a plurality of first resistors connected in series, wherein...

[0150] The first terminal of the fourth transistor is connected to the first voltage, and its second terminal is connected to the first terminal of the plurality of first resistors; the second terminals of the plurality of first resistors are connected to the first initial voltage.

[0151] At a first moment, the control terminal of the fourth transistor is connected to a first enable signal, and the feedback generator outputs the first feedback voltage; the first feedback voltage is the voltage between two of the plurality of first resistors.

[0152] Here, the fourth transistor, such as Figure 11 The fourth transistor T4 in the circuit. Multiple first resistors connected in series, such as... Figure 11 The diagram shows multiple first resistors R1 connected in series. A first terminal (e.g., the drain terminal) of a fourth transistor T4 is connected to a first voltage, and its second terminal is connected to the first terminals of the multiple first resistors R1. The second terminals of the multiple first resistors are connected to a first initial voltage pump_vreg. At a first moment, the control terminal of the fourth transistor T4 is connected to a first enable signal en1, and the feedback generator is connected to a first voltage with a value of 0, outputting a first feedback voltage Vbb_fb at the first moment. Subsequently, as the value of the first voltage changes, the first feedback voltage also changes. The value of the first feedback voltage at the first moment can be determined based on a first target voltage value to determine which two first resistors the first feedback voltage is between. One example is... Figure 11 As shown, the first feedback voltage is the voltage between the topmost first resistor and its adjacent first resistor. Specifically, the appropriate resistor can be selected based on the actual situation.

[0153] In some embodiments, the reference generator 1104 may include: a plurality of second resistors connected in series; wherein,

[0154] The first end of the plurality of second resistors is connected to the first initial voltage; the other end of the plurality of second resistors is grounded, wherein the reference voltage is the voltage between two of the plurality of second resistors.

[0155] For example, Figure 11As shown, the reference generator 1104 includes three second resistors R2, and the reference voltage vref can be the voltage between the uppermost second resistor and its adjacent second resistor. Specifically, the appropriate resistor can be selected based on the actual situation. In practical applications, to ensure a wider adjustment range for the reference voltage, some of the second resistors can be adjustable, for example... Figure 11 The second resistor shown as grounded is the adjustable resistor.

[0156] In some embodiments, such as Figure 11 As shown, the feedback generator may further include a fifth transistor and a sixth transistor, wherein,

[0157] The first terminal of the fifth transistor is connected to the first sub-voltage value included in the first initial voltage, and the second terminal is connected to the second terminal of the plurality of first resistors;

[0158] The first terminal of the sixth transistor is connected to the second sub-voltage value included in the first initial voltage, and the second terminal is connected to the second terminal of the plurality of first resistors;

[0159] Specifically, when a second control signal is connected to the control terminal of the fifth transistor, the first power supply circuit operates in a first mode; when a third control signal is connected to the control terminal of the sixth transistor, the first power supply circuit operates in a second mode.

[0160] The first mode is the normal operating mode, meaning the first power supply circuit operates in normal operating mode when the memory device performs read, write, and refresh operations. The second mode is the aging test mode, meaning the first power supply circuit operates in aging test mode when the memory device and other devices undergo electrical tests such as aging tests. Specifically, as shown... Figure 11 As shown, when the second control signal reg_burnin_n is applied to the control terminal of the fifth transistor T5, the first power supply circuit enters the first mode and operates; when the third control signal reg_burnin is applied to the control terminal of the sixth transistor T6, the first power supply circuit enters the second mode and operates. The first initial voltage can be the supplied power supply voltage, and the first sub-voltage value and the second sub-voltage value can be different. For example, the first sub-voltage value can be... Figure 11 The description of pump_vreg; the second sub-voltage value can be preceding it. Figure 11 The VDD2H described.

[0161] In some embodiments, such as Figure 12 As shown, the voltage generator 1102 may include: a clock drive sub-circuit 1201 and a negative charge pump sub-circuit 1202, wherein;

[0162] The clock driving sub-circuit 1201 is configured to: receive the first control signal and generate a fourth control signal based on the first control signal;

[0163] The negative charge pump sub-circuit 1202 is coupled to the clock drive sub-circuit and is configured to receive the fourth control signal and output the first voltage according to the fourth control signal.

[0164] In some embodiments, the negative charge pump circuit may include at least two negative charge pumps, wherein two adjacent negative charge pumps are connected in series or in parallel.

[0165] For example, such as Figure 13 As shown, the negative charge pump subcircuit includes two negative charge pumps, controlled by a control signal ctl and its inverse ctl_n. When ctl = 1, the two negative charge pumps are connected in parallel, making this a first-stage pump circuit; when ctl = 0, the two negative charge pumps are connected in series, making this a second-stage pump circuit. It should be understood that in practical use, this negative charge pump subcircuit can include more than two negative charge pumps, and each pair of adjacent negative charge pumps can be controlled in the above manner to ensure that adjacent negative charge pumps are connected in series or in parallel.

[0166] In some embodiments, as Figure 14 As shown, the first power supply circuit further includes a voltage regulator 1105, which can be configured to receive an adjustment control signal and, in response to the adjustment control signal, adjust the first voltage to a set target voltage value.

[0167] It should be noted that the first power supply circuit also includes a voltage regulator with pull-up capability. Its function is to enable the voltage regulator when the voltage value of the first voltage drops beyond a certain value due to coupling effects, thereby adjusting the voltage value of the first voltage to a set target voltage value. The specific value of the set target voltage can be selected according to the actual circuit and is not limited here. For example, when the voltage of the substrate of the first transistor described above drops by more than 50 millivolts (mV) due to coupling effects, the voltage regulator will be enabled to reduce the pull-down effect. The specific adjustment amount should be selected according to the actual situation. The following is a detailed explanation with reference to the accompanying drawings.

[0168] Specifically, in some embodiments, the adjustment control signal may include at least one sub-control signal; the set target voltage value may include at least one sub-target voltage value; the voltage regulator may include: at least one group of P-type transistors and N-type transistors; in each group, the first terminal of the P-type transistor is connected to a second initial voltage, and its second terminal is connected to the first terminal of the N-type transistor; the second terminal of the N-type transistor is connected to the first voltage; wherein, in each group, the control terminal of the P-type transistor is connected to a third enable signal and the control terminal of the N-type transistor is connected to a corresponding sub-control signal, thereby adjusting the first voltage to the corresponding sub-target voltage value of the corresponding group.

[0169] It should be noted that one sub-control signal corresponds to one sub-target voltage value; one sub-control signal and one sub-target voltage value correspond to a set of P-type transistors and N-type transistors. In each set, the first terminal of the P-type transistor is connected to a second initial voltage, and its second terminal is connected to the first terminal of the N-type transistor; the second terminal of the N-type transistor is connected to a first voltage, and a third enable signal is connected to the control terminal of the P-type transistor and the corresponding sub-control signal is connected to the control terminal of the N-type transistor, thus enabling the adjustment of this setting and adjusting the voltage value of the first voltage to the corresponding sub-target voltage value of the set. The second initial voltage can be the supplied power supply voltage, such as VDD2H.

[0170] For example, such as Figure 15 and Figure 16 As shown, where, Figure 15 This illustration shows a structural schematic of a voltage regulator provided in an embodiment of this application; Figure 16 This diagram illustrates another structural schematic of the voltage regulator provided in an embodiment of this application. Figure 15 In this code, pullup_en is the third enable signal; flag1, flag2, and flag3 are three sub-control signals; the voltage regulator includes three sets of P-type transistors and N-type transistors, which means it has three adjustment levels. Specifically, flag1 corresponds to a set of P-type transistors and N-type transistors, which corresponds to a sub-target voltage value; flag2 corresponds to a set of P-type transistors and N-type transistors, which corresponds to a sub-target voltage value; and flag3 corresponds to a set of P-type transistors and N-type transistors, which corresponds to a sub-target voltage value. Figure 16 The voltage regulator shown includes a set of P-type and N-type transistors, meaning it offers one level of adjustment. Furthermore, its corresponding sub-control signal is the inverse of the third enable signal, pullup_en_n.

[0171] In some embodiments, the first power supply circuit may further include: at least one second comparator; each second comparator is configured to: compare a reference voltage with a corresponding second feedback voltage and output a corresponding sub-control signal; the second feedback voltage is the voltage between two of the series-connected first resistors and is different from the first feedback voltage.

[0172] It should be noted that each second comparator is... Figure 15 The voltage regulator shown contains a set of corresponding P-type and N-type transistors, used to output the corresponding sub-control signals, namely one of flag1, flag2, and flag3.

[0173] For example, Figure 17 The diagram shown illustrates the circuit structure diagram for generating flag1, flag2, and flag3 provided in the embodiments of this application. Figure 17 In this diagram, vref represents the reference voltage. div70 is a voltage value of the second feedback voltage corresponding to flag1. div90 is a voltage value of the second feedback voltage corresponding to flag2. div99 is a voltage value of the second feedback voltage corresponding to flag3. The second feedback voltage is different from the first feedback voltage. The second feedback voltage is used to activate a specific adjustment level of the voltage regulator; the first feedback voltage is related to the first target voltage value of the first voltage and changes with the output of the voltage generator. Alternatively, the second feedback voltage can be a part of the first feedback voltage, meaning that the voltage value of the second feedback voltage is partially equal to the voltage value of the first feedback voltage, such as div70, div90, and div99.

[0174] In some embodiments, the peripheral circuit may further be configured as: a third comparator, configured to: compare a reference voltage and a third feedback voltage, and output a second enable signal according to the comparison result, and output the second enable signal to the second power supply circuit; wherein, the third feedback voltage is obtained when the voltage value of the first voltage reaches a preset voltage value.

[0175] It should be noted that, as described above, the second moment when the second power supply circuit starts to output the second voltage can be the moment when the first voltage rises to the preset voltage value. At this time, the feedback voltage corresponding to the first voltage can be the third feedback voltage. Based on this, the reference voltage is compared with the third feedback voltage using the third comparator, and the second enable signal is output.

[0176] For example, Figure 18 The diagram shown illustrates a structural schematic of a third comparator provided in an embodiment of this application. Figure 18In this circuit, en2 is the second enable signal. The third feedback signal is the feedback voltage when the first voltage rises to 70% of the first target voltage. At this point, the third comparator compares the third feedback voltage with the reference voltage and outputs the second enable signal en2 to the second power supply circuit. It should be noted that in practical applications, when the preset voltage value is 70% of the first target voltage, and the voltage regulator uses the adjustment circuit of the flag1 branch, the corresponding second and third comparators can be the same. That is, flag1 can be the same signal as the second enable signal en2, but it can provide control signals for different voltages.

[0177] The structure of the first power supply circuit has been described in detail above. The structure of the second power supply circuit, which supplies power to the source of the first transistor, and the third power supply circuit, which supplies power to the source of the third transistor, can be the same as or similar to that of the first power supply circuit.

[0178] Specifically, see Figure 11 Let's take the second power supply circuit as an example. First, the overall structure of the second power supply circuit is the same as the first power supply circuit, both including: a first comparator, a feedback generator, a reference generator, a voltage regulator, and a voltage generator. The differences between the second and first power supply circuits are: First, depending on the load, the number of negative charge pumps in the negative charge pump circuit of the voltage generator and the series / parallel connection method between the negative charge pumps can differ. Second, depending on the difference between the second target voltage value and the first target voltage value, such as... Figure 11 The feedback generator shown can include different numbers of first resistors R1, or different output terminals corresponding to Vbb and fb. For example, as... Figure 11 As shown, the exemplary first voltage feedback voltage Vbb_fb is the voltage between the two topmost first resistors R1. If the number of first resistors R1 in the first power supply circuit and the second power supply circuit is the same, then the feedback voltage for the second target voltage value can be the voltage between the other two first resistors R1. If the number of first resistors R1 in the first power supply circuit and the second power supply circuit is different, for example, the feedback voltage for both the first target voltage and the second target voltage can be the voltage between the two topmost first resistors R1, and the number of first resistors R1 in the second power supply circuit is different from the number of first resistors R1 in the first power supply circuit, for example... Figure 11As shown, the number of first resistors R1 in the first power supply circuit is 5; therefore, the number of first resistors R1 in the second power supply circuit can be 6 or more. Thirdly, the enable signal en1 for the fourth transistor T4 is different. Specifically, the enable signal for the fourth transistor T4 in the feedback generator of the first power supply circuit is the first enable signal; the enable signal for the fourth transistor T4 in the second power supply circuit is the second enable signal, which is generated when the first voltage rises to a preset voltage value (such as 70% of the first target voltage value).

[0179] The situation for the third power supply circuit is the same as that for the second power supply circuit. The differences between it and the second power supply circuit and the first construction site circuit can be understood by analogy from the above aspects. For the sake of space, it will not be elaborated here.

[0180] In some embodiments, the absolute value of the first target voltage value of the first voltage is greater than the absolute value of the second target voltage value of the second voltage.

[0181] It should be noted that, as Figure 7 As shown, if the substrate voltage VBB of the first transistor T in the word line driving circuit is greater than VWLN, it will lead to relatively large leakage. Furthermore, since both VBB and VWLN are negative voltages, only when VBB is more negative will the potential at the source terminal of the first transistor T1 be greater than the potential at its substrate. That is, the voltage value of VBB is greater than the voltage value of VWLN, meaning the absolute value of the first target voltage of the first voltage is greater than the second target voltage of the second voltage.

[0182] In some embodiments, such as Figure 19 As shown, the peripheral circuit also includes a fourth power supply circuit 6014, configured to generate a bit line voltage that reaches a fourth target voltage value before the first moment, and provide the bit line voltage to the corresponding bit line.

[0183] It should be noted that, as described above, the coupling effect also includes the coupling effect during the power-on process of the bit lines and word lines. Therefore, in order to reduce the coupling effect between the power-on of word lines and bit lines, the power-on of the corresponding bit lines is completed before the first moment. That is, the fourth supply voltage is used to generate a bit line voltage that reaches the fourth target voltage value before the first moment and is provided to the corresponding bit lines.

[0184] In this embodiment, by providing different start-amp voltages to the source terminal of the first transistor and the substrate of the word line driving circuit corresponding to the unselected word line, the coupling effect caused by power-on is reduced. Furthermore, based on the different distances from the selected word line, the unselected word line is divided into a first unselected word line and a second unselected word line, so that different negative voltage values ​​are applied to the source terminal of the first transistor contained therein. This effectively improves the impact of the unselected word line, which is closer to the selected word line, on the operation of the memory cell coupled to the selected memory cell.

[0185] Based on the memory devices described above, such as Figure 20 As shown, this application embodiment provides a power supply method for a memory device, which may include:

[0186] Step 2001: At a first moment, a first voltage is generated and provided to the substrate of the first transistor contained in the first word line driving circuit coupled to the first unselected word line;

[0187] Step 2002: At the second moment, a second voltage is generated and supplied to one end of the first transistor;

[0188] The first moment is earlier than the second moment.

[0189] In some embodiments, the second voltage is provided to the source terminal of the first transistor.

[0190] In some embodiments, the method further includes: in response to a first enable signal at a first moment, starting to generate the first voltage, and after a first duration, the voltage value of the first voltage reaches a preset voltage value; and after a second duration, the voltage value of the first voltage reaches a first target voltage value; wherein the preset voltage value accounts for 50% to 90% of the first target voltage value.

[0191] In some embodiments, the method further includes: in response to a second enable signal at a second time moment, starting to generate the second voltage, and after a third time period, the voltage value of the second voltage reaches a second target voltage value; wherein the second time moment corresponds to the time when the voltage value of the first voltage rises to the preset voltage value.

[0192] In some embodiments, the method further includes providing the first voltage to the substrate of a second transistor contained in a memory cell of the memory device.

[0193] In some embodiments, the first voltage and the second voltage are negative voltages, and the absolute value of the first target voltage value of the first voltage is greater than the absolute value of the second target voltage value of the second voltage.

[0194] In some embodiments, the method further includes: at a first moment, providing a first voltage to the substrate of a third transistor included in a second word line driving circuit coupled to a second unselected word line; at a third moment, starting to generate a third voltage and providing the third voltage to the source terminal of the third transistor; the first moment being earlier than the third moment; wherein the third voltage is a negative voltage, and the absolute value of a third target voltage value of the third voltage is greater than a second target voltage value of the second voltage.

[0195] In some embodiments, the memory device includes a plurality of memory blocks; each memory block includes a plurality of memory cell rows and word lines coupled to each memory cell row; wherein the second unselected word line includes word lines belonging to the same memory block as the selected word line.

[0196] In some embodiments, the second unselected word line also includes at least a portion of the word lines contained in a storage block adjacent to the storage block where the selected word line is located.

[0197] In some embodiments, the first unselected character line includes other unselected character lines besides the second unselected character line.

[0198] In some embodiments, generating the first voltage includes: comparing a reference voltage and a first feedback voltage, and generating a first control signal based on the comparison result; and generating the first voltage based on the first control signal; the first feedback voltage is a feedback voltage obtained based on the first voltage.

[0199] In some embodiments, the method further includes: receiving an adjustment control signal; and adjusting the first voltage to a set target voltage value in response to the adjustment control signal; wherein the adjustment control signal is obtained based on a comparison between a reference voltage and a second feedback voltage; and the second feedback voltage is obtained based on the first voltage and is different from the first feedback voltage.

[0200] In some embodiments, the method further includes: comparing a reference voltage and a third feedback voltage, and outputting a second enable signal based on the comparison result; wherein the third feedback voltage is obtained when the voltage value of the first voltage reaches the preset voltage value.

[0201] In some embodiments, the method further includes: generating a bit line voltage that reaches a fourth target voltage value before a first time moment, and providing the bit line voltage to the corresponding bit line.

[0202] It should be noted that the power supply method provided in this application embodiment is based on the use and control method of the power supply circuit included in the memory device provided above. Its specific working principle has been described in detail above, and will not be repeated here to save space.

[0203] Based on the preceding concept, as before Figure 21 As shown, this application embodiment also provides a charge pump circuit 210 for a memory device, including: a feedback generator 2103, a reference generator 2104, a first comparator 2101, and a voltage generator 2102, wherein,

[0204] The feedback generator 2103 is connected between the first node and the output terminal of the voltage generator, and it has an input terminal that receives the first enable signal, and one of its output terminals is connected to the first input terminal of the first comparator.

[0205] The reference generator 2104 is connected between the first node and ground, and its output is connected to the second input of the first comparator.

[0206] The output terminal of the first comparator 2101 is connected to the input terminal of the voltage generator;

[0207] The voltage generator 2102 outputs a negative voltage.

[0208] The first node can be connected to the first sub-voltage value of the first initial voltage described above.

[0209] In some embodiments, the feedback generator 2103 includes: a fourth transistor and a plurality of first resistors connected in series, wherein a first terminal of the fourth transistor is connected to the output terminal of the voltage generator, and a second terminal is connected to a first terminal of the plurality of first resistors connected in series; the second transistor further has a control terminal that receives the first enable signal; a second terminal of the plurality of first resistors connected in series is connected to the first node; and an output terminal led out between two of the plurality of first resistors connected in series is connected to a first input terminal of the first comparator.

[0210] In some embodiments, the feedback generator 2103 may further include: a fifth transistor and a sixth transistor, wherein a first terminal of the fifth transistor is connected to the first node, and a second terminal is connected to the second terminal of the series-connected plurality of first resistors; the fifth transistor also has a control terminal for receiving a second control signal; a first terminal of the sixth transistor is connected to the second node, and a second terminal is connected to the second terminal of the series-connected plurality of first resistors; the sixth transistor also has a control terminal for receiving a third control signal.

[0211] The second node can be connected to the second sub-voltage value of the first initial voltage described above.

[0212] In some embodiments, the reference generator 2104 may include: a plurality of second resistors connected in series; wherein a first terminal of the plurality of second resistors is connected to a second terminal of the fifth transistor and a second terminal of the sixth transistor; a second terminal of the plurality of second resistors is grounded; and an output terminal led out between two of the plurality of second resistors is connected to a second input terminal of the first comparator.

[0213] In some embodiments, the charge pump circuit may further include: a voltage regulator 2105; the voltage regulator includes: at least one set of P-type transistors and N-type transistors; in each set, a first terminal of the P-type transistor is connected to a third node, and a second terminal of the P-type transistor is connected to a first terminal of the N-type transistor; the P-type transistor also has a control terminal that receives a third enable signal; the second terminal of the N-type transistor is connected to the output terminal of the voltage generator; the N-type transistor also has a control terminal that receives a corresponding sub-control signal.

[0214] In some embodiments, the charge pump circuit may further include: at least one second comparator; a first input terminal of each second comparator is connected to an output terminal of the feedback generator, and a second input terminal is connected to an output terminal of the reference generator; and an output terminal of each second comparator is connected to a control terminal of the corresponding group of N-type transistors.

[0215] In some embodiments, the charge pump circuit may further include: a third comparator, the first input of which is connected to the first output of the feedback generator; the second input of which is connected to the output of the reference generator; and the output of the second comparator and an output second enable signal; wherein the voltage value output by the first output is a preset voltage value; and the second enable signal is used to enable other charge pump circuits.

[0216] In some embodiments, the voltage generator may include: a clock drive subcircuit and a negative charge pump subcircuit, wherein: the input terminal of the clock drive subcircuit is connected to the output terminal of the first comparator; the output terminal of the clock drive subcircuit is coupled to the input terminal of the negative charge pump subcircuit; and the output terminal of the negative charge pump subcircuit outputs the negative voltage.

[0217] In some embodiments, the negative charge pump circuit may include at least two negative charge pumps, wherein two adjacent negative charge pumps are connected in series or in parallel.

[0218] It should be noted that the charge pump circuit provided in this application embodiment is an exemplary structure of the first power supply circuit, the second power supply circuit, and the third power supply circuit described above. Its function has been described in detail above and will not be repeated here. Here, Vfb is the feedback voltage of the negative voltage.

[0219] Based on the preceding ideas, such as Figure 22 As shown, this application embodiment also provides a memory system 220, including: at least one of the above-described memory devices 2201 and a memory controller 2202, which is coupled to the memory devices and controls the memory devices.

[0220] Among them, such as Figure 22 As shown, the memory system 220 can be included in electronic device 1. Electronic device 1 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 22 As shown, electronic device 1 may include a host and a memory system 220. The memory system 220 includes a memory controller 2202 and one or more memory devices 2201. The host may be a processor of the electronic device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)). The host may be configured to send data to or receive data from the memory device 2201. The memory controller 2202 is coupled to the memory device 2201 and the host and is configured to control the memory device 2201. The memory controller 2202 may manage the data stored in the memory device 2201 and communicate with the host.

[0221] The memory controller 2202 can be configured to control the operation of the memory device 2201, such as read, erase, write, and refresh operations. In some embodiments, the memory controller 2202 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory device 2201. The memory controller 2202 can also perform any other suitable functions, such as formatting the memory device 2201.

[0222] In some specific embodiments, the memory controller 2202 and one or more memory devices 2201 can be integrated into various types of electronic devices. For example, the memory controller 2202 can be integrated into the northbridge of a computer motherboard or directly into the computer CPU, and multiple memory devices 2201 can be integrated into a memory module. In other words, the memory system 220 can be implemented and packaged into different types of terminal electronic products.

[0223] The memory controller 2202 can send data to / receive data from the host, and can send commands (CMD) and addresses (ADDR) to the memory device 2201. The memory controller 2202 may include a command generator 10, an address generator 20, a device interface 30, and a host interface 40. The host interface 40 can receive commands (CMD) and addresses (ADDR) from the host. The command generator 10 can generate access commands, row hammer refresh commands, etc., by decoding the commands (CMD) received from the host, and can provide access commands and row hammer refresh commands to the memory device 2201 through the device interface 30. An access command may be a signal instructing the memory device 2201 to write or read data by accessing a row of the memory cell array 50 corresponding to the address ADDR. A row hammer refresh command may be a signal instructing the memory device 2201 to perform an additional refresh operation on word lines adjacent to word lines that are frequently accessed in a short period. In other words, an additional refresh operation can be performed on word lines adjacent to word lines that are accessed multiple times in a short period.

[0224] The address generator 120 in the memory controller 2202 can generate the row and column addresses to be accessed in the memory cell array 50 by decoding the address ADDR received from the host interface 140. Furthermore, the memory device 2201 can generate addresses of the memory banks to be accessed when the memory cell array 50 comprises multiple banks.

[0225] Furthermore, the memory controller 2202 can control memory operations such as writing and reading by providing various signals to the memory device 2201 via the device interface 30. For example, the memory controller 2202 can provide a write command to the memory device 2201. The write command is used to instruct the memory device 2201 to perform a write operation to store data in the memory device 2201.

[0226] In some embodiments, the memory device 2201 includes a memory cell array 50 and peripheral circuitry 60; wherein, the memory cell array 50 is as described above. Figure 3The array includes multiple banks, each bank comprising multiple blocks, each block comprising multiple rows and columns of memory cells. Each row of memory cells is coupled to a corresponding word line, and each column of memory cells is coupled to a corresponding bit line. Peripheral circuitry 60 can write data to or read data from memory cell array 50 based on commands CMD and addresses ADDR received from memory controller 2202. Alternatively, it can provide control signals CTRL to the row decoding and column decoding circuits for refreshing the memory cells included in memory cell array 50. In other words, peripheral circuitry 60 can perform all operations to process data in memory cell array 50. Peripheral circuitry 60 may include: control circuitry corresponding to each memory block, such as SA and WLD; control circuitry corresponding to each bank, such as row decoding circuitry and column decoding circuitry; and control circuitry corresponding to all banks, such as command buffers, command decoders, address buffers, data input / output buffers, and mode registers.

[0227] The memory device 2201 may be a random access memory (RAM), such as DRAM, synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc. The following description uses DRAM as an example only.

[0228] Figure 23 This is a schematic block diagram illustrating the composition of an exemplary SSD / UFS according to an embodiment of this application. Here, SSD / UFS can be understood as the aforementioned Figure 22 In this example, DRAM can be used as a buffer memory, representing one type of memory system.

[0229] like Figure 23As shown, the SSD / UFS 30' may include an SSD / UFS controller 10', a buffer memory 20', and a non-volatile memory 40. The SSD / UFS controller 10' provides the physical connection between the host and the SSD / UFS 30'. That is, the SSD / UFS controller 10' can provide an interface between the host and the SSD / UFS 30' according to the host's bus format. The SSD controller 10' can decode instructions provided by the host. The SSD / UFS controller 10' can access the non-volatile memory 40 based on the decoding result. The buffer memory 20' can temporarily store write data provided by the host or data read from the non-volatile memory 40. When the host issues a read request, if the data present in the non-volatile memory 40 is cached, the buffer memory 20' can support caching functionality for directly providing cached data to the host. The data transfer rate through the host's bus format (e.g., SATA or SAS) is much higher than the data transfer rate of the SSD / UFS 30's memory channel. That is, when the host interface speed is significantly higher, the performance degradation caused by the speed difference can be minimized by providing a high-capacity buffer memory 20'. Additionally, the buffer memory 20' can store the address mapping table of the non-volatile memory 40. The buffer memory 20' can be, but is not limited to, DRAM. The non-volatile memory 40 can be configured as an SSD / UFS 30' storage medium. The non-volatile memory 40 can be, but is not limited to, NAND flash memory.

[0230] Figure 24 This is a schematic block diagram illustrating the composition of an exemplary memory according to an embodiment of this application; here, memory can be understood as the aforementioned Figure 22 One type of memory system, in this example, uses DRAM as a storage medium. For example... Figure 24 As shown, memory 30'' can be easily attached to or installed in an electronic device or removed from electronic device 1 via the illustrated interface. Memory 30'' may include multiple volatile memories 20'' (e.g., DRAM) and a memory controller 10''. The memory module memory 30'' can be used to write data, store data, retrieve (or read) data, and / or erase data under the control of the computer's processor. In some embodiments, the memory controller 10'' can communicate with the DRAM using at least one communication protocol or technology standard typically associated with, for example, dual in-line memory modules (DIMMs), register-equipped DIMMs (RDIMMs), low-load DIMMs (LRDIMMs), and registerless DIMMs (UDIMMs). It should be noted that... Figure 23 Buffer memory 20' and Figure 24 All 20'' of the medium volatile memory Figure 22The memory device 2201 is described in one application scenario, but it can also be applied to other application scenarios, and there are no limitations on this. The memory controller is an exemplary structure of the memory controller described above.

[0231] This application also provides a computer system that may include the aforementioned memory system and an image processor, which is coupled to and controls the memory system. In some embodiments, the image processor and the memory system are integrated on the same printed circuit board (PCB).

[0232] One example, such as Figure 25 As shown, it illustrates a schematic diagram of the structure of a computer system provided in an embodiment of this application. Figure 25 As shown, the computer system includes a system-on-chip (SoC) and one or more memory devices; the memory devices include one or more DRAMs 2501, and the SoC includes a graphics processing unit (GPU) 2502, a DRAM controller 2503, and a DRAM physical layer 2504; wherein, the DRAM controller 2503 is responsible for scheduling read and write instructions and timing control of the DRAMs 2501; the DRAM physical layer 2504 is responsible for encoding the scheduled instructions according to the requirements of the DRAMs 2501, sending the corresponding write data to the DRAMs 2501, and receiving data read from the DRAMs 2501. Figure 25 As shown, the computer system includes an image processor (GPU) 2502 and a memory controller (i.e., DRAM controller 2503) integrated on the same die; this die and the memory device (one or more DRAMs 2501) are integrated on the same printed circuit board. It should be noted that this computer system belongs to the same inventive concept as the aforementioned memory device and operating method. This computer system includes the aforementioned memory device or memory system, and in different computer system architectures, the image processor and memory device are integrated on the same PCB, or the image processor and memory controller are integrated on the same PCB. Therefore, the terms used herein have been explained in detail above and are equally applicable here, and will not be repeated here. It should be understood that only the structure most relevant to the technical solution of this application is described here.

[0233] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application.

Claims

1. A memory device, characterized in that, include: Storage cell array; The storage cell array includes: multiple rows of storage cells and word lines coupled to each row of storage cells; and The peripheral circuitry, which is row-coupled to the corresponding memory cell via the word line, includes: a first power supply circuit and a second power supply circuit, wherein... The first power supply circuit is configured to: at a first moment, start outputting a first voltage to the substrate of the first transistor included in the first word line driving circuit coupled to the first unselected word line; The second power supply circuit is configured to: at a second moment, start outputting a second voltage to one end of the first transistor; The first moment is earlier than the second moment.

2. The memory device according to claim 1, characterized in that, Both the first voltage and the second voltage are negative voltages.

3. The memory device according to claim 1, characterized in that, The second voltage is provided to the source terminal of the first transistor.

4. The memory device according to claim 1, characterized in that, The plurality of memory cell rows include a plurality of memory cells; the memory cell includes a second transistor and a capacitor; wherein a first terminal of the second transistor is connected to one end of the capacitor, a second terminal of the second transistor is connected to its corresponding bit line, and a control terminal of the second transistor is connected to its corresponding word line; wherein the first power supply circuit is further configured to provide the first voltage to the substrate of the second transistor.

5. The memory device according to claim 1, characterized in that, The first power supply circuit is further configured to: respond to the first enable signal at the first moment, start outputting the first voltage, and after a first duration, the voltage value of the first voltage reaches a preset voltage value; After a second period of time, the voltage value of the first voltage reaches the first target voltage value.

6. The memory device according to claim 5, characterized in that, The second power supply circuit is further configured to: respond to the second enable signal at the second moment, start outputting the second voltage, and after a third duration, the voltage value of the second voltage reaches the second target voltage value.

7. The memory device according to claim 6, characterized in that, The second moment corresponds to the moment when the voltage value of the first voltage rises to the preset voltage value.

8. The memory device according to claim 5, characterized in that, The preset voltage value accounts for 50% to 90% of the first target voltage value.

9. The memory device according to claim 1, characterized in that, The peripheral circuit also includes: a third power supply circuit; wherein... The first power supply circuit is further configured to: at the first moment, start outputting the first voltage to the substrate of the third transistor included in the second word line driving circuit coupled to the second unselected word line; The third power supply circuit is configured to: at a third moment, start outputting a third voltage to one end of the third transistor; The first moment is earlier than the third moment.

10. The memory device according to claim 9, characterized in that, The third voltage is provided to the source terminal of the third transistor.

11. The memory device according to claim 9, characterized in that, The storage cell array includes multiple storage blocks; each storage block includes the multiple storage cell rows and word lines coupled to each storage cell row; wherein, the second unselected word line includes word lines belonging to the same storage block as the selected word line.

12. The memory device according to claim 11, characterized in that, The second unselected word line also includes at least a portion of the word lines contained in the memory block adjacent to the memory block where the selected word line is located.

13. The memory device according to claim 11 or 12, characterized in that, The first unselected character line includes all other unselected character lines except the second unselected character line.

14. The memory device according to claim 13, characterized in that, The third voltage is a negative voltage, and the absolute value of the third target voltage value of the third voltage is greater than the second target voltage value of the second voltage.

15. The memory device according to claim 1, characterized in that, The first power supply circuit includes: a first comparator and a voltage generator, wherein, The first comparator is configured to compare a reference voltage and a first feedback voltage, and output a first control signal based on the comparison result; the first feedback voltage is obtained based on the first voltage output by the voltage generator. The voltage generator is configured to output the first voltage according to the first control signal.

16. The memory device according to claim 15, characterized in that, The first power supply circuit further includes: a feedback generator configured to: receive the first voltage and output the first feedback voltage according to the first voltage; The reference generator is configured to output the reference voltage.

17. The memory device according to claim 16, characterized in that, The feedback generator includes: a fourth transistor and a plurality of first resistors connected in series, wherein, The first terminal of the fourth transistor is connected to the first voltage, and its second terminal is connected to the first terminal of the plurality of first resistors; the second terminals of the plurality of first resistors are connected to the first initial voltage. At a first moment, the control terminal of the fourth transistor is connected to a first enable signal, and the feedback generator outputs the first feedback voltage; the first feedback voltage is the voltage between two of the plurality of first resistors.

18. The memory device according to claim 17, characterized in that, The feedback generator further includes a fifth transistor and a sixth transistor, wherein, The first terminal of the fifth transistor is connected to the first sub-voltage value included in the first initial voltage, and the second terminal is connected to the second terminal of the plurality of first resistors; The first terminal of the sixth transistor is connected to the second sub-voltage value included in the first initial voltage, and the second terminal is connected to the second terminal of the plurality of first resistors; Specifically, when a second control signal is connected to the control terminal of the fifth transistor, the first power supply circuit operates in a first mode; when a third control signal is connected to the control terminal of the sixth transistor, the first power supply circuit operates in a second mode.

19. The memory device according to claim 17 or 18, characterized in that, The reference generator includes: a plurality of second resistors connected in series; wherein, The first end of the plurality of second resistors is connected to the first initial voltage; the other end of the plurality of second resistors is grounded, wherein the reference voltage is the voltage between two of the plurality of second resistors.

20. The memory device according to claim 15, characterized in that, The voltage generator includes: a clock drive sub-circuit and a negative charge pump sub-circuit, wherein; The clock driving sub-circuit is configured to: receive the first control signal and generate a fourth control signal based on the first control signal; The negative charge pump sub-circuit is coupled to the clock drive sub-circuit and is configured to receive the fourth control signal and output the first voltage according to the fourth control signal.

21. The memory device according to claim 20, characterized in that, The negative charge pump circuit includes at least two negative charge pumps, wherein two adjacent negative charge pumps are connected in series or in parallel.

22. The memory device according to claim 21, characterized in that, The first power supply circuit further includes a voltage regulator configured to receive an adjustment control signal and, in response to the adjustment control signal, adjust the first voltage to a set target voltage value.

23. The memory device according to claim 22, characterized in that, The adjustment control signal includes at least one sub-control signal; The set target voltage value includes at least one sub-target voltage value; the voltage regulator includes: at least one set of P-type transistors and N-type transistors; in each set, the first terminal of the P-type transistor is connected to a second initial voltage, and its second terminal is connected to the first terminal of the N-type transistor; the second terminal of the N-type transistor is connected to the first voltage; In each group, the control terminal of the P-type transistor is connected to a third enable signal and the control terminal of the N-type transistor is connected to a corresponding sub-control signal, so as to adjust the first voltage to the corresponding sub-target voltage value of the group.

24. The memory device according to claim 23, characterized in that, The first power supply circuit further includes: at least one second comparator; each second comparator is configured to: compare a reference voltage with a corresponding second feedback voltage and output a corresponding sub-control signal; the second feedback voltage is the voltage between two of the series-connected first resistors and is different from the first feedback voltage.

25. The memory device according to claim 17, characterized in that, The peripheral circuit is further configured as follows: a third comparator is configured to compare a reference voltage and a third feedback voltage, and output a second enable signal according to the comparison result, and output the second enable signal to the second power supply circuit; wherein, the third feedback voltage is obtained when the voltage value of the first voltage reaches a preset voltage value.

26. The memory device according to claim 6, characterized in that, The absolute value of the first target voltage of the first voltage is greater than the absolute value of the second target voltage of the second voltage.

27. The memory device according to claim 1, characterized in that, The peripheral circuit also includes a fourth power supply circuit, configured to generate a bit line voltage that reaches a fourth target voltage value before the first moment, and to provide the bit line voltage to the corresponding bit line.

28. A method for supplying power to a memory device, characterized in that, include: At the first moment, a first voltage is generated and provided to the substrate of the first transistor contained in the first word line driving circuit coupled to the first unselected word line; At the second moment, a second voltage is generated and supplied to one end of the first transistor; The first moment is earlier than the second moment.

29. The method according to claim 28, characterized in that, The second voltage is provided to the source terminal of the first transistor.

30. The method according to claim 28, characterized in that, The method further includes: In response to the first enable signal at the first moment, the first voltage is generated, and after a first duration, the voltage value of the first voltage reaches a preset voltage value; after a second duration, the voltage value of the first voltage reaches a first target voltage value. The preset voltage value accounts for 50% to 90% of the first target voltage value.

31. The method according to claim 30, characterized in that, The method further includes: In response to the second enable signal at the second moment, the second voltage is generated, and after a third duration, the voltage value of the second voltage reaches the second target voltage value. The second moment corresponds to the moment when the voltage value of the first voltage rises to the preset voltage value.

32. The method according to claim 28, characterized in that, The method further includes: The first voltage is provided to the substrate of the second transistor contained in the memory cell of the memory device.

33. The method according to claim 31, characterized in that, The first voltage and the second voltage are negative voltages, and the absolute value of the first target voltage of the first voltage is greater than the absolute value of the second target voltage of the second voltage.

34. The method according to claim 28, characterized in that, The method further includes: At the first moment, the first voltage is provided to the substrate of the third transistor included in the second word line driving circuit coupled to the second unselected word line; At the third moment, a third voltage is generated and supplied to the source terminal of the third transistor; the first moment is earlier than the third moment. Wherein, the third voltage is a negative voltage, and the absolute value of the third target voltage value of the third voltage is greater than the second target voltage value of the second voltage.

35. The method according to claim 34, characterized in that, The memory device includes a plurality of memory blocks; each memory block includes a plurality of memory cell rows and word lines coupled to each memory cell row; wherein the second unselected word line includes word lines belonging to the same memory block as the selected word line.

36. The method according to claim 35, characterized in that, The second unselected word line also includes at least a portion of the word lines contained in the memory block adjacent to the memory block where the selected word line is located.

37. The method according to claim 35 or 36, characterized in that, The first unselected character line includes all other unselected character lines except the second unselected character line.

38. The method according to claim 28, characterized in that, The generation of the first voltage includes: A reference voltage and a first feedback voltage are compared, and a first control signal is generated based on the comparison result; and a first voltage is generated based on the first control signal; the first feedback voltage is a feedback voltage obtained based on the first voltage.

39. The method according to claim 38, characterized in that, The method further includes: Receives an adjustment control signal; and in response to the adjustment control signal, adjusts the first voltage to a set target voltage value; The adjustment control signal is obtained based on a comparison between a reference voltage and a second feedback voltage; the second feedback voltage is obtained based on the first voltage and is different from the first feedback voltage.

40. The method according to claim 31, characterized in that, The method further includes: The reference voltage and the third feedback voltage are compared, and the second enable signal is output according to the comparison result; wherein the third feedback voltage is obtained when the voltage value of the first voltage reaches the preset voltage value.

41. The method according to claim 28, characterized in that, The method further includes: Before the first moment, a bit line voltage that reaches the fourth target voltage value is generated to provide the bit line voltage to the corresponding bit line.

42. A charge pump circuit for a memory device, characterized in that, include: The circuit consists of a feedback generator, a reference generator, a first comparator, and a voltage generator. The feedback generator is connected between the first node and the output of the voltage generator, and it has an input terminal that receives the first enable signal, and one of its output terminals is connected to the first input terminal of the first comparator. The reference generator is connected between the first node and ground, and its output is connected to the second input of the first comparator. The output of the first comparator is connected to the input of the voltage generator; The voltage generator outputs a negative voltage.

43. The charge pump circuit according to claim 42, characterized in that, The feedback generator includes a fourth transistor and multiple first resistors connected in series, wherein, The first terminal of the fourth transistor is connected to the output terminal of the voltage generator, and the second terminal is connected to the first terminal of the series-connected plurality of first resistors; the second transistor also has a control terminal that receives the first enable signal; The second terminals of the series-connected plurality of first resistors are connected to the first node; The output terminal of the series of multiple first resistors, including two of the first resistors, is connected to the first input terminal of the first comparator.

44. The charge pump circuit according to claim 43, characterized in that, The feedback generator further includes a fifth transistor and a sixth transistor, wherein, The first terminal of the fifth transistor is connected to the first node, and its second terminal is connected to the second terminal of the series-connected plurality of first resistors; the fifth transistor also has a control terminal for receiving a second control signal; The first terminal of the sixth transistor is connected to the second node, and the second terminal is connected to the second terminal of the series-connected plurality of first resistors; the sixth transistor also has a control terminal for receiving a third control signal.

45. The charge pump circuit according to claim 44, characterized in that, The reference generator includes: a plurality of second resistors connected in series; wherein, The first terminals of the plurality of second resistors are connected to the second terminals of the fifth transistor and the sixth transistor; the second terminals of the plurality of second resistors are grounded. The output terminal between two of the plurality of second resistors is connected to the second input terminal of the first comparator.

46. ​​The charge pump circuit according to claim 42, characterized in that, Also includes: Voltage regulator; the voltage regulator includes: at least one set of P-type transistors and N-type transistors; In each group, the first terminal of the P-type transistor is connected to the third node, and its second terminal is connected to the first terminal of the N-type transistor; the P-type transistor also has a control terminal that receives a third enable signal. The second terminal of the N-type transistor is connected to the output terminal of the voltage generator; the N-type transistor also has a control terminal that receives the corresponding sub-control signal.

47. The charge pump circuit according to claim 46, characterized in that, Also includes: At least one second comparator; the first input of each second comparator is connected to an output of the feedback generator, and the second input is connected to the output of the reference generator; The output of each of the second comparators is connected to the control terminal of the corresponding group of N-type transistors.

48. The charge pump circuit according to claim 42, characterized in that, Also includes: A third comparator has its first input connected to the first output of the feedback generator; its second input connected to the output of the reference generator; and its output is connected to a second enable signal. The voltage value output by the first output is a preset voltage value. The second enable signal is used to enable other charge pump circuits.

49. The charge pump circuit according to claim 42, characterized in that, The voltage generator includes: a clock drive sub-circuit and a negative charge pump sub-circuit, wherein; The input terminal of the clock driving sub-circuit is connected to the output terminal of the first comparator; the output terminal of the clock driving sub-circuit is coupled to the input terminal of the negative charge pump sub-circuit. The negative voltage is output at the output terminal of the negative charge pump circuit.

50. The charge pump circuit according to claim 48, characterized in that, The negative charge pump circuit includes at least two negative charge pumps, wherein two adjacent negative charge pumps are connected in series or in parallel.

51. A memory system, characterized in that, include: At least one memory device according to any one of claims 1 to 27; as well as A memory controller that is coupled to and controls the memory device.

52. A computer system, characterized in that, include: The memory system of claim 51; And an image processor, which is coupled to and controls the memory system.

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