Semiconductor circuit structure with heat dissipation composite shallow trench isolation region and manufacturing method thereof
By using high thermal conductivity materials to fill shallow trenches in semiconductor circuits to form composite shallow trench isolation regions, the heat dissipation problem caused by transistor integration is solved, achieving a more efficient heat dissipation effect and supporting higher density transistor integration and chip performance improvement.
Patent Information
- Application Number
- CN202510538532.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-06-20
- Filing Date
- 2025-04-27
- Publication Date
- 2025-10-28
AI Technical Summary
Existing technologies struggle to effectively address the heat dissipation issues caused by high-density transistor integration, especially in semiconductor chips, leading to increased transistor junction temperatures and impacting chip performance and reliability.
The shallow trenches are filled with high thermal conductivity materials to form a composite shallow trench isolation zone, replacing traditional low thermal conductivity materials such as silicon dioxide. The thermal conductivity is improved by laser or thermal annealing treatment, and planarization is achieved by chemical mechanical polishing.
It significantly reduces transistor junction temperature, improves chip heat dissipation, supports higher density transistor integration, reduces power consumption, and improves chip performance and reliability.
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Figure CN120854375A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor circuit structure and its manufacturing method, and more particularly to a transistor structure surrounded by a composite shallow trench isolation region of a semiconductor material with heat dissipation properties and its manufacturing method. Background Technology
[0002] The technology of integrating silicon components onto a single integrated circuit (IC) chip achieved the integration of over 50 billion transistors on a single die in 2021, officially transitioning from the era of Very Large Scale Integration (VLSI, which integrates millions of transistors on a single die) to the era of Gigabyte-Scale Integration (GSI, which integrates billions of transistors on a single die). This achievement of higher transistor integration on a single die has significantly improved the PPAC (Power, Power, and Area) capabilities of microsystems, resulting in the creation of many powerful chips such as CPUs, GPUs, FPGAs, SoCs, SRAMs, and DRAMs. This enhances system capabilities, continuously supports Moore's Law, and forms the basis for exponential economic growth.
[0003] Moreover, the single-chip integration capability of silicon chips will soon evolve from gigascale integrated circuits (GSI: billions of transistors integrated on a single die) to trillion-scale integrated circuits (TSI: trillions of transistors integrated on a single die), and the performance of chips will be significantly improved.
[0004] However, operating such a massive number of transistors would drastically increase power consumption, adversely affecting transistor junction temperatures. This, coupled with the chip's limited heat dissipation capacity (e.g., the low thermal conductivity of silicon dioxide (SiO2), would further raise the overall chip temperature. This material and component structure problem leads to a negative cycle: increased chip temperature reduces transistor speed, inevitably requiring a forced increase in circuit power to accelerate transistor performance, which in turn causes a significant rise in chip temperature, exacerbating the heat dissipation problem.
[0005] In fact, this problem of insufficient heat dissipation leading to excessively high chip operating temperatures is considered one of the most serious issues in the entire chip industry and must be addressed to avoid becoming a major obstacle to integrating more components onto the chip. However, technologies to reduce GSI chip temperatures have not yet made smooth progress. Furthermore, with the further miniaturization of semiconductor technology nodes (e.g., the minimum feature size shrinking from 7 nanometers (nm) to 5 nanometers, then to 3 nanometers, and so on), transistor sizes must become smaller, and the percentage of oxide coverage in the total transistor size is increasing, while the heat dissipation capacity between component junctions has not been further enhanced. Although many heat dissipation solutions have been proposed in the industry, such as covering the entire chip with thermal pads with higher thermal coefficients or using liquid cooling circulation outside the chip, these solutions are very costly and still too inefficient to effectively reduce transistor junction temperatures. Summary of the Invention
[0006] One object of the present invention is to provide a method for manufacturing a semiconductor circuit structure. This method includes the following steps: first, providing a semiconductor substrate; forming shallow trenches extending from the original surface of the semiconductor substrate into the interior of the semiconductor substrate to surround an active region; forming dielectric layers on the sidewalls and bottom of the shallow trenches; and filling the shallow trenches with a thermally conductive semiconductor material, wherein the thermally conductive semiconductor material is isolated from the semiconductor substrate by the dielectric layers.
[0007] According to one embodiment of the present invention, the step of filling a shallow trench with a thermally conductive semiconductor material includes: first filling the shallow trench with an amorphous semiconductor material; and performing a laser annealing or thermal annealing process on the amorphous semiconductor material to form a thermally conductive semiconductor material.
[0008] According to one embodiment of the present invention, the thermally conductive semiconductor material comprises silicon with an average die thickness between 0.1 micrometers (µm) and 2 micrometers.
[0009] According to one embodiment of the present invention, before performing laser annealing or thermal annealing processes on the amorphous semiconductor material, the process further includes: curing the amorphous semiconductor material using ultraviolet light.
[0010] According to one embodiment of the present invention, a first capping layer is applied over the active region after the shallow trench is filled with an amorphous thermally conductive semiconductor material, which then covers the first capping layer.
[0011] According to one embodiment of the present invention, after filling the shallow trench with an amorphous thermally conductive semiconductor material, the top surface of the amorphous semiconductor material is substantially between 800 nanometers and 2000 nanometers higher than the top surface of the first capping layer.
[0012] According to one embodiment of the present invention, after performing laser annealing or thermal annealing on the crystalline semiconductor material, a planarization process is further included on the thermally conductive semiconductor material.
[0013] According to one embodiment of the present invention, after a planarization process, the top surface of the thermally conductive semiconductor material is substantially flush with the top surface of the first cover.
[0014] According to one embodiment of the present invention, after the planarization process, the process further includes etching the thermally conductive semiconductor material downwards so that the etched top surface of the thermally conductive semiconductor material is substantially lower than the original surface of the semiconductor substrate.
[0015] According to one embodiment of the present invention, after the thermally conductive semiconductor material is etched downwards, the etched top surface of the thermally conductive semiconductor material is substantially between 5 nanometers and 30 nanometers below the original surface of the semiconductor substrate.
[0016] According to one embodiment of the invention, after etching the thermally conductive semiconductor material downwards, a second capping layer is further deposited to cover the etched top surface of the thermally conductive semiconductor material.
[0017] According to one embodiment of the present invention, the thermally conductive semiconductor material includes silicon; and in the thermally conductive semiconductor material, the number of silicon dies along a depth direction of the thermally conductive semiconductor material is at most three. Attached Figure Description
[0018] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:
[0019] Figure 1A This is a top view of a process structure after a shallow trench isolation structure is formed in a semiconductor substrate to define at least one active region, according to an embodiment of the present invention.
[0020] Figure 1B , Figure 1C , Figure 1D , Figure 1E They are along Figure 1A The structural cross-section diagram is shown by tangents CA1, CA2, CA3, and CA4. Figure 1F It is based on Figure 1A A cross-sectional view of the manufacturing process structure of the peripheral circuit area of the dynamic random access memory circuit structure is shown.
[0021] Figure 2A This is a top view showing the process structure after the recessed gate pattern has been defined;
[0022] Figure 2B , Figure 2C , Figure 2D , Figure 2E The figures are respectively along Figure 2A The structural cross-section shown by tangents CB1, CB2, CB3, and CB4 in the diagram; Figure 2F It is based on Figure 2A A cross-sectional view of the manufacturing process structure of the peripheral circuit area of the dynamic random access memory circuit structure is shown.
[0023] Figure 3A This is a top view showing the process structure after the recessed gate pattern is transferred to the remaining silicon nitride layer;
[0024] Figure 3B , Figure 3C , Figure 3D , Figure 3E They are along Figure 3A The structural cross-section shown by tangents CC1, CC2, CC3, and CC4 in the diagram; Figure 3F It is based on Figure 3A A cross-sectional view of the manufacturing process structure of the peripheral circuit area of the dynamic random access memory circuit structure is shown.
[0025] Figure 4A This is a top view showing the process structure after at least one hollowed-out groove has been formed;
[0026] Figure 4B , Figure 4C , Figure 4D , Figure 4E They are along Figure 4A The structural cross-section shown by tangents CD1, CD2, CD3, and CD4 is shown in the figure. Figure 4F It is based on Figure 4A A cross-sectional view of the manufacturing process structure of the peripheral circuit area of the dynamic random access memory circuit structure is shown.
[0027] Figure 5A It is a top view showing the process structure after at least one heat-conducting area is formed in at least one hollowed-out groove;
[0028] Figure 5B , Figure 5C , Figure 5D , Figure 5E They are along Figure 5A The structural cross-section shown by tangents CE1, CE2, CE3, and CE4 in the diagram; Figure 5F It is based on Figure 5A A cross-sectional view of the manufacturing process structure of the peripheral circuit area of the dynamic random access memory circuit structure is shown.
[0029] Figure 6A This is a top view showing the fabrication structure after the formation of a silicon oxide hard mask layer and another amorphous carbon (aC) layer;
[0030] Figure 6B , Figure 6C , Figure 6D , Figure 6E They are along Figure 6A The structural cross-section shown by tangents CF1, CF2, CF3, and CF4 in the diagram; Figure 6F It is based on Figure 6A A cross-sectional view of the manufacturing process structure of the peripheral circuit area of the dynamic random access memory circuit structure is shown.
[0031] Figure 7A This is a top view showing the process structure after multiple gate recesses and multiple character line trenches have been formed;
[0032] Figure 7B , Figure 7C , Figure 7D , Figure 7E They are along Figure 7A The structural cross-section shown by tangents CG1, CG2, CG3, and CG4 in the diagram; Figure 7F It is based on Figure 7A A cross-sectional view of the manufacturing process structure of the peripheral circuit area of the dynamic random access memory circuit structure is shown.
[0033] Figure 8A This is a top view showing the fabrication structure after the semiconductor circuit structure has been fabricated;
[0034] Figure 8B , Figure 8C , Figure 8D , Figure 8E They are along Figure 8A The structural cross-section shown by the tangents CH1, CH2, CH3, and CH4 in the diagram; Figure 8F It is based on Figure 8A This is a cross-sectional view of the manufacturing process structure of the peripheral circuit area of a semiconductor circuit structure (dynamic random access memory circuit structure).
[0035] Figure label:
[0036] 100: Semiconductor circuit structure
[0037] 101: Semiconductor substrate
[0038] 101A: Active Area
[0039] 101S: Original Surface
[0040] 101P: Peripheral Circuits Area
[0041] 102: Composite isolation structure
[0042] 103: Shallow trench isolation structure
[0043] 103T: Shallow Ditch
[0044] 104: Hollowed-out groove
[0045] 104B: Bottom
[0046] 104S: Sidewall
[0047] 105: Dielectric layer
[0048] 106: High thermal conductivity zone
[0049] 107: Transistor
[0050] 107E: Gate electrode
[0051] 107S: Source Region
[0052] 107D: Drain region
[0053] 107L: Gate dielectric layer
[0054] 107F: Barrier / Work Function Layer
[0055] 108: Gate recess
[0056] 109: Pad Dielectric Layer
[0057] 110: Rigid Screen Layer
[0058] 110a: First silicon oxide layer
[0059] 110b: Amorphous carbon layer
[0060] 110c: Silicon nitride layer
[0061] 110d: Second silicon oxide layer
[0062] 110O: Concave Chamber
[0063] 111: Bottom anti-reflective layer
[0064] 112: Molecular layer deposition layer
[0065] 113: Bottom anti-reflective layer
[0066] 114: Recessed gate pattern
[0067] 115: Silicon nitride layer
[0068] 116: Silicon oxide hard mask layer
[0069] 118T: Character line groove
[0070] 118: Metallic Materials
[0071] 119: Protective layer
[0072] CA1, CA2, CA3, CA4: Tangents
[0073] CB1, CB2, CB3, CB4: Tangents
[0074] CC1, CC2, CC3, CC4: Tangents
[0075] CD1, CD2, CD3, CD4: Tangents
[0076] CE1, CE2, CE3, CE4: Tangent
[0077] CF1, CF2, CF3, CF4: Tangents
[0078] CG1, CG2, CG3, CG4: Tangents
[0079] CH1, CH2, CH3, CH4: Tangents
[0080] P1: Part 1
[0081] P2: Part Two
[0082] G: Gap
[0083] W: Character line Detailed Implementation
[0084] This invention provides a semiconductor circuit structure and its fabrication method, which can effectively reduce the junction temperature of transistors. To make the above embodiments and other objects, features, and advantages of this invention more apparent and understandable, several preferred embodiments are described below in detail with reference to the accompanying drawings.
[0085] However, it must be noted that these specific implementation examples and methods are not intended to limit the present invention. The present invention can still be implemented using other features, components, methods, and parameters. The proposed preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the patent application. Those skilled in the art will be able to make equivalent modifications and variations based on the following description of the invention without departing from the spirit and scope of the invention. In different embodiments and drawings, the same components will be represented by the same component symbols.
[0086] Example 1
[0087] This embodiment discloses a semiconductor circuit structure 100 with high heat dissipation capability. Taking a dynamic random access memory circuit structure including a memory cell circuit area and a peripheral circuit area as an example, the steps and methods for manufacturing the semiconductor circuit structure 100 are detailed below:
[0088] Step S11: Provide a semiconductor substrate 101;
[0089] Step S12: A composite isolation structure 102 is formed in the semiconductor substrate 101 to define at least one active region 101A within the semiconductor substrate 101; wherein the composite isolation structure 102 includes a high thermal conductivity region 106, the thermal conductivity of which is higher than that of silicon oxide; wherein step S12 of forming the composite isolation structure 102 includes sub-steps S121-S124:
[0090] Sub-step S121: Form a shallow trench isolation region with a shallow trench isolation structure 103; wherein the shallow trench isolation structure 103 extends from the original surface 101S of the semiconductor substrate 101 into the semiconductor substrate 101 and defines at least one active region 101A.
[0091] Sub-step S122: Remove all or part of the shallow trench isolation structure 103 to define at least one hollow trench 104;
[0092] Sub-step S123: Forming a dielectric layer 105 on the bottom 104B and sidewall 104S of at least one hollowed-out trench 104; and
[0093] Sub-step S124: Fill at least one hollow trench 104 with a high thermal conductivity material to form a high thermal conductivity region 106, and isolate the high thermal conductivity region 106 from the semiconductor substrate 101 by means of a dielectric layer 105;
[0094] Step S13: Form at least one transistor 107 using at least one active region 101A as a substrate. Step S13, forming the transistor 107, includes sub-steps S131-S134:
[0095] Sub-step S131: Form at least one gate recess 108 extending from the original surface 101S into at least one active region 101A of the semiconductor substrate 101;
[0096] Sub-step S132: Form a gate dielectric layer 107L covering the bottom and sidewalls of at least one gate recess 108;
[0097] Sub-step S133: Forming at least one gate electrode 107E in at least one gate recess 108; and
[0098] Sub-step S134: Form at least one source region 107S and a drain region 107D in at least one active region 101A, and adjacent to at least one gate electrode 107E.
[0099] Please refer to step S11: A semiconductor substrate 101 is provided. In some embodiments of the present invention, the semiconductor substrate 101 may be a silicon-containing substrate, such as a silicon wafer or a silicon-on-insulator (SOI) substrate. In some other embodiments of the present invention, the semiconductor substrate 101 may be made of other types of semiconductor materials such as silicon carbide (SiC), germanium (Ge), or compound semiconductor materials such as gallium arsenide (GaAs). In this embodiment, the semiconductor substrate 101 may be a silicon wafer.
[0100] Please refer to step S12: A composite isolation structure 102 is formed in the semiconductor substrate 101 to define at least one active region 101A within the semiconductor substrate 101; wherein, the composite isolation structure 102 includes a high thermal conductivity region 106, whose thermal conductivity is higher than that of silicon oxide; wherein, step S12 of forming the composite isolation structure 102 includes sub-steps S121-S124:
[0101] Please refer to sub-step S121: Form a shallow trench isolation region with a shallow trench isolation structure 103; wherein, the shallow trench isolation structure 103 extends from the original surface 101S of the semiconductor substrate 101 into the semiconductor substrate 101, and defines at least one active region 101A. Taking a dynamic random access memory circuit structure including a memory cell circuit region and a peripheral circuit region 101P as an example, Figure 1A This is a top view of the process structure after a shallow trench isolation structure 103 is formed extending into the interior of a semiconductor substrate 101 to define at least one active region 101A, according to an embodiment of the present invention. Figure 1B , Figure 1C , Figure 1D , Figure 1E They are along Figure 1A The structural cross-section diagram is shown by tangents CA1, CA2, CA3, and CA4. Figure 1F It is based on Figure 1A A cross-sectional view of the process structure of the peripheral circuit region 101P of the dynamic random access memory circuit is shown.
[0102] The formation of the shallow trench isolation structure 103 includes the following steps: First, an etching process is performed using a patterned pad dielectric layer 109 (including a patterned pad silicon oxide layer and a patterned pad silicon nitride layer (not shown)) as an etch mask to remove a portion of the silicon material of the semiconductor substrate 101, thereby forming a plurality of shallow trenches 103T. Then, dielectric material is filled into the shallow trenches 103T to define a plurality of fin structures in the semiconductor substrate 101. In some embodiments of the present invention, silicon oxide is filled into the shallow trenches 103T, and the remaining semiconductor structure of each dielectric material can serve as an active region 101A.
[0103] Next, refer to sub-step S122: remove a portion of the shallow trench isolation structure 103 to define at least one hollowed-out groove 104. The formation of the hollowed-out groove 104 includes the following steps:
[0104] First, a hard mask layer 110 is deposited on the pad dielectric layer 109. The hard mask layer 110 includes a first silicon oxide layer 110a, an amorphous carbon layer 110b, a silicon nitride layer 110c, and a second silicon oxide layer 110d. A bottom anti-reflective coating (BARC) 111 (as shown in Figure 1) is formed on the hard mask layer 110. A molecular layer deposition (MLD) layer 112 is formed on the bottom anti-reflective coating (BARC) layer (as shown in Figure 1), and after planarization, a bottom anti-reflective coating 113 (as shown in Figure 2) is formed on the MLD layer 112 (surrounded by another MLD layer of the same material as the MLD layer 112). Then, a recessed gate pattern 114 is defined using self-aligned double patterning (SADP) technology (or a character line pattern is defined in the semiconductor substrate 101 of the memory cell circuit area of the dynamic random access memory circuit structure).
[0105] like Figures 2A to 2F As shown, Figure 2A This is a top view showing the process structure after the recessed gate pattern 114 has been defined. Figure 2B , Figure 2C , Figure 2D , Figure 2E The figures are respectively along Figure 2A The structural cross-sections shown are tangents CB1, CB2, CB3, and CB4. Figure 2F It is based on Figure 2A A cross-sectional view of the process structure of the peripheral circuit region 101P of the dynamic random access memory circuit is shown.
[0106] Then, using the recessed gate pattern 114 as an etching mask, at least one etching process is performed to remove a portion of the hard mask layer 110, forming multiple recesses 110O, exposing a portion of the pad dielectric layer 109 and the shallow trench isolation structure 103. A silicon nitride layer 115 (also known as a first capping layer) is then formed to fill the multiple recesses 110O. After etching back the silicon nitride layer 115, the recessed gate pattern 114 can be transferred onto the remaining silicon nitride layer 115. Simultaneously, a portion of the hard mask layer 110 above the semiconductor substrate 101 of the peripheral circuit region 101P of the dynamic random access memory circuit structure is protected and no recesses 110O are formed. Furthermore, the above process can be included in the standard process for fabricating dynamic random access memory circuit structures.
[0107] like Figures 3A to 3F As shown, Figure 3A This is a top view showing the process structure after the recessed gate pattern is transferred to the remaining silicon nitride layer. Figure 3B , Figure 3C , Figure 3D , Figure 3E They are along Figure 3A The structural cross-section shown by tangents CC1, CC2, CC3, and CC4 is shown in the figure. Figure 3F It is based on Figure 3A This is a cross-sectional view of the manufacturing process structure of the peripheral circuit area of the dynamic random access memory circuit.
[0108] After stripping the remaining portion of the hard mask layer 110 and a portion of the pad dielectric layer 109 covered by the remaining portion of the hard mask layer 110, the remaining portion of the silicon nitride layer 115 is used as an etching mask for etching to remove a portion of the shallow trench isolation structure 103, forming at least one hollow trench 104 (also called a shallow trench) within the shallow trench isolation structure 103, while retaining a portion of the shallow trench isolation structure 103 covered by the remaining portion of the silicon nitride layer 115 (i.e., the recessed gate pattern 114 transferred to the silicon nitride layer 115) (such as...). Figure 4C and Figure 4E As shown). Although as Figure 4B As shown, the hollowed-out groove 104 completely lacks any remaining shallow trench isolation structure 103, but other embodiments of the present invention are not limited thereto. In another embodiment, a portion of the shallow trench isolation structure 103 may be retained in the hollowed-out groove 104 (as shown). In some embodiments of the present invention, each active region 101A is surrounded by the hollowed-out groove 104.
[0109] like Figures 4A to 4F As shown, Figure 4A This is a top view showing the process structure after at least one hollowed-out groove 104 has been formed. Figure 4B , Figure 4C, Figure 4D , Figure 4E They are along Figure 4A The structural cross-section shown by tangents CD1, CD2, CD3, and CD4 is shown in the figure. Figure 4F It is based on Figure 4A A cross-sectional view of the process structure of the peripheral circuit region 101P of the dynamic random access memory circuit is shown.
[0110] Please refer to sub-step S123: A dielectric layer 105 is formed on the bottom 104B and sidewalls 104S of at least one hollow trench 104. In some embodiments of the present invention, the dielectric layer 105 covering the active region 101A and the sidewalls 104S and bottom 104B of at least one hollow trench 104 can be formed by a dielectric material deposition process. In this embodiment, the dielectric layer 105 is a silicon oxide thin film (with a thickness of approximately 2 to 3 nanometers) formed by a thermal oxidation process on the portion of the semiconductor substrate 101 exposed through at least one hollow trench 104.
[0111] Please refer to sub-step S124: Fill at least one hollow trench 104 with a high thermal conductivity material to form at least one high thermal conductivity region 106, and isolate the high thermal conductivity region 106 from the semiconductor substrate 101 by a dielectric layer 105. The at least one high thermal conductivity region 106, the dielectric layer 105, and the remaining portion (if any) of the shallow trench isolation structure 103 can be combined to form a composite isolation structure 102 (or a composite shallow trench isolation region) surrounding each active region 101A.
[0112] like Figures 5A to 5F As shown, Figure 5A This is a top view showing the process structure after at least one high thermal conductivity region 106 is formed in at least one hollowed-out groove 104. Figure 5B , Figure 5C , Figure 5D , Figure 5E They are along Figure 5A The structural cross-section shown by tangents CE1, CE2, CE3, and CE4 is shown in the figure. Figure 5F It is based on Figure 5A A cross-sectional view of the process structure of the peripheral circuit region 101P of the dynamic random access memory circuit is shown.
[0113] In embodiments of the present invention, the high thermal conductivity region 106 can be formed by directly depositing a material with a thermal conductivity greater than that of silicon oxide to fill the hollow trench 104. The high thermal conductivity region 106 can be made of silicon, silicon carbide, boron nitride, aluminum nitride, or any combination thereof.
[0114] For example, to form polycrystalline silicon, undoped amorphous silicon can be deposited at low temperatures, and then laser recrystallization can be performed on the undoped amorphous silicon to obtain undoped crystalline silicon or undoped polycrystalline silicon for large dies. Subsequently, chemical mechanical polishing (CMP) can be performed on the undoped crystalline silicon or undoped polycrystalline silicon of the multiple large dies to achieve the required flatness.
[0115] In this embodiment, to address the gap filling problem, the formation of the high thermal conductivity region 106 may include the following steps: First, amorphous silicon is deposited on a semiconductor substrate 101 to cover the dielectric layer 105 and fill at least one hollow trench 104. In some embodiments of the present invention, after the amorphous silicon fills at least one hollow trench 104, the top surface of the amorphous silicon will be approximately 800 nanometers to 2000 nanometers higher than the top surface of the dielectric layer 105.
[0116] Next, the multiple amorphous silicon wafers are subjected to a UV curing process to form seamlessly gap-filled amorphous silicon. Then, laser annealing or rapid thermal annealing is performed to recrystallize the amorphous silicon filling at least one hollow trench 104 to form crystalline silicon or polycrystalline silicon, thereby improving the thermal conductivity of the high thermal conductivity region 106. The average die size of the high thermal conductivity region 106 can be between 0.5 micrometers and 2 micrometers. Subsequently, the multiple large-die undoped crystalline silicon wafers can be subjected to a chemical mechanical polishing process to achieve the required flatness. After the chemical mechanical polishing process, the top surface of the high thermal conductivity region 106 (high thermal conductivity material) is flush with the top surface of the dielectric layer 105.
[0117] Please refer to step S13: At least one transistor 107 is formed using at least one active region 101A as a substrate. Step S13, forming the transistor 107, includes sub-steps S131-S134:
[0118] Please refer to sub-step S131: forming at least one gate recess 108 extending from the original surface 101S into at least one active region 101A of the semiconductor substrate 101. The formation of at least one gate recess 108 includes the following steps:
[0119] First, the high thermal conductivity region 106 is etched back to expose the active region 101A of the semiconductor substrate 101. The height (top surface 106S) of the etched high thermal conductivity region 106 is positioned approximately below the surface of the silicon semiconductor substrate 101 (e.g., approximately 5 to 30 nanometers, or for example, 10 nanometers, below the original surface 101S of the semiconductor substrate 101) to prevent leakage. In other words, the top surface 106S of the high thermal conductivity region 106 (high thermal conductivity semiconductor material) is lower than the original surface 101S of the semiconductor substrate 101.
[0120] Next, a silicon oxide hard mask layer 116 (also known as a second capping layer) and another amorphous carbon layer 117 are formed sequentially to cover the high thermal conductivity region 106 and the exposed portion of the active region 101A of the semiconductor substrate 101. Then, the amorphous carbon layer 117 is planarized (e.g., by chemical mechanical polishing) using the remaining portion of the silicon nitride layer 115 as a stop layer.
[0121] like Figures 6A to 6F As shown, Figure 6A This is a top view showing the process structure after the formation of the silicon oxide hard mask layer 116 and another amorphous carbon layer 117. Figure 6B , Figure 6C , Figure 6D , Figure 6E They are along Figure 6A The structural cross-section shown by tangents CF1, CF2, CF3, and CF4 is shown in the figure. Figure 6F It is based on Figure 6A A cross-sectional view of the process structure of the peripheral circuit region 101P of the dynamic random access memory circuit is shown.
[0122] A combination of a silicon oxide hard mask layer 116 and an amorphous carbon layer 117 is used as an etching mask to perform at least one etching process to remove the remaining nitride layer 115, the patterned pad dielectric layer 109, a portion of the semiconductor substrate 101, and a portion of the shallow trench isolation structure 103 located below the remaining portion of the removed silicon nitride layer 115. This forms multiple character line trenches 118T and multiple gate recesses 108 overlapping with the character line trenches 118T. In this embodiment, the multiple character line trenches 118T can expose a portion of the shallow trench isolation structure 103 between a group of multiple active regions 101A in the memory cell circuit region of the dynamic random access memory circuit structure; and the multiple gate recesses 108 can expose a portion of the corresponding active region 101A. Notably, each gate recess 108 is located within a corresponding character line trench 118T; and each gate recess 108 is interconnected with its corresponding character line trench 118T.
[0123] like Figures 7A to 7F As shown, Figure 7A This is a top view showing the process structure after the formation of multiple gate recesses 108 and multiple character line trenches 118T. Figure 7B , Figure 7C , Figure 7D , Figure 7E They are along Figure 7A The structural cross-section shown by tangents CG1, CG2, CG3, and CG4 in the diagram; Figure 7F It is based on Figure 7A A cross-sectional view of the process structure of the peripheral circuit region 101P of the dynamic random access memory circuit is shown.
[0124] Please refer to sub-step S132: Form a gate dielectric layer 107L covering the bottom and sidewalls of at least one gate recess 108 / corresponding character line trench 118T. In one embodiment of the invention, the gate dielectric layer 107L can be formed using a dielectric material deposition process. However, in this embodiment, the gate dielectric layer 107L is a silicon oxide layer formed on a portion of the semiconductor substrate 101 exposed from the gate recess 108 / corresponding character line trench 118T using a thermal oxidation process. In another embodiment, the gate dielectric layer 107L can be a high dielectric constant (HK) dielectric layer.
[0125] Please refer to sub-step S133: At least one gate electrode 107E is formed in at least one gate recess 108. In one embodiment of the invention, the formation of the gate electrode 107E includes the following steps: First, a barrier / work function layer 107F (e.g., a titanium nitride (TN) layer) is formed to cover the bottom and sidewalls of the gate recess 108 / character line trench 118T. Subsequently, the gate recess 108 / corresponding character line trench 118T is filled with a metal material 118 (e.g., tungsten (W)) to form the gate electrode 107E in the gate recess 108 and to form a metal interconnect line that spans a plurality of active regions 101 and a portion of the shallow trench isolation structure 103 located between the plurality of active regions 101. Next, the metal material 118 is etched back. Then, a protective layer 119, such as a silicon nitride layer, is formed and fills and covers the gate electrode 107E located in the gate recess 108.
[0126] In this embodiment, a portion of the barrier / work function layer 107F and metal material 118 filling each gate recess 108 can serve as gate electrode 107E; another portion of the barrier / work function layer 107F and metal material 118 retained in the character line trench 118T can serve as character line W, used to connect the gate electrode 107E of the transistor (e.g., transistor 107) in the memory cell region of the dynamic random access memory circuit.
[0127] Please refer to sub-step S134: At least one source region 107S and one drain region 107D are formed in at least one active region 101A, adjacent to at least one gate electrode 107E. The source region 107S is adjacent to one side of the gate electrode 107E; the drain region 107D is adjacent to the other side of the gate electrode 107E. The gate dielectric layer 107L, gate electrode 107E, source region 107S, and drain region 107D formed in the same active region 101A together constitute a transistor 107. In this embodiment, multiple access transistors in the memory cell circuit region of the dynamic random access memory circuit are respectively formed in multiple active regions 101A, and their respective gate electrodes 107E can be interconnected by corresponding bit lines and arranged into an array of access transistors. Then, a stack of capacitors (not shown) can be formed to connect the source regions 107S of the access transistors in the memory cell circuit region. Next, a series of subsequent processes, such as metal inlay processes, are performed to form an inline structure (not shown), thus completing the fabrication of the semiconductor circuit structure 100.
[0128] like Figures 8A to 8F As shown, Figure 8A This is a top view showing the fabrication structure after the semiconductor circuit structure 100 has been fabricated. Figure 8B , Figure 8C , Figure 8D , Figure 8E They are along Figure 8A The structural cross-section shown by the tangents CH1, CH2, CH3, and CH4 is shown in the figure. Figure 8F It is based on Figure 8A This is a cross-sectional view of the manufacturing process structure of the peripheral circuit area of a semiconductor circuit structure (dynamic random access memory circuit structure).
[0129] In the top view of the dynamic random access memory circuit structure of this embodiment, as shown in Figure 1H(1), there is a gap G between two adjacent active regions 101A. A portion of the composite isolation structure 102 (or composite shallow trench isolation region) located inside the gap G can be referred to as the internal block, and the remaining portion of the composite isolation structure 102 (or composite shallow trench isolation region) located outside the gap G can be referred to as the external block. The internal block can be further divided into a first portion P1 that does not overlap with the metal material 118 (or character line trench 118T) and a second portion P2 that overlaps with the metal material 118 (or character line trench 118T). The metal connecting line (metal material 118) can span the first group of active regions 101A and the second portion P2 of the internal block of the composite isolation structure 102 (or composite shallow trench isolation region).
[0130] In this embodiment, the first portion P1 of the internal block of the composite isolation structure 102 (or composite shallow trench isolation region) includes a portion of a high thermal conductivity region 106 and a dielectric layer 105 (such as...). Figure 8B As shown). The second part P2 of the internal block of the composite isolation structure 102 (or composite shallow trench isolation area) includes the shallow trench isolation structure 103, but does not include any high thermal conductivity area 106 (as shown). Figure 8C (As shown).
[0131] In traditional dynamic random access memory (DRAM) circuit structures, the active region of the memory cell circuit is surrounded by a shallow trench isolation structure made of silicon dioxide, which is a poor conductor of heat. In embodiments of the present invention, since at least a portion of the silicon dioxide shallow trench isolation structure 103 surrounding the active region / transistor is replaced by a high thermal conductivity region 106 with higher heat dissipation capacity (higher than the silicon dioxide shallow trench isolation structure 103), the efficiency of reducing transistor junction temperature can be significantly improved. Taking the above-described DRAM circuit structure as an example, most of the silicon dioxide shallow trench isolation structure 103 located in the memory cell circuit region surrounding the active region / access transistor can be removed and replaced with a high thermal conductivity material (such as...). Figure 8F As shown), only a portion of the silica shallow trench isolation structure 103 located below the character line W is retained (as shown). Figure 8B (As shown). On the other hand, the silicon dioxide shallow trench isolation structure 103 surrounding the active region / transistor in the peripheral area 101P of the dynamic random access memory circuit structure can be further removed from the peripheral circuit of the circuit structure and replaced with a high thermal conductivity material, such as... Figure 8F As shown. High thermal conductivity materials can be semiconductor materials, such as silicon, silicon carbide, boron nitride, and aluminum nitride. Taking silicon as an example, following the above process, after thermal annealing, the silicon die size can be between 0.1 micrometers and 2 micrometers. Therefore, when the depth of the semiconductor material is between 250 nanometers and 500 nanometers, the maximum number of silicon dies along the depth direction of the semiconductor material is 3 (or, the maximum number of silicon die boundaries is 2).
[0132] Since the process and materials for forming the high thermal conductivity region 106 of the shallow trench isolation region can be provided by the standard process of the semiconductor circuit structure 100 and integrated therein, the heat dissipation capability of the semiconductor circuit structure 100 can be effectively improved without increasing expensive costs.
[0133] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the claims.
Claims
1. A method for fabricating a semiconductor circuit structure, comprising: Provide a semiconductor substrate; A shallow trench is formed extending from a raw surface of the semiconductor substrate into the interior of the semiconductor substrate to surround an active region; A dielectric layer is formed on one side wall and one bottom of the shallow trench; as well as The shallow trench is filled with a thermally conductive semiconductor material, wherein the thermally conductive semiconductor material is isolated from the semiconductor substrate by the dielectric layer.
2. The method for fabricating a semiconductor circuit structure as described in claim 1, characterized in that, The step of filling the shallow trench using the thermally conductive semiconductor material includes: The shallow trench is filled with an amorphous semiconductor material; and The amorphous semiconductor material is subjected to a laser annealing or a thermal annealing process to form the thermally conductive semiconductor material.
3. The method for fabricating a semiconductor circuit structure as described in claim 2, characterized in that, The thermally conductive semiconductor material comprises silicon with an average die thickness between 0.1 micrometers (µm) and 2 micrometers.
4. The method for fabricating a semiconductor circuit structure as described in claim 2, characterized in that, Before performing the laser annealing or thermal annealing process on the amorphous semiconductor material, the process further includes: curing the amorphous semiconductor material using ultraviolet light.
5. The method for fabricating a semiconductor circuit structure as described in claim 2, characterized in that, A first capping layer is applied over the active region. After the shallow trench is filled with the amorphous thermally conductive semiconductor material, the amorphous semiconductor material will cover the first capping layer.
6. The method for fabricating a semiconductor circuit structure as described in claim 5, characterized in that, After the shallow trench is filled with the amorphous thermally conductive semiconductor material, one top surface of the amorphous semiconductor material will be substantially between 800 nanometers and 2000 nanometers higher than one top surface of the first capping layer.
7. The method for fabricating a semiconductor circuit structure as described in claim 5, characterized in that, After performing the laser annealing or thermal annealing process on the amorphous semiconductor material, a planarization process is further performed on the thermally conductive semiconductor material.
8. The method for fabricating a semiconductor circuit structure as described in claim 7, characterized in that, After the planarization process, one top surface of the thermally conductive semiconductor material is substantially flush with the top surface of the first cover.
9. The method for fabricating a semiconductor circuit structure as described in claim 7, characterized in that, After the planarization process, the process further includes etching the thermally conductive semiconductor material downwards so that the top surface of the etched thermally conductive semiconductor material is substantially lower than the original surface of the semiconductor substrate.
10. The method for fabricating a semiconductor circuit structure as described in claim 9, characterized in that, After the thermally conductive semiconductor material is etched downwards, the etched top surface of the thermally conductive semiconductor material is substantially between 5 nanometers and 30 nanometers below the original surface of the semiconductor substrate.
11. The method for fabricating a semiconductor circuit structure as described in claim 9, characterized in that, After etching the thermally conductive semiconductor material downwards, a second capping layer is deposited to cover the top surface of the thermally conductive semiconductor material.
12. The method for fabricating a semiconductor circuit structure as described in claim 2, characterized in that, The thermally conductive semiconductor material includes silicon; and in the thermally conductive semiconductor material, the number of silicon dies along a depth direction of the thermally conductive semiconductor material is at most 3.