Driving circuit with clamping protection

Abstract

The invention provides a driving circuit with clamping protection, which comprises a clamping protection module, a driving module and a potential balance module, and can switch the working mode of the driving circuit between a normal driving mode and a clamping protection mode according to a received external logic signal through the cooperation of the clamping protection module and the potential balance module. And in the clamping protection mode, the voltage finally output by the driving module can be limited in a voltage interval between a low-level threshold signal and a high-level threshold signal which are externally input, so that external clamping of the driving circuit is realized. Furthermore, a low-level threshold signal and a high-level threshold signal which are externally input can be adjusted according to actual conditions, so that the problem that the clamping voltage of a traditional driving output protection circuit cannot be adjusted according to the actual conditions in the later period is solved, and the flexibility of the driving circuit is improved.

Description

Technical Field

[0001] This application relates to the field of drive circuit technology, and specifically to a drive circuit with clamping protection. Background Technology

[0002] Traditional drive output protection circuits are relatively simple in design, with a fixed clamping voltage that cannot be adjusted later via software. Furthermore, traditional drive output protection circuits use a single clamping method, only activating when the drive output voltage exceeds the preset clamping voltage. Summary of the Invention

[0003] This application provides a drive circuit with clamping protection, which can solve at least one of the following problems in traditional drive output protection circuits: the clamping voltage cannot be adjusted according to the actual situation in the later stage, and the clamping protection is only activated when the drive output voltage exceeds the preset clamping voltage.

[0004] This application provides a drive circuit with clamping protection, including:

[0005] The clamping protection module is used to receive external logic signals, external initial drive signals, and external high-level threshold signals and low-level threshold signals, and output complementary drive signals to subsequent circuits.

[0006] The driving module is used to receive the complementary driving signal and output different final driving signals to the subsequent circuit according to different working modes.

[0007] A potential balancing module acts on the output terminal of the drive module to make the output terminal of the drive module a high-impedance state;

[0008] The drive circuit with clamping protection is configured as follows:

[0009] When the logic signal is set to '1', the driving circuit with clamp protection operates in normal driving mode.

[0010] When the logic signal is set to '0', the operating mode of the drive circuit with clamp protection is clamp protection mode.

[0011] Optionally, in the drive circuit with clamping protection, the clamping protection module includes: first to fourth inverters, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, first to sixth diodes, first to twelfth current sources, first to eighth NPN transistors, first to eighth PNP transistors, and a buffer, wherein,

[0012] The input terminal of the first inverter is connected to the gate of the first PMOS transistor, the output terminal of the first inverter is connected to the gate of the first NMOS transistor, the source of the first PMOS transistor and the source of the first NMOS transistor are connected together and the source connection node is connected to the low-level threshold signal, the drain of the first PMOS transistor and the drain of the first NMOS transistor are connected together and the drain connection node is connected to the output terminal of the first diode, the first diode and the second diode are connected in series, and the input terminal of the second diode is connected to the base of the second NPN transistor.

[0013] The input terminal of the second inverter is connected to the gate of the second PMOS transistor, the output terminal of the second inverter is connected to the gate of the second NMOS transistor, the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected together and the drain connection node is connected to the high-level threshold signal, the source of the second PMOS transistor and the source of the second NMOS transistor are connected together and the source connection node is connected to the input terminal of the third diode, the third diode and the fourth diode are connected in series, the output terminal of the fourth diode is connected to the base of the second PNP transistor, and the input terminals of the first inverter and the second inverter are also connected to the external logic signal;

[0014] The input terminals of the first to sixth current sources and the collector of the fifth NPN transistor are all connected to the same node. The output terminal of the first current source is connected to the input terminal of the second diode, and the output terminal of the second current source is connected to the collector of the first NPN transistor. The emitter of the first NPN transistor, the cathode of the fifth diode, the emitter of the third PNP transistor, the collector of the fourth NPN transistor, and the collector of the fifth PNP transistor are all connected to the base of the sixth PNP transistor. The output terminal of the third current source is connected to the second NPN transistor. The collector of the NPN transistor is connected to the collector of the second NPN transistor, the emitter of the third NPN transistor is connected to the anode of the fifth diode, the output of the fourth current source is connected to the collector of the third PNP transistor, the output of the fifth current source is connected to the collector of the fourth PNP transistor, the output of the sixth current source is connected to the collector of the sixth NPN transistor, the emitter of the sixth NPN transistor and the collector of the sixth PNP transistor are connected, and the emitter of the fifth NPN transistor, the emitter of the fourth PNP transistor, the collector of the third NPN transistor, and the collector of the sixth PNP transistor are connected. The positive terminal of the transistor and the collector of the first PNP transistor are both connected to the base of the sixth NPN transistor. The output of the third inverter is connected to the base of the third PNP transistor. The base of the third NPN transistor is connected to the input of the third inverter and the external logic signal. The base of the fourth PNP transistor is connected to the input of the fourth inverter and the external logic signal. The base of the fourth NPN transistor is connected to the output of the fourth inverter. The input of the seventh current source is connected to the base of the second PNP transistor. The emitter of the PNP transistor is connected to the input terminal of the eighth current source, the cathode of the sixth diode is connected to the collector of the second PNP transistor, the emitter of the second PNP transistor is connected to the input terminal of the ninth current source, the emitter of the third NPN transistor is connected to the input terminal of the tenth current source, the emitter of the fourth NPN transistor is connected to the input terminal of the eleventh current source, the emitter of the sixth PNP transistor is connected to the input terminal of the twelfth current source, and the output terminals of the seventh to twelfth current sources and the emitter of the fifth PNP transistor are all connected to the same node.

[0015] The collectors of the seventh NPN transistor and the eighth NPN transistor are connected and then connected to the input terminal of the sixth current source. The emitters of the seventh NPN transistor and the eighth NPN transistor are connected and then connected to the subsequent circuit. The base of the seventh NPN transistor is connected to the base of the sixth NPN transistor. The collectors of the seventh PNP transistor and the eighth PNP transistor are connected and then connected to the subsequent circuit. The base of the seventh PNP transistor is connected to the base of the sixth PNP transistor. The bases of the eighth NPN transistor and the eighth PNP transistor are connected and then connected to the output terminal of the buffer. The bases of the fifth NPN transistor and the fifth PNP transistor are connected and then connected to the output terminal of the buffer. The output terminal of the buffer is connected to the series node between the emitter and the collector of the sixth NPN transistor. The input terminal of the buffer is connected to the external initial drive signal, and the enable signal terminal of the buffer is connected to the external logic signal.

[0016] Optionally, in the drive circuit with clamping protection, the drive module includes: a ninth NPN transistor, a ninth PNP transistor, a thirteenth current source, and a fourteenth current source. The input terminal of the thirteenth current source is connected to the input terminal of the first current source; the output terminal of the thirteenth current source is connected to the collector of the ninth NPN transistor; the emitter of the ninth NPN transistor is connected to the collector of the ninth PNP transistor; the emitter of the ninth PNP transistor is connected to the input terminal of the fourteenth current source; and the output terminal of the fourteenth current source is connected to the seventh current source. The output terminal of the current source is connected to the collector of the seventh PNP transistor and the collector of the eighth PNP transistor, and then to the base of the ninth NPN transistor. The emitter of the seventh NPN transistor and the emitter of the eighth NPN transistor are connected to the base of the ninth PNP transistor. The series connection between the ninth NPN transistor and the ninth PNP transistor is the output terminal of the drive module. The output terminal of the drive module is connected to the series connection between the first NPN transistor and the first PNP transistor in the clamping protection module.

[0017] Optionally, in the drive circuit with clamping protection, the potential balancing module includes: fifteenth to twenty-third current sources, a seventh diode, an eighth diode, a fifth inverter, tenth to fifteenth PNP transistors, and tenth to thirteenth NPN transistors. The input terminals of the fifteenth to nineteenth current sources are all connected to the same node. The output terminal of the fifteenth current source is connected to the collector of the twelfth NPN transistor. The base of the twelfth NPN transistor is connected to its collector. The emitter of the twelfth NPN transistor is connected to the collector of the thirteenth NPN transistor. The emitter of the thirteenth NPN transistor is connected to the twentyth NPN transistor. The input terminal of the first current source is connected to the input terminal of the 16th current source. The output terminal of the 16th current source is connected to the collector of the 12th PNP transistor. The emitter of the 12th PNP transistor is connected to the collector of the 13th PNP transistor. The emitter of the 13th PNP transistor is connected to the input terminal of the 20th current source. The output terminal of the 17th current source is connected to the collector of the 15th PNP transistor. The emitter of the 15th PNP transistor is connected to the collector of the 14th PNP transistor. The output terminal of the 18th current source is connected to the collector of the 11th PNP transistor. The emitter of the 11th PNP transistor is connected to the collector of the 11th NPN transistor. The emitter of the 11th NPN transistor is connected to the input terminal of the 20th current source. Connect the input terminal of the twenty-second current source. Connect the output terminal of the nineteenth current source to the collector of the tenth PNP transistor. Connect the emitter of the tenth PNP transistor to the collector of the tenth NPN transistor. Connect the emitter of the tenth NPN transistor to the input terminal of the twenty-third current source. Connect the emitters of the fourteenth and thirteenth PNP transistors to the base of the eleventh PNP transistor. Connect the base of the fifteenth PNP transistor to the base of the tenth PNP transistor. Connect the base of the fifteenth PNP transistor to the emitter of the fifteenth PNP transistor. Connect the base of the eleventh NPN transistor to the base of the tenth NPN transistor. The base of the eleventh NPN transistor is connected to the collector of the eleventh NPN transistor. The outputs of the twentieth to the twenty-third current sources are all connected to the same node. The seventh diode is connected in series between the outputs of the nineteenth and fifteenth current sources. The eighth diode is connected in series between the outputs of the twentieth and the twenty-third current sources. The input of the fifth inverter is connected to the base of the thirteenth NPN transistor and the external logic signal. The output of the fifth inverter is connected to the base of the twelfth PNP transistor. The series node between the tenth PNP transistor and the tenth NPN transistor is connected to the output of the drive module.

[0018] Optionally, in the drive circuit with clamping protection, when the operating mode is clamping protection mode, the output terminal of the drive module is in a high-impedance state when the output terminal of the drive module is not connected to an external power supply.

[0019] Optionally, in the drive circuit with clamping protection, when the operating mode is clamping protection mode, if the output terminal of the drive module is connected to an external power supply, and the voltage of the external power supply is greater than the external low-level threshold signal and less than the high-level threshold signal, the voltage of the output terminal of the drive module is the voltage of the external power supply.

[0020] Optionally, in the drive circuit with clamping protection, when the working mode is clamping protection mode, when the output terminal of the drive module is connected to an external power supply, and the voltage of the external power supply is less than or equal to the external low-level threshold signal, the voltage of the output terminal of the drive module is the low-level threshold signal.

[0021] When the operating mode is clamping protection mode, if the output terminal of the drive module is connected to an external power supply and the voltage of the external power supply is greater than or equal to the external high-level threshold signal, the voltage of the output terminal of the drive module is the high-level threshold signal.

[0022] The technical solution of this application has at least the following advantages:

[0023] In the drive circuit with clamping protection provided in this application, the drive module, in cooperation with the clamping protection module and the potential balancing module, can switch the working mode of the drive circuit between normal drive mode and clamping protection mode according to the received external logic signal. In the clamping protection mode, the voltage of the final output of the drive module can be limited to the voltage range between the low-level threshold signal and the high-level threshold signal of the external input.

[0024] Furthermore, the driving circuit provided in this application can directly select the clamping protection mode. When the external power supply voltage of the driving module exceeds the preset clamping voltage range, the external power supply voltage of the driving module is clamped, so that the output voltage of the driving module is limited to the vicinity of the low-level threshold signal or the vicinity of the high-level threshold signal. That is, clamping protection can be realized outside the driving circuit, thereby solving the problem that the clamping protection of the traditional driving output protection circuit only starts when the driving output voltage exceeds the preset clamping voltage.

[0025] Furthermore, the low-level threshold signal and high-level threshold signal of the external input in this application can be adjusted according to the actual situation, thereby solving the problem that the clamping voltage of the traditional drive output protection circuit cannot be adjusted according to the actual situation in the later stage, and improving the flexibility of the drive circuit. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the circuit structure of the drive circuit with clamping protection according to an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram illustrating the change of the output current of the drive module as a function of an external power supply according to an embodiment of the present invention.

[0029] The reference numerals in the attached figures are explained as follows:

[0030] 11-Clamping protection module, 12-Drive module, 13-Potential balance module. Detailed Implementation

[0031] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0033] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0034] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0035] This application provides a driving circuit with clamping protection, see reference. Figure 1 , Figure 1 This is a schematic diagram of the circuit structure of a drive circuit with clamping protection according to an embodiment of the present invention. The drive circuit with clamping protection includes:

[0036] The clamping protection module 11 is used to receive external logic signal LOGIC, external initial drive signal Driver_in, and external high-level threshold signal CPHV and low-level threshold signal CPLV, and output complementary drive signals to the subsequent circuit.

[0037] The driver module 12 is used to receive the complementary drive signal and output the final drive signal Driver_OUT to the subsequent circuit according to different working modes.

[0038] The potential balancing module 13 acts on the output terminal of the drive module to make the output terminal of the drive module a high-impedance state;

[0039] The drive circuit with clamping protection is configured as follows:

[0040] When the logic signal LOGIC is set to '1', the driving circuit with clamping protection operates in normal driving mode.

[0041] When the logic signal LOGIC is set to '0', the operating mode of the drive circuit with clamping protection is clamping protection mode.

[0042] In normal drive mode, the clamping protection module 11 does not intervene; in clamping protection mode, the clamping protection module 11 is activated, clamping the output voltage to prevent overvoltage damage to the transistor. The upper limit value CPHV (high-level threshold signal) and the lower limit value CPLV (low-level threshold signal) of the clamping voltage can be set using a conventional DAC (Digital-to-Analog Converter) to adapt to different application scenarios, thereby solving the problem that the clamping voltage of traditional drive output protection circuits cannot be adjusted according to actual conditions later.

[0043] Specifically, the clamping protection module 11 has a complementary symmetrical structure. Specifically, the clamping protection module 11 includes: first to fourth inverters X1-X4, a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, a second PMOS transistor P2, first to sixth diodes D1-D6, first to twelfth current sources I1-I12, first to eighth NPN transistors QN1-QN8, first to eighth PNP transistors QP1-QP8, and a buffer B1.

[0044] The input terminal of the first inverter X1 is connected to the gate of the first PMOS transistor P1, and the output terminal of the first inverter X1 is connected to the gate of the first NMOS transistor N1. The source of the first PMOS transistor P1 and the source of the first NMOS transistor N1 are connected together, and the connection node of their sources is connected to the low-level threshold signal CPLV. The drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 are connected together, and the connection node of their drains is connected to the output terminal of the first diode D1. The first diode D1 and the second diode D2 are connected in series, and the input terminal of the second diode D2 is connected to the base of the second NPN transistor QN2.

[0045] The input terminal of the second inverter D2 is connected to the gate of the second PMOS transistor QP2, and the output terminal of the second inverter D2 is connected to the gate of the second NMOS transistor N2. The drains of the second PMOS transistor P2 and the drains of the second NMOS transistor N2 are connected, and the connection node of their drains is connected to the high-level threshold signal CPHV. The sources of the second PMOS transistor P2 and the sources of the second NMOS transistor N2 are connected, and the connection node of their sources is connected to the input terminal of the third diode D3. The third diode D3 and the fourth diode D4 are connected in series. The output terminal of the fourth diode D4 is connected to the base of the second PNP transistor. The input terminals of the first inverter X1 and the second inverter X2 are also connected to the external logic signal LOGIC.

[0046] The input terminals of the first to sixth current sources I1-I6 and the collector of the fifth NPN transistor QN5 are all connected to the same node. The output terminal of the first current source I1 is connected to the input terminal of the second diode D2, and the output terminal of the second current source I2 is connected to the collector of the first NPN transistor QN1. The emitter of the first NPN transistor QN1, the cathode of the fifth diode D5, the emitter of the third PNP transistor QP3, the collector of the fourth NPN transistor QN4, and the collector of the fifth PNP transistor QP5 are all connected to the base of the sixth PNP transistor QP6. The output terminal of the third current source I3 is connected to the second NPN transistor. The collector of transistor QN2 is connected to the collector of the third PNP transistor QP3, the emitter of the second NPN transistor QN2 is connected to the anode of the fifth diode D5, the output of the fourth current source I4 is connected to the collector of the third PNP transistor QP3, the output of the fifth current source I5 is connected to the collector of the fourth PNP transistor QP4, the output of the sixth current source I6 is connected to the collector of the sixth NPN transistor QN6, the emitter of the sixth NPN transistor QN6 is connected to the collector of the sixth PNP transistor QP6, and the emitter of the fifth NPN transistor QN5, the emitter of the fourth PNP transistor QP4, the collector of the third NPN transistor QN3, and the collector of the sixth diode D6 are connected. The positive terminal and the collector of the first PNP transistor QP1 are both connected to the base of the sixth NPN transistor QN6. The output of the third inverter X3 is connected to the base of the third PNP transistor QP3. The base of the third NPN transistor QN3 is connected to the input of the third inverter X3 and the external logic signal LOGIC. The base of the fourth PNP transistor QP4 is connected to the input of the fourth inverter X4 and the external logic signal LOGIC. The base of the fourth NPN transistor QN4 is connected to the output of the fourth inverter X4. The input of the seventh current source I7 is connected to the base of the second PNP transistor QP2. The first PNP transistor... The emitter of P-transistor QP1 is connected to the input terminal of the eighth current source I8. The cathode of the sixth diode D6 is connected to the collector of the second PNP transistor QP2. The emitter of the second PNP transistor QP2 is connected to the input terminal of the ninth current source I9. The emitter of the third NPN transistor QN3 is connected to the input terminal of the tenth current source I10. The emitter of the fourth NPN transistor QN4 is connected to the input terminal of the eleventh current source I11. The emitter of the sixth PNP transistor QP6 is connected to the input terminal of the twelfth current source I12. The output terminals of the seventh to twelfth current sources I7-I12 and the emitter of the fifth PNP transistor QP5 are all connected to the same node.

[0047] The collector of the seventh NPN transistor QN7 and the collector of the eighth NPN transistor QN8 are connected and then connected to the input terminal of the sixth current source I6. The emitter of the seventh NPN transistor QN7 and the emitter of the eighth NPN transistor QN8 are connected and then connected to the subsequent circuit. The base of the seventh NPN transistor QN7 is connected to the base of the sixth NPN transistor QN6. The collector of the seventh PNP transistor QP7 and the collector of the eighth PNP transistor QP8 are connected and then connected to the subsequent circuit. The base of the seventh PNP transistor QP7 is connected to the base of the sixth PNP transistor QP6. The bases of the eighth NPN transistor QN8 and the eighth PNP transistor QP8 are connected to the output of the buffer B1. The bases of the fifth NPN transistor QN5 and the fifth PNP transistor QP5 are connected to the output of the buffer B1. The output of the buffer B1 is connected to the series node between the emitter and collector of the sixth NPN transistor QN6 and the sixth PNP transistor QP6. The input of the buffer B1 is connected to the external initial drive signal Driver_in, and the enable signal of the buffer B1 is connected to the external logic signal LOGIC.

[0048] Furthermore, the driving module 12 comprises an AB-class push-pull output structure consisting of a high-power NPN transistor QN7 and a PNP transistor QP7. Specifically, the driving module 12 includes: a ninth NPN transistor QN9, a ninth PNP transistor QP9, a thirteenth current source I13, and a fourteenth current source I14. The input terminal of the thirteenth current source I13 is connected to the input terminal of the first current source I1, the output terminal of the thirteenth current source I13 is connected to the collector of the ninth NPN transistor QN9, the emitter of the ninth NPN transistor QN9 is connected to the collector of the ninth PNP transistor QP9, the emitter of the ninth PNP transistor QP9 is connected to the input terminal of the fourteenth current source I14, and the output terminal of the fourteenth current source I14 is connected to the input terminal of the seventh current source I7. At the output terminal, the collector of the seventh PNP transistor QP7 and the collector of the eighth PNP transistor QP8 are connected to the base of the ninth NPN transistor QN9. The emitter of the seventh NPN transistor QN7 and the emitter of the eighth NPN transistor QN8 are connected to the base of the ninth PNP transistor QP9. The series connection between the ninth NPN transistor QN9 and the ninth PNP transistor QP9 is the output terminal of the drive module. The output terminal of the drive module is connected to the series connection between the first NPN transistor QN1 and the first PNP transistor QP1 in the clamping protection module 11.

[0049] Preferably, the potential balancing module 13 includes: fifteenth to twenty-third current sources I15-I19, seventh diode D7, eighth diode D8, fifth inverter X5, tenth to fifteenth PNP transistors QP10-QP15, and tenth to thirteenth NPN transistors QN10-QN13. The input terminals of the fifteenth to nineteenth current sources I15-I19 are all connected to the same node. The output terminal of the fifteenth current source I15 is connected to the collector of the twelfth NPN transistor QN12. The base of the twelfth NPN transistor QN12 is connected to its collector. The emitter of the twelfth NPN transistor QN12 is connected to the collector of the thirteenth NPN transistor QN13. The emitter of N-type transistor QN13 is connected to the input of the 21st current source I21. The output of the 16th current source I16 is connected to the collector of the 12th PNP transistor QP12. The emitter of the 12th PNP transistor QP12 is connected to the collector of the 13th PNP transistor QP13. The emitter of the 13th PNP transistor QP13 is connected to the input of the 20th current source I20. The output of the 17th current source I17 is connected to the collector of the 15th PNP transistor QP15. The emitter of the 15th PNP transistor QP15 is connected to the collector of the 14th PNP transistor QP14. The gate of the 14th PNP transistor QP14 is connected to an external bias compensation voltage VBIS. The output of the 18th current source I18 is connected to... The collector of the eleventh PNP transistor QP11 is connected to the collector of the eleventh NPN transistor QN11. The emitter of the eleventh NPN transistor QN11 is connected to the input of the twenty-second current source I22. The output of the nineteenth current source I19 is connected to the collector of the tenth PNP transistor QP10. The emitter of the tenth PNP transistor QP10 is connected to the collector of the tenth NPN transistor QN10. The emitter of the tenth NPN transistor QN10 is connected to the input of the twenty-third current source I23. The emitters of the fourteenth PNP transistor QP14 and the thirteenth PNP transistor QP13 are both connected to the base of the eleventh PNP transistor QP11. The fifteenth... The base of PNP transistor QP15 is connected to the base of the tenth PNP transistor QP10. The base of the fifteenth PNP transistor QP15 is connected to its emitter. The base of the eleventh NPN transistor QN11 is connected to the base of the tenth NPN transistor QN10. The base of the eleventh NPN transistor QN11 is connected to its collector. The outputs of the twentieth to twenty-third current sources I20-I23 are all connected to the same node. The output of the nineteenth current source I19 and the output of the fifteenth current source I15 are connected in series with the seventh diode D7. The output of the twentieth current source I20 and the output of the twenty-third current source I23 are connected in series with the eighth diode D8.The input of the fifth inverter X5 is connected to the base of the thirteenth NPN transistor QN13 and the external logic signal LOGIC. The output of the fifth inverter X5 is connected to the base of the twelfth PNP transistor QP12. The series connection between the tenth PNP transistor QP10 and the tenth NPN transistor QN10 is connected to the output of the drive module.

[0050] When the operating mode is normal drive mode (logic signal LOGIC set to '1'), QN3 and QP3 are turned on, QN4 and QP4 are turned off, buffer B1 is turned on, and currents from I4 and I10 flow to QP5 and QN5. The bases of QP5 and QN5 are controlled by the output of buffer B1, and their voltage level is Driver_in. The emitters and bases of QN6 and QP6 are reverse biased and cannot conduct. The base voltage of QN8 / QP8 on the right side of the two differential pairs is higher than that of QN7 / QP7 on the left side, causing the right side to conduct. Driver_OUT is output through QP9 and QN9 in a push-pull manner and has the same potential as Driver_in. At the same time, QP12 and QN13 are turned on, and the current sources I19 and I23 are pulled by QN12 and QP13 through diodes D7 and D8. The currents of QN10 and QP10 are reduced or canceled out. The collectors of QN10 and QP10 are in a high-impedance state, which does not affect the Driver_OUT output. In this way, the drive circuit realizes the drive path from Driver_in to Driver_OUT.

[0051] Furthermore, when the operating mode is clamp protection mode (logic signal LOGIC is set to '0'), buffer B1 is turned off, and the initial drive signal Driver_in input from the external input does not affect the loop voltage. If the external voltage applied to the output of the drive module is within the clamping window (CPHV-CPLV), the port voltage is determined by the external voltage, and the current at the output of the drive module is only the leakage current under high impedance. If the external voltage applied to the output is outside the clamping window (CPHV-CPLV), it will be clamped near the clamping voltage, and the resulting clamping current will be discharged through the power transistor.

[0052] Specifically, the clamping protection mode is subdivided into the following three cases:

[0053] 1) When the output of the drive module is not connected to an external power supply, the output of the drive module is in a high-impedance state. Specifically, QP4 and QN4 are turned on, QN3 and QP3 are turned off, buffer B1 is disconnected, the current in the circuit system is rebalanced, and the current from current sources I5 and I11 flows to QP1, QP2 and QN1, QN2. QN5 and QP5 lose current, causing their base-emitter voltage (VBE) to lose its normal level transmission function. The base voltage of QN7 and QP7 on the left side of the two differential pairs is higher than that of QN8 and QP8 on the right side, causing the left side to conduct. Driver_OUT, through the feedback path, cuts off QN9 and QP9, thus losing its level connection with the left-hand circuit. At this time, the lower circuits QP12 and QN13 are cut off, and current sources I19 and I23 flow to QP10 and QN10. Setting the currents of QP10 and QN10 to be equal (i.e., no current flows out), the Driver_OUT voltage is controlled by the collectors of QP10 and QN10. The currents of QP10 and QN10 can be set to be equal, and the output voltage is close to the midpoint between the upper and lower power rails. The output terminal Driver_OUT exhibits a high-impedance state. Here, VBE is the base-emitter voltage of the transistor, also known as the forward voltage drop, typically 0.6V-0.7V.

[0054] 2) When the output terminal of the drive module is connected to an external power supply, and the voltage of the external power supply is greater than the external low-level threshold signal and less than the high-level threshold signal, the voltage at the output terminal of the drive module is the voltage of the external power supply. Specifically, all transistor states are consistent with the transistor states described in case 1). Since Drive_OUT is in a high-impedance state, its voltage is determined by the external power supply.

[0055] 3) When the output terminal of the drive module is connected to an external power supply, and the voltage of the external power supply is less than or equal to the external low-level threshold signal, the voltage at the output terminal of the drive module is the low-level threshold signal; when the operating mode is clamping protection mode, when the output terminal of the drive module is connected to an external power supply, and the voltage of the external power supply is greater than or equal to the external high-level threshold signal, the voltage at the output terminal of the drive module is the high-level threshold signal. Specifically, QP4 and QN4 are turned on, and QN3 and QP3 are turned off. The logic signal LOGIC controls the switch outputs CPHV and CPLV. Since the output voltage of the driver module is less than CPLV or greater than CPHV, the feedback output voltage causes diodes D3 and D4 to conduct. Current flows from QP4 and QN4 to QP2 and QN2, causing the output voltage of the driver module to approach CPHV / CPLV. At this time, QN7 and QP7 control power transistors QP9 and QN9 to provide a current discharge path, keeping the Driver_OUT voltage clamped near CPHV / CPLV to prevent overvoltage damage to other components in the system. When the external power supply voltage is greater than or equal to CPHV, the voltage at the cathode of D6 is greater than or equal to CPHV-VBE, and the voltage at the base of QP2 is CPHV-2VBE. Therefore, QP2 is turned on, and the current from D3, D4 and the base of QP2 flows to I7, causing the anode of D6 to approach CPHV. The voltage is then transferred to the base of QN7 through diode D6, and the voltage transferred to the collector of QP9 is CPHV. This achieves the clamping circuit clamping the voltage at the Driver_OUT terminal at CPHV when the output is greater than CPHV. Similarly, the same applies when the external power supply voltage is less than or equal to CPLV.

[0056] When the driving circuit operates in clamping protection mode, refer to Figure 2 , Figure 2 This diagram illustrates the change in output current of the drive module as a function of an external power supply, according to an embodiment of the present invention. The vertical axis represents the initial drive signal Drive_in (current signal), in milliamperes (mA); the horizontal axis represents the output voltage value Driver_OUT of the drive module, in volts (V). Assume H_CLAMP (CPHV) = 6.5V and L_CLAMP (CPLV) = -1.5V. When the external voltage is within the range of CPHV to CPLV, dynamic clamping is not triggered, the output current of the drive module is 0, and the output power transistor is off. If the external power supply voltage exceeds the range of CPHV - CPLV (H_CLAMP - L_CLAMP), dynamic clamping is triggered, the output power transistor operates in the amplification region, and the output current of the drive module increases linearly with the absolute value of the external power supply voltage. This achieves current venting from the drive circuit output, protecting the internal circuitry, and conforms to the clamping protection mode of the drive circuit with respect to the external output voltage (external power supply).

[0057] In this application, by dynamically balancing the current under different logic states, the potential at the output terminal of the drive module is level-shifted and transmitted through a transistor, and the drive module achieves a high-impedance output state and enables voltage clamping function to protect the internal circuit.

[0058] Furthermore, with the cooperation of the clamping protection module and the potential balancing module, the drive module can switch the operating mode of the drive circuit between the normal drive mode and the clamping protection mode according to the received external logic signal. In the clamping protection mode, the voltage output by the drive module can be limited to the voltage range between the low-level threshold signal and the high-level threshold signal of the external input, and the internal voltage is limited to this voltage range window.

[0059] Furthermore, the driving circuit provided in this application can directly select the clamping protection mode. When the external power supply voltage of the driving module exceeds the preset clamping voltage range, the external power supply voltage of the driving module is clamped, so that the output voltage of the driving module is limited to the vicinity of the low-level threshold signal or the vicinity of the high-level threshold signal. That is, clamping protection can be realized outside the driving circuit, thereby solving the problem that the clamping protection of the traditional driving output protection circuit only starts when the driving output voltage exceeds the preset clamping voltage.

[0060] Furthermore, the low-level threshold signal and high-level threshold signal of the external input in this application can be adjusted according to the actual situation, thereby solving the problem that the clamping voltage of the traditional drive output protection circuit cannot be adjusted according to the actual situation in the later stage, and improving the flexibility of the drive circuit.

[0061] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A drive circuit with clamping protection, characterized in that, include: The clamping protection module is used to receive external logic signals, external initial drive signals, and external high-level threshold signals and low-level threshold signals, and output complementary drive signals to subsequent circuits. The driving module is used to receive the complementary driving signal and output the final driving signal to the subsequent circuit according to different working modes. A potential balancing module acts on the output terminal of the drive module to make the output terminal of the drive module a high-impedance state; The drive circuit with clamping protection is configured as follows: When the logic signal is set to '1', the driving circuit with clamp protection operates in normal driving mode. When the logic signal is set to '0', the operating mode of the drive circuit with clamp protection is clamp protection mode.

2. The drive circuit with clamping protection according to claim 1, characterized in that, The clamping protection module includes: first to fourth inverters, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, first to sixth diodes, first to twelfth current sources, first to eighth NPN transistors, first to eighth PNP transistors, and a buffer, wherein... The input terminal of the first inverter is connected to the gate of the first PMOS transistor, the output terminal of the first inverter is connected to the gate of the first NMOS transistor, the source of the first PMOS transistor and the source of the first NMOS transistor are connected together and the source connection node is connected to the low-level threshold signal, the drain of the first PMOS transistor and the drain of the first NMOS transistor are connected together and the drain connection node is connected to the output terminal of the first diode, the first diode and the second diode are connected in series, and the input terminal of the second diode is connected to the base of the second NPN transistor. The input terminal of the second inverter is connected to the gate of the second PMOS transistor, the output terminal of the second inverter is connected to the gate of the second NMOS transistor, the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected together and the drain connection node is connected to the high-level threshold signal, the source of the second PMOS transistor and the source of the second NMOS transistor are connected together and the source connection node is connected to the input terminal of the third diode, the third diode and the fourth diode are connected in series, the output terminal of the fourth diode is connected to the base of the second PNP transistor, and the input terminals of the first inverter and the second inverter are also connected to the external logic signal; The input terminals of the first to sixth current sources and the collector of the fifth NPN transistor are all connected to the same node. The output terminal of the first current source is connected to the input terminal of the second diode, and the output terminal of the second current source is connected to the collector of the first NPN transistor. The emitter of the first NPN transistor, the cathode of the fifth diode, the emitter of the third PNP transistor, the collector of the fourth NPN transistor, and the collector of the fifth PNP transistor are all connected to the base of the sixth PNP transistor. The output terminal of the third current source is connected to the second NPN transistor. The collector of the NPN transistor is connected to the collector of the second NPN transistor, the emitter of the third NPN transistor is connected to the anode of the fifth diode, the output of the fourth current source is connected to the collector of the third PNP transistor, the output of the fifth current source is connected to the collector of the fourth PNP transistor, the output of the sixth current source is connected to the collector of the sixth NPN transistor, the emitter of the sixth NPN transistor and the collector of the sixth PNP transistor are connected, and the emitter of the fifth NPN transistor, the emitter of the fourth PNP transistor, the collector of the third NPN transistor, and the collector of the sixth PNP transistor are connected. The positive terminal of the transistor and the collector of the first PNP transistor are both connected to the base of the sixth NPN transistor. The output of the third inverter is connected to the base of the third PNP transistor. The base of the third NPN transistor is connected to the input of the third inverter and the external logic signal. The base of the fourth PNP transistor is connected to the input of the fourth inverter and the external logic signal. The base of the fourth NPN transistor is connected to the output of the fourth inverter. The input of the seventh current source is connected to the base of the second PNP transistor. The emitter of the PNP transistor is connected to the input terminal of the eighth current source, the cathode of the sixth diode is connected to the collector of the second PNP transistor, the emitter of the second PNP transistor is connected to the input terminal of the ninth current source, the emitter of the third NPN transistor is connected to the input terminal of the tenth current source, the emitter of the fourth NPN transistor is connected to the input terminal of the eleventh current source, the emitter of the sixth PNP transistor is connected to the input terminal of the twelfth current source, and the output terminals of the seventh to twelfth current sources and the emitter of the fifth PNP transistor are all connected to the same node. The collectors of the seventh NPN transistor and the eighth NPN transistor are connected and then connected to the input terminal of the sixth current source. The emitters of the seventh NPN transistor and the eighth NPN transistor are connected and then connected to the subsequent circuit. The base of the seventh NPN transistor is connected to the base of the sixth NPN transistor. The collectors of the seventh PNP transistor and the eighth PNP transistor are connected and then connected to the subsequent circuit. The base of the seventh PNP transistor is connected to the base of the sixth PNP transistor. The bases of the eighth NPN transistor and the eighth PNP transistor are connected and then connected to the output terminal of the buffer. The bases of the fifth NPN transistor and the fifth PNP transistor are connected and then connected to the output terminal of the buffer. The output terminal of the buffer is connected to the series node between the emitter and the collector of the sixth NPN transistor. The input terminal of the buffer is connected to the external initial drive signal, and the enable signal terminal of the buffer is connected to the external logic signal.

3. The drive circuit with clamping protection according to claim 2, characterized in that, The driving module includes: a ninth NPN transistor, a ninth PNP transistor, a thirteenth current source, and a fourteenth current source. The input terminal of the thirteenth current source is connected to the input terminal of the first current source; the output terminal of the thirteenth current source is connected to the collector of the ninth NPN transistor; the emitter of the ninth NPN transistor is connected to the collector of the ninth PNP transistor; the emitter of the ninth PNP transistor is connected to the input terminal of the fourteenth current source; and the output terminal of the fourteenth current source is the output terminal of the seventh current source. The collector of the seventh PNP transistor is connected to the collector of the eighth PNP transistor and then to the base of the ninth NPN transistor. The emitter of the seventh NPN transistor is connected to the emitter of the eighth NPN transistor and then to the base of the ninth PNP transistor. The series connection between the ninth NPN transistor and the ninth PNP transistor is the output terminal of the drive module. The output terminal of the drive module is connected to the series connection between the first NPN transistor and the first PNP transistor in the clamping protection module.

4. The drive circuit with clamping protection according to claim 3, characterized in that, The potential balancing module includes: the fifteenth to twenty-third current sources, the seventh diode, the eighth diode, the fifth inverter, the tenth to fifteenth PNP transistors, and the tenth to thirteenth NPN transistors. The input terminals of the fifteenth to nineteenth current sources are all connected to the same node. The output terminal of the fifteenth current source is connected to the collector of the twelfth NPN transistor. The base of the twelfth NPN transistor is connected to its collector. The emitter of the twelfth NPN transistor is connected to its collector. The emitter of the thirteenth NPN transistor is connected to the input terminal of the twenty-first current source. The sixteenth current source... The output terminal of the 17th current source is connected to the collector of the 12th PNP transistor, the emitter of the 12th PNP transistor is connected to the collector of the 13th PNP transistor, the emitter of the 13th PNP transistor is connected to the input terminal of the 20th current source, the output terminal of the 17th current source is connected to the collector of the 15th PNP transistor, the emitter of the 15th PNP transistor is connected to the collector of the 14th PNP transistor, the output terminal of the 18th current source is connected to the collector of the 11th PNP transistor, the emitter of the 11th PNP transistor is connected to the collector of the 11th NPN transistor, and the emitter of the 11th NPN transistor is connected to the input terminal of the 22nd current source. The nineteenth current source's output is connected to the collector of the tenth PNP transistor. The emitter of the tenth PNP transistor is connected to the collector of the tenth NPN transistor. The emitter of the tenth NPN transistor is connected to the input of the twenty-third current source. The emitters of the fourteenth and thirteenth PNP transistors are both connected to the base of the eleventh PNP transistor. The base of the fifteenth PNP transistor is connected to the base of the tenth PNP transistor, and the base of the fifteenth PNP transistor is connected to its emitter. The base of the eleventh NPN transistor is connected to the base of the tenth NPN transistor. The base of an NPN transistor is connected to the collector of an eleventh NPN transistor. The outputs of the twentieth to twenty-third current sources are all connected to the same node. A seventh diode is connected in series between the outputs of the nineteenth and fifteenth current sources. An eighth diode is connected in series between the outputs of the twentieth and twenty-third current sources. The input of the fifth inverter is connected to the base of the thirteenth NPN transistor and the external logic signal. The output of the fifth inverter is connected to the base of the twelfth PNP transistor. The series node between the tenth PNP transistor and the tenth NPN transistor is connected to the output of the drive module.

5. The drive circuit with clamping protection according to claim 1, characterized in that, When the operating mode is clamping protection mode, the output terminal of the drive module is in a high impedance state when the external power supply is not connected.

6. The drive circuit with clamping protection according to claim 1, characterized in that, When the operating mode is clamping protection mode, and the output terminal of the drive module is connected to an external power supply, and the voltage of the external power supply is greater than the external low-level threshold signal and less than the high-level threshold signal, the voltage of the output terminal of the drive module is the voltage of the external power supply.

7. The drive circuit with clamping protection according to claim 1, characterized in that, When the operating mode is clamping protection mode, when the output terminal of the drive module is connected to an external power supply, and the voltage of the external power supply is less than or equal to the external low-level threshold signal, the voltage of the output terminal of the drive module is the low-level threshold signal. When the operating mode is clamping protection mode, if the output terminal of the drive module is connected to an external power supply and the voltage of the external power supply is greater than or equal to the external high-level threshold signal, the voltage of the output terminal of the drive module is the high-level threshold signal.

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