TNPC converter single-phase power module and packaging method

Abstract

The invention discloses a TNPC converter single-phase power module and a packaging method, and belongs to the technical field of power device packaging, the TNPC converter single-phase power module is characterized in that conducting layers of two layers of DBC substrates are oppositely arranged, a SiC-MOS chip and a molybdenum block are installed between the conducting layers of the two layers of DBC substrates, an original source electrode of the SiC-MOS chip is divided into a source electrode and a Kelvin source electrode, and the source electrode and the molybdenum block are connected with each other. A drain electrode of the SiC-MOS chip is connected with the conductive layer of the DBC substrate, a source electrode molybdenum block is arranged on a source electrode, a grid electrode is connected with a grid electrode signal terminal, and a Kelvin source electrode is connected with a Kelvin source electrode signal terminal; the heat dissipation mode of the TNPC converter single-phase power module is the layout of the TNPC converter single-phase module packaged by double-sided heat dissipation, the two-dimensional conversion loop of the TNPC converter single-phase module is changed into the three-dimensional conversion loop, the mutual inductance cancellation principle is utilized, the parasitic inductance of all the conversion loops is reduced, the thermal resistance of the module can be reduced by an additional thermal path, and the power consumption of the TNPC converter single-phase power module is reduced. The maximum junction temperature of the chip can be effectively reduced, and the chip is not prone to thermal failure.

Description

Technical Field

[0001] This invention belongs to the field of power device packaging technology, specifically relating to a TNPC converter single-phase power module and its packaging method. Background Technology

[0002] Compared to two-level converters, T-type three-level (T-type neutral point clamped, TNPC) converters, while increasing complexity and chip costs, are highly attractive in fields such as aircraft propulsion, motor drives, and photovoltaic inverters due to their lower losses and lower harmonic output at high switching frequencies.

[0003] These low- and medium-voltage applications require converters to achieve high frequencies and high power densities, and TNPC converters are gradually replacing two-level converters, becoming the ideal choice. However, existing packaging methods cannot meet the demands for high frequencies and high power densities, and TNPC converters urgently need advanced packaging methods to support their application in these situations.

[0004] Existing technical solution 1: Utilize the wide variety of commercially available half-bridge (HB) modules and implement the entire TNPC converter through appropriate bus design. Solution 2: Integrate one phase of the TNPC converter (such as Infineon's Easy1B-TNPC module), and then use these three single-phase modules to implement the TNPC converter.

[0005] Existing technologies still have the following drawbacks: 1. Excessive parasitic inductance: Scheme 1 uses six HB modules to assemble a TNPC converter, which increases the size of the equipment and cannot be applied to high power density applications; furthermore, the corresponding commutation loop exists between different HB modules, resulting in a large parasitic inductance in the loop. Scheme 2 uses three TNPC single-phase modules to assemble a TNPC converter, which reduces the size of the equipment and shortens the commutation loop path. However, currently commercially available TNPC single-phase modules still use traditional wire-bonded packaging, and the parasitic inductance of the loop does not reach the ideal level (the parasitic inductance of the Infineon Easy1B-TNPC module is greater than 12nH). Excessive parasitic inductance will generate a large voltage overshoot under high switching frequencies and high di / dt, causing chip failure. 2. Poor heat dissipation performance: The modules used in Schemes 1 and 2 are both traditional single-sided heat dissipation methods. With the increase in power density, this heat dissipation method can no longer meet the application requirements. The most advanced silicon carbide half-bridge modules currently use double-sided heat dissipation, which greatly improves heat dissipation capacity compared to single-sided heat dissipation. Furthermore, the double-sided heat dissipation packaged modules eliminate the need for leads and use a metal molybdenum block for electrical connection, avoiding failure problems caused by leads and further improving the reliability of the modules. Summary of the Invention

[0006] The purpose of this invention is to overcome the problems of large parasitic inductance hindering high-frequency applications and large thermal resistance hindering high power density applications in traditional TNPC modules. This invention proposes a TNPC converter single-phase power module and its packaging method. The TNPC converter single-phase power module with double-sided heat dissipation packaging can reduce both the parasitic inductance and thermal resistance of the module at the same time.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a TNPC converter single-phase power module, comprising two DBC substrates with conductive layers disposed opposite to each other. A SiC-MOS chip and a molybdenum block are mounted between the conductive layers of the two DBC substrates. One side of the SiC-MOS chip is the drain, and the other side of the SiC-MOS chip is the source and gate. The original source of the SiC-MOS chip is divided into a source and a Kelvin source. The drain of the SiC-MOS chip is connected to the conductive layer of the DBC substrate. A source molybdenum block is disposed on the source of the SiC-MOS chip. The gate of the SiC-MOS chip is connected to a gate signal terminal, and the Kelvin source of the SiC-MOS chip is connected to a Kelvin source signal terminal. The heat dissipation method of the TNPC converter single-phase power module is double-sided heat dissipation.

[0008] Furthermore, the two-layer DBC substrate includes a first layer DBC substrate and a second layer DBC substrate; The first DBC substrate includes a first insulating ceramic layer, a first conductive layer is disposed on one side of the first insulating ceramic layer, and a first heat dissipation layer is disposed on the other side of the first insulating ceramic layer. The second DBC substrate includes a second insulating ceramic layer, a second conductive layer is disposed on one side of the second insulating ceramic layer, and a second heat dissipation layer is disposed on the other side of the second insulating ceramic layer.

[0009] Furthermore, both the first and second insulating ceramic layers are made of aluminum nitride ceramic.

[0010] Furthermore, the SiC-MOS chip includes a first chip, a second chip, a third chip, a fourth chip, a fifth chip, a sixth chip, a seventh chip, and an eighth chip; the first chip and the second chip constitute a first switch M1, the third chip and the fourth chip constitute a second switch M2, the fifth chip and the sixth chip constitute a third switch M3, and the seventh chip and the eighth chip constitute a fourth switch M4; The first conductive layer includes a first conductive region, a second conductive region, a third conductive region, and a fourth conductive region; the second conductive layer includes a fifth conductive region, a sixth conductive region, and a seventh conductive region. The drain of the first switch M1 is connected to the first conductive area, which is connected to the positive terminal of the DC power supply; the drain of the second switch M2 is connected to the second conductive area, which is connected to the ground terminal of the DC power supply; the third conductive area is connected to the negative terminal of the DC power supply; and the fourth conductive area is provided with a first conductive molybdenum block and a second conductive molybdenum block. The drain of the third switch M3 and the drain of the fourth switch M4 are connected to the fifth conductive area, which is connected to the AC power supply terminal. The source of the first switch M1 is connected to the fifth conductive region via the source molybdenum block; the source of the third chip is connected to the sixth conductive region via the source molybdenum block; the first conductive molybdenum block is connected to the sixth conductive region; the source of the fourth chip is connected to the seventh conductive region via the source molybdenum block; and the second conductive molybdenum block is connected to the seventh conductive region. The source of the third switch M3 is connected to the fourth conductive region via a source molybdenum block, and the source of the fourth switch M4 is connected to the third conductive region via a source molybdenum block.

[0011] Furthermore, the SiC-MOS of the third, fourth, fifth, and sixth chips is allowed to have a minimum withstand voltage of half that of the SiC-MOS of the first, second, seventh, and eighth chips.

[0012] Furthermore, the first, second, seventh, and eighth chips are SiC-MOS chips with a rated voltage of 1200V and a rated current of 120A, while the third, fourth, fifth, and sixth chips are SiC-MOS chips with a rated voltage of 650V and a rated current of 120A.

[0013] Furthermore, nano-silver solder paste is used as the solder during chip assembly.

[0014] Furthermore, the conductive layers of both DBC substrates are made of conductive copper.

[0015] Furthermore, the heat dissipation path of the SiC-MOS chip in the TNPC converter single-phase power module includes heat dissipation through a molybdenum block.

[0016] Secondly, the present invention provides a packaging method for a single-phase power module of a TNPC converter, comprising the following steps: dividing the original source of a SiC-MOS chip into a source and a Kelvin source; A source molybdenum block is installed on the source of the SiC-MOS chip, a Kelvin source signal terminal is connected to the Kelvin source of the SiC-MOS chip, and a gate signal terminal is connected to the gate of the SiC-MOS chip. The conductive layers of two DBC substrates are mounted opposite each other. A SiC-MOS chip and a molybdenum block are mounted between the conductive layers of the two DBC substrates. The drain of the SiC-MOS chip is connected to the conductive layer of the DBC substrate.

[0017] Compared with the prior art, the present invention has the following beneficial technical effects: This invention proposes a TNPC converter single-phase power module with a double-sided heat-dissipating package. This layout transforms the commutation circuit of the TNPC converter single-phase module from two-dimensional to three-dimensional, utilizing the mutual inductance cancellation principle to reduce the parasitic inductance of all commutation circuits. Simulation results show that the parasitic inductance of each commutation circuit is 6.45nH. Under high switching frequencies and large di / dt, the voltage overshoot is reduced by half compared to current commercial TNPC converter single-phase modules. Compared to single-sided heat dissipation, the double-sided heat-dissipating package of the module proposed in this invention provides an additional thermal path. Heat can be transferred through the molybdenum block connected to the source of the MOS chip to another DBC, instead of only being transferred to the DBC connected to the drain of the MOS chip. This additional thermal path reduces the module's thermal resistance. Under the same operating conditions and heat dissipation conditions, it effectively reduces the maximum junction temperature of the chip, making the chip less prone to thermal failure. Attached Figure Description

[0018] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of the invention in any way. Furthermore, the shapes and proportions of the components in the drawings are merely schematic to aid in understanding the invention and do not specifically limit the shapes and proportions of the components. In the drawings: Figure 1 This is a circuit topology diagram of the single-phase power module of the TNPC converter of the present invention.

[0019] Figure 2 This is a schematic diagram of the lower DBC substrate of the TNPC converter single-phase power module in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the upper DBC substrate of the single-phase power module of the TNPC converter in an embodiment of the present invention.

[0021] Figure 4 This is a front view of a common SiC-MOS chip.

[0022] Figure 5 This is a schematic diagram of the converter loop for a single-phase circuit topology of the TNPC converter of the present invention.

[0023] Figure 6 This is a schematic diagram of a converter circuit for a single-phase power module of the TNPC converter of the present invention.

[0024] Figure 7 This is a schematic diagram of another converter circuit for the single-phase power module of the TNPC converter of the present invention.

[0025] Figure 8 This is a schematic diagram of the heat flow path of the single-phase power module of the TNPC converter of the present invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0027] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only embodiments.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0029] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] Example 1 See Figure 2 , Figure 3 , Figure 4 , Figure 6 , Figure 7A TNPC converter single-phase power module includes two DBC substrates with conductive layers facing each other. A SiC-MOS chip and a molybdenum block are mounted between the conductive layers of the two DBC substrates. One side of the SiC-MOS chip is the drain, and the other side is the source and gate. The original source of the SiC-MOS chip is divided into a source and a Kelvin source. The drain of the SiC-MOS chip is connected to the conductive layer of the DBC substrate. A source molybdenum block is disposed on the source of the SiC-MOS chip. The gate of the SiC-MOS chip is connected to a gate signal terminal, and the Kelvin source of the SiC-MOS chip is connected to a Kelvin source signal terminal. The heat dissipation method of the TNPC converter single-phase power module is double-sided heat dissipation.

[0031] The TNPC converter single-phase power module adopts a double-layer DBC substrate and a double-sided heat dissipation structure, integrating SiC-MOS chips and a Kelvin source design, demonstrating significant advantages in performance, reliability, and system integration. Double-sided heat dissipation significantly improves heat dissipation efficiency through bidirectional heat conduction between the two DBC substrates. Traditional single-sided heat dissipation concentrates heat on one side, easily forming localized hotspots, while double-sided heat dissipation evenly distributes heat to both sides, effectively reducing chip junction temperature and extending device lifespan. Simultaneously, this structure adapts to the high-frequency, high-power-density characteristics of SiC-MOS chips, solving the thermal management challenges caused by their high power consumption per unit area, and ensuring stable operation of the module under high-temperature, high-load conditions. The combination of SiC-MOS chips and the Kelvin source design further optimizes electrical performance. The high electron mobility and low on-resistance of SiC material significantly reduce switching losses and greatly improve efficiency; while the Kelvin source, through independent signal terminals isolating the gate drive circuit and the main current path, eliminates the influence of parasitic inductance on the switching process, reduces voltage oscillations and EMI noise, and improves the consistency of switching speed and the current sharing characteristics of multi-chip parallel operation. The double-layer DBC substrate shortens the current path, reduces parasitic inductance, and enhances the electrical safety of the module. The molybdenum block, acting as an intermediate layer, alleviates thermal stress between the chip and the substrate, improving soldering reliability. At the system level, double-sided heat dissipation significantly reduces the size of the heat sink, supports natural cooling designs, and reduces system complexity and cost. The reduction in module thickness and the increase in power density drive the development of converters towards compactness and integration, making them suitable for applications with stringent requirements for size and efficiency.

[0032] The two-layer DBC substrate includes a first DBC substrate and a second DBC substrate. The first DBC substrate includes a first insulating ceramic layer, a first conductive layer disposed on one side of the first insulating ceramic layer, and a first heat dissipation layer disposed on the other side of the first insulating ceramic layer. The second DBC substrate includes a second insulating ceramic layer, a second conductive layer disposed on one side of the second insulating ceramic layer, and a second heat dissipation layer disposed on the other side of the second insulating ceramic layer. Both the first and second insulating ceramic layers are made of aluminum nitride ceramic.

[0033] The SiC-MOS chip includes a first chip, a second chip, a third chip, a fourth chip, a fifth chip, a sixth chip, a seventh chip, and an eighth chip. The first and second chips constitute a first switch M1, the third and fourth chips constitute a second switch M2, the fifth and sixth chips constitute a third switch M3, and the seventh and eighth chips constitute a fourth switch M4. The first conductive layer includes a first conductive region, a second conductive region, a third conductive region, and a fourth conductive region. The second conductive layer includes a fifth conductive region, a sixth conductive region, and a seventh conductive region. The drain of the first switch M1 is connected to the first conductive region, which is connected to the positive terminal of a DC power supply. The drain of the second switch M2 is connected to the second conductive region, which... The DC power supply grounding terminal is connected; the third conductive area is connected to the negative terminal of the DC power supply; the first and second conductive molybdenum blocks are disposed on the fourth conductive area; the drain of the third switch M3 and the drain of the fourth switch M4 are connected to the fifth conductive area, which is connected to the AC power supply terminal; the source of the first switch M1 is connected to the fifth conductive area via the source molybdenum block, the source of the third chip is connected to the sixth conductive area via the source molybdenum block, the first conductive molybdenum block is connected to the sixth conductive area, the source of the fourth chip is connected to the seventh conductive area via the source molybdenum block, and the second conductive molybdenum block is connected to the seventh conductive area; the source of the third switch M3 is connected to the fourth conductive area via the source molybdenum block, and the source of the fourth switch M4 is connected to the third conductive area via the source molybdenum block.

[0034] The minimum allowable withstand voltage of the SiC-MOS chips in the third, fourth, fifth, and sixth chips is half that of the SiC-MOS chips in the first, second, seventh, and eighth chips. Optionally, the first, second, seventh, and eighth chips are SiC-MOS chips with a rated voltage of 1200V and a rated current of 120A, while the third, fourth, fifth, and sixth chips are SiC-MOS chips with a rated voltage of 650V and a rated current of 120A.

[0035] Nano-silver solder paste is used as the solder during chip assembly. The conductive layers of both DBC substrates are made of conductive copper. The heat dissipation path of the SiC-MOS chip in the TNPC converter single-phase power module includes heat dissipation through a molybdenum block.

[0036] The dual-layer DBC substrate structure significantly improves the module's electrical isolation and thermal conductivity efficiency. The aluminum nitride ceramic layers (first and second insulating ceramic layers) combine high thermal conductivity with high insulation strength, ensuring safe isolation between the conductive layers (copper material) and providing a bidirectional heat dissipation channel for the chip: the first and second heat dissipation layers dissipate heat through external heat sinks, while the molybdenum block between the conductive layer and the chip further optimizes the heat flow path, forming a multi-level heat dissipation structure of "chip-molybdenum block-conductive layer-heat dissipation layer," effectively reducing the chip junction temperature and improving stability under high-frequency switching. The voltage-dividing SiC-MOS chip configuration precisely matches the voltage stress requirements of the TNPC topology. Chips one, two, seven, and eight in the module are designed with a 1200V withstand voltage, directly bearing the full voltage of the DC bus; chips three to six are designed with a 650V withstand voltage, only needing to withstand half the voltage. This differentiated configuration avoids the redundant design of fully withstand voltage chips, reducing material costs while ensuring system safety. Meanwhile, 650V chips typically have lower on-resistance, working in conjunction with 1200V chips to optimize overall efficiency and loss distribution. The application of nano-silver solder paste further enhances the reliability of chip connections. Compared to traditional solders, nano-silver solder paste has a higher melting point, lower contact resistance, and stronger resistance to thermal fatigue, effectively alleviating mechanical stress caused by the difference in thermal expansion coefficients between the chip and the DBC substrate, preventing solder layer cracking, and extending module lifespan. The high conductivity of the conductive copper layer reduces power loss in the conductive layer, improving system energy efficiency. This embodiment achieves a balance between high power density, high reliability, and low cost through synergistic optimization of structure, materials, and processes, making it suitable for scenarios with stringent requirements for efficiency and size, such as electric vehicles and photovoltaic inverters.

[0037] Example 2 A packaging method for a single-phase power module of a TNPC converter includes the following steps: The original source of the SiC-MOS chip is divided into the source and the Kelvin source; A source molybdenum block is installed on the source of the SiC-MOS chip, a Kelvin source signal terminal is connected to the Kelvin source of the SiC-MOS chip, and a gate signal terminal is connected to the gate of the SiC-MOS chip. The conductive layers of two DBC substrates are mounted opposite each other. A SiC-MOS chip and a molybdenum block are mounted between the conductive layers of the two DBC substrates. The drain of the SiC-MOS chip is connected to the conductive layer of the DBC substrate.

[0038] This embodiment divides the original source of the SiC-MOS chip into an independent source and a Kelvin source, which are then connected to the main current path and the gate drive circuit, respectively. This design completely isolates the main current parasitic inductance from interfering with the gate signal, eliminating interference during switching. di / dtThe gate voltage oscillations caused by this design result in more stable switching speeds and lower losses. Simultaneously, the independent layout of the Kelvin source and gate signal terminals simplifies the high-frequency signal transmission path, reduces electromagnetic interference (EMI), and improves current sharing consistency when multiple chips are connected in parallel. Two DBC substrate conductive layers are mounted opposite each other, forming a "sandwich" structure, sandwiching the SiC-MOS chip and the molybdenum block in between. The high thermal conductivity and high insulation strength of the aluminum nitride ceramic substrate (DBC) combine to achieve efficient bidirectional heat conduction from the chip to the heat dissipation layers on both sides, while ensuring electrical isolation between the high-voltage DC side and the AC side. The partitioned design of the conductive layer (copper) further shortens the current path, reduces parasitic inductance, and improves the module's safety under high-frequency switching. The source molybdenum block, as a transition layer between the chip and the conductive layer, utilizes its coefficient of thermal expansion, which is close to that of SiC, to effectively alleviate the mechanical stress generated by thermal cycling and prevent solder layer fatigue failure. At the same time, the high thermal and electrical conductivity of the molybdenum block optimizes the heat flow path from the chip to the conductive layer. Combined with the double-sided heat dissipation structure, this significantly reduces the chip junction temperature and extends device lifespan. This packaging method is compatible with standard DBC substrate processes and chip mounting technologies, requiring no special equipment or materials and reducing manufacturing costs. The compact stack-up design reduces module size, supports high power density integration, and the double-sided heat dissipation structure reduces the need for external heat sinks, further improving system energy efficiency and reliability.

[0039] Example 3 like Figure 1 As shown, this embodiment proposes a 1200V / 240A TNPC converter single-phase power module. M1, M2, M3, and M4 refer to different switching positions. Each switching position uses two silicon carbide metal oxide field-effect transistors (SiC-MOS), and the gate control signals of SiC-MOS transistors in the same switching position are identical. Based on circuit characteristics, the minimum allowable withstand voltage of the SiC-MOS transistors in positions M2 / M3 can be half that of those in positions M1 / M4. Therefore, commercially available 1200V / 120A SiC-MOS chips are selected for positions M1 / M4, while commercially available 650V / 120A SiC-MOS chips are selected for positions M2 / M3. Figure 1 K1~K4 / KS1~KS4 in the diagram represent the Kelvin connection of the corresponding SiC-MOS chip. In subsequent modules, for example, K1 is the gate signal terminal, KS1 is the Kelvin source signal terminal, and so on. Further details will not be provided.

[0040] The TNPC converter single-phase power module proposed in this embodiment has a size of 45.5mm × 43mm. Figure 2This is a schematic diagram of the lower direct-bonding copper (DBC) substrate of the proposed TNPC converter single-phase power module. Figure 3 This is a schematic diagram of the upper DBC substrate of the proposed TNPC converter single-phase power module. The DBC substrate is a common material in power modules. Similar to a double-layer PCB structure, it is a three-layer structure with an insulating ceramic layer in the middle, copper plating on both sides (one side as a conductive layer and the other as a heat dissipation layer). It should be noted that for SiC-MOS chips, the back side is the drain, and the front side contains the source and gate. A portion of the source electrode will be separated into Kelvin source electrodes. Figure 4 This demonstrates the front side of a common SiC-MOS chip. In this double-sided heatsink package, a molybdenum block replaces the traditional bonding wires for source electrical connection. Furthermore, Kelvin connections help avoid coupling between the power loop and the gate drive loop caused by common-source inductance; Kelvin connections are necessary in high-frequency applications. To improve thermal performance, materials with high thermal conductivity are selected as much as possible in the module; for example, aluminum nitride ceramic is used for the ceramic layer of the DBC substrate, and nano-silver solder paste is used during soldering. According to... Figure 1 The circuit connections shown are soldered accordingly to realize one phase of the TNPC converter.

[0041] In a single-phase TNPC converter, there are three output states: P state (output + voltage), N state (output - voltage), and O state (output 0 voltage). The transition between P and N states must be done through the O state. Figure 5 Four possible commutation paths in a single phase are shown. Due to the bidirectional conduction capability of the MOS and the symmetry of the TNPC circuit, its commutation loop can be simplified to two types, and their corresponding commutation paths on the proposed module are as follows: Figure 6 , Figure 7 As shown. The heat dissipation path of the SiC-MOS chip is as follows. Figure 8 As shown.

[0042] Many embodiments and applications beyond the examples provided will be apparent to those skilled in the art upon reading the foregoing description. Therefore, the scope of this teaching should not be determined by reference to the foregoing description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed inventive subject matter.

[0043] The above content provides a further detailed description of the present invention. It should not be construed that the specific embodiments of the present invention are limited to this. For those skilled in the art, several simple deductions or substitutions can be made without departing from the concept of the present invention, and all such deductions or substitutions should be considered to fall within the defined protection scope of the present invention.

Claims

1. A TNPC converter single-phase power module, characterized in that, The device comprises two DBC substrates with their conductive layers facing each other. A SiC-MOS chip and a molybdenum block are mounted between the conductive layers of the two DBC substrates. One side of the SiC-MOS chip is the drain, and the other side is the source and gate. The original source of the SiC-MOS chip is divided into a source and a Kelvin source. The drain of the SiC-MOS chip is connected to the conductive layer of the DBC substrate. A source molybdenum block is disposed on the source of the SiC-MOS chip. The gate of the SiC-MOS chip is connected to a gate signal terminal, and the Kelvin source of the SiC-MOS chip is connected to a Kelvin source signal terminal. The heat dissipation method of the TNPC converter single-phase power module is double-sided heat dissipation.

2. A TNPC converter single-phase power module according to claim 1, characterized in that, The two-layer DBC substrate includes a first layer DBC substrate and a second layer DBC substrate; The first DBC substrate includes a first insulating ceramic layer, a first conductive layer is disposed on one side of the first insulating ceramic layer, and a first heat dissipation layer is disposed on the other side of the first insulating ceramic layer; The second DBC substrate includes a second insulating ceramic layer, a second conductive layer is disposed on one side of the second insulating ceramic layer, and a second heat dissipation layer is disposed on the other side of the second insulating ceramic layer.

3. A TNPC converter single-phase power module according to claim 2, characterized in that, Both the first insulating ceramic layer and the second insulating ceramic layer are made of aluminum nitride ceramic.

4. A TNPC converter single-phase power module according to claim 2, characterized in that, The SiC-MOS chip includes a first chip, a second chip, a third chip, a fourth chip, a fifth chip, a sixth chip, a seventh chip, and an eighth chip; the first chip and the second chip constitute a first switch M1, the third chip and the fourth chip constitute a second switch M2, the fifth chip and the sixth chip constitute a third switch M3, and the seventh chip and the eighth chip constitute a fourth switch M4. The first conductive layer includes a first conductive region, a second conductive region, a third conductive region, and a fourth conductive region; the second conductive layer includes a fifth conductive region, a sixth conductive region, and a seventh conductive region. The drain of the first switch M1 is connected to the first conductive area, which is connected to the positive terminal of the DC power supply; the drain of the second switch M2 is connected to the second conductive area, which is connected to the ground terminal of the DC power supply; the third conductive area is connected to the negative terminal of the DC power supply; and the fourth conductive area is provided with a first conductive molybdenum block and a second conductive molybdenum block. The drain of the third switch M3 and the drain of the fourth switch M4 are connected to the fifth conductive area, which is connected to the AC power supply terminal. The source of the first switch M1 is connected to the fifth conductive region via a source molybdenum block; the source of the third chip is connected to the sixth conductive region via a source molybdenum block; the first conductive molybdenum block is connected to the sixth conductive region; the source of the fourth chip is connected to the seventh conductive region via a source molybdenum block; and the second conductive molybdenum block is connected to the seventh conductive region. The source of the third switch M3 is connected to the fourth conductive region via a source molybdenum block, and the source of the fourth switch M4 is connected to the third conductive region via a source molybdenum block.

5. A TNPC converter single-phase power module according to claim 2, characterized in that, The minimum allowable withstand voltage of the SiC-MOS chips in the third, fourth, fifth, and sixth chips is half that of the SiC-MOS chips in the first, second, seventh, and eighth chips.

6. A TNPC converter single-phase power module according to claim 2, characterized in that, The first, second, seventh, and eighth chips are SiC-MOS chips with a rated voltage of 1200V and a rated current of 120A, while the third, fourth, fifth, and sixth chips are SiC-MOS chips with a rated voltage of 650V and a rated current of 120A.

7. A TNPC converter single-phase power module according to claim 1, characterized in that, The chip is soldered with nano-silver solder paste during installation.

8. A TNPC converter single-phase power module according to claim 1, characterized in that, The conductive layers of both DBC substrates are made of conductive copper.

9. A TNPC converter single-phase power module according to claim 1, characterized in that, The heat dissipation path of the SiC-MOS chip in the single-phase power module of the TNPC converter includes heat dissipation through a molybdenum block.

10. A packaging method for a single-phase power module of a TNPC converter, characterized in that, Includes the following steps: The original source of the SiC-MOS chip is divided into the source and the Kelvin source; A source molybdenum block is installed on the source of the SiC-MOS chip, a Kelvin source signal terminal is connected to the Kelvin source of the SiC-MOS chip, and a gate signal terminal is connected to the gate of the SiC-MOS chip. The conductive layers of two DBC substrates are mounted opposite each other. A SiC-MOS chip and a molybdenum block are mounted between the conductive layers of the two DBC substrates. The drain of the SiC-MOS chip is connected to the conductive layer of the DBC substrate.

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