Switch topological structure and control method for alternating current solid state power controller

Abstract

The invention relates to a switch topological structure for an alternating current solid state power controller and a control method, the topological structure comprises a main branch and a current limiting branch, and the main branch and the current limiting branch form a double-branch cooperative current limiting switch topological structure; the main branch comprises a first SiC-MOSFET and a second SiC-MOSFET, the first SiC-MOSFET and the second SiC-MOSFET adopt an anti-series MOSFET switch configuration, and on-off of the main branch is completed through driving control of a signal Q1 and a signal Q2; and the current limiting branch comprises a third SiC-MOSFET and a fourth SiC-MOSFET, the third SiC-MOSFET and the fourth SiC-MOSFET adopt an anti-series MOSFET switch configuration and are driven and controlled by a control signal Q34, so that a current limiting protection function is realized. According to the invention, a sequential on-off sequential control strategy is provided, high-precision zero-crossing detection is not needed, and natural zero-voltage switching-on and zero-current switching-off are realized.

Description

Technical Field

[0001] This invention relates to the field of power distribution for unmanned devices, specifically a switching topology and control method for an AC solid-state power controller. Background Technology

[0002] With the rapid development of unmanned devices, their power distribution systems face the following technical bottlenecks:

[0003] 1. System stability challenges

[0004] The integration of new energy sources triggers bidirectional power flow and pulse load surges, leading to voltage fluctuations and energy feedback issues.

[0005] The increased complexity of power electronic conversion processes makes traditional electromagnetic protection devices bulky and difficult to meet the requirements for lightweight integration.

[0006] 2. Inherent defects of traditional mechanical circuit breakers

[0007] Insufficient response speed: Action delay > 20ms, unable to suppress microsecond-level surge current;

[0008] Rigid protection strategy: lacking real-time monitoring and adaptive mechanisms, it can only permanently cut off the power supply when encountering high instantaneous current;

[0009] Lifespan and reliability limitations: The mechanical structure results in a limited operational lifespan, making it unsuitable for high-frequency fault isolation scenarios at the kHz level (such as the power distribution system of unmanned aerial vehicles).

[0010] 3. Technical bottlenecks of solid-state power controllers (SSPC)

[0011] Energy efficiency loss problem: Full-wave bridge / anti-parallel configuration requires series diodes, which increases the on-state voltage drop and causes significant conduction losses;

[0012] High hardware complexity: The switching action relies on voltage / current zero-crossing detection, which requires strict synchronization accuracy and increases the difficulty of control;

[0013] Risk of false triggering: The "one-size-fits-all" current limiting strategy is difficult to distinguish between fault current and capacitive load inrush current, resulting in a high false triggering rate and making it difficult to adapt to capacitive load startup scenarios.

[0014] In summary, existing protection solutions have systemic shortcomings in terms of dynamic response speed, energy efficiency optimization, intelligent protection strategies, and spatial integration, which urgently need to be addressed. Summary of the Invention

[0015] To address the aforementioned shortcomings of existing technologies, this invention provides a switching topology and control method for an AC solid-state power controller. It employs a wide-bandgap semiconductor MOSFET to construct an anti-series switch configuration, achieving zero-voltage turn-on (ZVS) and zero-current turn-off (ZCS), reducing the on-state voltage drop to the 2V level (compared to >3V in traditional SSPCs due to series diodes), thus overcoming synchronization dependence limitations. A sequential on / off timing control strategy is proposed, eliminating the need for high-precision zero-crossing detection and achieving natural zero-voltage turn-on and zero-current turn-off. Furthermore, a dual-branch collaborative inverse-time current limiting protection strategy is proposed, adaptively distinguishing between fault current and capacitive load inrush current, reducing false triggering rate.

[0016] A switching topology for an AC solid-state power controller, characterized in that it includes a main branch and a current-limiting branch, wherein the main branch and the current-limiting branch constitute a dual-branch cooperative current-limiting switching topology.

[0017] The main branch includes a first SiC-MOSFET and a second SiC-MOSFET. The first SiC-MOSFET and the second SiC-MOSFET adopt an anti-series MOSFET switching configuration, and the main branch is turned on and off by driving and controlling the signals Q1 and Q2.

[0018] The current-limiting branch includes a third SiC-MOSFET and a fourth SiC-MOSFET. The third SiC-MOSFET and the fourth SiC-MOSFET adopt an anti-series MOSFET switching configuration and are driven and controlled by the control signal Q_34 to achieve the current-limiting protection function.

[0019] Furthermore, the anti-series MOSFET switch configuration in the main branch is specifically composed of a first SiC-MOSFET and a second SiC-MOSFET connected in reverse series, with the sources of the first and second SiC-MOSFETs connected to ground, and their drains connected to the AC power supply and the load, respectively; the anti-series MOSFET switch configuration in the current-limiting branch is specifically composed of a third SiC-MOSFET and a fourth SiC-MOSFET connected in reverse series, with the sources of the third and fourth SiC-MOSFETs connected to ground, and their drains connected to the AC power supply and the load, respectively.

[0020] Furthermore, in the anti-series MOSFET switch configuration of the main branch, the body diodes of the first SiC-MOSFET and the second SiC-MOSFET are connected in reverse parallel to form a parasitic diode back-to-back connection structure; in the anti-series MOSFET switch configuration of the current-limiting branch, the body diodes of the third SiC-MOSFET and the fourth SiC-MOSFET are connected in reverse parallel to form a parasitic diode back-to-back connection structure.

[0021] Furthermore, the anti-series MOSFET switch configuration of the current-limiting branch is connected in series with a current-limiting resistor RL.

[0022] Furthermore, it also includes a driving circuit; in the driving circuit, the first SiC-MOSFET and the second SiC-MOSFET of the main branch are independently driven by control signals Q_1 and Q_2 respectively, and the on-off timing of the first SiC-MOSFET and the second SiC-MOSFET is independently controlled by a sequential on-off timing control strategy.

[0023] Furthermore, in the driving circuit, the current limiting branch shares two driving paths. The control signal Q_34 drives the third and fourth SiC-MOSFETs in the current limiting branch to turn on and off quickly, while the control signal Q_SLOW enables the third and fourth SiC-MOSFETs to be turned off slowly by short-circuiting.

[0024] Furthermore, the on-state voltage drop of the anti-series MOSFET configuration is ≤2V, and the operating frequency range is 1kHz~100kHz.

[0025] Furthermore, the switching response time of the current-limiting branch is ≤10μs, which can support the accurate differentiation between impulsive load current and short-circuit fault.

[0026] A control method for an AC solid-state power controller as described above includes the following steps:

[0027] Step 1: Sequential On / Off Timing Control

[0028] 1.1 During the positive half-cycle, the second SiC-MOSFET is turned on first, and the current flows through the channel of the second SiC-MOSFET and the body diode of the first SiC-MOSFET;

[0029] 1.2 During the negative half-cycle, the first SiC-MOSFET is turned on, and the current naturally commutates to the channel of the first SiC-MOSFET, achieving zero-voltage turn-on;

[0030] 1.3 During the turn-off cycle, the second SiC-MOSFET is turned off during the positive half-cycle, and the current is commutated to the body diode of the first SiC-MOSFET; during the negative half-cycle, the body diode of the first SiC-MOSFET is turned off, achieving zero-current turn-off.

[0031] Step 2: Current limiting protection control strategy

[0032] 2.1 Real-time monitoring of the line load current I. When I exceeds the threshold Ip but is below the short-circuit protection current level, the first and second SiC-MOSFETs of the main branch are turned off, utilizing the current-limiting resistor R of the current-limiting branch. LImplement flow control protection;

[0033] 2.2 If the current I continuously exceeds Ip, the current limiting branch switches to current limiting mode within microseconds. The current limiting mode limits the overload current I to a safe value. As the load current increases, the protection time automatically decreases, triggering the inverse time current limiting protection strategy.

[0034] 2.3 During the current limiting process, if the circuit is further determined to be short-circuit fault, the short-circuit signal Q_SLOW becomes effective, and the third and fourth SiC-MOSFETs in the current limiting branch are slowly turned off to achieve short-circuit protection.

[0035] Step 3: Fault Type Identification

[0036] 3.1 Based on the time-frequency characteristics of current and the load voltage threshold, distinguish between short-circuit faults and capacitive impulse loads;

[0037] 3.2 In the event of a short-circuit fault, the main branch and the current-limiting branch are disconnected; under capacitive impact load, it enters current-limiting mode until normal operation is restored. Furthermore,

[0038] Furthermore, the inverse time-limited rate limiting protection strategy is as follows:

[0039] ;

[0040] Where I is the circuit output current; I p The operating value is the protection current; k is a constant with the dimension of time; r is a constant, usually ranging from 0 to 2; t p This is a defined time constant.

[0041] Compared to power distribution systems based on traditional mechanical circuit breakers, this invention simplifies the zero-crossing detection circuit, reduces hardware complexity, lowers conduction voltage drop, reduces switching losses, improves the success rate of electrical load fault isolation for unmanned devices, and reduces the probability of false triggering by capacitive and impact loads, providing key technical support for building a highly reliable intelligent power distribution system. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the anti-series configuration of the main branch in an embodiment of the present invention.

[0043] Figure 2 This is a schematic diagram of the anti-series configuration of the current-limiting branch in an embodiment of the present invention.

[0044] Figure 3 This is a schematic diagram of the dual-branch cooperative current limiting switch topology according to an embodiment of the present invention.

[0045] Figure 4 This is a schematic diagram of the current flow during the zero-voltage start-up process in an embodiment of the present invention.

[0046] Figure 5 This is a schematic diagram of the current flow direction during the zero-current turn-off process according to an embodiment of the present invention.

[0047] Figure 6 This is a flowchart of the current limiting protection control strategy according to an embodiment of the present invention. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] Please see Figure 1-3 This invention provides a switching topology for an AC solid-state power controller for an unmanned aerial vehicle, comprising: a main branch 10 and a current-limiting branch 20, wherein the main branch 10 and the current-limiting branch 20 are connected in parallel to form a dual-branch cooperative current-limiting switch topology 30.

[0050] The main branch 10 includes two SiC-MOSFETs (MOS1 and MOS2). The two SiC-MOSFETs adopt an anti-series MOSFET switching configuration and are driven and controlled by signals Q1 and Q2 to complete the on / off of the main branch.

[0051] The current limiting branch 20 includes two SiC-MOSFETs (MOS3 and MOS4). The two SiC-MOSFETs adopt an anti-series MOSFET switching configuration and are driven and controlled by the control signal Q_34 to achieve the current limiting protection function.

[0052] The anti-series MOSFET switch configuration in the main branch 10 is specifically composed of two SiC-MOSFETs (MOS1, MOS2) connected in reverse series. The sources of the two SiC-MOSFETs are connected to ground, and their drains are connected to the AC power supply and the load, respectively. The anti-series MOSFET switch configuration in the current-limiting branch 20 is specifically composed of two SiC-MOSFETs (MOS3, MOS4) connected in reverse series. The sources of the two SiC-MOSFETs are connected to ground, and their drains are connected to the AC power supply and the load, respectively.

[0053] In the anti-series MOSFET switch configuration of the main branch 10, the body diode (D1) of MOS1 and the body diode (D2) of MOS2 are connected in reverse parallel, forming a parasitic diode back-to-back connection structure to ensure no leakage current when turned off. In the anti-series MOSFET switch configuration of the current limiting branch 20, the body diode (D3) of MOS3 and the body diode (D4) of MOS4 are connected in reverse parallel, forming a parasitic diode back-to-back connection structure to ensure no leakage current when turned off.

[0054] The current-limiting branch 20 has an anti-series MOSFET switch configuration connected in series with a current-limiting resistor RL.

[0055] The switching topology also includes a driving circuit; in the driving circuit, MOS1 and MOS2 of the main branch 10 are driven independently by control signals Q_1 and Q_2 respectively, and the on / off timing of MOS1 and MOS2 is independently controlled by a sequential on / off timing control strategy.

[0056] In the driving circuit, the current limiting branch 20 uses two driving signals. The control signal Q_34 drives the MOS3 and MOS4 in the current limiting branch 20 to turn on and off quickly, while the control signal Q_SLOW enables the short-circuit "slow turn-off" of MOS3 and MOS4.

[0057] The on-state voltage drop of the anti-series MOSFET configuration is ≤2V, and the operating frequency range is 1kHz~100kHz.

[0058] The switching response time of the current limiting branch 20 is ≤10μs, which can support the accurate differentiation between impulsive load current and short-circuit fault.

[0059] This invention also provides a control method for the AC solid-state power controller as described above, comprising the following steps:

[0060] Step 1: Sequential On / Off Timing Control

[0061] 1.1 During the positive half-cycle, the lower MOSFET 2 is turned on first, and the current flows through the channel of MOSFET 2 and the body diode (D1) of MOSFET 1.

[0062] 1.2 During the negative half-cycle, the upper MOSFET 1 is turned on, and the current naturally commutates to the MOSFET 1 channel, achieving zero-voltage turn-on (ZVS).

[0063] 1.3 During turn-off, MOS2 is turned off during the positive half-cycle, and the current is commutated to D1; MOS1 is turned off during the negative half-cycle, achieving zero-current turn-off (ZCS).

[0064] In the anti-series switch configuration, a control strategy of "the upper and lower transistors conducting in a certain sequence" is adopted, such as the direction of the current flow during the switching process. Figure 4 As shown:

[0065] During the positive half-cycle, the lower MOSFET 2 is turned on first, and the current flows through the channel of MOSFET 2 and the body diode of MOSFET 1. During the negative half-cycle, the upper MOSFET MOSFET 1 is turned on, and the current naturally commutates to the channel of MOSFET 1, achieving zero-voltage turn-on.

[0066] The control strategy of "turning on the upper and lower tubes in a certain sequence" has the following current flow direction during the turn-off process: Figure 5 As shown.

[0067] During the positive half-cycle, the lower transistor MOS2 is turned off, and the current is commutated to the body diode of MOS1; during the negative half-cycle, the upper transistor MOS1 is turned off, achieving zero-current turn-off.

[0068] This control strategy avoids simultaneous transmission of drive signals for the two MOSFETs in an anti-series structure. Instead, the signals are integrated with the positive and negative half-cycles of the AC power supply, controlling the MOSFETs' on / off states in a specific sequence. The power transistors naturally turn on at zero crossing, ensuring zero-crossing accuracy. The high accuracy is achieved by integrating the MOSFETs with the positive and negative half-cycles of the AC power supply during turn-on and turn-off. Only a turn-on signal needs to be sent to the corresponding MOSFET within half a cycle. Compared to simultaneous on / off of both transistors, this approach reduces the stringent requirements for zero-crossing detection, thus lowering control difficulty and circuit complexity. Furthermore, it completely suppresses du / dt and di / dt during turn-on and turn-off, effectively reducing interference in the circuit and improving system stability and reliability.

[0069] In step 1, the on / off signal only needs to be sent to the corresponding MOSFET within half a power cycle. It has high zero-crossing accuracy, drive signal delay ≤ 100ns, turn-on delay time ≤ half a power cycle, and turn-off delay time ≤ half a power cycle.

[0070] Step 2: Current limiting protection control strategy

[0071] Assuming the overcurrent ratio remains constant when an overcurrent occurs, meaning the load current does not change over time, the inverse-time current limiting protection mechanism is as follows: Figure 6 As shown.

[0072] 2.1 Real-time monitoring of the line load current I. When I exceeds the threshold Ip but is below the short-circuit protection current level, the main branch MOS1 and MOS2 are turned off, and the current-limiting branch MOS3 and MOS4, i.e., the current-limiting resistor R, are used. L Implement flow control protection;

[0073] 2.2 If the current I continuously exceeds Ip, the current limiting branch (20) switches to current limiting mode within microseconds. The current limiting mode limits the overload current I to a safe value. As the load current increases, the protection time automatically decreases, triggering the inverse time current limiting protection strategy;

[0074] 2.3 During the current limiting process, if the circuit is further determined to be short-circuit fault, the short-circuit signal Q_SLOW becomes effective, and the current limiting branch MOS3 and MOS4 are slowly turned off to achieve short-circuit protection.

[0075] When a short circuit fault occurs in the circuit, or when the circuit is turned on or subjected to a sudden impact load, the rapidly rising current in the line exceeds the set threshold. The dual-branch coordinated inverse time current limiting protection strategy can achieve current limiting protection.

[0076] Current-limiting protection effectively prevents equipment damage caused by overload, while ensuring rapid system response under abnormal conditions and avoiding prolonged fault states. The inverse-time characteristic means that the protection action time is inversely proportional to the current magnitude; the larger the current, the shorter the protection action time, thereby improving system safety and stability. Furthermore, inverse-time overcurrent protection has the advantage of adapting to different load characteristics, providing consistent protection under various operating conditions, further enhancing the overall performance and service life of the SSPC.

[0077] The mathematical model for the inverse time-limited current limiting protection strategy is as follows:

[0078] ;

[0079] Where I is the circuit output current; I p The operating value is the protection current; k is a constant with the dimension of time; r is a constant, usually ranging from 0 to 2; t p This is a defined time constant.

[0080] Among them, the time-limited current-limiting protection strategy parameters k=0.1s and r=1.5 are suitable for the capacitive load startup scenario of unmanned aerial vehicles.

[0081] The mathematical model of inverse-time overcurrent protection shows that the inverse-time overcurrent protection time t changes with the output current in the circuit. When I / I p When I / I < 1, t < 0, and the inverse time protection does not operate; when I / I p When I / I = 1, t = ∞, and the inverse time protection does not operate; when I / I p When the current input value is greater than 1, the inverse time protection starts to work. As the current input value in the circuit increases, the protection time t becomes smaller.

[0082] In the inverse-time overcurrent protection strategy, if the current overload multiple M is between 3.5 and 6, the circuit breaker will trip with a delay; if it is greater than 6, the circuit breaker will trip instantly; otherwise, the circuit breaker will not trip.

[0083] Step 3: Fault Type Identification

[0084] 3.1 Based on the time-frequency characteristics of current (such as the rate of rise) and the load voltage threshold, distinguish between short-circuit faults and capacitive impact loads;

[0085] 3.2 In case of a short circuit fault, disconnect the main branch (10) and the current-limiting branch (20); in case of capacitive impact load, enter the current-limiting mode until the normal state is restored.

[0086] This invention reduces the dependence on zero-crossing detection accuracy through a time-division staggered driving strategy, suppresses transient stress in switching, and achieves efficient and low-loss switching action. Combined with a dual-branch collaborative current limiting control strategy, it accurately distinguishes between impact loads and short-circuit faults, improving system reliability and scenario adaptability.

[0087] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A switching topology for an AC solid-state power controller, characterized in that: It includes a main branch (10) and a current-limiting branch (20), wherein the main branch (10) and the current-limiting branch (20) constitute a dual-branch cooperative current-limiting switch topology (30). The main branch (10) includes a first SiC-MOSFET (MOS1) and a second SiC-MOSFET (MOS2). The first SiC-MOSFET (MOS1) and the second SiC-MOSFET (MOS2) adopt an anti-series MOSFET switching configuration, and the main branch is turned on and off by driving and controlling the signals Q1 and Q2. The current limiting branch (20) includes a third SiC-MOSFET (MOS3) and a fourth SiC-MOSFET (MOS4). The third SiC-MOSFET (MOS3) and the fourth SiC-MOSFET (MOS4) adopt an anti-series MOSFET switching configuration and are driven and controlled by the control signal Q_34 to realize the current limiting protection function.

2. The switching topology for an AC solid-state power controller as described in claim 1, characterized in that: The anti-series MOSFET switch configuration in the main branch (10) is specifically composed of a first SiC-MOSFET (MOS1) and a second SiC-MOSFET (MOS2) connected in reverse series. The sources of the first SiC-MOSFET (MOS1) and the second SiC-MOSFET (MOS2) are connected to ground, and the drains are connected to the AC power supply (AC) and the load, respectively. The anti-series MOSFET switch configuration in the current limiting branch (20) is specifically composed of a third SiC-MOSFET (MOS3) and a fourth SiC-MOSFET (MOS4) connected in reverse series. The sources of the third SiC-MOSFET (MOS3) and the fourth SiC-MOSFET (MOS4) are connected to ground, and the drains are connected to the AC power supply (AC) and the load, respectively.

3. The switching topology for an AC solid-state power controller as described in claim 1, characterized in that: In the anti-series MOSFET switch configuration of the main branch (10), the body diode (D1) of the first SiC-MOSFET (MOS1) and the body diode (D2) of the second SiC-MOSFET (MOS2) are connected in reverse parallel to form a parasitic diode back-to-back connection structure; in the anti-series MOSFET switch configuration of the current limiting branch (20), the body diode (D3) of the third SiC-MOSFET (MOS3) and the body diode (D4) of the fourth SiC-MOSFET (MOS4) are connected in reverse parallel to form a parasitic diode back-to-back connection structure.

4. The switching topology for an AC solid-state power controller as described in claim 1, characterized in that: The current-limiting branch (20) has an anti-series MOSFET switch configuration connected in series with a current-limiting resistor RL.

5. The switching topology for an AC solid-state power controller as described in claim 1, characterized in that: It also includes a driving circuit; in the driving circuit, the first SiC-MOSFET (MOS1) and the second SiC-MOSFET (MOS2) of the main branch (10) are driven independently by control signals Q_1 and Q_2 respectively, and the on and off timing of the first SiC-MOSFET (MOS1) and the second SiC-MOSFET (MOS2) is controlled independently by a sequential on and off timing control strategy.

6. The switching topology for an AC solid-state power controller as described in claim 5, characterized in that: In the driving circuit, the current limiting branch (20) shares two driving paths. The control signal Q_34 drives the third SiC-MOSFET (MOS3) and the fourth SiC-MOSFET (MOS4) in the current limiting branch (20) to turn on and off quickly, while the control signal Q_SLOW enables the third SiC-MOSFET (MOS3) and the fourth SiC-MOSFET (MOS4) to be short-circuited and "slowly turned off".

7. The switching topology for an AC solid-state power controller as described in claim 1, characterized in that: The on-state voltage drop of the anti-series MOSFET configuration is ≤2V, and the operating frequency range is 1kHz~100kHz.

8. The switching topology for an AC solid-state power controller as described in claim 1, characterized in that: The switching response time of the current limiting branch (20) is ≤10μs, which can support the accurate distinction between impulsive load current and short circuit fault.

9. A control method for an AC solid-state power controller as described in any one of claims 1-8, characterized in that: Includes the following steps: Step 1: Sequential On / Off Timing Control 1.1 During the positive half-cycle, the second SiC-MOSFET (MOS2) is turned on first, and the current flows through the channel of the second SiC-MOSFET (MOS2) and the body diode (D1) of the first SiC-MOSFET (MOS1). 1.2 During the negative half-cycle, the first SiC-MOSFET (MOS1) is turned on, and the current naturally commutates to the channel of the first SiC-MOSFET (MOS1), achieving zero-voltage turn-on (ZVS). 1.3 During the turn-off cycle, the second SiC-MOSFET (MOS2) is turned off during the positive half-cycle, and the current is commutated to the body diode (D1) of the first SiC-MOSFET (MOS1); during the negative half-cycle, the body diode (D1) of the first SiC-MOSFET (MOS1) is turned off, achieving zero-current turn-off (ZCS). Step 2: Current limiting protection control strategy 2.1 Real-time monitoring of line load current I. When I exceeds the threshold Ip and is below the short-circuit protection current level, the first SiC-MOSFET (MOS1) and the second SiC-MOSFET (MOS2) of the main branch (10) are turned off, and the current limiting resistor R of the current limiting branch (20) is used. L Implement flow control protection; 2.2 If the current I continues to exceed Ip, the current limiting branch (20) switches to the current limiting mode within microseconds. The current limiting mode limits the overload current I to a safe value. As the load current increases, the protection time automatically decreases, triggering the inverse time current limiting protection strategy. 2.3 During the current limiting process, if the circuit is further determined to be short-circuit fault, the short-circuit signal Q_SLOW is effective, and then the third SiC-MOSFET (MOS3) and the fourth SiC-MOSFET (MOS4) of the current limiting branch (20) are slowly turned off to achieve short-circuit protection; Step 3: Fault Type Identification 3.1 Based on the time-frequency characteristics of current and the load voltage threshold, distinguish between short-circuit faults and capacitive impulse loads; 3.2 In case of a short circuit fault, disconnect the main branch (10) and the current-limiting branch (20); in case of capacitive impact load, enter the current-limiting mode until the normal state is restored.

10. The control method for an AC solid-state power controller as described in claim 9, characterized in that: The inverse time-limited rate-limiting protection strategy is as follows: ； Where I is the circuit output current; I p The protective current operating value; k is a constant with the dimension of time; r is a constant, usually ranging from 0 to 2; t p This is a defined time constant.

Images