Common-mode voltage elimination method based on three-phase four-leg flexible interconnection device

Abstract

The invention relates to a common-mode voltage elimination method based on a three-phase four-bridge-arm flexible interconnection device, the flexible interconnection device comprises a first converter and a second converter which are connected back to back, the first converter and the second converter are respectively located at a rectification side and an inversion side, and the method comprises the following steps: increasing each duty ratio of the second converter by T at the same time, obtaining various new duty ratios of the second converter; alternately sorting the duty ratios of the first converter and the new second converter from large to small; decomposing each duty ratio after the alternate sorting; the decomposed duty ratios are corrected, and virtual duty ratios on the two sides are obtained; under the constraint that the difference value between the virtual duty ratios on the two sides is kept unchanged, the amplitude of the virtual duty ratios is adjusted, so that the conduction number of the upper bridge arms on the two sides of the flexible interconnection device is matched in real time to eliminate the common-mode voltage. Compared with the prior art, the method has the advantages that the calculated amount is small, and common-mode voltage elimination is rapidly achieved.

Description

Technical Field

[0001] This invention relates to the field of power system application technology, and in particular to a common-mode voltage elimination method based on a three-phase four-arm flexible interconnection device. Background Technology

[0002] With the rapid development of new energy sources such as photovoltaics and new loads such as electric vehicles, distribution network systems are becoming increasingly larger and more complex. The increasing penetration rate of distributed photovoltaic power sources in distribution networks is seriously affecting power flow changes, and distribution areas frequently experience overcapacity or undercapacity. Currently, AC distribution networks are characterized by "closed-loop design and open-loop operation," with inter-distribution interconnection switches often in a cold standby state. To achieve "closed-loop operation" in AC distribution networks, some scholars have proposed flexible interconnection devices to replace these interconnection switches. Flexible interconnection devices can be connected between different distribution areas, efficiently and controllably realizing energy flow and power balance between them.

[0003] Conventional flexible interconnection devices have a three-phase, three-arm topology, which can only achieve energy flow under balanced power conditions. Under complex operating conditions, the lack of a neutral wire in a three-phase, three-arm flexible interconnection device means the sum of the three-phase currents must be zero. When the three-phase power to be transmitted is unbalanced, the currents in each phase will be severely distorted. To solve these problems, some researchers have proposed a three-phase, four-arm flexible interconnection device, which can adapt to more complex distribution network conditions.

[0004] There are two connection methods for flexible interconnection devices to the power grid: isolated and non-isolated. Isolated connection methods include adding a power frequency isolation transformer on the AC side and a high-frequency isolation transformer on the DC side. Compared to power frequency isolation transformers, high-frequency isolation transformers are smaller, but their topology is more complex and more prone to failure. In distribution networks, the size and failure rate of flexible interconnection devices are key issues for large-scale application. To improve the power density and reduce the size of flexible interconnection devices, a non-isolated connection method can be used when connecting them to the power grid. The non-isolated connection method eliminates the bulky isolation transformer and does not increase the complexity of the topology, making it one method to achieve high power density for flexible interconnection devices.

[0005] Because the converter achieves AC-DC conversion through the volt-second balance principle, a high-frequency square wave pulse common-mode voltage with a large amplitude and dv / dt will be generated at the neutral point of the AC side during the high-frequency switching process. This voltage not only generates shaft current in motors connected to the AC side, shortening their lifespan, but may also cause malfunctions in the low-voltage distribution network's leakage protection system, affecting users' power supply. Low-voltage distribution networks are generally directly grounded transformer neutral points. When non-isolated flexible interconnection devices are directly applied to low-voltage distribution networks, their common-mode voltage can cause problems such as circulating current to ground and leakage current to ground. This not only affects power quality but may also cause leakage protection system malfunctions.

[0006] Existing research on common-mode voltage suppression methods can be divided into hardware-based suppression and software-based suppression. Hardware-based suppression mainly uses devices such as common-mode transformers and common-mode chokes to increase the impedance of the common-mode circuit and suppress common-mode voltage. While hardware-based suppression methods offer high reliability, the additional hardware reduces the power density of flexible interconnect devices. Software-based suppression, on the other hand, addresses common-mode voltage at its source, without increasing the size of the flexible interconnect device. Therefore, to improve the power density of devices and enable their more flexible application in the power grid, common-mode voltage suppression based on software control strategies is a crucial technical problem that needs to be solved.

[0007] A search revealed Chinese invention patent application publication number CN117240062A, which discloses a common-mode circulating current suppression method for flexible interconnection devices in low-voltage distribution networks. This method involves closed-loop control of sampled signals to obtain modulation signals, followed by SVPWM modulation to obtain the gate signal duty cycles da, db, and dc of the three-phase upper bridge arm power switching devices in two modules. The average common-mode voltage within a single switching cycle is calculated, and the third harmonic component of the average common-mode voltage is extracted to derive the duty cycle change Δd that satisfies common-mode voltage suppression. The duty cycle change is calculated using the third harmonic component of the common-mode voltage, and the gate signal duty cycle of the power switching devices at both ends of the converter is coordinated to generate a new modulation wave at the zero vector action moment. The resulting gate signal controls the operation of the power switching converter circuit, thereby reducing the average common-mode voltage. However, this existing patent application has the problem of failing to eliminate common-mode voltage.

[0008] How to eliminate common-mode voltage based on software control strategies has become a technical problem that needs to be solved. Summary of the Invention

[0009] The purpose of this invention is to overcome the defects of the prior art by providing a common-mode voltage elimination method based on a three-phase four-bridge-arm flexible interconnect device.

[0010] The objective of this invention can be achieved through the following technical solutions:

[0011] According to one aspect of the present invention, a common-mode voltage elimination method based on a three-phase four-arm flexible interconnect device is provided, wherein the flexible interconnect device includes a first converter and a second converter connected back-to-back, the first converter and the second converter being located on the rectifier side and the inverter side, respectively, and the method includes:

[0012] Increase each duty cycle of the second converter by ΔT simultaneously to obtain a new duty cycle for the second converter;

[0013] The duty cycles of the first converter and the new second converter are sorted alternately from largest to smallest.

[0014] Decompose the duty cycles after alternating sorting;

[0015] The decomposed duty cycles are corrected to obtain the virtual duty cycles on both sides;

[0016] Under the constraint that the difference between the virtual duty cycles on both sides remains constant, the common-mode voltage is eliminated by adjusting the amplitude of the virtual duty cycle to match the number of conducting arms on both sides of the flexible interconnect device in real time.

[0017] Preferably, △T is specifically the difference between the sum of the duty cycles of the first converter and the sum of the duty cycles of the second converter, divided by 4.

[0018] Preferably, the step of alternately sorting the duty cycles of the first converter and the new second converter from largest to smallest specifically means: sorting the duty cycles T of the first converter... a T b T c T n Sort by size from largest to smallest, and denote as T. 1max T 1midh T 1midl T 1min ; the duty cycle T of the new second converter u ', T v ', T w ', T m Sort by size from largest to smallest, and denote as T. 2max T 2midh T 2midl T 2min The duty cycles of the first converter and the new second converter are sorted alternately from largest to smallest: T 1max T 2max T 1midh T 2midh T 1midl T 2midl T 1min T 2min .

[0019] More preferably, decomposing the alternately sorted duty cycles includes the following steps:

[0020] Step 1: Place T 1max Decompose it into (T1-T2), and then... 2max Decompose it into (T3-T2), and make T2 = 0;

[0021] Step 2: Place T 1midh Decomposed into (T3-T4);

[0022] Step 3: Place T 2midh Decomposed into (T5-T4);

[0023] Step 4: Place T 1midl Decomposed into (T5-T6);

[0024] Step 5: Place T 2midl Decomposed into (T7-T6);

[0025] Step 6: Place T 1min Decomposed into (T7-T8);

[0026] Step 7: Place T 2min Decomposed into (T9-T8);

[0027] Step 8: Since the sum of the duty cycles of the first converter is equal to the sum of the duty cycles of the new second converter, T9 = T1 in Step 7;

[0028] The values ​​of T1 to T8 are:

[0029]

[0030] More preferably, the correction of each duty cycle after decomposition includes:

[0031] Re-evaluate T2, ensuring that the values ​​of T1 to T8 are within the range of 0 to 1, and update the value of T2 to T2':

[0032]

[0033] The virtual duty cycle can be expressed as:

[0034] T i ′=T i +T′2

[0035] Where T i ′ represents the virtual duty cycle, i∈{1,2,3,4,5,6,7,8}.

[0036] Preferably, the method further includes restoring and sorting each virtual duty cycle, comparing it with the PWM carrier, and subtracting the corresponding virtual duty cycle switching states to obtain the duty cycle switching states of the first converter and the second converter.

[0037] Preferably, the duty cycles of the first and second converters are obtained through model predictive control, the process of which includes:

[0038] First, a continuous-time model is established for the three-phase four-bridge-arm flexible interconnection device;

[0039] Discretize the continuous-time model and obtain the instantaneous predicted output current at time k+1 using the forward Euler method;

[0040] Construct a cost function that is a quadratic function of the instantaneous expected output current and the instantaneous predicted output current of the three phases at time k+1.

[0041] By taking the partial derivative of the cost function with respect to the duty cycle of the switching transistors and setting the partial derivative to zero, we can obtain the extreme value of the cost function. This extreme value is the duty cycle of each switching transistor when the cost function is at its minimum.

[0042] More preferably, the process of establishing the continuous-time model includes:

[0043] Based on Kirchhoff's voltage and current laws, the following equations are established for the first and second converters:

[0044]

[0045] Among them, L eq1 and R eq1 These are the inductor matrix and resistor matrix connected to the first converter, respectively. eq2 and R eq2 i1 and i2 are the inductor and resistor matrices connected to the second converter, respectively; i1 and i2 are the discrete-domain three-phase currents of the first and second converters, respectively; e1 and e2 are the discrete-domain three-phase grid voltages of the first and second converters, respectively; and v1 and v2 are the voltage differences between the phase nodes and the clamping points in the first and second converters, respectively.

[0046] More preferably, the cost function is specifically:

[0047]

[0048]

[0049] I1 = i1(k+1), I2 = i2(k+1),

[0050] Where J is the cost function, and I1 and I2 are the instantaneous expected output current matrices of the three phases c of the first and second converters at time k+1, respectively, and the instantaneous predicted output current matrices of the three phases c of the first and second converters at time k+1, respectively.

[0051] More preferably, the duty cycle of each switch at the minimum value of the cost function is specifically:

[0052]

[0053] Where T1 and T2 are the bridge arm duty cycles of the first and second converters, respectively; Ω1 and Ω2 are the bridge arm duty cycle coefficients of the first and second converters, respectively; Φ1 and Φ2 are the current matrix coefficients of the first and second converters, respectively; and Γ1 and Γ2 are the inductance matrix coefficients of the first and second converters, respectively. Specifically, this can be expressed by the following formula:

[0054]

[0055] Among them, T s To control the cycle, V dc This is the DC bus voltage.

[0056] Compared with the prior art, the present invention has the following beneficial effects:

[0057] 1) The present invention simultaneously increases the duty cycle of each of the second converters by ΔT, and then sorts, decomposes and corrects the duty cycles of the two converters in alternating order of large and small values ​​to obtain the virtual duty cycles on both sides. Under the constraint that the difference between the virtual duty cycles on both sides remains unchanged, the number of upper bridge arms on both sides of the flexible interconnect device is matched in real time by adjusting the amplitude of the virtual duty cycle, thereby eliminating common mode voltage.

[0058] 2) This invention improves the cost function of model predictive control. The cost function is a quadratic function of the instantaneous expected output current and the instantaneous predicted output current of the three phases at time k+1. By taking the partial derivative of the cost function with respect to the duty cycle of the switching transistors and setting the partial derivative to zero, the extreme value of the cost function can be obtained. This extreme point is the duty cycle of each switching transistor when the cost function is minimized. This cost function helps to improve control accuracy and reduce the amount of calculation. In this way, the duty cycle of each switching transistor corresponding to the minimum current distortion can be found, thereby quickly achieving common-mode voltage elimination. Attached Figure Description

[0059] Figure 1 This is a topology diagram of the three-phase four-bridge-arm flexible interconnection device in this invention;

[0060] Figure 2 This is a diagram showing the adjustment of the zero vector action time in this invention;

[0061] Figure 3This is a diagram showing the sorting results of the bridge arm duty cycles in this invention;

[0062] Figure 4 This is a diagram showing the decomposition results of the duty cycle in this invention;

[0063] Figure 5 This is a diagram showing the result of duty cycle decomposition and correction in this invention;

[0064] Figure 6 This is the overall control block diagram of the common-mode voltage suppression method based on duty cycle decomposition of the present invention;

[0065] Figure 7 This is a common-mode voltage waveform diagram under traditional PWM control.

[0066] Figure 8 This is a waveform diagram of the common-mode voltage under the control of the method of the present invention. Detailed Implementation

[0067] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0068] This embodiment relates to a common-mode voltage elimination method based on a three-phase four-arm flexible interconnect device. By decomposing the duty cycle of each arm into two virtual duty cycles with adjustable amplitudes and a constant difference, the number of upper arms on both sides of the converter is matched in real time, theoretically eliminating the common-mode voltage completely. Under the constraint that the difference between the two virtual duty cycles remains constant, the common-mode voltage is eliminated by adjusting the amplitude of the virtual duty cycles to match the number of upper arms on both sides of the flexible interconnect device in real time.

[0069] The topology of a three-phase four-arm flexible interconnect device is as follows: Figure 1 As shown, the flexible interconnect device consists of a first converter (located in...) Figure 1 The left side (i.e., the rectifier side) and the second converter (located on the left side) Figure 1 The right side (i.e., the inverter side) consists of back-to-back connections. The switching transistor of the first converter is denoted as S. 11 -S 18 The voltage of each bridge arm is expressed as u. a u b u c u n The switching transistor of the second converter is represented as S. 21 -S 28 The voltage of each bridge arm is expressed as u. u u v u w um The grid voltage connected to the first converter is e. a e b e c The current flowing through the inductor is i a i b i c i n The grid voltage connected to the second converter is e. u e v e w The current flowing through the inductor on the grid side is i u i v i w i m The voltage on the DC bus connecting the first and second converters is V. dc L1 and L2 are the AC filter inductors of the first and second converters, respectively, and R... L1 R L2 These are the parasitic resistances of inductors L1 and L2, respectively. n L m The neutral filter inductors R of the first converter and the second converter are respectively. Ln R Lm Inductance L n L m Parasitic resistance.

[0070] Under stable operation of the flexible interconnection device, the upper pipe of each bridge arm in one control cycle ( Figure 1 The duty cycle of a switch (with an odd last digit) is T. x (x∈{a,b,c,n,u,v,w,m}), and corresponding to each lower pipe of each bridge arm ( Figure 1 For the switching transistor whose last digit is even, the on-state is opposite to that of the upper transistor. According to the volt-second balance principle, the voltage of each bridge arm can be obtained as follows:

[0071] u x =T x ·V dc (1)

[0072] Among them, u x T represents the voltage of each bridge arm. x V represents the duty cycle of the upper pipe of each bridge arm. dc This is the DC bus voltage.

[0073] Let the duty cycle of the turn-on time of each bridge arm transistor in the first and second converters be:

[0074]

[0075] Among them, T C1 and TC2 These are the duty cycles of the on-time of each bridge arm of the first and second converters (referred to as the duty cycles of each bridge arm).

[0076] The magnitude of the common-mode voltage is related to both the rectifier and inverter sides, therefore it is necessary to control both sides uniformly. To achieve complete elimination of the common-mode voltage, it can be expressed as:

[0077]

[0078] From the above analysis, it can be concluded that for the common-mode voltage to be completely eliminated, i.e., U cmv =0, which requires the sum of the duty cycles on the first converter side to be equal to the sum of the duty cycles on the second converter side, while also ensuring that the final control effect is not affected.

[0079] like Figure 2 The diagram shown illustrates the zero-vector action time adjustment of this invention. To achieve the above objectives, as... Figure 6 As shown, the T of the second converter u T v T w T m Simultaneously increasing △T, from the perspective of vector action, only changes V0 (corresponding to V) in the zero vector. (0000) (All bridge arms are configured with the lower bridge arm closed and the upper bridge arm open) and V 15 (corresponding to V) (1111) (All bridge arms are in a state where the lower bridge arm is open and the upper bridge arm is closed) The duration of action does not affect the duration of action of the effective voltage vector. The four duty cycles (T) of the second converter... u T v T w T m Increasing ΔT does not change the effective vector's duration, and its effect remains essentially unchanged. Therefore, the duty cycle of each switch can be altered by adjusting the zero vector's duration.

[0080] Apply ΔT to all four duty cycles on the second converter side simultaneously, making them equal to the sum of the duty cycles on the first converter side. Here, ΔT can be expressed as:

[0081]

[0082] The duty cycle of the new second converter is obtained as follows:

[0083]

[0084] like Figure 3 The image shown is a ranking result of the bridge arm duty cycles according to the present invention. Figure 6 and Figure 3 As shown, the four duty cycles T of the first convertera T b T c T n Sort by size from largest to smallest and denote as T 1max T 1midh T 1midl T 1min The four duty cycles T of the obtained second converter u ', T v ', T w ', T m Sort by size from largest to smallest and denote as T 2max T 2midh T 2midl T 2min The duty cycles of the first converter and the new second converter are alternately sorted from largest to smallest as follows: T 1max T 2max T 1midh T 2midh T 1midl T 2midl T 1min T 2min .

[0085] like Figure 4 The diagram shown illustrates the duty cycle decomposition results of this invention. Based on the common-mode voltage decomposition mechanism, the sorted duty cycles are decomposed. The specific steps are as follows:

[0086] Step 1: Place T 1max Decompose it into (T1-T2), and then... 2max Decompose it into (T3-T2) and make T2=0.

[0087] Step 2: Place T 1midh It is decomposed into (T3-T4).

[0088] Step 3: Place T 2midh It is decomposed into (T5-T4).

[0089] Step 4: Place T 1midl It is decomposed into (T5-T6).

[0090] Step 5: Place T 2midl It is decomposed into (T7-T6).

[0091] Step 6: Place T 1min It is decomposed into (T7-T8).

[0092] Step 7: Place T 2min It is decomposed into (T9-T8).

[0093] Step 8: Since the sum of the duty cycles on the first converter side is equal to the sum of the duty cycles on the second converter side, T9 = T1 in Step 7.

[0094] After the above steps, the values ​​of T1 to T8 can be obtained as follows:

[0095]

[0096] like Figure 5 The diagram shown is a result of the duty cycle decomposition correction of the present invention. Since T2 = 0, T 1max and T 2max The corresponding bridge arm, with inconsistent operating frequency with other bridge arms, will increase the total harmonic distortion (THD) of the current. Therefore, based on equation (6), T2 is revalued, while ensuring that the values ​​of T1 to T8 are within the range of 0 to 1. The value of T2 is then updated to T′2:

[0097]

[0098] Ultimately, the virtual duty cycle can be expressed as:

[0099] T i ′=T i +T′2,i∈{1,2,3,4,5,6,7,8} (8)

[0100] According to formula (8), T1'~T′8 are obtained, and then the sorting is restored to obtain T. a ~T m .

[0101] Sorted T a ~T m Comparing with the PWM carrier, the difference between the corresponding virtual duty cycle switching states yields the duty cycle switching states S of the first and second converters. a ~S m .

[0102] In summary, as mentioned above, Figure 6 The diagram shown is the overall control block diagram of the common-mode voltage suppression method based on duty cycle decomposition proposed in this invention. The duty cycle T... C1 and T C2 The following is a detailed description of the specific methods of model predictive control, obtained through model predictive control.

[0103] Based on the voltage of each bridge arm, the voltage difference v1 between points A, B, and C in the first converter and point N (clamping point) and the voltage difference v2 between points U, V, and W in the second converter and point M (clamping point) can be obtained as follows:

[0104] v1 = [u an u bn ucn ] T =α·u1 (9)

[0105] v2 = [u um u vm u wm ] T =α·u2 (10)

[0106]

[0107] Among them, u an u bn u cn These represent the voltage differences between points A, B, and C in the first converter and point N, respectively, u. um u vm u wm These represent the voltage differences between points U, V, and W and point M in the first converter.

[0108] First, a continuous-time model is established for the three-phase four-arm flexible interconnection device. Based on Kirchhoff's voltage and current laws, the following equations can be established for the first and second converters:

[0109]

[0110] Where: L eq1 and R eq1 These are the inductor matrix and resistor matrix connected to the first converter, respectively. eq2 and R eq2 Let i1 and i2 be the inductor and resistor matrices connected to the second converter, respectively; let i1 and i2 be the discrete-domain three-phase currents of the first and second converters, respectively; and let e1 and e2 be the discrete-domain three-phase grid voltages of the first and second converters, respectively. The specific formulas are as follows:

[0111]

[0112] According to equations (11) and (12), we can obtain:

[0113]

[0114] Discretizing the continuous-time model, the instantaneous predicted output current at time k+1 can be obtained by the forward Euler method as follows:

[0115]

[0116] Where i1(k) and i2(k) are the discrete-domain three-phase currents of the first converter and the second converter at time k, respectively, and e1(k) and e2(k) are the discrete-domain three-phase grid voltages of the first converter and the second converter at time k, respectively. 3×3It is a 3×3 unit diagonal matrix.

[0117] The cost function of model predictive control can be expressed as:

[0118]

[0119] Among them, i x (k+1)* represents the instantaneous expected output current of phases a, b, and c at time k+1, i x (k+1) Instantaneous predicted output current of phases a, b, and c at time k+1.

[0120] Finite set model predictive control finds the state variables that minimize the cost function by substituting the state variables of a finite set into the cost function. However, this method suffers from high computational cost and limited control accuracy, and there is a positive correlation between computational cost and control accuracy.

[0121] To improve control accuracy and reduce computational load, observing the cost function reveals it to be a quadratic function with multiple variables. Finding the minimum value of the cost function is essentially a problem of finding the minimum value of a multivariate quadratic function. The duty cycle of each switch is a control variable of the flexible interconnect device. Taking the partial derivative of the cost function with respect to the switch duty cycle and setting the partial derivative to zero yields the extreme values ​​of the cost function. The extreme points represent the duty cycles of each switch at the minimum cost function. Using this method, we can find the duty cycles of each switch that minimize current distortion. The cost function can be expressed in matrix form as follows:

[0122]

[0123] in:

[0124]

[0125] I1 = i1(k+1), I2 = i2(k+1),

[0126] J is the cost function. and I1 and I2 are the instantaneous expected output current matrices of the three phases c of the first and second converters at time k+1, respectively, and the instantaneous predicted output current matrices of the three phases c of the first and second converters at time k+1, respectively.

[0127] Taking the partial derivative of equation (18) yields:

[0128]

[0129] Substitute equations (11) and (12) into equation (16), and let The duty cycle of the upper switch of each bridge arm can be obtained by solving:

[0130]

[0131] Where T1 and T2 are the bridge arm duty cycles of the first and second converters, respectively; Ω1 and Ω2 are the bridge arm duty cycle coefficients of the first and second converters, respectively; Φ1 and Φ2 are the current matrix coefficients of the first and second converters, respectively; and Γ1 and Γ2 are the inductance matrix coefficients of the first and second converters, respectively. Specifically, this can be expressed by the following formula:

[0132]

[0133] Among them, T s To control the cycle, V dc This is the DC bus voltage.

[0134] The duty cycle T for the switching transistors of each bridge arm can be obtained using equation (20). c1 and T c2 .

[0135] like Figure 7 The image shows the common-mode voltage under traditional PWM control. From... Figure 7 It can be seen that the common-mode voltage exhibits large peak and RMS values ​​without suppression. The common-mode voltage U between the first and second converters... cm1 and U cm2 Under the superposition of the two AC power grids, the common-mode voltage U between the two AC power grids cmv The voltage reaches twice the DC bus voltage, therefore it is necessary to suppress the common-mode voltage between AC power grids.

[0136] like Figure 8 As shown, this invention proposes a common-mode voltage elimination scheme. Although the common-mode voltage amplitudes of the first and second converters remain unchanged, the total common-mode voltage is eliminated. This achieves a total common-mode voltage of zero without significantly reducing control degrees of freedom, ensuring that current quality is not substantially affected.

[0137] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A common-mode voltage elimination method based on a three-phase four-arm flexible interconnection device, characterized in that, The flexible interconnect device includes a first converter and a second converter connected back-to-back, the first converter and the second converter being located on the rectifier side and the inverter side, respectively. The method includes: Increase each duty cycle of the second converter by ΔT simultaneously to obtain the new duty cycles of the second converter; The duty cycles of the first converter and the new second converter are sorted alternately from largest to smallest. Decompose the duty cycles after alternating sorting; The decomposed duty cycles are corrected to obtain the virtual duty cycles on both sides; Under the constraint that the difference between the virtual duty cycles on both sides remains constant, the common-mode voltage is eliminated by adjusting the amplitude of the virtual duty cycle to match the number of conducting arms on both sides of the flexible interconnect device in real time.

2. The common-mode voltage elimination method based on a three-phase four-arm flexible interconnection device according to claim 1, characterized in that, Specifically, △T is the difference between the sum of the duty cycles of the first converter and the sum of the duty cycles of the second converter, divided by 4.

3. The common-mode voltage elimination method based on a three-phase four-arm flexible interconnection device according to claim 1, characterized in that, The specific method of alternately sorting the duty cycles of the first converter and the new second converter from largest to smallest is as follows: for each duty cycle T of the first converter... a T b T c T n Sort by size from largest to smallest, and denote as T. 1max T 1midh T 1midl T 1min ; the duty cycle T of the new second converter u ', T v ', T w ', T m Sort by size from largest to smallest, and denote as T. 2max T 2midh T 2midl T 2min The duty cycles of the first converter and the new second converter are sorted alternately from largest to smallest: T 1max T 2max T 1midh T 2midh T 1midl T 2midl T 1min T 2min .

4. The common-mode voltage elimination method based on a three-phase four-arm flexible interconnection device according to claim 3, characterized in that, Decomposing the duty cycles after alternating sorting includes the following steps: Step 1: Place T 1max Decompose it into (T1-T2), and then... 2max Decompose it into (T3-T2), and make T2 = 0; Step 2: Place T 1midh Decomposed into (T3-T4); Step 3: Place T 2midh Decomposed into (T5-T4); Step 4: Place T 1midl Decomposed into (T5-T6); Step 5: Place T 2midl Decomposed into (T7-T6); Step 6: Place T 1min Decomposed into (T7-T8); Step 7: Place T 2min Decomposed into (T9-T8); Step 8: Since the sum of the duty cycles of the first converter is equal to the sum of the duty cycles of the new second converter, T9 = T1 in Step 7; The values ​​of T1 to T8 are:

5. The common-mode voltage elimination method based on a three-phase four-arm flexible interconnection device according to claim 4, characterized in that, The correction of each duty cycle after decomposition includes: Re-evaluate T2, ensuring that the values ​​of T1 to T8 are within the range of 0 to 1, and update the value of T2 to T2': The virtual duty cycle can be expressed as: T i ′=T i +T′2 Where T i ' represents the virtual duty cycle, i∈{1,2,3,4,5,6,7,8}.

6. The common-mode voltage elimination method based on a three-phase four-arm flexible interconnection device according to claim 1, characterized in that, The method further includes restoring and sorting each virtual duty cycle, comparing it with the PWM carrier, and subtracting the corresponding virtual duty cycle switching states to obtain the duty cycle switching states of the first converter and the second converter.

7. The common-mode voltage elimination method based on a three-phase four-arm flexible interconnection device according to claim 1, characterized in that, The duty cycles of the first and second converters are obtained through model predictive control, and the process includes: First, a continuous-time model is established for the three-phase four-bridge-arm flexible interconnection device; Discretize the continuous-time model and obtain the instantaneous predicted output current at time k+1 using the forward Euler method; Construct a cost function that is a quadratic function of the instantaneous expected output current and the instantaneous predicted output current of the three phases at time k+1. By taking the partial derivative of the cost function with respect to the duty cycle of the switching transistors and setting the partial derivative to zero, we can obtain the extreme value of the cost function. This extreme value is the duty cycle of each switching transistor when the cost function is at its minimum.

8. The common-mode voltage elimination method based on a three-phase four-arm flexible interconnection device according to claim 7, characterized in that, The process of establishing the continuous-time model includes: Based on Kirchhoff's voltage and current laws, the following equations are established for the first and second converters: Among them, L eq1 and R eq1 These are the inductor matrix and resistor matrix connected to the first converter, respectively. eq2 and R eq2 i1 and i2 are the inductor and resistor matrices connected to the second converter, respectively; i1 and i2 are the discrete-domain three-phase currents of the first and second converters, respectively; e1 and e2 are the discrete-domain three-phase grid voltages of the first and second converters, respectively; and v1 and v2 are the voltage differences between the phase nodes and the clamping points in the first and second converters, respectively.

9. A common-mode voltage elimination method based on a three-phase four-arm flexible interconnection device according to claim 7, characterized in that, The cost function is specifically as follows: Where J is the cost function, and I1 and I2 are the instantaneous expected output current matrices of the three phases c of the first and second converters at time k+1, respectively, and the instantaneous predicted output current matrices of the three phases c of the first and second converters at time k+1, respectively.

10. A common-mode voltage elimination method based on a three-phase four-arm flexible interconnection device according to claim 8, characterized in that, The duty cycle of each switch at the minimum value of the cost function is specifically as follows: Where T1 and T2 are the bridge arm duty cycles of the first and second converters, respectively; Ω1 and Ω2 are the bridge arm duty cycle coefficients of the first and second converters, respectively; Φ1 and Φ2 are the current matrix coefficients of the first and second converters, respectively; and Γ1 and Γ2 are the inductance matrix coefficients of the first and second converters, respectively. Specifically, this can be expressed by the following formula: Among them, T s To control the cycle, V dc This is the DC bus voltage.

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