Anti-interference circuit, chip and electrical equipment

Abstract

According to the anti-interference circuit, the chip and the electrical equipment provided by the embodiment of the invention, the control module receives the two signals and then outputs the second state feedback signal, and the signal is consistent with the reading state indicated by the first state feedback signal when the power supply is not interfered; it is ensured that the central processing unit can accurately read the digital signal of the analog-to-digital conversion module according to the second state feedback signal under the normal condition; and when the power supply is interfered and the first state feedback signal indicates that the analog-to-digital conversion module finishes reading, the second state feedback signal indicates that the reading is not finished, so that the central processing unit does not read data mistakenly when the analog-to-digital conversion result is not reliable due to the interference of the power supply, the influence of interference on data reading is avoided, and the data reading efficiency is improved. The accuracy and reliability of the central processing unit for reading digital signals are ensured, the anti-interference capability of the whole circuit is improved, and the accuracy of data acquisition of the analog-to-digital converter is improved.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to an anti-interference circuit, chip, and electrical device. Background Technology

[0002] With the rapid development of technology, motors are increasingly used in various application scenarios. In current motor applications, three-phase current is converted into voltage through current sensing resistors and sampled and quantized by an ADC (Analog-to-Digital Converter). The quantized value is used to control the PWM (Pulse Width Modulation) wave, thereby controlling the on and off of the IGBT (Insulated Gate Bipolar Transistor). The on and off of the IGBT generates large-amplitude high-frequency interference signals, which cause serious instantaneous interference to the entire system. Due to the common ground design, this interference causes interference to the ADC power supply, thus affecting the accuracy of the ADC data acquisition. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide an anti-interference circuit, chip, and electrical device that overcomes or at least partially solves the above problems.

[0004] To address the above problems, this invention discloses an anti-interference circuit, which includes:

[0005] An analog-to-digital converter module is used to convert the acquired voltage signal into a digital signal and output a first status feedback signal; the first status feedback signal is used to indicate the reading status of the analog-to-digital converter module.

[0006] The detection module is used to detect the power supply and output a detection signal, which is used to indicate whether the power supply is being interfered with.

[0007] A control module, connected to the analog-to-digital conversion module and the detection module, is used to receive the first state feedback signal and the detection signal, and output a second state feedback signal. The second state feedback signal is used to indicate the reading state of the analog-to-digital conversion module. When the detection signal indicates that the power supply is not interfered with, the reading state indicated by the second state feedback signal is the same as the reading state indicated by the first state feedback signal. When the detection signal indicates that the power supply is interfered with, if the first state feedback signal indicates that the analog-to-digital conversion module has completed reading, then the second state feedback signal indicates that the analog-to-digital conversion module has not completed reading.

[0008] The central processing unit is connected to both the control module and the analog-to-digital converter module, and is used to receive the second status feedback signal and read the digital signal of the analog-to-digital converter module according to the second status feedback signal.

[0009] Optionally, the control module includes:

[0010] An inverter, connected to the analog-to-digital converter module, is used to invert the first state feedback signal.

[0011] A first logic processor, connected to the inverter, is used to acquire a reset signal and an inverted first state feedback signal, and to perform a logical AND operation on the reset signal and the inverted first state feedback signal to obtain a first processed signal.

[0012] The second logic processor, connected to the inverter and the detection module, is used to acquire the detection signal and the inverted first state feedback signal, and to perform logical AND-NOT processing on the detection signal and the inverted first state feedback signal to obtain the second processed signal.

[0013] A trigger is connected to the first logic processor and the second logic processor respectively, and is used to acquire the first processing signal and the second processing signal, determine whether to perform a reset based on the second processing signal, and output a third processing signal based on the reset status.

[0014] A third logic processor is connected to the flip-flop and the central processing unit respectively, and is used to acquire the first state feedback signal and the third processing signal, and perform a logical AND operation on the third processing signal and the first state feedback signal to obtain a second state feedback signal.

[0015] Optionally, the inverter is used to invert the first state feedback signal to obtain an inverted first state feedback signal when the first state feedback signal is a high-level signal, wherein the inverted first state feedback signal is a low-level signal.

[0016] Optionally, the reset signal is a high-level signal, and the first logic processor is used to perform a logical AND operation on the inverted first state feedback signal and the reset signal to obtain the first processing signal, which is a low-level signal.

[0017] Optionally, the detection signal is a high-level signal, and the second logic processor is used to perform a logical AND-NOT operation on the inverted first state feedback signal and the detection signal to obtain the second processing signal, which is a high-level signal.

[0018] Optionally, the trigger is configured not to reset when the second processing signal is a high-level signal, and to output the third processing signal, which is a low-level signal.

[0019] Optionally, the third logic processor is configured to perform a logical AND operation on the third processing signal and the first state feedback signal to obtain the second state feedback signal, wherein the second state feedback signal is a low-level signal.

[0020] Optionally, the detection component includes:

[0021] Acquisition module, the acquisition module is used to acquire the output voltage of the power supply;

[0022] The comparison module, connected to the acquisition module, is used to acquire the reference voltage and the output voltage, determine whether the power supply is interfered with based on the output voltage and the reference voltage, and output the detection signal.

[0023] Optionally, the comparison module is used to determine whether the output voltage is greater than the reference voltage. If the output voltage is greater than the reference voltage, it is determined that the power supply is interfered with, and the detection signal is output, wherein the detection signal is a high-level signal.

[0024] Optionally, the acquisition module includes a first resistor, a second resistor, and a third resistor. One end of the first resistor is connected to the power supply, the other end of the first resistor is connected to one end of the second resistor, the other end of the second resistor and one end of the third resistor are connected to the comparator, and the other end of the third resistor is grounded.

[0025] Optionally, the acquisition module is a bandgap basic unit of a microcontroller.

[0026] Optionally, the comparison module is a comparator of a microcontroller.

[0027] The present invention also discloses a chip, which includes the anti-interference circuit described above.

[0028] The present invention also discloses an electrical device, which includes the above-described anti-interference circuit.

[0029] The embodiments of the present invention have the following advantages:

[0030] In this invention, an analog-to-digital converter (ADC) module converts the acquired voltage signal into a digital signal and outputs a first state feedback signal indicating its own reading status. A detection module detects the power supply and outputs a detection signal indicating whether the power supply is being interfered with. After receiving these two signals, the control module outputs a second state feedback signal. When the power supply is not interfered with, this signal is consistent with the reading status indicated by the first state feedback signal, ensuring that the central processing unit (CPU) can accurately read the digital signal from the ADC module according to the second state feedback signal under normal circumstances. However, when the power supply is interfered with and the first state feedback signal indicates that the ADC has completed reading, the second state feedback signal will indicate that reading is not complete. This prevents the CPU from erroneously reading data when power supply interference may lead to unreliable ADC results, thus avoiding the impact of interference on data reading. In this way, the circuit achieves effective control of the ADC module's reading status under power supply interference, ensuring the accuracy and reliability of the CPU's reading of digital signals, improving the overall circuit's anti-interference capability, and enhancing the accuracy of the data acquired by the ADC. Attached Figure Description

[0031] Figure 1 This is a structural block diagram of an anti-interference circuit provided by the present invention;

[0032] Figure 2 This is a structural block diagram of a detection module provided by the present invention;

[0033] Figure 3 This invention provides a signal timing diagram;

[0034] Figure 4 This is a structural block diagram of a chip provided by the present invention. Detailed Implementation

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] One of the core concepts of this invention is that the present invention can convert the acquired voltage signal into a digital signal through an analog-to-digital converter (ADC) module and output a first state feedback signal indicating its own reading status. The detection module detects the power supply and outputs a detection signal indicating whether the power supply is interfered with. After receiving these two signals, the control module outputs a second state feedback signal. When the power supply is not interfered with, this signal is consistent with the reading status indicated by the first state feedback signal, ensuring that the central processing unit (CPU) can accurately read the digital signal from the ADC module according to the second state feedback signal under normal circumstances. However, when the power supply is interfered with and the first state feedback signal indicates that the ADC has completed reading, the second state feedback signal will indicate that reading is not completed. This prevents the CPU from erroneously reading data when power supply interference may lead to unreliable ADC results, thus avoiding the impact of interference on data reading. In this way, the circuit achieves effective control of the ADC reading status under power supply interference, ensuring the accuracy and reliability of the CPU reading digital signals, improving the anti-interference capability of the entire circuit, and improving the accuracy of the data acquired by the ADC.

[0037] Reference Figure 1 The diagram shows a structural block diagram of an anti-interference circuit 10 according to the present invention. The anti-interference circuit may include:

[0038] The analog-to-digital converter module 101 is used to convert the acquired voltage signal into a digital signal and output a first state feedback signal; the first state feedback signal is used to indicate the reading status of the analog-to-digital converter module.

[0039] The analog-to-digital converter module 101 can be a successive approximation digital-to-analog converter, which can convert the input analog signal into a digital signal code, such as a 12-bit SAR ADC. The output code is Data<11:0>, where 111111111111 represents the input signal reaching its maximum value, typically full-scale VCC, and 000000000000 represents the input signal reaching its minimum value, typically 0. The quantization process takes a certain amount of time. Once quantization is complete, Data<11:0> is fully determined. At this point, the SAR ADC digital logic will emit an EOC (End Of Conversion) high pulse signal to indicate that quantization is complete. The CPU will simultaneously receive the EOC pulse signal and the quantized code Data<11:0> to complete the data quantization and reception operation. If no EOC high pulse signal appears, the value of Data<11:0> cannot be recognized and received by the CPU, and this set of data will be ignored.

[0040] In this embodiment of the invention, the analog-to-digital conversion module 101 can convert the acquired voltage signal into a digital signal and output a first state feedback signal. The first state feedback signal can indicate its own reading status. If the first state feedback signal indicates that reading is complete, it means that the current data has been quantized. If the first state feedback signal indicates that reading is not complete, it means that the current data is in the process of quantization. Specifically, a high-level signal can indicate that the first state feedback signal indicates that reading is complete, and a low-level signal can indicate that the first state feedback signal indicates that reading is not complete.

[0041] In one example, in a motor application scenario, the voltage value of the three-phase current can be detected by an ADC module. The three-phase current is converted into voltage through a current sensing resistor and sampled and quantized by the ADC. The quantized value can be used to control the PWM wave, thereby controlling the IGBT's turn-on and turn-off.

[0042] The detection module 102 is used to detect the power supply and output a detection signal, which is used to indicate whether the power supply is interfered with.

[0043] In this embodiment of the invention, the detection module 102 can continuously monitor the stability of the power supply voltage. Once the power supply voltage fluctuation exceeds the threshold or abnormal ripple or other interference signs are detected, a high-level detection signal is immediately output; otherwise, a low-level detection signal is output.

[0044] The control module 103, connected to the analog-to-digital conversion module and the detection module, is used to receive a first state feedback signal and a detection signal, and output a second state feedback signal. The second state feedback signal is used to indicate the reading status of the analog-to-digital conversion module. When the detection signal indicates that the power supply is not interfered with, the reading status indicated by the second state feedback signal is the same as the reading status indicated by the first state feedback signal. When the detection signal indicates that the power supply is interfered with, if the first state feedback signal indicates that the analog-to-digital conversion module has completed reading, the second state feedback signal indicates that the analog-to-digital conversion module has not completed reading.

[0045] In this embodiment of the invention, the control module 103 serves as the decision-making center, which can receive the output signals of the first two modules and perform logical processing, and output the second state feedback signal after logical processing.

[0046] When the detection signal is low (no interference), the first state feedback signal is directly output as the second state feedback signal. However, when the detection signal is high (interference exists), if the analog-to-digital converter module claims that the conversion has been completed, the control module will force the second state feedback signal to be set to incomplete, thereby preventing the central processing unit from reading the quantized digital signal.

[0047] The central processing unit 104 is connected to the control module and the analog-to-digital converter module respectively, and is used to receive the second state feedback signal and read the digital signal of the analog-to-digital converter module according to the second state feedback signal.

[0048] In this embodiment of the invention, the central processing unit 104 can determine when to read digital signals from the analog-to-digital conversion module based on the second state feedback signal, ensuring that data acquisition is only performed when the circuit is operating in a reliable state. Specifically, when the second state feedback signal is a high-level signal, digital signals can be read, and when the second state feedback signal is a low-level signal, digital signals are not read.

[0049] This invention discloses an anti-interference circuit. An analog-to-digital converter (ADC) module converts the acquired voltage signal into a digital signal and outputs a first state feedback signal indicating its own reading status. A detection module detects the power supply and outputs a detection signal indicating whether the power supply is being interfered with. A control module receives these two signals and outputs a second state feedback signal. When the power supply is not interfered with, this second state feedback signal is consistent with the reading status indicated by the first state feedback signal, ensuring that the central processing unit (CPU) can accurately read the digital signal from the ADC module according to the second state feedback signal under normal conditions. However, when the power supply is interfered with and the first state feedback signal indicates that the ADC has completed reading, the second state feedback signal indicates that reading is incomplete. This prevents the CPU from erroneously reading data when power supply interference may lead to unreliable ADC results, thus avoiding the impact of interference on data reading. In this way, the circuit effectively controls the reading status of the ADC module under power supply interference, ensuring the accuracy and reliability of the CPU's digital signal reading, improving the overall circuit's anti-interference capability, and enhancing the accuracy of the data acquired by the ADC.

[0050] In one embodiment of the present invention, the control module 103 may include:

[0051] Inverter 1031, connected to the analog-to-digital converter module, is used to invert the first state feedback signal.

[0052] In this embodiment of the invention, the inverter 1031 receives the first state feedback signal from the analog-to-digital conversion module 101. In one example, if the signal is high, inverting it will result in a low-level signal; if the signal is low, inverting it will result in a high-level signal.

[0053] The first logic processor 1032 is connected to the inverter and is used to acquire the reset signal and the inverted first state feedback signal, and to perform a logical AND operation on the reset signal and the inverted first state feedback signal to obtain the first processed signal.

[0054] In this embodiment of the invention, the first logic processor 1032 performs an AND operation between the inverted first state feedback signal and an external reset signal. The reset signal is a high-level signal. The first processing signal can be obtained by performing an AND logic operation between the reset signal and the first state feedback signal, which is used to trigger subsequent reset operations.

[0055] If the first feedback signal after inversion is a high-level signal, then the first processed signal output is a high-level signal; if the first feedback signal after inversion is a low-level signal, then the first processed signal output is a low-level signal.

[0056] The second logic processor 1033 is connected to the inverter and the detection module. It is used to acquire the detection signal and the inverted first state feedback signal, and to perform logical AND-NOT processing on the detection signal and the inverted first state feedback signal to obtain the second processed signal.

[0057] In this embodiment of the invention, the second logic processor 1033 can perform a NAND operation between the inverted first state feedback signal and the interference signal from the detection module. When interference is detected and analog-to-digital conversion is completed, a high-level second processing signal is output to indicate that the trigger should not be reset. When interference is detected and analog-to-digital conversion is not completed, a low-level second processing signal is output to indicate that the trigger should be reset.

[0058] The trigger 1034 is connected to the first logic processor and the second logic processor respectively, and is used to acquire the first processing signal and the second processing signal, determine whether to perform a reset based on the second processing signal, and output the third processing signal based on the reset status.

[0059] In this embodiment of the invention, the trigger 1034 can determine whether to reset based on the second processing signal. If the second processing signal is a low-level signal, a reset is performed and a low-level third processing signal is output. If the second processing signal is a high-level signal, it indicates that there is no reset, and the third processing signal is kept consistent with the first processing signal.

[0060] The third logic processor 1035 is connected to the flip-flop and the central processing unit respectively. It is used to acquire the first state feedback signal and the third processing signal, and to perform a logical AND operation on the third processing signal and the first state feedback signal to obtain the second state feedback signal.

[0061] In this embodiment of the invention, the third logic processor 1035 can perform an AND operation between the first state feedback signal and the third processing signal to generate a second state feedback signal. If the trigger is reset due to interference, the third processing signal is low, and the second state feedback signal is low, so the central processing unit does not read data. If the trigger 1034 is not reset, the third processing signal is high, and the second state feedback signal follows the input first state feedback signal. The logic conversion and processing of the signal can be realized by using an inverter and a multi-level logic processor. The trigger determines the reset based on the second processing signal and outputs the third processing signal. Finally, the second state feedback signal is generated by the third logic processor, which effectively improves the stability and reliability of the system and ensures that the system can respond and adjust in a timely manner according to different states.

[0062] In one embodiment of the present invention, the inverter is used to invert the first state feedback signal when the first state feedback signal is a high-level signal to obtain an inverted first state feedback signal, which is a low-level signal.

[0063] In this embodiment of the invention, when the analog-to-digital converter 101 completes the voltage signal conversion and outputs a high-level first state feedback signal, for example, logic 1 to indicate that the conversion is complete, the inverter inverts the signal and outputs a low-level signal, i.e., logic 0. This process provides the necessary signal conditions for subsequent logic operations.

[0064] In this invention, the inverter serves as a basic logic element with extremely low power consumption. Its output signal directly drives subsequent logic gates, reducing energy loss during signal transmission and meeting low-power design requirements. The inverter inverts the high-level first state feedback signal, converting it into a low-level inverted first state feedback signal. This provides the subsequent logic processor with a logic input opposite to the original signal, enabling the control module to perform diverse signal processing and state control based on different logic states, effectively expanding the system's response capability to different signal states.

[0065] In one embodiment of the present invention, the reset signal is a high-level signal, and the first logic processor is used to perform a logical AND operation on the inverted first state feedback signal and the reset signal to obtain a first processing signal, which is a low-level signal.

[0066] In this embodiment of the invention, the reset signal refers to the RESET signal, that is... Figure 1The first logic processor 1032 receives the operation command sent by the external control system. A high level indicates that the circuit state needs to be reset, which is usually used in system initialization or fault recovery scenarios. The principle of the first logic processor is that the output is high only when all inputs are high; otherwise, the output is low. At this time, the inverted first state feedback signal is a low level signal, the reset signal is a high level signal, and the output first processing signal is a low level signal.

[0067] In one embodiment of the present invention, the detection signal is a high-level signal, and the second logic processor is used to perform a logical AND-NOT operation on the inverted first state feedback signal and the detection signal to obtain a second processing signal, which is a high-level signal.

[0068] In this embodiment of the invention, if the detection signal is high, it indicates that the power supply has been interfered with, which may lead to unreliable analog-to-digital conversion results. The logic rule of the NAND gate is: the output is low only when all inputs are high; otherwise, the output is high. At this time, the first state feedback signal after inversion is a low-level signal, the detection signal is a high-level signal, and the output second processing signal is a high-level signal.

[0069] In one embodiment of the present invention, a trigger is configured to not reset when the second processing signal is a high-level signal, and to output a third processing signal, which is a low-level signal.

[0070] In this embodiment of the invention, the flip-flop 1034 can be a D flip-flop. When power interference occurs and analog-to-digital conversion is completed, the second logic processor outputs a high-level second processing signal. The flip-flop reset terminal is low-level active, so the flip-flop should not be reset, that is, the third processing signal is consistent with the first processing signal. At this time, the first processing signal is a low-level signal, so the third processing signal is output as 0.

[0071] In one embodiment of the present invention, a third logic processor is used to perform a logical AND operation on a third processing signal and a first state feedback signal to obtain a second state feedback signal, wherein the second state feedback signal is a low-level signal.

[0072] In an embodiment of the present invention, in the control module of the anti-interference circuit, the third logic processor 1035 serves as the final state decision-making unit. By performing a logical AND operation on the third processing signal and the first state feedback signal, a second state feedback signal for indicating the reading state of the analog-to-digital conversion module is generated. Since the third processing signal is a low-level signal at this time, the output second state signal is a low-level signal, which filters out the interfered EOC and normally outputs the non-interfered EOC, thereby automatically filtering out the error data caused by the motor interfering with the power supply, realizing the automatic filtering effect of the power supply on the output data during ADC data quantization, and avoiding the abnormal jump of the ADC quantization result caused by power supply interference in the motor application, which triggers the misoperation of the overcurrent protection.

[0073] In an embodiment of the present invention, the detection component includes:

[0074] An acquisition module for acquiring the output voltage of the power supply;

[0075] A comparison module, connected to the acquisition module, for obtaining a reference voltage and an output voltage, judging whether the power supply is interfered according to the output voltage and the reference voltage, and outputting a detection signal.

[0076] In an embodiment of the present invention, as Figure 2 , a structural block diagram of a detection component provided by an embodiment of the present invention is shown. The detection component 102 includes an acquisition module 1021 and a comparison module 1022.

[0077] As the core front end of the anti-interference circuit, the detection component 102 can realize the rapid identification of power supply interference through the real-time monitoring and comparison of the power supply output voltage. The acquisition module 1021 can obtain the real-time output voltage of the power supply through a voltage division circuit, a sample and hold circuit, etc. For example, for a 5V DC power supply, the acquisition module can reduce the voltage to the range of 0-3V that can be processed by the analog-to-digital converter ADC through precise resistor voltage division and continuously monitor the voltage fluctuation at a certain sampling frequency.

[0078] The reference voltage is provided by a high-precision voltage reference source and represents the ideal interference-free output value of the power supply, which can be set according to user requirements. The comparison module 1022 can dynamically compare the real-time acquired output voltage with the reference voltage to determine whether interference occurs. By comparing two analog power supply voltages VIP and the reference voltage VIN, when VIP > VIN, it means that the interfered output is a high level, and when VIP < VIN, it means that the non-interfered output is a low level; by acquiring the output voltage of the power supply in real time through the acquisition module and comparing it with the reference voltage by the comparison module, it is possible to timely and accurately judge whether the power supply is interfered, and then output a corresponding detection signal.

[0079] In one embodiment of the present invention, a comparison module is used to determine whether the output voltage is greater than a reference voltage. If the output voltage is greater than the reference voltage, it is determined that the power supply is interfered with, and a detection signal is output. The detection signal is a high-level signal.

[0080] In this embodiment of the invention, the comparison module 102 can determine whether the power supply is interfered with based on the output voltage and the reference voltage. If the output voltage is greater than the reference voltage, it indicates that the power supply is interfered with, and a high-level signal can be output at this time. If the output voltage is not greater than the reference voltage, it indicates that the power supply is not interfered with, and a low-level signal can be output at this time. This invention can specifically detect scenarios where the power supply voltage rises abnormally by setting a reference voltage threshold.

[0081] In one embodiment of the present invention, such as Figure 3 The diagram illustrates a signal timing diagram provided by an embodiment of the present invention, used to explain the operation of the entire anti-interference circuit:

[0082] (1) When starting up and without interference: The reset signal RESET is a high-level signal: Before and during initial quantization, EOC = '0', and inverter NET1 = 1; after AND operation by the first logic processor, NET2 outputs a high-level signal: The ACMP_OUT detection signal outputs a low-level signal: Before and during initial quantization, EOC = 0, the inverter output NET1 = '1', ACMP_OUT = '0', and NET1 = '1'. After the second logic processor performs a NAND operation, the output signal NET3 is high. At this time, the flip-flop is not reset and is working normally. The third processing signal NET4 is consistent with the first processing signal NET2. When NET2 changes from low to high, i.e., a rising edge occurs, as shown below: Trigger 1034 can output the third processing signal NET4=VCC=1. After I5 AND operation, the second state feedback signal completely follows the EOC state, thus ensuring normal quantization and output after startup and before interference, that is, D1<11:0> is normally output before t1.

[0083] (2) When interference occurs, the power supply interference detection signal ACMP_OUT is a high-level signal: Before and during initial quantization, EOC = '0', and inverter NET1 outputs a high-level signal; after NAND operation by the second logic processor 1033', the output second processing signal NET3 is a low-level signal. At this point, the trigger is reset, and the third processing signal NET4 is '0'. Even if quantization is complete, a high pulse appears at EOC. After being processed by the third logic processor, EOC_NEW will still output '0'. That is, when the power supply is disturbed, after detection by the circuit design 3, EOC_NEW will shield the current EOC pulse, so that the quantized data disturbed by the power supply is filtered out and will not be output to the CPU, thus achieving the anti-interference capability of the motor application. That is, the digital signal D2<11:0> between t1 and t3 in the figure will not be output.

[0084] (3) When the interference is removed, although EOC is shielded and will not be output to the CPU, ACMP_OUT has become a low-level signal because the interference duration is very short. Before the initial quantization and during the quantization, the first state feedback signal EOC = '0', and the inverter outputs the first state feedback signal NET1 = '1' after inversion, which is a high-level signal.

[0085] After being processed by the second logic processor and NOT logic, the second processing signal NET3 is a high-level signal, the flip-flop is no longer in the reset state and is in the normal working state. The third processing signal will arrive with the rising edge of NET2, NET4 = VCC = 1. At this time, the second state feedback signal EOC_NEW completely follows the EOC state, thus ensuring that after startup, before the next interference, normal quantization and output are achieved, that is, D3<11:0> is output normally at this time.

[0086] Therefore, when the interference is removed, although the EOC high pulse that appeared under the current interference is blocked, the falling edge of the current EOC high pulse returns it to the normal working state without interference, and EOC_NEW follows EOC to output quantized data to the CPU as expected.

[0087] Until ACMP_OUT reappears, indicating that power supply interference is detected again, the EOC currently being generated during quantization is shielded again. The shielded EOC, namely EOC_NEW, is not output to the CPU. For example, when interference occurs again at t4, D4<11:0> is not output. After the interference is removed, the detection circuit returns to the normal quantization process until the next interference occurs, at which point the EOC affected by the interference is shielded again. This process is repeated to ultimately achieve the anti-interference design for motor applications.

[0088] In one embodiment of the present invention, the acquisition module includes a first resistor, a second resistor, and a third resistor. One end of the first resistor is connected to a power supply, the other end of the first resistor is connected to one end of the second resistor, the other end of the second resistor and one end of the third resistor are connected to a comparator, and the other end of the third resistor is grounded.

[0089] In this embodiment of the invention, to improve detection accuracy, the power supply voltage can be divided, that is, a first resistor R1, a second resistor R2, and a third resistor R3 are set in the acquisition module.

[0090] Assume VCC = 3V, VREF = 1V. After setting appropriate R1, R2, and R3 such that VCC * R3 / (R1 + R2 + R3) = 1V, the input of the comparison module 1022 is vip = vin = 1V. When VCC is interfered and the voltage value becomes 4V, then VCC * R3 / (R1 + R2 + R3) = 1.33V, while vref has a strong anti-interference ability and the voltage value becomes 1.1V. After comparison, a high level will be output, indicating that there is interference in the circuit at this time. By reasonably selecting the resistance values and precisely controlling the voltage division ratio, it is ensured that the comparator can receive an effective signal comparable to the reference voltage, which not only avoids the risk of damage to the subsequent circuit by high voltage but also provides a stable and reliable input signal for the comparison module, thereby improving the accuracy and safety of the entire detection component for power supply voltage monitoring.

[0091] In an embodiment of the present invention, VREF = 0.8V, the power supply voltage VCC = 3.3V. R1 and R3 can be understood as two options for adjustable voltages. One of the paths can be bypassed through switches VCC_NR_SW1 and VCC_NR_SW2. Only R1 or R2 participates in the voltage division of the circuit. For the convenience of analysis, here it is assumed that only R1 participates. The switch VCC_NR_SW1 corresponding to R1 is open, R2 does not participate, and the switch VCC_NR_SW1 corresponding to R2 is short-circuited. When VCC is interfered, the swing changes by 1V, and when VREF is interfered, the swing changes by 50mV. If normal interference detection is required without affecting normal operation, then:

[0092] R3 * (VCC + 1V) / (R1 + R3) > VREF + 50mV Formula (1)

[0093] R3 * (VCC) / (R1 + R3) < VREF Formula (2)

[0094] Substituting VCC = 3.3V and VREF = 0.8V into the simultaneous equations, the value ranges of R1 and R3 can be obtained: 2.5 / 0.8 < R1 / R3 < 3.45 / 0.85. To further ensure reliability, the actual fluctuation range of VCC, 3.3V ± 10%, that is, 2.97 - 3.63V, can be considered, and at the same time, the values of R1 and R3 can be increased to reduce power consumption. Similarly, R2 can also be designed in a similar way. By choosing different detection levels according to the value differences between R1 and R2, the flexibility of the detected interference degree value can be further improved.

[0095] In an embodiment of the present invention, the acquisition module is the bandgap basic unit of the microcontroller.

[0096] In this embodiment of the invention, the bandgap base unit is a high-precision voltage reference source inside the microcontroller. It has excellent temperature stability and is often used for high-precision voltage reference, which can significantly improve the accuracy of voltage acquisition. By utilizing the high precision and low temperature coefficient characteristics of the bandgap base unit, the power supply output voltage can be accurately acquired, and it has a strong ability to suppress interference power supply fluctuations.

[0097] In one embodiment of the present invention, the comparison module is a comparator of a microcontroller.

[0098] In this embodiment of the invention, the comparator integrated inside the MCU is less affected by external electromagnetic interference, and the shielding layer inside the chip can be used to reduce noise coupling. While ensuring detection accuracy and response speed, it significantly reduces hardware complexity and power consumption. It is especially suitable for embedded systems that are sensitive to cost, size and power consumption, such as smart home controllers and portable instruments. In actual tests in industrial environments, it can achieve real-time monitoring and rapid protection against power interference.

[0099] like Figure 2 When detecting interference, the comparator's channel selection signal PSEL can be used. <0> =1,NSEL <0> =1 indicates that the comparator's VIP channel selects the signal after the VCC voltage divider, and the comparator's VIN selects the VREF signal. This means the comparator is used in motor power supply interference monitoring mode. PSEL <0> =1,NSEL <0> =1 The two control signals are ANDed to control the high-current MOS gate terminal to make this high-current path conduct. At this time, the internal iadd current path is opened, and the comparator's operating current ib automatically increases, thereby speeding up the comparison speed.

[0100] This invention discloses an anti-interference circuit. An analog-to-digital converter (ADC) module converts the acquired voltage signal into a digital signal and outputs a first state feedback signal indicating its own reading status. A detection module detects the power supply and outputs a detection signal indicating whether the power supply is being interfered with. A control module receives these two signals and outputs a second state feedback signal. When the power supply is not interfered with, this second state feedback signal is consistent with the reading status indicated by the first state feedback signal, ensuring that the central processing unit (CPU) can accurately read the digital signal from the ADC module according to the second state feedback signal under normal conditions. However, when the power supply is interfered with and the first state feedback signal indicates that the ADC has completed reading, the second state feedback signal indicates that reading is incomplete. This prevents the CPU from erroneously reading data when power supply interference may lead to unreliable ADC results, thus avoiding the impact of interference on data reading. In this way, the circuit effectively controls the reading status of the ADC module under power supply interference, ensuring the accuracy and reliability of the CPU's digital signal reading, improving the overall circuit's anti-interference capability, and enhancing the accuracy of the data acquired by the ADC.

[0101] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0102] like Figure 4 The diagram shows a structural block diagram of a chip 20 provided in an embodiment of the present invention. The chip 20 may include the anti-interference circuit 10 described above.

[0103] This invention also provides an electrical device that includes the anti-interference circuit described above and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0104] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0105] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0106] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0107] The anti-interference circuit, chip, and electrical device provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An anti-interference circuit, characterized in that, The anti-interference circuit includes: An analog-to-digital converter module is used to convert the acquired voltage signal into a digital signal and output a first status feedback signal; the first status feedback signal is used to indicate the reading status of the analog-to-digital converter module. The detection module is used to detect the power supply and output a detection signal, which is used to indicate whether the power supply is being interfered with. A control module, connected to the analog-to-digital conversion module and the detection module, is used to receive the first state feedback signal and the detection signal, and output a second state feedback signal. The second state feedback signal is used to indicate the reading state of the analog-to-digital conversion module. When the detection signal indicates that the power supply is not interfered with, the reading state indicated by the second state feedback signal is the same as the reading state indicated by the first state feedback signal. When the detection signal indicates that the power supply is interfered with, if the first state feedback signal indicates that the analog-to-digital conversion module has completed reading, then the second state feedback signal indicates that the analog-to-digital conversion module has not completed reading. The central processing unit is connected to both the control module and the analog-to-digital converter module, and is used to receive the second status feedback signal and read the digital signal of the analog-to-digital converter module according to the second status feedback signal.

2. The anti-interference circuit according to claim 1, characterized in that, The control module includes: An inverter, connected to the analog-to-digital conversion module, is used to invert the first state feedback signal. A first logic processor, connected to the inverter, is used to acquire a reset signal and an inverted first state feedback signal, and to perform a logical AND operation on the reset signal and the inverted first state feedback signal to obtain a first processed signal. The second logic processor, connected to the inverter and the detection module, is used to acquire the detection signal and the inverted first state feedback signal, and to perform logical AND-NOT processing on the detection signal and the inverted first state feedback signal to obtain the second processed signal. A trigger is connected to the first logic processor and the second logic processor respectively, and is used to acquire the first processing signal and the second processing signal, determine whether to perform a reset based on the second processing signal, and output a third processing signal based on the reset status. A third logic processor is connected to the flip-flop and the central processing unit respectively, and is used to acquire the first state feedback signal and the third processing signal, and perform a logical AND operation on the third processing signal and the first state feedback signal to obtain a second state feedback signal.

3. The anti-interference circuit according to claim 2, characterized in that, The inverter is used to invert the first state feedback signal when the first state feedback signal is a high-level signal to obtain an inverted first state feedback signal, wherein the inverted first state feedback signal is a low-level signal.

4. The anti-interference circuit according to claim 3, characterized in that, The reset signal is a high-level signal. The first logic processor performs a logical AND operation on the inverted first state feedback signal and the reset signal to obtain the first processing signal, which is a low-level signal.

5. The anti-interference circuit according to claim 4, characterized in that, The detection signal is a high-level signal. The second logic processor performs a logical AND-NOT operation on the inverted first state feedback signal and the detection signal to obtain the second processed signal, which is a high-level signal.

6. The anti-interference circuit according to claim 5, characterized in that, The trigger is configured to not reset when the second processing signal is a high-level signal, and to output the third processing signal, which is a low-level signal.

7. The anti-interference circuit according to claim 6, characterized in that, The third logic processor is used to perform a logical AND operation on the third processing signal and the first state feedback signal to obtain the second state feedback signal, which is a low-level signal.

8. The anti-interference circuit according to claim 1, characterized in that, The detection component includes: Acquisition module, the acquisition module is used to acquire the output voltage of the power supply; The comparison module, connected to the acquisition module, is used to acquire the reference voltage and the output voltage, determine whether the power supply is interfered with based on the output voltage and the reference voltage, and output the detection signal.

9. The anti-interference circuit according to claim 8, characterized in that, The comparison module is used to determine whether the output voltage is greater than the reference voltage. If the output voltage is greater than the reference voltage, it is determined that the power supply is interfered with, and the detection signal is output. The detection signal is a high-level signal.

10. The anti-interference circuit according to claim 8, characterized in that, The acquisition module includes a first resistor, a second resistor, and a third resistor. One end of the first resistor is connected to the power supply, the other end of the first resistor is connected to one end of the second resistor, the other end of the second resistor and one end of the third resistor are connected to the comparator, and the other end of the third resistor is grounded.

11. The anti-interference circuit according to claim 8, characterized in that, The acquisition module is a bandgap basic unit of a microcontroller.

12. The anti-interference circuit according to claim 8, characterized in that, The comparison module is a comparator for a microcontroller.

13. A chip, characterized in that, The chip includes an anti-interference circuit as described in any one of claims 1-12.

14. An electrical appliance, characterized in that, The electrical equipment includes an anti-interference circuit as described in any one of claims 1-12.

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