An anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method

Abstract

This invention discloses an anti-interference delay-type NMOS high-side output overcurrent and short-circuit protection method, relating to the field of power semiconductor protection circuit technology. This method dynamically detects the NMOS transistor voltage difference through a voltage divider resistor network to generate a trigger difference voltage that adapts to the system voltage; it uses a high-voltage comparator directly connected to V... C The power supply and trigger voltage difference are significantly increased, effectively suppressing electromagnetic interference. The MCU control signal synchronously manages the U1 power supply switch and gate control circuit, combined with a multi-delay mechanism to delay comparator power-on and reference voltage establishment, collaboratively preventing MOS startup mis-triggering. When overcurrent or short circuit causes the voltage difference to exceed the threshold, the comparator outputs a high level to trigger protection: immediately pulling / CON0 low, quickly discharging the gate voltage to turn off the NMOS, and locking the protection until the CON0 level transitions to reset; when CON0 is low, the circuit has zero static power consumption. This method achieves full-condition short-circuit protection, improves anti-interference capability, and achieves near-zero static power consumption. Furthermore, the current limiting threshold can be flexibly set by adjusting the resistor or voltage divider coefficient.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor protection circuit technology, and in particular to an anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method. Background Technology

[0002] The rapid development of automotive electrical technology in recent years has brought about strong electromagnetic interference (EMI) phenomena. Control and acquisition signals are susceptible to interference, leading to severe EMI in normally operating automotive electrical systems. This can directly cause the electronic control unit (ECU) to receive incorrect signals, triggering system malfunctions. The vehicle's electronic controller is subject to electromagnetic interference from the external environment and from various components within the vehicle body. External EMI includes high-frequency electromagnetic pulses generated by lightning strikes or severe weather, and electromagnetic interference from external facilities such as high-voltage power lines and substations. Internal EMI arises from high-frequency electromagnetic waves generated by motors, pumps, and high-power devices, which can conduct or radiate through wires, interfering with other components. Bundled cables cause signal crosstalk, and switching operations trigger transient voltage surges. Sudden changes in wiring current or voltage cause instantaneous changes in the ground voltage relative to zero, affecting vehicle control signals and weak sampling signals. In the complex electromagnetic environment of the vehicle body, the electronic controller is susceptible to conducted and radiated interference from high-power devices such as motors and relays, resulting in high false trigger rates and high static power consumption in traditional protection circuits. If a low-voltage comparator (5V power supply) is used to detect the voltage difference of the MOSFET, its trigger threshold is limited (usually <200mV) and its anti-interference capability is insufficient.

[0003] Based on existing technologies, the core problems that this invention needs to solve include:

[0004] ① Anti-interference defect: The low-voltage comparator is prone to false triggering under EMC conditions in the vehicle body;

[0005] ② Risk of false triggering: The transient voltage drop during startup of the MOSFET overlaps with the short-circuit voltage drop, which cannot be distinguished by a single delay mechanism;

[0006] ③ NMOS transistor latch-up and failure to start: When the NMOS transistor is outputting high-side, an effective start-up control strategy, utilizing a comparator to detect voltage and a delay mechanism, allows the NMOS transistor to start normally. However, without comparator delay processing, NMOS transistor latch-up and failure to start may occur due to comparator issues. Summary of the Invention

[0007] In view of the aforementioned existing problems, the present invention is proposed.

[0008] Therefore, the present invention provides an anti-interference delay type NMOS high-side output overcurrent short-circuit protection method that solves the problems of anti-interference defects, false triggering risk, NMOS transistor lock-in and inability to start.

[0009] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0010] In a first aspect, the present invention provides an anti-interference delay type NMOS high-side output overcurrent short-circuit protection method, comprising the following steps:

[0011] S1. Dynamic differential voltage detection: The NMOS transistor differential voltage is acquired in real time through a voltage divider resistor network R1-R4. Generates voltage that varies with system voltage Adaptive trigger differential voltage The calculation formula is:

[0012]

[0013] in / This is the negative voltage divider coefficient. / This is the positive terminal voltage divider coefficient;

[0014] S2. High-voltage anti-interference comparison: A 32V high-voltage comparator U1 is used, whose operating voltage is controlled by CON0 and by... Direct power supply, when Output protection signal at the time;

[0015] S3. Multi-delay collaborative startup:

[0016] The delay is achieved by the R5-C3 circuit after Q4 is turned on. Then power is supplied to U1;

[0017] The R4-C2 circuit delays the establishment time of the positive terminal voltage. ;

[0018] Delay settling time via R19-C4 circuit This has a delay effect on the power supply to transistor Q4. The R19-C4 circuit is... and The first stage delay of the two delays ensures that the MOSFET is in Startup completes within the time limit;

[0019] S4. Protection Execution and Lockout: When U1 outputs a high level, NPN transistor Q1 immediately pulls down the / CON0 signal and discharges the gate voltage through the transistor. The voltage drops to 0V, locking the protection state until the CON0 level changes to reset; where CON0 represents a high-level active signal and / CON0 represents a low-level active signal.

[0020] S5. Optimized design for capacitive loads: adaptive delay adjustment;

[0021] The adaptive delay adjustment in the capacitive load optimization design of S5:

[0022] load capacitor Testing: A 1ms test pulse is injected into the MCU before startup, and the result is measured. Ascent Time ;

[0023] Dynamically configure delay parameters:

[0024] Forward delay capacitor C2: Constraints:

[0025] Power supply delay capacitors C3 and C4: Constraints:

[0026] in, Indicates the charging time of a capacitive load;

[0027] Anti-false triggering timing control:

[0028] Capacitive startup characteristic compensation:

[0029] The timing constraints are:

[0030] calculate:

[0031] The threshold value for enabling the load circuit. The on-resistance of the MOSFET;

[0032] Accidental trigger shielding mechanism: CON0 controls Q4 and Q5 to conduct. When U1 is not powered and U1 is not working, in... The comparator output is forcibly disabled during this period.

[0033] As a preferred embodiment of the anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method described in this invention, wherein the hardware implementation of the dynamic differential voltage detection in S1 is as follows:

[0034] Negative-terminal voltage divider circuit construction: (The text abruptly ends here, likely due to an incomplete sentence or One end is connected to the system voltage. The other end is connected to a resistor. and the negative input terminal of comparator U1; resistor The other end is grounded;

[0035] Negative terminal voltage divider point The calculation formula is: ;

[0036] Constructing a positive voltage divider circuit: Using resistors... One end connection The other end is connected to a resistor. and the positive input terminal of comparator U1; resistor The other end is grounded;

[0037] Positive terminal voltage divider point The calculation formula is: ;

[0038] Triggering condition determination: and Connect the negative and positive terminals of U1 respectively, and the comparator outputs a protection signal, triggered by the following condition: This triggering condition is equivalent to ;

[0039] Because MOSFETs have internal resistance, a voltage difference will be generated between the MOSFET and the resistive load RL; the larger the current, the larger the voltage difference; the voltage division coefficients of the positive and negative terminals can be adjusted so that the voltage at the negative terminal is higher than the voltage at the positive terminal under normal current.

[0040] As a preferred embodiment of the anti-interference delay-type NMOS high-side output overcurrent and short-circuit protection method described in this invention, wherein the anti-interference design of the high-voltage comparator U1 in S2 is as follows:

[0041] Extended operating voltage range: U1 supply voltage Directly taken from system voltage ;

[0042] U1 power supply switch circuit: CON0 is the control signal for the MCU, typically 5V or 3.3V; R18 and C4 act as a delay mechanism, delaying the conduction of Q5 and Q4. ;

[0043] Trigger voltage difference threshold: the minimum trigger voltage difference of U1 That is, the trigger voltage difference threshold Minimum trigger voltage difference of U1 The overcurrent and short-circuit protection current can be changed by adjusting the voltage division coefficient between the positive and negative input terminals of the comparator and adjusting the minimum trigger voltage difference.

[0044] Noise suppression verification: by setting a trigger voltage difference threshold The minimum signal change required to identify a real fault is significantly higher than the estimated peak value of the worst electromagnetic interference noise in the vehicle body. Then, apply corresponding noise interference in a high-intensity EMI test environment and observe whether the noise signal is always lower than the trigger voltage difference threshold. Only when the noise signal is consistently below the trigger voltage difference threshold. This is to ensure that noise does not falsely trigger the protection.

[0045] As a preferred embodiment of the anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method described in this invention, wherein: the multi-delay cooperative control of S3 specifically comprises:

[0046] U1 power supply delay circuit: When CON0 is high, transistor Q4 conducts after a delay, and the system power...

[0047] Pressure Resistor R5 charges capacitor C3, providing the operating voltage for comparator U1. powered by;

[0048] The power supply delay time is determined by R5, C3 and R19, C4:

[0049]

[0050] in Charging voltage for C3, The voltage between R5 and C3. Charging voltage for C4, This refers to the voltage between R19 and C4.

[0051] Forward delay circuit: Capacitor C2 is connected in parallel across resistor R4; Capacitor C4 is connected in parallel across resistor R19.

[0052] Both ends; when powered on, C2 and C4 discharge. V, charged with C2 and C4. Ascending along the exponential curve:

[0053]

[0054] ;

[0055] Delay time Defined as Time to reach 95% of steady-state value:

[0056] Among them, satisfying

[0057] The delay parameters satisfy:

[0058] in For load inductance, This is the on-resistance of the MOSFET to ensure that the MOSFET starts up completely;

[0059] Timing constraints:

[0060] in: Indicates the maximum startup time of the MOSFET; This indicates the interference pulse shielding window.

[0061] As a preferred embodiment of the anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method described in this invention, wherein: the protection execution circuit of S4 achieves rapid shutdown and state locking through a three-level linkage structure:

[0062] The protection control circuit consists of an NPN transistor Q1: when the comparator U1 outputs a high level, Q1 is turned on → / CON0 is pulled low to GND, and T1 is turned off; the SVG gate drive voltage discharges quickly, quickly turning off the MOSFET;

[0063] The gate voltage controlled switching circuit consists of a PNP transistor Q2 and an NPN transistor Q3: when / CON0 outputs a high level, Q3 turns on → Q2 turns on → MOS transistor T1 turns on;

[0064] When CON0 changes from low to high, the MOSFET turns on. If the load on the MOSFET is too heavy or short-circuited, the steady-state time of the MOSFET output will be greater than the delay time. When the comparator outputs a high level, protection control will be activated and locked. When the MOSFET output reaches a steady state, if the MOSFET is overloaded or short-circuited, the voltage drop across the MOSFET and RL will increase. When the voltage difference reaches the trigger voltage, protection control will be activated and locked. Both processes can achieve short-circuit protection.

[0065] Gate discharge circuit: When Q1 is on, the short-circuit current protection circuit activates, causing rapid discharge; when T1 is switching normally, the gate drive voltage... via discharge channel The resistor discharges to ground.

[0066] As a preferred embodiment of the anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method described in this invention, wherein: the protection locking mechanism of S4 is as follows:

[0067] Hardware locking layer:

[0068] / CON0 forced pull-low circuit: When protection is triggered, Q3 turns on → / CON0 is collected by Q1

[0069] The emitter-pole path and D1 are pulled down to GND → Q3 is cut off → Q2 is cut off;

[0070] Self-holding bias network: Resistors R8 and R9 are connected in parallel between the base and emitter of Q3 to form a voltage divider holding circuit.

[0071]

[0072] When Q3 is turned on, as long as / CON0 outputs a high level, U1 outputs a high level, and Q1 remains on, i.e., locked. When U1 outputs a protection control signal, MOSFET T1 turns off. =0, =0, regardless Whether the load fault is cleared or not, U1 always outputs a protection control signal that is locked.

[0073] U1 power supply control: After CON0 outputs a low level, Q5 is cut off → cutting off the power supply to comparator U1. When the power supply switch circuit of U1 is disconnected, U1 is de-energized and reset; this eliminates the possibility of false triggering, and the static power consumption is close to 0 μA.

[0074] Software locking layer:

[0075] Dual-condition fault status detection:

[0076] Voltage threshold: The proportional threshold is compatible with 12V / 24V systems;

[0077] Control signal status: MCU output CON0 is high, logic "1";

[0078] That is, when the MCU outputs CON0 at a high level and detects... When CON0 is low, the MCU actively pulls it low and maintains it low until the system is reset.

[0079] Lockout Execution: When the protection condition is met, U1 outputs a high level, Q1 conducts, and the gate voltage of T1... Pull down, T1 cutoff, Output low level, When V and CON0 output a high level, Q4 is turned on. When the output is high, U1 outputs a high level, locking the state and maintaining it unchanged.

[0080] Unlock conditions: A high-low-high transition in CON0 level resets the self-holding circuit; or a system power failure followed by a restart in a 12V system. A drop below 7V lasting >5ms or in a 24V system If the voltage drops below 15V, a power monitoring signal is generated; or a forced reset command is executed. The interface receives the ISO 14229-1 0x11 service code, and the MCU performs a watchdog reset.

[0081] As a preferred embodiment of the anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method described in this invention, wherein: the triggering protection mechanism of S4 is as follows:

[0082] when When U1 outputs a high level, it triggers protection and activates the differential voltage.

[0083] Internal resistance of MOSFET and protection current Decide: During the protection lockout period, / CON0 is forced to a low level, and the gate discharge circuit discharges during the discharge time. Internal shutdown MOSFET.

[0084] In a second aspect, the present invention provides a computer device, including a memory and a processor, wherein the memory stores a computer program, wherein when the computer program is executed by the processor, it implements any step of the anti-interference delay type NMOS high-side output overcurrent short-circuit protection method as described in the first aspect of the present invention.

[0085] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the anti-interference delay type NMOS high-side output overcurrent short-circuit protection method as described in the first aspect of the present invention.

[0086] The anti-interference delay-type NMOS high-side output overcurrent and short-circuit protection method provided by this invention achieves multiple significant benefits through systematic innovative design: First, this method creatively uses a high-voltage comparator directly connected to the system voltage V C (12V / 24V) power supply, operating voltage range extended to 8-32V, trigger differential voltage The voltage is increased to more than five times that of a traditional 5V comparator (typical value >1V), reducing the false trigger rate of the circuit to below 0.1% under the severe electromagnetic interference environment specified by the ISO 7637-2 standard, completely solving the problem of protection malfunction caused by strong interference sources such as vehicle motors and relays. Secondly, the unique multi-delay coordination mechanism delays the comparator's power-on through a power supply delay circuit, while simultaneously delaying the establishment of the reference voltage through a positive-side delay circuit, and constraining timing relationships. This ensures that the MOSFET obtains sufficient stabilization time under heavy-load startup or capacitive load scenarios, and dynamically adjusts... The design can adaptively match different load characteristics. Furthermore, the protection execution stage innovatively adopts a gate discharge structure to achieve gate voltage turn-off, greatly reducing losses during MOSFET protection, and can be dual-monitored via MCU software. With a low level and CON0 high level, a dual locking mechanism of hardware self-holding and software locking is constructed, compressing the static power consumption in the locked state to <10μA. Simultaneously, the reset process introduces CON0 transition timing constraints and a hard reset by the power monitoring IC to avoid false locking caused by electrostatic interference. Ultimately, this solution only requires adjusting the voltage divider resistor ratio to set the current limiting threshold, eliminating the need for additional current sampling devices, thus providing a highly reliable and ultra-low power protection solution for intelligent vehicle power management. Attached Figure Description

[0087] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0088] Figure 1 This is a circuit schematic diagram of an anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method.

[0089] Figure 2 This is a flowchart illustrating the process of an anti-interference delay-type NMOS high-side output overcurrent and short-circuit protection method. Detailed Implementation

[0090] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0091] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0092] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0093] Figure 1 is a circuit schematic diagram of the present invention;

[0094] in, System voltage: The vehicle body is typically 24V or 12V.

[0095] The high-side gate drive voltage of an NMOS transistor is higher than that of a standard NMOS transistor. The voltage is approximately 10V.

[0096] : MOS output voltage;

[0097] CON0: Control signal output by the processing unit, typically 5V or 3.3V;

[0098] U1: Comparator;

[0099] Q: Three-stage tube;

[0100] T: MOSFET;

[0101] D1: One-way conduction diode, to prevent the gate voltage from being connected to the / CON0 control voltage and affecting the switching of the gate voltage control switching circuit;

[0102] RL: Current limiting protection resistor.

[0103] Referring to Figure 1, which is an embodiment of the present invention, this embodiment provides an anti-interference delay type NMOS high-side output overcurrent short circuit protection method, which consists of four parts: voltage detection circuit, protection control circuit, U1 power supply switch circuit, and gate voltage control switch circuit.

[0104] Because MOSFETs have internal resistance, a voltage difference will be generated between the MOSFET and the resistive load RL; the larger the current, the larger the voltage difference. The voltage divider ratios at the positive and negative terminals can be adjusted so that, under normal current conditions, the voltage at the negative terminal is higher than the voltage at the positive terminal.

[0105] U1ra = R3 / R4 is the positive terminal voltage divider coefficient, and U2ra = R1 / R2 is the negative terminal voltage divider coefficient.

[0106] Voltage value lower than The difference in voltage values, and at this time the comparator triggers a high-level output, this voltage difference is called the trigger difference voltage.

[0107] When the MOSFET is outputting and there is no load, the voltage difference between the positive and negative input terminals of U1 is called the trigger input voltage difference.

[0108] In the normal output mode of the MOSFET, the voltage at the negative input terminal of U1 is higher than the voltage at the positive input terminal; when the voltage at the negative input terminal of the comparator is lower than the voltage at the positive input terminal, the comparator will output a high voltage signal, which is called a protection signal.

[0109] U1 is a high-voltage comparator. The operating voltage of U1 is controlled by the power supply switching circuit of U1, which is controlled by CON0. The voltage is turned on and off; R5, C3 and R19, C4 constitute the power supply delay circuit for U1.

[0110] R4 and C2 form a delay circuit for the negative input terminal, which is called the positive input delay circuit.

[0111] When the MCU issues a control command, and CON0 changes from low to high, the U1 power supply switch circuit supplies power to the comparator through the U1 power supply delay circuit. The power supply is provided, and the positive terminal delay circuit delays the rise of the positive terminal voltage. During this delay period, the output voltage of the MOSFET rises to a steady state of normal output voltage, allowing the MOSFET to output normally and avoiding triggering the protection.

[0112] When the MCU controls the MOSFET to conduct and power on, if the MOSFET is overloaded or short-circuited, the steady-state time of the MOSFET output will be greater than the delay time. The comparator outputs a high level, and the protection control circuit will play a protective role by pulling the CON0 signal low and simultaneously discharging the SVG gate drive voltage quickly to turn off the MOSFET. This process is called protection control.

[0113] This is the short-circuit overcurrent protection process upon power-up, and the protection control will remain locked until CON0 returns to a low level and then goes high again. During this protection control process, the protection circuit needs to re-detect and re-control. The process of CON0 changing from a high level to a low level and then back to a high level is called the control signal change.

[0114] Alternatively, a combination of hardware and software can be used. The MCU detects the output state of the MOSFET and makes a logical judgment. If CON0 is high and the MOSFET output is low, the MCU knows that the protection circuit is in the protection control state. The MCU will no longer output CON0 high and will keep the protection circuit in the protection lockout state until the MCU system is powered on again.

[0115] Once the MOSFET output reaches a steady state, if the MOSFET is overloaded or short-circuited, the voltage drop across the MOSFET and RL increases. When this voltage reaches the trigger differential voltage, the protection control is activated and the MOSFET is locked. This is the short-circuit and overcurrent protection during MOSFET operation.

[0116] Referring to Figure 2, which illustrates a second embodiment of the present invention, this embodiment provides an anti-interference delay type NMOS high-side output overcurrent short-circuit protection method, comprising the following steps:

[0117] S1. Dynamic differential voltage detection: The NMOS transistor differential voltage is acquired in real time through a voltage divider resistor network R1-R4. Generates voltage that varies with system voltage Adaptive trigger differential voltage The calculation formula is:

[0118]

[0119] in / This is the negative voltage divider coefficient. / This is the positive terminal voltage divider coefficient;

[0120] S2. High-voltage anti-interference comparison: A 32V high-voltage comparator U1 is used, whose operating voltage is controlled by CON0 and by... Direct power supply, when Output protection signal at the time;

[0121] S3. Multi-delay collaborative startup:

[0122] The delay is achieved by the R5-C3 circuit after Q4 is turned on. Then power is supplied to U1;

[0123] The R4-C2 circuit delays the establishment time of the positive terminal voltage. ;

[0124] Delay settling time via R19-C4 circuit This has a delay effect on the power supply to transistor Q4. The R19-C4 circuit is... and The first stage delay of the two delays ensures that the MOSFET is in Startup completes within the time limit;

[0125] S4. Protection Execution and Lockout: When U1 outputs a high level, NPN transistor Q1 immediately pulls down the / CON0 signal and discharges the gate voltage through the transistor. The voltage drops to 0V, locking the protection state until the CON0 level changes to reset; where CON0 represents a high-level active signal and / CON0 represents a low-level active signal.

[0126] S5. Optimized design for capacitive loads: adaptive delay adjustment.

[0127] The hardware implementation of dynamic differential pressure detection in S1 is as follows:

[0128] Negative-terminal voltage divider circuit construction: (The text abruptly ends here, likely due to an incomplete sentence or One end is connected to the system voltage. The other end is connected to a resistor. and the negative input terminal of comparator U1; resistor The other end is grounded;

[0129] Negative terminal voltage divider point The calculation formula is: ;

[0130] Constructing a positive voltage divider circuit: Using resistors... One end connection The other end is connected to a resistor. and the positive input terminal of comparator U1; resistor The other end is grounded;

[0131] Positive terminal voltage divider point The calculation formula is: ;

[0132] Triggering condition determination: and Connect the negative and positive terminals of U1 respectively, and the comparator outputs a protection signal, triggered by the following condition: This triggering condition is equivalent to ;

[0133] Because MOSFETs have internal resistance, a voltage difference will be generated between the MOSFET and the resistive load RL; the larger the current, the larger the voltage difference; the voltage division coefficients of the positive and negative terminals can be adjusted so that the voltage at the negative terminal is higher than the voltage at the positive terminal under normal current.

[0134] The anti-interference design of the high-voltage comparator U1 in S2 is as follows:

[0135] Extended operating voltage range: U1 supply voltage Directly taken from system voltage ;

[0136] U1 power supply switch circuit: CON0 is the control signal for the MCU, typically 5V or 3.3V; R18 and C4 act as a delay mechanism, delaying the conduction of Q5 and Q4. ;

[0137] Trigger voltage difference threshold: the minimum trigger voltage difference of U1 That is, the trigger voltage difference threshold Minimum trigger voltage difference of U1 The overcurrent and short-circuit protection current can be changed by adjusting the voltage division coefficient between the positive and negative input terminals of the comparator and adjusting the minimum trigger voltage difference.

[0138] Noise suppression verification: by setting a trigger voltage difference threshold The minimum signal change required to identify a real fault is significantly higher than the estimated peak value of the worst electromagnetic interference noise in the vehicle body. Then, apply corresponding noise interference in a high-intensity EMI test environment and observe whether the noise signal is always lower than the trigger voltage difference threshold. Only when the noise signal is consistently below the trigger voltage difference threshold. This is to ensure that noise does not falsely trigger the protection.

[0139] The S3 multi-delay cooperative control is specifically as follows:

[0140] U1 power supply delay circuit: When CON0 is high, transistor Q4 conducts after a delay, and the system power...

[0141] Pressure Resistor R5 charges capacitor C3, providing the operating voltage for comparator U1. powered by;

[0142] The power supply delay time is determined by R5, C3 and R19, C4:

[0143]

[0144] in Charging voltage for C3, The voltage between R5 and C3. Charging voltage for C4, This refers to the voltage between R19 and C4.

[0145] Forward delay circuit: Capacitor C2 is connected in parallel across resistor R4; Capacitor C4 is connected in parallel across resistor R19.

[0146] Both ends; when powered on, C2 and C4 discharge. V, charged with C2 and C4. Ascending along the exponential curve:

[0147]

[0148] ;

[0149] Delay time Defined as Time to reach 95% of steady-state value:

[0150] Among them, satisfying

[0151] The delay parameters satisfy:

[0152] in For load inductance, This is the on-resistance of the MOSFET to ensure that the MOSFET starts up completely;

[0153] Timing constraints:

[0154] in: Indicates the maximum startup time of the MOSFET; This indicates the interference pulse shielding window.

[0155] The protection execution circuit of S4 achieves rapid shutdown and status locking through a three-level linkage structure:

[0156] The protection control circuit consists of an NPN transistor Q1: when the comparator U1 outputs a high level, Q1 is turned on → / CON0 is pulled low to GND, and T1 is turned off; the SVG gate drive voltage discharges quickly, quickly turning off the MOSFET;

[0157] The gate voltage controlled switching circuit consists of a PNP transistor Q2 and an NPN transistor Q3: when / CON0 outputs a high level, Q3 turns on → Q2 turns on → MOS transistor T1 turns on;

[0158] When CON0 changes from low to high, the MOSFET turns on. If the load on the MOSFET is too heavy or short-circuited, the steady-state time of the MOSFET output will be greater than the delay time. When the comparator outputs a high level, protection control will be activated and locked. When the MOSFET output reaches a steady state, if the MOSFET is overloaded or short-circuited, the voltage drop across the MOSFET and RL will increase. When the voltage difference reaches the trigger voltage, protection control will be activated and locked. Both processes can achieve short-circuit protection.

[0159] Gate discharge circuit: When Q1 is on, the short-circuit current protection circuit activates, causing rapid discharge; when T1 is switching normally, the gate drive voltage... via discharge channel The resistor discharges to ground.

[0160] S4's protection and locking mechanism is as follows:

[0161] Hardware locking layer:

[0162] / CON0 forced pull-low circuit: When protection is triggered, Q3 turns on → / CON0 is collected by Q1

[0163] The emitter-pole path and D1 are pulled down to GND → Q3 is cut off → Q2 is cut off;

[0164] Self-holding bias network: Resistors R8 and R9 are connected in parallel between the base and emitter of Q3 to form a voltage divider holding circuit.

[0165]

[0166] When Q3 is turned on, as long as / CON0 outputs a high level, U1 outputs a high level, and Q1 remains on, i.e., locked. When U1 outputs a protection control signal, MOSFET T1 turns off. =0, =0, regardless Whether the load fault is cleared or not, U1 always outputs a protection control signal that is locked.

[0167] U1 power supply control: After CON0 outputs a low level, Q5 is cut off → cutting off the power supply to comparator U1. When the power supply switch circuit of U1 is disconnected, U1 is de-energized and reset; this eliminates the possibility of false triggering, and the static power consumption is close to 0 μA.

[0168] Software locking layer:

[0169] Dual-condition fault status detection:

[0170] Voltage threshold: The proportional threshold is compatible with 12V / 24V systems;

[0171] Control signal status: MCU output CON0 is high, logic "1";

[0172] That is, when the MCU outputs CON0 at a high level and detects... When CON0 is low, the MCU actively pulls it low and maintains it low until the system is reset.

[0173] Lockout Execution: When the protection condition is met, U1 outputs a high level, Q1 conducts, and the gate voltage of T1... Pull down, T1 cutoff, Output low level, When V and CON0 output a high level, Q4 is turned on. When the output is high, U1 outputs a high level, locking the state and maintaining it unchanged.

[0174] Unlock conditions: A high-low-high transition in CON0 level resets the self-holding circuit; or a system power failure followed by a restart in a 12V system. A drop below 7V lasting >5ms or in a 24V system If the voltage drops below 15V, a power monitoring signal is generated; or a forced reset command is executed. The interface receives the ISO 14229-1 0x11 service code, and the MCU performs a watchdog reset.

[0175] The trigger protection mechanism of S4 is as follows:

[0176] when When U1 outputs a high level, it triggers protection and activates the differential voltage.

[0177] Internal resistance of MOSFET and protection current Decide: During the protection lockout period, / CON0 is forced to a low level, and the gate discharge circuit discharges during the discharge time. Internal shutdown MOSFET.

[0178] Adaptive delay adjustment in the capacitive load optimization design of S5:

[0179] load capacitor Testing: A 1ms test pulse is injected into the MCU before startup, and the result is measured. Ascent Time ;

[0180] Dynamically configure delay parameters:

[0181] Forward delay capacitor C2: Constraints:

[0182] Power supply delay capacitors C3 and C4: Constraints:

[0183] in, Indicates the charging time of a capacitive load;

[0184] Anti-false triggering timing control:

[0185] Capacitive startup characteristic compensation:

[0186] The timing constraints are:

[0187] calculate:

[0188] Set the threshold for the load circuit to open;

[0189] Accidental trigger shielding mechanism: CON0 controls Q4 and Q5 to conduct. When U1 is not powered and U1 is not working, in... The comparator output is forcibly disabled during this period.

[0190] The following is the workflow of an embodiment of an anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method:

[0191] S1. Dynamic differential pressure detection

[0192] The system uses a precision voltage divider resistor network to collect the voltage difference across the NMOS transistor in real time, and generates a trigger threshold voltage that automatically adjusts with the system power supply voltage based on the resistor ratio. This threshold is not a fixed value, but dynamically changes according to fluctuations in the 12V or 24V vehicle body power supply to ensure consistent protection under different operating conditions.

[0193] S2. High Voltage Interference Immunity Comparison

[0194] A high-voltage comparator with an operating voltage range of 8-32V is used, directly powered by the vehicle body power supply (not the traditional 5V). When the NMOS transistor voltage difference exceeds the dynamic threshold, the comparator outputs a high-level protection signal. The high-voltage design increases the trigger threshold to more than 5 times that of traditional solutions, significantly suppressing electromagnetic interference generated by motors, relays, etc.

[0195] S3. Multi-delay collaborative startup

[0196] Power supply delay: After the MCU sends a high-level control signal, the power supply to the comparator is delayed by a resistor-capacitor circuit to avoid the instantaneous voltage surge caused by vehicle electromagnetic interference.

[0197] Forward delay: Synchronous delay to establish the reference voltage at the positive terminal of the comparator, ensuring that the comparator only starts working after the NMOS transistor has fully started up under heavy load or capacitive load conditions.

[0198] Multiple delays create a time difference protection window, completely resolving the problem of accidental triggering at startup.

[0199] When the MCU outputs the CON0 control signal, it transitions from low to high, triggering the parallel startup of the multi-delay link: First, the system voltage... (24V) The capacitor C3 is charged through resistor R5, and its voltage rises exponentially. After t1, the voltage of C3 reaches the stable operating voltage. At this time, the V of comparator U1 is... CC The pin receives a stable operating voltage, completing the comparator power-on preparation; simultaneously, the CON0 transition synchronously activates the positive input delay circuit. Since the initial voltage of capacitor C2 is 0V, the comparator's positive input... As C2 charges via R4, The voltage rises gradually and reaches a steady-state value only after t2. Within this collaborative delay window (between t1 and t2), the MOS transistor gate drive voltage V... G Load current is established via a charge pump. From 0A to the rated value; key timing constraints ensure that after t2... The effective threshold has been reached; at this point, the MOSFET has already completed startup and meets the requirements. Normal operating conditions are ensured, completely avoiding false triggering caused by startup surges.

[0200] S4. Protection Execution and Locking

[0201] When the comparator triggers protection, it immediately performs three steps:

[0202] 1. Forcefully pull the MCU control signal low to ground potential to cut off the comparator power supply;

[0203] 2. The gate voltage is brought to zero in a very short time through the transistor discharge circuit, quickly turning off the NMOS transistor;

[0204] 3. Activate the hardware self-locking circuit to maintain the protection state, and the static current drops to 8.7 microamps.

[0205] The locked state requires the MCU control signal to complete a "high-low-high" transition, the system to be powered off and restarted, or a forced reset command to unlock.

[0206] S5. Capacitive Load Optimization

[0207] Adaptive delay: The MCU injects a test pulse to measure the load capacitance value and adjusts the startup delay parameter proportionally to ensure smooth startup of large capacitive loads.

[0208] Achieving a closed-loop technological advantage:

[0209] 1. Startup Phase: Multiple delay mechanisms (S3) shield transient interference, and capacitive optimization (S5) ensures reliable startup for various loads;

[0210] 2. Operation phase: Real-time monitoring of pressure difference using dynamic detection (S1) and high-pressure comparison (S2);

[0211] 3. Fault Response: Fast shutdown (S4) protects power devices;

[0212] 4. Energy efficiency management: After protection lockout, the static current drops to the microampere level (S4), meeting the most stringent automotive-grade low power consumption standards.

[0213] Actual test results: In the 2000μF capacitive load and 200A short circuit impact test, the present invention achieved zero false triggering and 100% successful protection, with static power consumption only 2% of the traditional solution.

[0214] This embodiment also provides a computer device applicable to an anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method, comprising: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method proposed in the above embodiment.

[0215] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0216] This embodiment also provides a storage medium storing a computer program. When executed by a processor, the program implements an anti-interference delay-type NMOS high-side output overcurrent short-circuit protection method as proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0217] The anti-interference delay-type NMOS high-side output overcurrent and short-circuit protection method provided by this invention achieves multiple significant benefits through systematic and innovative design:

[0218] 1. Comparator U1 is a high-voltage comparator; its operating voltage is controlled by CON0. C The system voltage and operating voltage can reach up to 32V. The input voltage difference of the trigger is relatively large. Compared with the comparator that operates at 5V, the voltage difference can be more than 5 times larger, which significantly improves its anti-interference ability.

[0219] 2. Both the gate voltage control switch circuit and the U1 power supply switch circuit are controlled by CON0. When CON0 is low, the circuit does not consume power, which can effectively reduce static power consumption.

[0220] 3. When protection control occurs, the SVG voltage can be discharged quickly, and the MOSFET can be turned off quickly, effectively reducing the loss of the MOSFET.

[0221] 4. This protection circuit uses a comparator to detect the voltage difference across the MOSFET, and the reference voltage at the positive terminal of the comparator is not a fixed value, but rather varies with V. C The condition for the comparator to output a high level, which varies with the value, is only related to the voltage difference across the MOSFET.

[0222] 5. The U1 power supply delay circuit and the positive terminal delay circuit are used to enable the MOSFET to start normally.

[0223] 6. This circuit is a hardware short-circuit and overcurrent protection circuit. When the MOS output voltage is overcurrent or short-circuited, the short-circuit and overcurrent protection circuit can protect the MOS from damage by short circuit in real time and lock the protection until the control signal changes.

[0224] 7. It can effectively protect against short circuits or overloads before the MOSFET is turned on and started, as well as short circuits or overloads after the MOSFET is working normally.

[0225] 8. Adjusting the value of RL or changing the internal resistance of T1 can change the magnitude of the current limiting protection current.

[0226] In summary, firstly, this method innovatively employs a high-voltage comparator directly derived from the system voltage V. C (12V / 24V) power supply, operating voltage range extended to 8-32V, trigger differential voltage The voltage is increased to more than five times that of a traditional 5V comparator (typical value >1V), reducing the false trigger rate of the circuit to below 0.1% under the severe electromagnetic interference environment specified by the ISO 7637-2 standard, completely solving the problem of protection malfunction caused by strong interference sources such as vehicle motors and relays. Secondly, the unique multi-delay coordination mechanism delays the comparator's power-on through a power supply delay circuit, while simultaneously delaying the establishment of the reference voltage through a positive-side delay circuit, and constraining timing relationships. This ensures that the MOSFET obtains sufficient stabilization time under heavy-load startup or capacitive load scenarios, and dynamically adjusts... The design can adaptively match different load characteristics. Furthermore, the protection execution stage innovatively adopts a gate discharge structure to achieve gate voltage turn-off, greatly reducing losses during MOSFET protection, and can be dual-monitored via MCU software. With a low level and CON0 high level, a dual locking mechanism of hardware self-holding and software locking is constructed, compressing the static power consumption in the locked state to <10μA. Simultaneously, the reset process introduces CON0 transition timing constraints and a hard reset by the power monitoring IC to avoid false locking caused by electrostatic interference. Ultimately, this solution only requires adjusting the voltage divider resistor ratio to set the current limiting threshold, eliminating the need for additional current sampling devices, thus providing a highly reliable and ultra-low power protection solution for intelligent vehicle power management.

[0227] Example 3, referring to Table 1, is the third embodiment of the present invention. To further verify the technical solution of the present invention, the following are the experimental simulation data of Example 3, which are verified based on the key technical indicators of an anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method:

[0228] The details are shown in Table 1 below:

[0229] Table 1: Simulation Verification Results of Key Technical Indicators

[0230]

[0231] This embodiment is verified through systematic experiments:

[0232] Anti-interference performance: False trigger rate of 0.05% under 200V / m radiated field, meeting the most stringent level of ISO 11452-4;

[0233] Startup reliability: 100% success rate for starting a 2000μF capacitive load;

[0234] In summary, this invention provides a highly reliable, ultra-fast, and zero-malfunction protection solution for high-side drive systems in intelligent vehicles.

[0235] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for overcurrent and short-circuit protection of high-side output of an anti-interference delay type NMOS, characterized in that, Includes the following steps: S1. Dynamic differential voltage detection: The NMOS transistor differential voltage is acquired in real time through a voltage divider resistor network R1-R4. Generates voltage that varies with system voltage Adaptive trigger differential voltage The calculation formula is: ； in / This is the negative voltage divider coefficient. / This is the positive terminal voltage divider coefficient; S2. High-voltage anti-interference comparison: A 32V high-voltage comparator U1 is used, whose operating voltage is controlled by CON0 and by... Direct power supply, when Output protection signal at the time; S3. Multi-delay collaborative startup: The delay is achieved by the R5-C3 circuit after Q4 is turned on. Then power is supplied to U1; The R4-C2 circuit delays the establishment time of the positive terminal voltage. ; Delay settling time via R19-C4 circuit This has a delay effect on the power supply to transistor Q4. The R19-C4 circuit is... and The first stage delay of the two delays ensures that the MOSFET is in Startup completes within the time limit; S4. Protection Execution and Lockout: When U1 outputs a high level, NPN transistor Q1 immediately pulls down the / CON0 signal and discharges the gate voltage through the transistor. The voltage drops to 0V, locking the protection state until the CON0 level changes to reset; where CON0 represents a high-level active signal and / CON0 represents a low-level active signal. S5. Optimized design for capacitive loads: adaptive delay adjustment; The adaptive delay adjustment in the capacitive load optimization design of S5: load capacitor Testing: A 1ms test pulse is injected into the MCU before startup, and the result is measured. Ascent Time ; Dynamically configure delay parameters: Forward delay capacitor C2: Constraints: ; Power supply delay capacitors C3 and C4: Constraints: ; in, Indicates the charging time of a capacitive load; Anti-false triggering timing control: Capacitive startup characteristic compensation: The timing constraints are: ; calculate: ; The threshold value for enabling the load circuit. The on-resistance of the MOSFET; False trigger shielding mechanism: CON0 controls Q4 and Q5 to conduct. When U1 is not powered and U1 is not working, in... The comparator output is forcibly disabled during this period.

2. The anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method as described in claim 1, characterized in that... The hardware implementation of dynamic differential pressure detection in S1 is as follows: Construction of negative terminal voltage divider circuit: Using resistors One end is connected to the system voltage. The other end is connected to a resistor. and the negative input terminal of comparator U1; resistor The other end is grounded; Negative terminal voltage divider point The calculation formula is: ; Constructing a positive voltage divider circuit: Using resistors... One end connection The other end is connected to a resistor. and the positive input terminal of comparator U1; resistor The other end is grounded; Positive terminal voltage divider point The calculation formula is: ; Triggering condition determination: and Connect the negative and positive terminals of U1 respectively, and the comparator outputs a protection signal, triggered by the following condition: This triggering condition is equivalent to ; Because the MOSFET has internal resistance, a voltage difference will be generated between the MOSFET and the resistive load RL; the larger the current, the larger the voltage difference; by adjusting the voltage division coefficients of the positive and negative terminals, the voltage at the negative terminal will be higher than the voltage at the positive terminal under normal current conditions.

3. The anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method as described in claim 2, characterized in that... The anti-interference design of the high-voltage comparator U1 in S2 is as follows: Extended operating voltage range: U1 supply voltage Taken directly from system voltage ; U1 power supply switch circuit: CON0 is the control signal for the MCU, typically 5V or 3.3V; R18 and C4 act as a delay mechanism, delaying the conduction of Q5 and Q4. ; Trigger voltage difference threshold: the minimum trigger voltage difference of U1 That is, the trigger voltage difference threshold Minimum trigger voltage difference of U1 The overcurrent and short-circuit protection current can be changed by adjusting the voltage division coefficient between the positive and negative input terminals of the comparator and adjusting the minimum trigger voltage difference. Noise suppression verification: by setting a trigger voltage difference threshold The minimum signal change required to identify a real fault is significantly higher than the estimated peak value of the worst electromagnetic interference noise in the vehicle body. Then, apply corresponding noise interference in a high-intensity EMI test environment and observe whether the noise signal is always lower than the trigger voltage difference threshold. Only when the noise signal is consistently below the trigger voltage difference threshold. This is to ensure that noise does not falsely trigger the protection.

4. The anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method as described in claim 3, characterized in that, The multi-delay coordinated control of S3 specifically refers to: U1 power supply delay circuit: When CON0 is high, transistor Q4 conducts after a delay, and the system voltage... Resistor R5 charges capacitor C3, providing the operating voltage for comparator U1. powered by; The power supply delay time is determined by R5, C3 and R19, C4: in Charging voltage for C3, The voltage between R5 and C3. The charging voltage for C4 is = This refers to the voltage between R19 and C4. Forward delay circuit: Capacitor C2 is connected in parallel across resistor R4; Capacitor C4 is connected in parallel across resistor R19. Both ends; when powered on, C2 and C4 discharge. V, charged with C2 and C4. Ascending along the exponential curve: ； ； Delay time Defined as Time to reach 95% of steady-state value: Among them, satisfying ; The delay parameters satisfy: in For load inductance, This is the on-resistance of the MOSFET to ensure that the MOSFET starts up completely; Timing constraints: ; in: Indicates the maximum startup time of the MOSFET; This indicates the interference pulse shielding window.

5. The anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method as described in claim 4, characterized in that... The protection execution circuit of S4 achieves rapid shutdown and state locking through a three-level linkage structure: The protection control circuit consists of an NPN transistor Q1: when the comparator U1 outputs a high level, Q1 is turned on → / CON0 is pulled low to GND, and T1 is turned off; the SVG gate drive voltage discharges quickly, quickly turning off the MOSFET; The gate voltage controlled switching circuit consists of a PNP transistor Q2 and an NPN transistor Q3: when / CON0 outputs a high level, Q3 turns on → Q2 turns on → MOS transistor T1 turns on; When CON0 changes from low to high, the MOSFET turns on. If the load on the MOSFET is too heavy or short-circuited, the steady-state time of the MOSFET output will be greater than the delay time. When the comparator outputs a high level, protection control will be activated and locked. When the MOSFET output reaches a steady state, if the MOSFET is overloaded or short-circuited, the voltage drop across the MOSFET and RL will increase. When the voltage difference reaches the trigger voltage, protection control will be activated and locked. Both processes can achieve short-circuit protection. Gate discharge circuit: When Q1 is on, the short-circuit current protection circuit activates, causing rapid discharge; during normal switching of T1, the gate drive voltage... via discharge channel The resistor discharges to ground.

6. The anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method as described in claim 5, characterized in that, The protection locking mechanism of S4 is as follows: Hardware locking layer: / CON0 forced pull-low circuit: When protection is triggered, Q3 turns on → / CON0 is collected by Q1 The emitter-pole path and D1 are pulled down to GND → Q3 is cut off → Q2 is cut off; Self-holding bias network: Resistors R8 and R9 are connected in parallel between the base and emitter of Q3 to form a voltage divider holding circuit. When Q3 is turned on, as long as / CON0 outputs a high level, U1 outputs a high level, and Q1 remains on, i.e., locked. When U1 outputs a protection control signal, MOSFET T1 turns off. =0, =0, regardless Whether the load fault is cleared or not, U1 always outputs a protection control signal that is locked. U1 power supply control: After CON0 outputs a low level, Q5 is cut off → cutting off the power supply to comparator U1. When the power supply switch circuit of U1 is disconnected, U1 is de-energized and reset; this eliminates the possibility of false triggering, and the static power consumption is close to 0 μA. Software locking layer: Dual-condition fault condition detection: Voltage threshold: The proportional threshold is compatible with 12V / 24V systems; Control signal status: MCU output CON0 is high, logic "1"; That is, when the MCU outputs CON0 at a high level and detects... When CON0 is low, the MCU actively pulls it low and maintains it low until the system is reset. Lockout Execution: When the protection condition is met, U1 outputs a high level, Q1 conducts, and the gate voltage of T1... Pull down, T1 cutoff, Output low level, When V and CON0 output a high level, Q4 is turned on. When the output is high, U1 outputs a high level, locking the state and maintaining it unchanged. Unlock conditions: A high-low-high transition in CON0 level resets the self-holding circuit; or a system power failure followed by a restart in a 12V system. A drop below 7V lasting >5ms or in a 24V system If the voltage drops below 15V, a power monitoring signal is generated; or a forced reset command is executed. The interface receives the ISO 14229-1 0x11 service code, and the MCU performs a watchdog reset.

7. The anti-interference delay type NMOS high-side output overcurrent and short-circuit protection method as described in claim 6, characterized in that, The trigger protection mechanism of S4 is as follows: when When U1 outputs a high level, it triggers protection and activates the differential voltage. , The internal resistance of the MOSFET during conduction and protection current Decide: During the protection lockout period, / CON0 is forced to a low level, and the gate discharge circuit discharges during the discharge time. Internal shutdown MOSFET.

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