A differential digital-to-analog converter

Abstract

The application relates to the technical field of integrated circuits and provides a differential digital-to-analog converter. The differential digital-to-analog converter comprises two groups of N-bit resistance arrays and a three-state switch array with the same resistance array structure. The differential digital-to-analog converter provides a three-level segmented structure including three different reference voltages, reduces the area overhead of switches, improves on-resistance matching, avoids introducing additional dynamic circuits, helps to reduce static power consumption, and is beneficial to static circuit application and high-precision resistance-type digital-to-analog converter related application.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a differential digital-to-analog converter. BACKGROUND

[0002] In the technical field of integrated circuits, resistive digital-to-analog converters are widely used in low-speed digital-to-analog converters, and the accuracy thereof is generally limited by the matching of unit resistors, switch on-resistance and layout parasitic resistance. The matching of unit resistors can be improved by increasing the area, the matching of layout parasitic resistance can be improved by back-end simulation and layout optimization, and the matching of switch on-resistance can be improved by adjusting the width-length ratio or gate-source voltage of the switch, which is exponentially increased with the increase of the number of bits of the digital-to-analog converter. For a 13-bit analog-to-digital converter, if only a full binary structure is used, the maximum and minimum width-length ratios of the switch will differ by 4096 times. Thus, the area consumption of the switch and the layout difficulty will be very large. In order to reduce the requirements of high-precision digital-to-analog converters on the matching of unit resistors, switches and layout, a segmented structure is generally used. For example, an 8+5 segmented structure with an 8-bit binary segment and a 5-bit thermometer code segment can be used. In the prior art, in order to further reduce the area of resistors, the area of switches and the layout difficulty, a three-level segmented structure is used, and a third reference voltage is added between the first reference voltage and the second reference voltage. However, the three-level segmented structure with the third reference voltage has a high matching requirement for switch on-resistance, because the same switch size is more affected by process deviation, thus easily leading to mismatch between the switch on-resistance and the resistor array. A scheme of a three-level differential digital-to-analog converter in the prior art is to use a transmission gate as a switch to reduce the on-resistance, but the size of the switch is not reduced, which may lead to failure of the switch function in low-voltage design. Another scheme of a three-level differential digital-to-analog converter in the prior art is to increase the opening voltage of the switch by using a charge pump, which can reduce the size of the switch and improve the matching of the on-resistance, but this requires a large capacitor and a clock, thus introducing an additional dynamic circuit, which may cause additional signal interference and is not conducive to reducing the static power consumption in static circuit applications.

[0003] Therefore, the present application provides a differential digital-to-analog converter, which provides a three-level segmented structure including three different reference voltages, reduces the area consumption of the switch and improves the on-resistance matching, avoids introducing an additional dynamic circuit, helps to reduce the static power consumption, and is conducive to static circuit applications and high-precision resistive digital-to-analog converter applications. SUMMARY

[0004] In a first aspect, the present application provides a differential digital-to-analog converter. The differential digital-to-analog converter comprises: two groups of N-bit resistor arrays with the same resistor array structure, where N is a positive integer greater than 1, the two groups of N-bit resistor arrays are respectively a P-terminal N-bit resistor array and an N-terminal N-bit resistor array, an output terminal of the P-terminal N-bit resistor array is a P-terminal output terminal of the differential digital-to-analog converter, and an output terminal of the N-terminal N-bit resistor array is an N-terminal output terminal of the differential digital-to-analog converter; a three-state switch array, configured to select a P-type reference voltage, an N-type reference voltage, or an intermediate reference voltage as an input voltage of the two groups of N-bit resistor arrays based on a digital input signal, the P-type reference voltage is higher than the N-type reference voltage, and the intermediate reference voltage is between the P-type reference voltage and the N-type reference voltage, the P-terminal N-bit resistor array and the N-terminal N-bit resistor array each comprise a plurality of input terminals, the three-state switch array comprises a plurality of three-state switch units corresponding to the plurality of input terminals one by one, each of the plurality of three-state switch units comprises a first pair of N-type field effect tubes connected in common source, a drain of the first pair of N-type field effect tubes serves as an output of the corresponding three-state switch unit when the intermediate reference voltage is selected, and when the digital input signal is switched, a voltage of a gate of the first pair of N-type field effect tubes is located in a voltage domain associated with the P-type reference voltage, and when switching of the digital input signal is completed, the voltage of the gate of the first pair of N-type field effect tubes is switched from the voltage domain associated with the P-type reference voltage to a voltage domain of a first power supply, and the first power supply is configured to provide a voltage equal to a sum of the P-type reference voltage and the intermediate reference voltage to clamp a voltage of a common source of the first pair of N-type field effect tubes at the intermediate reference voltage.

[0005] By the first aspect of the present application, a three-level segmented structure including three different reference voltages is provided, and the area overhead of switches is reduced, the on-resistance matching is improved, and additional dynamic circuits are avoided, which helps to reduce static power consumption and is conducive to static circuit applications and high-precision resistor-type digital-to-analog converter applications.

[0006] In a possible implementation of the first aspect of the present application, the intermediate reference voltage is a sum of a first proportion of the P-type reference voltage and a second proportion of the N-type reference voltage, and the sum of the first proportion and the second proportion is 1.

[0007] In a possible implementation of the first aspect of the present application, the first proportion is 50%, and the second proportion is 50%.

[0008] In a possible implementation form of the first aspect of the application, the drains of the first pair of N-type field effect transistors are respectively configured to provide input voltages for corresponding input terminals of the P-terminal N-bit resistance array and the N-terminal N-bit resistance array, and the common source of the first pair of N-type field effect transistors is a switch shorting point of the corresponding input terminals of the P-terminal N-bit resistance array and the N-terminal N-bit resistance array.

[0009] In a possible implementation form of the first aspect of the application, the intermediate reference voltage is generated on the common source of the first pair of N-type field effect transistors when the corresponding input terminals of the P-terminal N-bit resistance array and the N-terminal N-bit resistance array are shorted by a switch.

[0010] In a possible implementation form of the first aspect of the application, each of the plurality of tri-state switch units comprises a common-source connected first pair of N-type field effect transistors, a common-source connected P-type field effect transistor pair, and a common-source connected second pair of N-type field effect transistors, wherein a voltage of the common source of the P-type field effect transistor pair is clamped at the P-type reference voltage, a voltage of the common source of the second pair of N-type field effect transistors is clamped at the N-type reference voltage, drains of the first pair of N-type field effect transistors are respectively connected to a P-terminal common connection point and an N-terminal common connection point of a corresponding tri-state switch unit, drains of the P-type field effect transistor pair are respectively connected to the P-terminal common connection point and the N-terminal common connection point, drains of the second pair of N-type field effect transistors are respectively connected to the P-terminal common connection point and the N-terminal common connection point, the P-terminal common connection point is configured to provide an input voltage for a corresponding input terminal of the P-terminal N-bit resistance array, and the N-terminal common connection point is configured to provide an input voltage for a corresponding input terminal of the N-terminal N-bit resistance array.

[0011] In a possible implementation form of the first aspect of the application, the digital input signal comprises a first pair of digital control codes for controlling voltages of gates of the first pair of N-type field effect transistors so as to select the intermediate reference voltage as input voltages for the corresponding input terminals of the two groups of N-bit resistance arrays, the digital input signal further comprises a second pair of digital control codes for controlling voltages of gates of the P-type field effect transistor pair so as to select the P-type reference voltage as input voltages for the corresponding input terminals of the two groups of N-bit resistance arrays, and the digital input signal further comprises a third pair of digital control codes for controlling voltages of gates of the second pair of N-type field effect transistors so as to select the N-type reference voltage as input voltages for the corresponding input terminals of the two groups of N-bit resistance arrays.

[0012] In a possible implementation form of the first aspect of the application, when any of the first pair of digital control codes, the second pair of digital control codes and the third pair of digital control codes performs code pattern switching, the voltage of the gate of the first pair of N-type field effect transistors is in the voltage domain associated with the P-type reference voltage, and when all of the first pair of digital control codes, the second pair of digital control codes and the third pair of digital control codes complete code pattern switching, the voltage of the gate of the first pair of N-type field effect transistors switches from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply.

[0013] In a possible implementation form of the first aspect of the application, the differential digital-to-analog converter further comprises a gate voltage control circuit, the gate voltage control circuit comprises a plurality of level conversion circuits, each of the plurality of level conversion circuits corresponds to the gate of the first pair of N-type field effect transistors included in the corresponding one of the plurality of tri-state switch units, each of the plurality of level conversion circuits selects the P-type reference voltage or the output of the first power supply as the high power input based on a gate voltage control signal, the gate voltage control signal is determined based on the change of the digital input signal, and each of the plurality of level conversion circuits outputs a corresponding one of the plurality of tri-state switch units to drive the corresponding gate of the corresponding first pair of N-type field effect transistors of the corresponding tri-state switch unit.

[0014] In a possible implementation form of the first aspect of the application, when the gate voltage control signal is low, the transmission gate pair associated with each of the plurality of level conversion circuits connects the high power input of the corresponding one of the plurality of level conversion circuits to the P-type reference voltage, when the gate voltage control signal is high, the transmission gate pair associated with each of the plurality of level conversion circuits connects the high power input of the corresponding one of the plurality of level conversion circuits to the output of the first power supply, and the output of each of the plurality of level conversion circuits is determined based on the first pair of digital control codes.

[0015] In a possible implementation of the first aspect of the application, the P-terminal N-bit resistor array comprises an L-bit binary R-2R resistor array and an M-bit thermometer code resistor array and a bridge resistor, where N = L + M, L and M are both positive integers greater than 0, the output terminal of the L-bit binary R-2R resistor array is connected to the output terminal of the M-bit thermometer code resistor array through the bridge resistor, the L-bit binary R-2R resistor array constitutes a low-order segment of the P-terminal N-bit resistor array and comprises L+1 resistor pairs, the 2nd to the L+1th resistor pairs in the L+1 resistor pairs are sequentially the lowest-order resistor pair to the highest-order resistor pair from the second farthest to the closest to the bridge resistor, the 1st resistor pair in the L+1 resistor pairs is the farthest to the bridge resistor and is a virtual resistor pair, the M-bit thermometer code resistor array constitutes a high-order segment of the P-terminal N-bit resistor array and comprises 2 M -1 thermometer code resistor pairs, the output terminal of the M-bit thermometer code resistor array is the output terminal of the P-terminal N-bit resistor array, and the tri-state switch array comprises L+2 M tri-state switch units for respectively connecting the input terminals of the L+1 resistor pairs and the input terminals of the 2 M -1 thermometer code resistor pairs, and the digital input signal comprises an L+2 M -bit digital control code.

[0016] In a possible implementation of the first aspect of the application, the P-terminal N-bit resistor array comprises an L-bit binary R-2R resistor array and an M-bit thermometer code resistor array and a bridge resistor, where N = L + M, L and M are both positive integers greater than 0, the output terminal of the L-bit binary R-2R resistor array is connected to the output terminal of the M-bit thermometer code resistor array through the bridge resistor, the L-bit binary R-2R resistor array constitutes a low-order segment of the P-terminal N-bit resistor array and comprises L+1 resistor pairs, the 2nd to the L+1th resistor pairs in the L+1 resistor pairs are sequentially the lowest-order resistor pair to the highest-order resistor pair from the second farthest to the closest to the bridge resistor, the 1st resistor pair in the L+1 resistor pairs is the farthest to the bridge resistor and is a virtual resistor pair, the M-bit thermometer code resistor array constitutes a high-order segment of the P-terminal N-bit resistor array and comprises 2 M -1 thermometer code resistor pairs, the output terminal of the M-bit thermometer code resistor array is the output terminal of the P-terminal N-bit resistor array, and the tri-state switch array comprises L+2 M tri-state switch units for respectively connecting the input terminals of the L+1 resistor pairs and the input terminals of the 2 M -1 thermometer code resistor pairs, and the digital input signal comprises an L+2 M -bit digital control code.

[0017] In a possible implementation form of the first aspect of the application, the differential digital-to-analog converter is a three-level resistive high-precision digital-to-analog converter. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0019] Figure 1 A schematic diagram of a differential digital-to-analog converter provided by an embodiment of the present application;

[0020] Figure 2 A schematic diagram of a tri-state switch unit in a tri-state switch array of a differential digital-to-analog converter provided by an embodiment of the present application;

[0021] Figure 3 A timing diagram of voltage change of a gate of a first N-type field effect transistor pair in a tri-state switch unit with respect to a digital input signal provided by an embodiment of the present application;

[0022] Figure 4 A schematic diagram of an N-bit resistance array at the P terminal of a differential digital-to-analog converter provided by an embodiment of the present application;

[0023] Figure 5 A schematic diagram of an N-bit resistance array at the N terminal of a differential digital-to-analog converter provided by an embodiment of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present application will be further described in detail below with reference to the drawings.

[0025] It should be understood that in the description of the present application, "at least one" means one or more than one, and "multiple" means two or more than two. In addition, the words "first", "second", etc. are used only for the purpose of distinguishing the description, unless otherwise specified, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating or implying order.

[0026] Figure 1 A schematic diagram of a differential digital-to-analog converter provided by an embodiment of the present application. As Figure 1As shown, the differential digital-to-analog converter comprises two groups of N-bit resistor arrays with the same resistor array structure, where N is a positive integer greater than 1, and the two groups of N-bit resistor arrays are a P-terminal N-bit resistor array A110 and an N-terminal N-bit resistor array A120, respectively. An output terminal of the P-terminal N-bit resistor array A110 is a P-terminal output terminal of the differential digital-to-analog converter, and an output terminal of the N-terminal N-bit resistor array A120 is an N-terminal output terminal of the differential digital-to-analog converter. The differential digital-to-analog converter further comprises a tri-state switch array A130. The tri-state switch array A130 is configured to select, based on a digital input signal, a P-type reference voltage, an N-type reference voltage, or an intermediate reference voltage as an input voltage of the two groups of N-bit resistor arrays, the P-type reference voltage being higher than the N-type reference voltage, and the intermediate reference voltage being between the P-type reference voltage and the N-type reference voltage. The P-terminal N-bit resistor array A110 and the N-terminal N-bit resistor array A120 each comprise a plurality of input terminals, and the tri-state switch array A130 comprises a plurality of tri-state switch units corresponding to the plurality of input terminals one by one. Each of the plurality of tri-state switch units comprises a first pair of N-type field effect tubes connected in common source, and a drain of the first pair of N-type field effect tubes is an output of the corresponding tri-state switch unit when the intermediate reference voltage is selected. When the digital input signal is switched, a voltage of a gate of the first pair of N-type field effect tubes is in a voltage domain associated with the P-type reference voltage, and when the switching of the digital input signal is completed, the voltage of the gate of the first pair of N-type field effect tubes is switched from the voltage domain associated with the P-type reference voltage to a voltage domain of a first power supply. The first power supply is configured to provide a voltage equal to a sum of the P-type reference voltage and the intermediate reference voltage so as to clamp a voltage of a common source of the first pair of N-type field effect tubes at the intermediate reference voltage.

[0027] Referring to Figure 1The differential analog-to-digital converter adopts a three-level segmented structure, and three reference voltages are introduced, which are a P-type reference voltage, an N-type reference voltage, and an intermediate reference voltage. The P-type reference voltage is higher than the N-type reference voltage, and the intermediate reference voltage is between the P-type reference voltage and the N-type reference voltage. In addition, the differential analog-to-digital converter includes two groups of N-bit resistance arrays with the same resistance array structure, namely a P-end N-bit resistance array A110 and an N-end N-bit resistance array A120. The corresponding reference voltage is selected as the input voltage of the two groups of N-bit resistance arrays through the control of the three-state switch array A130. In this way, in combination with the specific structure of the N-bit resistance array, on the one hand, the macro adjustment accuracy is provided through the selection of the reference voltage, and on the other hand, the micro adjustment accuracy is provided through the voltage division of the resistance array, so that the adjustment requirements of the analog-to-digital converter can be better met. Here, because the intermediate reference voltage is between the relatively high P-type reference voltage and the relatively low N-type reference voltage, the adaptability problem between the on-resistance of the switch and the resistance array, i.e. the on-resistance impedance matching, needs to be considered. In addition, considering the process deviation, the working temperature and the working voltage may cause the on-resistance of the switch to deviate from the design value, which may cause the mismatch between the on-resistance and the resistance array. Therefore, special optimization design is needed for the case of selecting the intermediate reference voltage. Because the P-type reference voltage can adapt to the switch using a P-type field effect transistor, and the N-type reference voltage can adapt to the switch using an N-type field effect transistor, but the intermediate reference voltage is higher than the N-type reference voltage and lower than the P-type reference voltage, which means that the case of too high transient gate voltage and breakdown needs to be considered, the case of too low gate voltage and switch failure needs to be considered, and the problem of additional interference and increased static power consumption caused by introducing dynamic circuits also needs to be considered. Therefore, for the case of selecting the intermediate reference voltage, each three-state switch unit of the plurality of three-state switch units has a specially optimized circuit and operating principle. Specifically, each three-state switch unit of the plurality of three-state switch units includes a first N-type field effect transistor pair connected in common source, and the drain of the first N-type field effect transistor pair is the output of the corresponding three-state switch unit when the intermediate reference voltage is selected. Here, the digital input signal is used to select the P-type reference voltage, the N-type reference voltage, or the intermediate reference voltage as the input voltage of the two groups of N-bit resistance arrays. When the digital input signal is switched, the voltage at the gate of the first N-type field effect transistor pair is in the voltage domain associated with the P-type reference voltage, and when the switching of the digital input signal is completed, the voltage at the gate of the first N-type field effect transistor pair is switched from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply.Thus, considering the on-resistance of the switch and the mismatch of the resistance array that can exist in non-ideal cases, a first power source is introduced as an external power source to generate an intermediate reference voltage. With the first power source, the voltage can be clamped at the intermediate reference voltage, and a lower driving capability is required, resulting in a smaller circuit overhead. In some embodiments, the common source of the first N-type field effect transistor can be clamped at the intermediate reference voltage with the first power source. However, considering the effects of various non-ideal cases, an additional voltage source can be used to support the stabilization of the common source of the first N-type field effect transistor at the desired intermediate reference voltage. Moreover, this additional voltage source only serves to stabilize the voltage, and thus does not require a high driving capability, resulting in a smaller circuit overhead.

[0028] With continued reference to Figure 1, the digital input signal can be a plurality of digital control codes for controlling the voltage of the gate of the corresponding field effect transistor, thereby controlling the opening and closing of the corresponding field effect transistor, and further controlling the switch to select the corresponding reference voltage as the input of the resistance array. Here, when the digital input signal is stable, that is, when the switching of the digital input signal is completed, the voltage of the drain of the first pair of N-type field effect transistors is relatively stable, so that the transient voltage of the gate is effectively prevented from exceeding the transient voltage of the drain too much to cause the field effect transistor to be broken down due to the excessively high transient gate voltage. However, when the digital input signal is switching, it means that the input digital control code can change, for example, from "1100" to "0111", so the change of the code bit of the corresponding digital control code faced by each tri-state switch unit of the tri-state switch array is unpredictable, which can remain the original control level, or switch from high level to low level, or from low level to high level, which means that when the digital input signal changes, for example, switches, the voltage of the drain of the first pair of N-type field effect transistors is relatively unstable. Therefore, during the switching of the digital input signal, the voltage of the gate of the first pair of N-type field effect transistors is in the voltage domain associated with the P-type reference voltage, where the P-type reference voltage is the highest reference voltage among the three reference voltages, for example, the P-type reference voltage is 1.8 volts, and the voltage of the common source of the first pair of N-type field effect transistors is clamped at the intermediate reference voltage, for example, the intermediate reference voltage is 0.9 volts, so the voltage of the first power supply is equal to the sum of the P-type reference voltage and the intermediate reference voltage, that is, 2.7 volts. Therefore, when the digital input signal is switching, the voltage of the gate of the first pair of N-type field effect transistors is in the voltage domain associated with the P-type reference voltage (for example, 1.8 volts), so that by using the characteristic that the P-type reference voltage minus the voltage of the drain of the first pair of N-type field effect transistors is less than the gate-drain breakdown voltage of the first pair of N-type field effect transistors (the transient voltage of the gate exceeds the transient voltage of the drain too much to cause breakdown), the gate-drain breakdown of the first pair of N-type field effect transistors can be avoided. Therefore, when the digital input signal is switching, the voltage difference between the gate and the drain of the first pair of N-type field effect transistors gradually increases and tends to be stable, while the voltage of the common source of the first pair of N-type field effect transistors is clamped at the intermediate reference voltage; when the switching of the digital input signal is completed, the voltage domain is switched, the voltage of the gate of the first pair of N-type field effect transistors is switched from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply, and the voltage provided by the first power supply for driving the field effect transistor is equal to the sum of the P-type reference voltage and the intermediate reference voltage (for example, 2.7 volts).Thus, when the digital input signal is completed switching, the voltage of the gate of the first N-type field effect transistor pair is raised to the voltage of the first power supply (2.7 volts) through the voltage domain switching, so that the voltage of the common source of the first N-type field effect transistor pair is clamped at the intermediate reference voltage (0.9 volts), naturally making the voltage difference between the gate and the common source of the first N-type field effect transistor pair be the P-type reference voltage (1.8 volts). Thus, by introducing the first power supply as an external power supply to generate a stable intermediate reference voltage, the voltage can be clamped at the intermediate reference voltage by using the first power supply, and in combination with the voltage domain switching operation, not only can the phenomenon of the transient voltage being too high to cause breakdown when the digital input signal is switching be avoided, but also the characteristic that the voltage of the common source can be naturally clamped at the intermediate reference voltage when the digital input signal is stable, so that the mismatch problem of the on-resistance of the switch and the resistance array caused by process deviation, operating voltage and operating temperature in a non-ideal case can be overcome, and the static power consumption of the external power supply is greatly reduced, so the switch size and switch area overhead are also reduced. In addition, because the turn-on voltage of the switch is not changed, but a special optimization design is made for the case of selecting the intermediate reference voltage, no additional capacitance and clock are needed, so that additional dynamic circuits and additional interference factors are avoided. In addition, by setting the intermediate reference voltage to be the intermediate value of the P-type reference voltage and the N-type reference voltage, if a short circuit occurs in an ideal case, the voltage generated is the intermediate value of the P-type reference voltage and the N-type reference voltage, i.e. the intermediate reference voltage, which means that by setting the intermediate reference voltage to be the intermediate value of the P-type reference voltage and the N-type reference voltage, the voltage of the common source is naturally clamped at the designed intermediate reference voltage by using the common source connection method, which means that the static power consumption of the external power supply is the lowest and the circuit area is also optimized. In addition, depending on specific needs, the intermediate reference voltage can be set to be the weighted sum of the P-type reference voltage and the N-type reference voltage, which provides more flexibility. As described above, in some embodiments, the common source of the first N-type field effect transistor can be clamped at the intermediate reference voltage by using the first power supply, but considering the influence of various non-ideal cases, an additional voltage source can be used to support the common source of the first N-type field effect transistor to be stabilized at the desired intermediate reference voltage. Moreover, this additional voltage source only plays a voltage stabilizing role, so it does not need a high driving capability and has a small circuit overhead.

[0029] With reference to the foregoing Figure 1, through digital input signals, a plurality of different sets of digital control codes can be provided for controlling corresponding reference voltages. In some embodiments, the first N-type field effect transistor pair is a pair of Negative Channel-Metal-Oxide-Semiconductor (NMOS) transistors for inputting a middle reference voltage (VCM). In contrast, the tri-state switching unit can also include a pair of Positive Channel-Metal-Oxide-Semiconductor (PMOS) transistors for inputting a P-type reference voltage (VREFP). The tri-state switching unit can also include a second pair of NMOS transistors for inputting an N-type reference voltage (VREFN). Thus, each tri-state switching unit can include a first pair of N-type field effect transistors connected in common source, a pair of P-type field effect transistors connected in common source, and a second pair of N-type field effect transistors connected in common source, wherein a voltage at a common source of the pair of P-type field effect transistors is clamped at the P-type reference voltage, a voltage at a common source of the second pair of N-type field effect transistors is clamped at the N-type reference voltage, drains of the first pair of N-type field effect transistors are connected to a P-terminal common connection point and an N-terminal common connection point of a corresponding tri-state switching unit, respectively, drains of the pair of P-type field effect transistors are connected to the P-terminal common connection point and the N-terminal common connection point, respectively, drains of the second pair of N-type field effect transistors are connected to the P-terminal common connection point and the N-terminal common connection point, respectively, the P-terminal common connection point is for providing an input voltage to a corresponding input terminal of a P-terminal N-bit resistive array, and the N-terminal common connection point is for providing an input voltage to a corresponding input terminal of an N-terminal N-bit resistive array. In this way, three different pairs of field effect transistors are provided for selecting corresponding reference voltages as inputs to the resistive arrays. In addition, the digital input signals can include a plurality of sets of digital control codes for controlling voltages at gates of the corresponding pairs of field effect transistors. In some embodiments, the digital input signals include a first pair of digital control codes (Dcp and Dcn) for controlling a voltage at gates of the first pair of N-type field effect transistors, a second pair of digital control codes (Dpp and Dpn) for controlling a voltage at gates of the pair of P-type field effect transistors, and a third pair of digital control codes (Dnp and Dnn) for controlling a voltage at gates of the second pair of N-type field effect transistors.Thus, there is a group of PMOSs with common source and common source clamping at VREFP, the voltage of the gate of the group of PMOSs is controlled by two external control signals Dpp and Dpn, so that VREFP can be selected as the input voltage of the P-end N-bit resistance array and the N-end N-bit resistance array; there is a group of NMOSs with common source and common source clamping at VCM, the voltage of the gate of the group of NMOSs is controlled by two external control signals Dcp and Dcn, so that VCM can be selected as the input voltage of the P-end N-bit resistance array and the N-end N-bit resistance array; there is a group of NMOSs with common source and common source clamping at VREFN, the voltage of the gate of the group of NMOSs is controlled by two external control signals Dnp and Dnn, so that VREFN can be selected as the input voltage of the P-end N-bit resistance array and the N-end N-bit resistance array. In addition, VCM is the proportional sum of VREFP and VREFN, and the total proportion is 1, and in some embodiments, the proportion is 50% respectively, which means that the static power consumption is the lowest. Moreover, the voltage domain switching operation of the voltage of the gate of the first pair of N-type field effect transistors can be controlled by providing an additional gate voltage control circuit, and the first power supply (VDDH) is introduced, so that the voltage of the gate of the first pair of N-type field effect transistors is switched between the two voltage domains of VREFP and VDDH, thereby realizing the gate voltage control algorithm of the NMOS corresponding to the intermediate reference voltage VCM which is specially optimized for the case of selecting the intermediate reference voltage. Thus, by selecting the reference voltage as the input voltage of the resistance array, the output of the analog voltage is fine controlled through the voltage division inside the resistance array.

[0030] In summary, Figure 1 The differential digital-to-analog converter shown, by introducing a high power supply, i.e. the first power supply (VDDH), and the first power supply is used to provide a voltage equal to the sum of the P-type reference voltage and the intermediate reference voltage, i.e. VDDH=VREFP+VCM, thus improving the on-state of the third reference voltage switch, i.e. the first pair of N-type field effect transistors, in the differential digital-to-analog converter, reducing the switch size and improving the on-resistance matching. Since the high power supply VDDH drives the gate of the MOS transistor, almost no static drive current is needed, and the analog circuit overhead for generating the high power supply VDDH is small. It can be applied to various designs of low-voltage circuits, static circuits and dynamic circuits, without causing additional noise interference, meeting the design requirements of high precision. At the same time, by using the switch timing optimized for the intermediate reference voltage, the voltage domain switching is operated in combination with the change of the digital input signal, which can avoid the risk of overvoltage failure of the NMOS. Thus, a three-level segmented structure including three different reference voltages is provided, and the area overhead of the switch is reduced and the on-resistance matching is improved, which avoids introducing additional dynamic circuits, helps to reduce static power consumption, and is conducive to static circuit applications and high-precision resistance-type digital-to-analog converter applications.

[0031] Figure 2 A schematic diagram of a tri-state switch cell in a tri-state switch array of a differential digital-to-analog converter is provided for embodiments of the present application. As described above, the P-end N-bit resistor array and the N-end N-bit resistor array each include a plurality of input terminals, and the tri-state switch array includes a plurality of tri-state switch cells corresponding to the plurality of input terminals one-to-one. Each of the plurality of tri-state switch cells includes a first pair of N-type field effect transistors (N-type field effect transistor A 210 and N-type field effect transistor B 220) connected in common source. The drains of the first pair of N-type field effect transistors (drain 216 of N-type field effect transistor A 210 and drain 226 of N-type field effect transistor B 220) serve as the output of the corresponding tri-state switch cell when the intermediate reference voltage is selected. Also, when the digital input signal is switching, the voltages of the gates of the first pair of N-type field effect transistors (gate 212 of N-type field effect transistor A 210 and gate 222 of N-type field effect transistor B 220) are in the voltage domain associated with the P-type reference voltage 290, and when the switching of the digital input signal is complete, the voltages of the gates of the first pair of N-type field effect transistors (gate 212 of N-type field effect transistor A 210 and gate 222 of N-type field effect transistor B 220) are switched from the voltage domain associated with the P-type reference voltage 290 to the voltage domain of the first power supply 209. The first power supply 209 is configured to provide a voltage equal to the sum of the P-type reference voltage 290 and the intermediate reference voltage 294 to clamp the voltage of the common source of the first pair of N-type field effect transistors (source 214 of N-type field effect transistor A 210 and source 224 of N-type field effect transistor B 220) at the intermediate reference voltage 294.

[0032] Referring to Figure 2, each of the plurality of tri-state switching units comprises a common-source connected first pair of N-type field effect transistors (N-type field effect transistor A 210 and N-type field effect transistor B 220), a common-source connected pair of P-type field effect transistors (P-type field effect transistor A 230 and P-type field effect transistor B 240), and a common-source connected second pair of N-type field effect transistors (N-type field effect transistor C 250 and N-type field effect transistor D 260). In this way, three different pairs of field effect transistors are provided for selecting a corresponding reference voltage as an input for the resistance array. The voltage of the common-source (source 234 of P-type field effect transistor A 230 and source 244 of P-type field effect transistor B 240) of the pair of P-type field effect transistors (P-type field effect transistor A 230 and P-type field effect transistor B 240) is clamped to the P-type reference voltage 290. The voltage of the common-source (source 254 of N-type field effect transistor C 250 and source 264 of N-type field effect transistor D 260) of the second pair of N-type field effect transistors (N-type field effect transistor C 250 and N-type field effect transistor D 260) is clamped to the N-type reference voltage 292. The drains (drain 216 of N-type field effect transistor A 210 and drain 226 of N-type field effect transistor B 220) of the first pair of N-type field effect transistors (N-type field effect transistor A 210 and N-type field effect transistor B 220) are connected to the P-terminal common connection point 280 and the N-terminal common connection point 282, respectively, of the corresponding tri-state switching unit. The drains (drain 236 of P-type field effect transistor A 230 and drain 246 of P-type field effect transistor B 240) of the pair of P-type field effect transistors (P-type field effect transistor A 230 and P-type field effect transistor B 240) are connected to the P-terminal common connection point 280 and the N-terminal common connection point 282, respectively. The drains (drain 256 of N-type field effect transistor C 250 and drain 266 of N-type field effect transistor D 260) of the second pair of N-type field effect transistors (N-type field effect transistor C 250 and N-type field effect transistor D 260) are connected to the P-terminal common connection point 280 and the N-terminal common connection point 282, respectively. The P-terminal common connection point 280 is used to provide an input voltage for a corresponding input terminal of the P-terminal N-bit resistance array, and the N-terminal common connection point 282 is used to provide an input voltage for a corresponding input terminal of the N-terminal N-bit resistance array. In this way, a three-level segmented structure comprising three different reference voltages is provided, and a specially optimized gate voltage control algorithm is implemented by providing an additional gate voltage control circuit 202.And, using the three common source connection method field effect transistor pair, and using the field effect transistor drain access to the common connection point as a three-state switch unit output, thus, using the first power supply 209 can achieve voltage clamping at the intermediate reference voltage 294, combined with voltage domain switching operation, not only avoids the phenomenon of transient voltage too high caused by digital input signal switching and breakdown, but also naturally cooperates with the common source voltage clamped at the intermediate reference voltage 294 when the digital input signal is stable, thus overcoming the mismatch problem of switch on-resistance and resistance array caused by process deviation, operating voltage and operating temperature in non-ideal conditions, and greatly reducing the static power consumption of external power supply, thus reducing the switch size and switch area overhead. In addition, because the opening voltage of the switch is not changed, but a special optimization design is made for the case of selecting the intermediate reference voltage 294, so no additional capacitance and clock are needed, thus avoiding additional dynamic circuit and additional interference factors.

[0033] Referring to Figure 2, the digital input signal includes a first pair of digital control codes 204 for controlling the voltage of the gates (gate 212 of N-type field effect transistor A 210 and gate 222 of N-type field effect transistor B 220) of the first pair of N-type field effect transistors (N-type field effect transistor A 210 and N-type field effect transistor B 220) so as to select the intermediate reference voltage 294 as the input voltage of the corresponding input terminals of the two sets of N-bit resistance arrays. The digital input signal further includes a second pair of digital control codes 206 for controlling the voltage of the gates (gate 232 of P-type field effect transistor A 230 and gate 242 of P-type field effect transistor B 240) of the pair of P-type field effect transistors (P-type field effect transistor A 230 and P-type field effect transistor B 240) so as to select the P-type reference voltage 290 as the input voltage of the corresponding input terminals of the two sets of N-bit resistance arrays. The digital input signal further includes a third pair of digital control codes 208 for controlling the voltage of the gates (gate 252 of N-type field effect transistor C 250 and gate 262 of N-type field effect transistor D 260) of the second pair of N-type field effect transistors (N-type field effect transistor C 250 and N-type field effect transistor D 260) so as to select the N-type reference voltage 292 as the input voltage of the corresponding input terminals of the two sets of N-bit resistance arrays. In this way, three different pairs of field effect transistors are provided for selecting the corresponding reference voltage as the input of the resistance array, and by using a plurality of different digital control codes, the voltage of the gates of the corresponding pair of field effect transistors can be controlled, thereby achieving the effect of fine control of the output of the analog voltage by selecting the reference voltage as the input voltage of the resistance array. And for the first pair of digital control codes 204, the first pair of digital control codes 204 is not directly acting on the gates (gate 212 of N-type field effect transistor A 210 and gate 222 of N-type field effect transistor B 220) of the first pair of N-type field effect transistors (N-type field effect transistor A 210 and N-type field effect transistor B 220), but through the gate voltage control circuit 202, a specially optimized gate voltage control algorithm is implemented. In this way, the first power supply 209 is introduced to overcome the mismatch problem of the on-state impedance of the switch and the resistance array that may be caused by process deviation, operating voltage and operating temperature under non-ideal conditions, and by using the gate voltage control circuit 202, the switch timing optimized for the intermediate reference voltage is designed in combination with the change of the digital input signal to operate the voltage domain switching, which can avoid the risk of overvoltage failure of the NMOS transistor, and when the digital input signal is stable, it can naturally cooperate with the characteristic that the voltage of the common source is clamped at the intermediate reference voltage 294.

[0034] With continued reference to Figure 2When any of the first pair of digital control codes 204, the second pair of digital control codes 206, and the third pair of digital control codes 208 is toggled, the voltage of the gates (gate 212 of N-type field effect transistor A 210 and gate 222 of N-type field effect transistor B 220) of the first pair of N-type field effect transistors (N-type field effect transistor A 210 and N-type field effect transistor B 220) is in the voltage domain associated with the P-type reference voltage 290. When all of the first pair of digital control codes 204, the second pair of digital control codes 206, and the third pair of digital control codes 208 are toggled, the voltage of the gates (gate 212 of N-type field effect transistor A 210 and gate 222 of N-type field effect transistor B 220) of the first pair of N-type field effect transistors (N-type field effect transistor A 210 and N-type field effect transistor B 220) is toggled from the voltage domain associated with the P-type reference voltage 290 to the voltage domain of the first power supply 209. When the digital input signal is toggled, it means that the input digital control codes can change, for example, from "1100" to "0111", and thus the change of the code bits of the corresponding digital control codes faced by each tri-state switch cell of the tri-state switch array is unpredictable, which can be keeping the original control level, or toggling from high level to low level, or toggling from low level to high level. This means that when the digital input signal is changed, for example, toggled, the voltage of the drains (drain 216 of N-type field effect transistor A 210 and drain 226 of N-type field effect transistor B 220) of the first pair of N-type field effect transistors (N-type field effect transistor A 210 and N-type field effect transistor B 220) is in a relatively unstable state. Therefore, when the digital input signal is toggled, the voltage of the gates (gate 212 of N-type field effect transistor A 210 and gate 222 of N-type field effect transistor B 220) of the first pair of N-type field effect transistors (N-type field effect transistor A 210 and N-type field effect transistor B 220) is in the voltage domain associated with the P-type reference voltage 290, so that the voltage of the drains (drain 216 of N-type field effect transistor A 210 and drain 226 of N-type field effect transistor B 220) of the first pair of N-type field effect transistors (N-type field effect transistor A 210 and N-type field effect transistor B 220) minus the P-type reference voltage 290 is less than the gate-drain breakdown voltage of the first pair of N-type field effect transistors (N-type field effect transistor A 210 and N-type field effect transistor B 220), which can avoid the gate-drain breakdown phenomenon of the first pair of N-type field effect transistors (N-type field effect transistor A 210 and N-type field effect transistor B 220).Therefore, when the digital input signal is switching, the gate-drain voltage difference of the first N-type field effect transistor pair (N-type field effect transistor A 210 and N-type field effect transistor B 220) is gradually raised to be stable, and the voltage of the common source (the source 214 of N-type field effect transistor A 210 and the source 224 of N-type field effect transistor B 220) of the first N-type field effect transistor pair (N-type field effect transistor A 210 and N-type field effect transistor B 220) is clamped at the intermediate reference voltage 294. When the switching of the digital input signal is completed, the voltage domain switching is performed, the gate (the gate 212 of N-type field effect transistor A 210 and the gate 222 of N-type field effect transistor B 220) of the first N-type field effect transistor pair (N-type field effect transistor A 210 and N-type field effect transistor B 220) is switched from the voltage domain associated with the P-type reference voltage 290 to the voltage domain of the first power supply 209, and the voltage provided by the first power supply 209 for driving the field effect transistor is equal to the sum of the P-type reference voltage 290 and the intermediate reference voltage 294. Thus, when the digital input signal is completed, the voltage of the gate (the gate 212 of N-type field effect transistor A 210 and the gate 222 of N-type field effect transistor B 220) of the first N-type field effect transistor pair (N-type field effect transistor A 210 and N-type field effect transistor B 220) is raised to the voltage of the first power supply 209 through the voltage domain switching, and the voltage of the common source (the source 214 of N-type field effect transistor A 210 and the source 224 of N-type field effect transistor B 220) of the first N-type field effect transistor pair (N-type field effect transistor A 210 and N-type field effect transistor B 220) is clamped at the intermediate reference voltage 294, which naturally makes the gate-source voltage difference of the first N-type field effect transistor pair (N-type field effect transistor A 210 and N-type field effect transistor B 220) be the P-type reference voltage 290.

[0035] With reference to the accompanying drawings, the present application will be described in detail. Figure 2 The differential digital-to-analog converter further comprises a gate voltage control circuit 202. The gate voltage control circuit 202 comprises a plurality of level conversion circuits, each of which is connected to the gate of the first N-type field effect transistor pair (N-type field effect transistor A 210 and N-type field effect transistor B 220) included in each of the plurality of tri-state switch units. Figure 2 The gate (the gate 212 of N-type field effect transistor A 210 and the gate 222 of N-type field effect transistor B 220) of the first N-type field effect transistor pair (N-type field effect transistor A 210 and N-type field effect transistor B 220) included in each of the plurality of tri-state switch units is connected to the output of each of the plurality of level conversion circuits. Figure 2 The gate (the gate 212 of N-type field effect transistor A 210 and the gate 222 of N-type field effect transistor B 220) of the first N-type field effect transistor pair (N-type field effect transistor A 210 and N-type field effect transistor B 220) included in each of the plurality of tri-state switch units is connected to the output of each of the plurality of level conversion circuits. The high power input of each of the plurality of level conversion circuits is selected based on a gate voltage control signal, and the gate voltage control signal is determined based on the change of the digital input signal. The output of each of the plurality of level conversion circuits is used to drive the corresponding first N-type field effect transistor pair (N-type field effect transistor A 210 and N-type field effect transistor B 220) of the corresponding tri-state switch unit in the plurality of tri-state switch units.Figure 2 The corresponding gates of the N-type field effect transistor A210 and the N-type field effect transistor B220 of a tri-state switch unit are exemplarily shown in FIG. 2B. Figure 2 The gate 212 of the N-type field effect transistor A210 and the gate 222 of the N-type field effect transistor B220 of a tri-state switch unit are exemplarily shown in FIG. 2C. Thus, by using the gate voltage control circuit 202, the switch timing optimized for the intermediate reference voltage 294 is achieved, and the voltage domain switching is operated in combination with the change of the digital input signal, which can avoid the risk of overvoltage failure of the NMOS transistor.

[0036] Figure 3 A timing diagram of the voltage of the gate of the first pair of N-type field effect transistors in a tri-state switch unit relative to the change of the digital input signal is provided for the embodiments of the present application. Referring to FIG. 2D, Figure 1 and Figure 2 The tri-state switch unit includes a PMOS with a source connected to a first reference voltage VREFP, an NMOS with a source connected to a second reference voltage VREFN, and an NMOS with a source connected to a third reference voltage VCM. The gate of the PMOS with the source connected to the first reference voltage VREFP in the tri-state switch array at the P end receives a first group of digital input signals Dpp M -1:0> control, the gate of the NMOS with the source connected to the second reference voltage VREFN at the P end receives a second group of digital input signals Dnp M -1:0> control, and the gate of the NMOS with the source connected to the third reference voltage VCM at the P end receives a third group of digital input signals Dcp M -1:0> control. Conversely, the gate of the PMOS with the source connected to the first reference voltage VREFP in the tri-state switch array at the N end receives a fourth group of digital input signals Dpn M -1:0> control, the gate of the NMOS with the source connected to the second reference voltage VREFN at the N end receives a fifth group of digital input signals Dnn M -1:0> control, and the gate of the NMOS with the source connected to the third reference voltage VCM at the N end receives a sixth group of digital input signals Dcn M -1:0> control. The drains of the three MOS transistors in the tri-state switch unit are connected to each other to form a connection point, which is the output of the tri-state switch unit and is connected to the input end in the resistance array. As can be seen, Figure 3 The tri-state switch unit includes a PMOS with a source connected to a first reference voltage VREFP, an NMOS with a source connected to a second reference voltage VREFN, and an NMOS with a source connected to a third reference voltage VCM. The gate of the PMOS with the source connected to the first reference voltage VREFP in the tri-state switch array at the P end receives a first group of digital input signals Dpp Figure 3The third reference voltage VCM, i.e. the middle reference voltage, is shown in the example. The gate voltage control algorithm corresponding to the NMOS of VCM for the differential analog-to-digital converter is shown in the example. It can be seen that when the first group of digital input signals Dpp<L+2 M -1:0>, the second group of digital input signals Dnp<L+2 M -1:0>, the third group of digital input signals Dcp<L+2 M -1:0>, the fourth group of digital input signals Dpn<L+2 M -1:0>, the fifth group of digital input signals Dnn<L+2 M -1:0>, the sixth group of digital input signals Dcn<L+2 M -1:0> changes, the gate voltage control signal (VDD_SEL) is low; when the first group of digital input signals Dpp<L+2 M -1:0>, the second group of digital input signals Dnp<L+2 M -1:0>, the third group of digital input signals Dcp<L+2 M -1:0>, the fourth group of digital input signals Dpn<L+2 M -1:0>, the fifth group of digital input signals Dnn<L+2 M -1:0>, the sixth group of digital input signals Dcn<L+2 M -1:0> stabilizes, the gate voltage control signal (VDD_SEL) becomes high. In this way, the gate voltage control signal (VDD_SEL) is determined based on the change of the digital input signal. When the first group of digital input signals Dpp<L+2 M -1:0> changes, such as the transition phase between Dpp_data0 and Dpp_data1, the gate voltage control signal (VDD_SEL) is set to low at this time, so that the P-type reference voltage can be selected based on the gate voltage control signal, so that when the digital input signal is switched, the voltage of the gate of the first N-type field effect transistor pair is located in the voltage domain associated with the P-type reference voltage. Conversely, when the first group of digital input signals Dpp<L+2 M-1:0> stable, such as the duration of Dpp_data2 and Dpp_data1, at this time the gate voltage control signal (VDD_SEL) is set to high, so that the output of the first power supply can be selected based on the gate voltage control signal, so that when the switching of the digital input signal is completed, the voltage of the gate of the first N-type field effect transistor pair is switched from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply. In this way, by introducing the first power supply as an external power supply to generate a stable intermediate reference voltage, the voltage can be clamped at the intermediate reference voltage by using the first power supply, and in combination with the voltage domain switching operation, not only can the phenomenon of excessive transient voltage breakdown caused by the switching of the digital input signal be avoided, but also the voltage of the common source can be naturally clamped at the intermediate reference voltage during the stable state of the digital input signal, thus overcoming the mismatch problem of the on-resistance of the switch and the resistance array caused by process deviation, operating voltage and operating temperature in non-ideal conditions, and greatly reducing the static power consumption of the external power supply, thereby reducing the switch size and switch area overhead. In addition, because the turn-on voltage of the switch is not changed, but a special optimization design is made for the selection of the intermediate reference voltage, additional capacitors and clocks are not required, thereby avoiding additional dynamic circuits and additional interference factors. In some embodiments, the first N-type field effect transistor can be clamped at the intermediate reference voltage by using the first power supply, but considering the influence of various non-ideal conditions, an additional voltage source can be used to support the stabilization of the common source of the first N-type field effect transistor at the desired intermediate reference voltage. Moreover, this additional voltage source only serves to stabilize the voltage, so it does not require high driving capability and has small circuit overhead.

[0037] Referring to Figure 1 , Figure 2 and Figure 3 , in a possible implementation, the intermediate reference voltage is the sum of a first proportion of the P-type reference voltage and a second proportion of the N-type reference voltage, and the sum of the first proportion and the second proportion is 1. In this way, in combination with the specific structure of the N-bit resistance array, on the one hand, the macro adjustment accuracy is provided by the selection of the reference voltage, and on the other hand, the micro adjustment accuracy is provided by the voltage division of the resistance array, so that the adjustment requirements of the digital-to-analog converter can be better met.

[0038] In some embodiments, the first proportion is 50% and the second proportion is 50%. In this way, by setting the intermediate reference voltage as the intermediate value of the P-type reference voltage and the N-type reference voltage, the voltage of the common source is naturally clamped at the designed intermediate reference voltage by using the common source connection method, which means that the static power consumption of the external power supply is minimized and the circuit area is optimized.

[0039] In some embodiments, the drain of the first N-type field effect transistor pair is used to provide input voltage for the corresponding input terminal of the P-terminal N-bit resistance array and the corresponding input terminal of the N-terminal N-bit resistance array, respectively, and the common source of the first N-type field effect transistor pair is the shorting point of the corresponding input terminal of the P-terminal N-bit resistance array and the corresponding input terminal of the N-terminal N-bit resistance array. In this way, by introducing the first power supply as an external power supply to generate a stable intermediate reference voltage, the voltage can be clamped at the intermediate reference voltage by using the first power supply, and in combination with the voltage domain switching operation, not only can the phenomenon of breakdown caused by the transient voltage being too high when the digital input signal is switched be avoided, but also the voltage of the common source can be naturally clamped at the intermediate reference voltage when the digital input signal is stable, thus overcoming the mismatch problem of the on-resistance of the switch and the resistance array caused by process deviation, operating voltage and operating temperature in a non-ideal situation, and greatly reducing the static power consumption of the external power supply, thereby reducing the switch size and switch area overhead. In addition, because the turn-on voltage of the switch is not changed, but a special optimization design is made for the case of selecting the intermediate reference voltage, no additional capacitance and clock is needed, thus avoiding additional dynamic circuits and additional interference factors. By setting the intermediate reference voltage to be the intermediate value of the P-type reference voltage and the N-type reference voltage, the voltage generated by the shorting in an ideal case is the intermediate value of the P-type reference voltage and the N-type reference voltage, i.e. the intermediate reference voltage, which means that by setting the intermediate reference voltage to be the intermediate value of the P-type reference voltage and the N-type reference voltage, the voltage of the common source is naturally clamped at the designed intermediate reference voltage by using the common source connection method, which means that the static power consumption of the external power supply is minimized and the circuit area is optimized.

[0040] In some embodiments, the intermediate reference voltage is generated on the common source of the first pair of N-type field effect transistors when the corresponding input of the P-end N-bit resistor array and the corresponding input of the N-end N-bit resistor array are shorted through a switch. In this way, the voltage generated if the shorting occurs is ideally the intermediate value of the P-type reference voltage and the N-type reference voltage, i.e. the intermediate reference voltage. This means that by setting the intermediate reference voltage to be the intermediate value of the P-type reference voltage and the N-type reference voltage, the voltage at the common source is naturally clamped to the designed intermediate reference voltage using the common source connection, which means that the static power consumption of the external power supply is minimized and the circuit area is optimized. Considering non-ideal conditions, the first power supply is introduced as an external power supply to generate a stable intermediate reference voltage, and the voltage can be clamped to the intermediate reference voltage using the first power supply. In some embodiments, the common source of the first N-type field effect transistor can be clamped to the intermediate reference voltage using the first power supply, but considering the influence of various non-ideal conditions, an additional voltage source can be used to support the stabilization of the common source of the first N-type field effect transistor at the desired intermediate reference voltage. Moreover, this additional voltage source only serves to stabilize the voltage, so it does not require high driving capability and has a small circuit overhead.

[0041] In one possible implementation, each of the plurality of tri-state switch units comprises a pair of first N-type field effect transistors connected in common source, a pair of P-type field effect transistors connected in common source, and a pair of second N-type field effect transistors connected in common source, wherein the voltage of the common source of the pair of P-type field effect transistors is clamped at the P-type reference voltage, the voltage of the common source of the pair of second N-type field effect transistors is clamped at the N-type reference voltage, the drains of the pair of first N-type field effect transistors are connected to a P-terminal common connection point and an N-terminal common connection point of the corresponding tri-state switch unit respectively, the drains of the pair of P-type field effect transistors are connected to the P-terminal common connection point and the N-terminal common connection point respectively, the drains of the pair of second N-type field effect transistors are connected to the P-terminal common connection point and the N-terminal common connection point respectively, the P-terminal common connection point is used to provide an input voltage of a corresponding input terminal of the P-terminal N-bit resistance array, and the N-terminal common connection point is used to provide an input voltage of a corresponding input terminal of the N-terminal N-bit resistance array. In this way, three different pairs of field effect transistors are provided for selecting a corresponding reference voltage as an input of a resistance array. Moreover, three pairs of field effect transistors connected in common source are used, and the drains of the field effect transistors are connected to the common connection points as outputs of the tri-state switch units. In this way, the voltage can be clamped at the middle reference voltage by using a first power supply, and in combination with the voltage domain switching operation, not only can the phenomenon of breakdown caused by excessively high transient voltage during switching of a digital input signal be avoided, but also the characteristics of the voltage of the common source being clamped at the middle reference voltage during stable digital input signals can be naturally matched, so that the mismatching problems of the on-resistance of the switch and the resistance array caused by process deviation, working voltage and working temperature in a non-ideal case can be overcome, and the static power consumption of the external power supply is greatly reduced, so the size and area of the switch are also reduced. In addition, because the turn-on voltage of the switch is not changed, but a special optimization design is made for the case of selecting the middle reference voltage, no additional capacitor and clock are needed, so additional dynamic circuit and additional interference factors are avoided.

[0042] In some embodiments, the digital input signal includes a first pair of digital control codes for controlling the voltage of the gates of the first pair of N-type field effect transistors to select the intermediate reference voltage as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays, the digital input signal further includes a second pair of digital control codes for controlling the voltage of the gates of the P-type field effect transistor pair to select the P-type reference voltage as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays, and the digital input signal further includes a third pair of digital control codes for controlling the voltage of the gates of the second pair of N-type field effect transistors to select the N-type reference voltage as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays. In this way, three different pairs of field effect transistors are provided for selecting the corresponding reference voltage as the input of the resistor arrays, and with a plurality of different sets of digital control codes, the voltage of the gates of the corresponding pairs of field effect transistors can be controlled to achieve the effect of fine control of the output of the analog voltage by selecting the reference voltage as the input voltage of the resistor arrays, and achieving the effect of fine control of the voltage inside the resistor arrays.

[0043] In some embodiments, when any of the first pair of digital control codes, the second pair of digital control codes, and the third pair of digital control codes is toggled, the voltage at the gate of the first pair of N-type field effect transistors is in the voltage domain associated with the P-type reference voltage, and when all of the first pair of digital control codes, the second pair of digital control codes, and the third pair of digital control codes are toggled, the voltage at the gate of the first pair of N-type field effect transistors is toggled from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply. When the digital input signal is toggled, it means that the input digital control codes can change, for example, from "1100" to "0111", and thus the change of the code bits of the corresponding digital control codes that each tri-state switch cell of the tri-state switch array faces is unpredictable, which can be a change from a high level to a low level, or a change from a low level to a high level, which means that when the digital input signal is changed, for example, toggled, the voltage at the drain of the first pair of N-type field effect transistors is in a relatively unstable state. Therefore, during the period when the digital input signal is toggled, the voltage at the gate of the first pair of N-type field effect transistors is in the voltage domain associated with the P-type reference voltage. When the digital input signal is toggled, the voltage difference between the gate and the drain of the first pair of N-type field effect transistors gradually increases and stabilizes, while the voltage at the common source of the first pair of N-type field effect transistors is clamped at the intermediate reference voltage; when the toggling of the digital input signal is completed, the voltage domain is toggled, the voltage at the gate of the first pair of N-type field effect transistors is toggled from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply, and the voltage provided by the first power supply for driving the field effect transistor is equal to the sum of the P-type reference voltage and the intermediate reference voltage (for example, 2.7 volts). In this way, when the digital input signal is completed, the voltage at the gate of the first pair of N-type field effect transistors is raised to the voltage of the first power supply (2.7 volts) through voltage domain switching, which naturally makes the voltage difference between the gate and the common source of the first pair of N-type field effect transistors the P-type reference voltage (1.8 volts) by combining the voltage at the common source of the first pair of N-type field effect transistors being clamped at the intermediate reference voltage (0.9 volts). In this way, by introducing the first power supply as an external power supply to generate a stable intermediate reference voltage, the voltage at the common source of the first pair of N-type field effect transistors can be clamped at the intermediate reference voltage using the first power supply, and combined with the voltage domain switching operation, not only can the phenomenon of excessive transient voltage breakdown caused by the toggling of the digital input signal be avoided, but also the characteristics of the voltage at the common source being clamped at the intermediate reference voltage can be naturally matched when the digital input signal is stable, thus overcoming the mismatch problem of the on-resistance of the switch and the resistance array caused by process deviation, operating voltage, and operating temperature in non-ideal conditions, and greatly reducing the static power consumption of the external power supply, thereby reducing the switch size and switch area overhead.In addition, because the opening voltage of the switch is not changed, but is specially optimized for the case of selecting the intermediate reference voltage, no additional capacitor and clock are needed, thus avoiding additional dynamic circuit and additional interference factors.

[0044] In some embodiments, the differential current-to-voltage converter further comprises a gate voltage control circuit, the gate voltage control circuit comprises a plurality of level conversion circuits, each of the plurality of level conversion circuits corresponds to a pair of gates of a corresponding pair of the first N-type field effect transistors included in a corresponding one of the plurality of tri-state switch units, a high power input of each of the plurality of level conversion circuits is selected based on a gate voltage control signal to output the P-type reference voltage or the first power supply, the gate voltage control signal is determined based on a change of the digital input signal, and an output of each of the plurality of level conversion circuits is used to drive a corresponding one of the plurality of tri-state switch units. In this way, by using the gate voltage control circuit, the switch timing optimized for the intermediate reference voltage is realized, and the switching of the voltage domain is operated in combination with the change of the digital input signal, which can avoid the risk of overvoltage failure of the NMOS transistor.

[0045] In some embodiments, when the gate voltage control signal is at a low level, a pair of transmission gates associated with each of the plurality of level conversion circuits connects the high power input of the corresponding one of the plurality of level conversion circuits to the P-type reference voltage, when the gate voltage control signal is at a high level, the pair of transmission gates associated with each of the plurality of level conversion circuits connects the high power input of the corresponding one of the plurality of level conversion circuits to the output of the first power supply, and the output of each of the plurality of level conversion circuits is determined based on the first pair of digital control codes. In this way, by using the gate voltage control circuit and the level conversion circuit, the switch timing optimized for the intermediate reference voltage is realized, and the switching of the voltage domain is operated in combination with the change of the digital input signal, which can avoid the risk of overvoltage failure of the NMOS transistor.

[0046] In one possible implementation, the P-terminal N-bit resistor array includes an L-bit binary R-2R resistor array and an M-bit thermometer code resistor array and a bridge resistor, where N = L + M, L and M are both positive integers greater than 0, the output terminal of the L-bit binary R-2R resistor array is connected to the output terminal of the M-bit thermometer code resistor array through the bridge resistor, the L-bit binary R-2R resistor array constitutes a low-order segment of the P-terminal N-bit resistor array and includes L + 1 resistor pairs, the 2nd to the L+1th resistor pairs in the L + 1 resistor pairs are sequentially the lowest-order resistor pair to the highest-order resistor pair from the second farthest to the closest to the bridge resistor, the 1st resistor pair in the L + 1 resistor pairs is the farthest to the bridge resistor and is a dummy resistor pair, the M-bit thermometer code resistor array constitutes a high-order segment of the P-terminal N-bit resistor array and includes 2 M -1 thermometer code resistor pairs, the output terminal of the M-bit thermometer code resistor array is the output terminal of the P-terminal N-bit resistor array, and the tri-state switch array includes L + 2 M tri-state switch units for respectively connecting the input terminals of the L + 1 resistor pairs and the input terminals of the 2 M -1 thermometer code resistor pairs, and the digital input signal includes an L + 2 M -bit digital control code. In this way, in combination with the specific structure of the N-bit resistor array, on the one hand, the macro adjustment accuracy is provided by the selection of the reference voltage, and on the other hand, the micro adjustment accuracy is provided by the voltage division of the resistor array, so that the adjustment requirements of the digital-to-analog converter can be better met. The segmented structure of the L-bit binary R-2R resistor array and the M-bit thermometer code resistor array helps to reduce the requirements of the high-precision digital-to-analog converter on the unit resistance matching, switch matching and layout matching.

[0047] In one possible implementation, the P-terminal N-bit resistor array includes an L-bit binary R-2R resistor array and an M-bit thermometer code resistor array and a bridge resistor, where N = L + M, L and M are both positive integers greater than 0, the output terminal of the L-bit binary R-2R resistor array is connected to the output terminal of the M-bit thermometer code resistor array through the bridge resistor, the L-bit binary R-2R resistor array constitutes a low-order segment of the P-terminal N-bit resistor array and includes L + 1 resistor pairs, the 2nd to the L+1th resistor pairs in the L + 1 resistor pairs are sequentially the lowest-order resistor pair to the highest-order resistor pair from the second farthest to the closest to the bridge resistor, the 1st resistor pair in the L + 1 resistor pairs is the farthest to the bridge resistor and is a dummy resistor pair, the M-bit thermometer code resistor array constitutes a high-order segment of the P-terminal N-bit resistor array and includes 2 M-1 thermometer-coded resistor pair, the output terminal of the M-bit thermometer-coded resistor array serves as the output terminal of the N-bit resistor array, and the tri-state switch array includes L+2 M Each three-state switch unit is used to connect the input terminals of the L+1 resistor pairs and the 2... M -1 thermometer-coded resistor pair input terminal, the digital input signal including L+2 M This involves an N-bit digital control code. By combining this with the specific structure of an N-bit resistor array, macroscopic adjustment accuracy can be provided through the selection of a reference voltage, while microscopic adjustment accuracy can be provided through the voltage division effect of the resistor array, thus better meeting the adjustment requirements of digital-to-analog converters (DACs). Utilizing the segmented structure of an L-bit binary R-2R resistor array and an M-bit thermometer-code resistor array helps reduce the requirements of high-precision DACs on unit resistance matching, switch matching, and layout matching.

[0048] In one possible implementation, the differential analog-to-digital converter is a three-level resistive high-precision digital-to-analog converter. This provides a three-level segmented structure with three different reference voltages, reduces switching area overhead, improves on-resistance matching, avoids the introduction of additional dynamic circuitry, helps reduce static power consumption, and is beneficial for static circuit applications and applications related to high-precision resistive digital-to-analog converters.

[0049] Figure 4 This is a schematic diagram of an N-bit resistor array on the P-side of a differential fractional-to-analog converter provided in an embodiment of this application. Figure 4 As shown, the P-terminal N-bit resistor array B410 includes an L-bit binary R-2R resistor array A450, an M-bit thermometer code resistor array A454, and a bridging resistor A452. Here, N = L + M, where L and M are both positive integers greater than 0. The output terminals of the L-bit binary R-2R resistor array A450 and the M-bit thermometer code resistor array A454 are connected via the bridging resistor A452. The L-bit binary R-2R resistor array A450 constitutes the low-order segment of the P-terminal N-bit resistor array B410 and includes L+1 resistor pairs. Among the L+1 resistor pairs, the 2nd to L+1th resistor pairs are arranged from the second furthest to the closest to the bridging resistor A452, representing the least significant to the most significant resistor pair. The first resistor pair among the L+1 resistor pairs, being the furthest from the bridging resistor A452, is a dummy resistor pair. The M-bit thermometer-type resistor array A454 constitutes the high-bit segment of the P-terminal N-bit resistor array B410 and includes 2 M-1 thermometer-coded resistor pair. The output terminal of the M-bit thermometer-coded resistor array A454 serves as the output terminal 456 of the P-terminal N-bit resistor array B410. Furthermore, the tri-state switch array includes L+2... M Each three-state switch unit is used to connect the input terminals of the L+1 resistor pairs and the 2... M -1 thermometer-coded resistor pair input terminal, the digital input signal including L+2 M This involves an N-bit digital control code. By combining this with the specific structure of an N-bit resistor array, macroscopic adjustment accuracy can be provided through the selection of a reference voltage, while microscopic adjustment accuracy can be provided through the voltage division effect of the resistor array, thus better meeting the adjustment requirements of digital-to-analog converters (DACs). Utilizing the segmented structure of an L-bit binary R-2R resistor array and an M-bit thermometer-code resistor array helps reduce the requirements of high-precision DACs on unit resistance matching, switch matching, and layout matching.

[0050] Figure 5 This is a schematic diagram of an N-terminal N-bit resistor array for a differential fractional-to-analog converter provided in an embodiment of this application. Figure 5 As shown, the N-terminal N-bit resistor array B520 includes an L-bit binary R-2R resistor array B550, an M-bit thermometer code resistor array B554, and a bridging resistor B552. Where N = L + M, and L and M are both positive integers greater than 0. The output of the L-bit binary R-2R resistor array B550 is connected to the output of the M-bit thermometer code resistor array B554 via the bridging resistor B552. The L-bit binary R-2R resistor array B550 constitutes the low-order segment of the N-terminal N-bit resistor array B520 and includes L+1 resistor pairs. Among the L+1 resistor pairs, the 2nd to L+1th resistor pairs are arranged from the second furthest to the closest to the bridging resistor B552, representing the least significant to the most significant resistor pair. The first resistor pair among the L+1 resistor pairs, being the furthest from the bridging resistor B552, is a dummy resistor pair. The M-bit thermometer-type resistor array B554 constitutes the high-bit segment of the N-terminal N-bit resistor array B520 and includes 2 M -1 thermometer-coded resistor pair. The output terminal of the M-bit thermometer-coded resistor array B554 serves as the output terminal 556 of the N-bit resistor array B520. Furthermore, the tri-state switch array includes L+2... M Each three-state switch unit is used to connect the input terminals of the L+1 resistor pairs and the 2... M -1 thermometer-coded resistor pair input terminal, the digital input signal including L+2 MThe digital control code is a number of bits. Thus, the specific structure of the N-bit resistance array can be combined to provide macro adjustment accuracy by selecting the reference voltage and micro adjustment accuracy by the voltage division of the resistance array, so that the adjustment requirements of the digital-to-analog converter can be better met. The segmented structure of the L-bit binary R-2R resistance array and the M-bit thermometer code resistance array helps to reduce the requirements of high-precision digital-to-analog converters on unit resistance matching, switch matching and layout matching.

[0051] The method and the device provided by the embodiments of the present application are based on the same inventive concept, and the embodiments, the implementation manners, the examples or the implementation manners of the method and the device can be referred to each other because the principles of the method and the device for solving problems are similar, and the repeated parts will not be described herein. The embodiments of the present application further provide a system, which includes a plurality of computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be described herein.

[0052] The embodiments of the present application further provide a computer readable storage medium, which stores computer instructions, and when the computer instructions run on a computer device (such as one or more processors), the method steps in the above method embodiments can be implemented. The specific implementation of the processor of the computer readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be described herein.

[0053] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, apparatus, or computer program product. The present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both software and hardware aspects. The embodiments of the present application can be implemented partially or wholly in software, hardware, firmware, or any combination thereof. When implemented in software, the embodiments of the present application can be implemented using one or more computer program products. The computer program product can be stored on one or more computer readable storage media, which can include any available media that can be accessed by a general purpose or special purpose computing system. By way of example, such computer readable storage media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other storage medium that can be used to carry or store desired computer program code in the form of computer readable instructions or data structures and that can be accessed by a general purpose or special purpose computing system. When the computer program code is loaded into and executed by a general purpose or special purpose computing system, it can generate an apparatus, the operation of which can produce a result.

[0054] The present application is described in reference to the flowchart illustrations and / or block diagrams according to embodiments of the application. Each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, an embedded processing chip or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart Figure 1 The means can be hardware, firmware, software, or any combination thereof. Such embodiments can be implemented as computer program products. The computer program product can be tangibly embodied in an information carrier, such as in a machine-readable storage device or in an electronic, optical, or other form of carrier signal. The computer program product can include one or more computer instructions that, when executed by a computer, cause the computer to perform the functions of the embodiments of the present application. Figure 1 The means can be hardware, firmware, software, or any combination thereof. Such embodiments can be implemented as computer program products. The computer program product can be tangibly embodied in an information carrier, such as in a machine-readable storage device or in an electronic, optical, or other form of carrier signal. The computer program product can include one or more computer instructions that, when executed by a computer, cause the computer to perform the functions of the embodiments of the present application. Figure 1one or more processes and / or functions specified in one or more blocks Figure 1 These computer program instructions can also be loaded into computer or other programmable data processing devices, so that a series of operation steps are performed on the computer or other programmable data processing devices to generate computer-implemented processes, thus the instructions executed on the computer or other programmable data processing devices provide a process for implementing the functions specified in the flow Figure 1 one or more processes and / or functions specified in one or more blocks Figure 1 one or more processes and / or functions specified in one or more blocks

[0055] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiments of the present application can be adjusted, combined or deleted according to actual needs; the modules in the system of the embodiments of the present application can be divided, combined or deleted according to actual needs. If these modifications and variations of the embodiments of the present application belong to the scope of the claims of the present application and the equivalent technologies thereof, the present application also intends to include these modifications and variations.

Claims

1. A differential digital-to-analog converter, comprising: The differential digital-to-analog converter comprises: two groups of N-bit resistor arrays with the same resistor array structure, wherein N is a positive integer greater than 1, the two groups of N-bit resistor arrays are respectively a P-terminal N-bit resistor array and an N-terminal N-bit resistor array, an output terminal of the P-terminal N-bit resistor array is a P-terminal output terminal of the differential digital-to-analog converter, and an output terminal of the N-terminal N-bit resistor array is an N-terminal output terminal of the differential digital-to-analog converter; a tri-state switch array, configured to select a P-type reference voltage, an N-type reference voltage, or an intermediate reference voltage as an input voltage of the two groups of N-bit resistor arrays based on a digital input signal, the P-type reference voltage is higher than the N-type reference voltage, and the intermediate reference voltage is between the P-type reference voltage and the N-type reference voltage, the P-terminal N-bit resistor array and the N-terminal N-bit resistor array each comprise a plurality of input terminals, the tri-state switch array comprises a plurality of tri-state switch units corresponding to the plurality of input terminals one by one, each of the plurality of tri-state switch units comprises a first pair of N-type field effect tubes connected in common source, a drain of the first pair of N-type field effect tubes serves as an output of the corresponding tri-state switch unit when the intermediate reference voltage is selected, and when the digital input signal is switched, a voltage of a gate of the first pair of N-type field effect tubes is located in a voltage domain associated with the P-type reference voltage, and when switching of the digital input signal is completed, the voltage of the gate of the first pair of N-type field effect tubes is switched from the voltage domain associated with the P-type reference voltage to a voltage domain of a first power supply, and the first power supply is configured to provide a voltage equal to a sum of the P-type reference voltage and the intermediate reference voltage so as to clamp a voltage of a common source of the first pair of N-type field effect tubes at the intermediate reference voltage.

2. The differential digital-to-analog converter of claim 1, wherein, The intermediate reference voltage is a sum of a first proportion of the P-type reference voltage and a second proportion of the N-type reference voltage, and the sum of the first proportion and the second proportion is 1.

3. The differential current mode digital to analog converter of claim 2, wherein, The first proportion is 50%, and the second proportion is 50%.

4. The differential current mode digital to analog converter of claim 3, wherein, The drains of the first pair of N-type field effect tubes are respectively configured to provide an input voltage of a corresponding input terminal of the P-terminal N-bit resistor array and an input voltage of a corresponding input terminal of the N-terminal N-bit resistor array, and the common source of the first pair of N-type field effect tubes is a switch shorting point of the corresponding input terminal of the P-terminal N-bit resistor array and the corresponding input terminal of the N-terminal N-bit resistor array.

5. The differential current mode digital to analog converter of claim 4, wherein, When the corresponding input terminal of the P-terminal N-bit resistor array and the corresponding input terminal of the N-terminal N-bit resistor array are shorted by a switch, the intermediate reference voltage is generated on the common source of the first pair of N-type field effect tubes.

6. The differential digital-to-analog converter of claim 1, wherein, Each of the plurality of tri-state switch units comprises a pair of first N-type field effect transistors connected in common source, a pair of P-type field effect transistors connected in common source, and a pair of second N-type field effect transistors connected in common source, wherein a voltage of the common source of the pair of P-type field effect transistors is clamped at the P-type reference voltage, a voltage of the common source of the pair of second N-type field effect transistors is clamped at the N-type reference voltage, drains of the pair of first N-type field effect transistors are connected to a P-terminal common connection point and an N-terminal common connection point of a corresponding tri-state switch unit respectively, drains of the pair of P-type field effect transistors are connected to the P-terminal common connection point and the N-terminal common connection point respectively, drains of the pair of second N-type field effect transistors are connected to the P-terminal common connection point and the N-terminal common connection point respectively, the P-terminal common connection point is configured to provide an input voltage of a corresponding input terminal of the P-terminal N-bit resistance array, and the N-terminal common connection point is configured to provide an input voltage of a corresponding input terminal of the N-terminal N-bit resistance array.

7. The differential current mode digital to analog converter of claim 6, wherein, The digital input signal comprises a first pair of digital control codes for controlling a voltage of the gates of the pair of first N-type field effect transistors so as to select the intermediate reference voltage as the input voltage of the corresponding input terminals of the two groups of N-bit resistance arrays, the digital input signal further comprises a second pair of digital control codes for controlling a voltage of the gates of the pair of P-type field effect transistors so as to select the P-type reference voltage as the input voltage of the corresponding input terminals of the two groups of N-bit resistance arrays, and the digital input signal further comprises a third pair of digital control codes for controlling a voltage of the gates of the pair of second N-type field effect transistors so as to select the N-type reference voltage as the input voltage of the corresponding input terminals of the two groups of N-bit resistance arrays.

8. The differential analog-to-digital converter of claim 7, wherein, When any one of the first pair of digital control codes, the second pair of digital control codes, and the third pair of digital control codes switches code type, the voltage of the gates of the pair of first N-type field effect transistors is in a voltage domain associated with the P-type reference voltage, and when all of the first pair of digital control codes, the second pair of digital control codes, and the third pair of digital control codes complete code type switching, the voltage of the gates of the pair of first N-type field effect transistors switches from the voltage domain associated with the P-type reference voltage to a voltage domain of the first power supply.

9. The differential current mode digital to analog converter of claim 8, wherein, The differential digital-to-analog converter further comprises a gate voltage control circuit, the gate voltage control circuit comprises a plurality of level conversion circuits, each of the plurality of level conversion circuits corresponds to a gate of a corresponding one of the pair of first N-type field effect transistors comprised by each of the plurality of tri-state switch units, a high power input of each of the plurality of level conversion circuits is selected from the P-type reference voltage or an output of the first power supply based on a gate voltage control signal, the gate voltage control signal is determined based on a change of the digital input signal, and an output of each of the plurality of level conversion circuits is configured to drive a corresponding gate of a corresponding one of the pair of first N-type field effect transistors of a corresponding one of the plurality of tri-state switch units.

10. The differential current mode digital to analog converter of claim 9, wherein, When the gate voltage control signal is low, the pass gates associated with the plurality of level shifting circuits couple a high supply input of each of the plurality of level shifting circuits to the P-type reference voltage, when the gate voltage control signal is high, the pass gates associated with the plurality of level shifting circuits couple a high supply input of each of the plurality of level shifting circuits to an output of the first power supply, and the output of each of the plurality of level shifting circuits is determined based on the first pair of digital control codes.

11. The differential digital-to-analog converter of claim 1, wherein, The P-terminal N-bit resistance array includes an L-bit binary type R-2R resistance array and an M-bit thermometer code type resistance array and a bridge resistance, wherein N=L+M, L and M are both positive integers greater than 0, the output end of the L-bit binary type R-2R resistance array is connected with the output end of the M-bit thermometer code type resistance array through the bridge resistance, the L-bit binary type R-2R resistance array constitutes a low bit section of the P-terminal N-bit resistance array and includes L+1 resistance pairs, the 2nd to the L+1th resistance pairs in the L+1 resistance pairs are the lowest bit resistance pair to the highest bit resistance pair in turn from the second farthest to the closest to the bridge resistance, the 1st resistance pair in the L+1 resistance pairs is the farthest to the bridge resistance and is a virtual resistance pair, the M-bit thermometer code type resistance array constitutes a high bit section of the P-terminal N-bit resistance array and includes 2 M -1 thermometer code type resistance pairs, the output end of the M-bit thermometer code type resistance array is the output end of the P-terminal N-bit resistance array, and the tri-state switch array includes L+2 M Tri-state switch units for respectively connecting the input ends of the L+1 resistance pairs and the input ends of the 2 M -1 thermometer code type resistance pairs, and the digital input signal includes L+2 M bit digital control codes.

12. The differential analog-to-digital converter of claim 1, wherein, The N-bit resistance array includes an L-bit binary R-2R resistance array, an M-bit thermometer code resistance array, and a bridge resistance, wherein N=L+M, L and M are positive integers greater than 0, an output end of the L-bit binary R-2R resistance array is connected with an output end of the M-bit thermometer code resistance array through the bridge resistance, the L-bit binary R-2R resistance array constitutes a low-order segment of the N-bit resistance array and includes L+1 resistance pairs, the 2nd to the L+1th resistance pairs in the L+1 resistance pairs are the lowest resistance pair to the highest resistance pair in turn from the second farthest to the closest to the bridge resistance, the 1st resistance pair in the L+1 resistance pairs is the farthest to the bridge resistance and is a virtual resistance pair, the M-bit thermometer code resistance array constitutes a high-order segment of the N-bit resistance array and includes 2 M -1 thermometer code resistance pairs, the output end of the M-bit thermometer code resistance array is an output end of the N-bit resistance array, and the tri-state switch array includes L+2 M tri-state switch units for respectively connecting input ends of the L+1 resistance pairs and input ends of the 2 M -1 thermometer code resistance pairs, and the digital input signal includes an L+2 M -bit digital control code.

13. The differential digital-to-analog converter of claim 1, wherein, The differential digital-to-analog converter is a three-level resistor string high precision digital-to-analog converter.

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