Capacitor structure and preparation method thereof

Abstract

The invention provides a capacitor structure and a preparation method thereof, and the preparation method comprises the steps: forming a first capacitor structure which comprises a first substrate, a first groove-type capacitor, a first interlayer dielectric layer and a first electrode structure, and forming a second capacitor structure which comprises a second substrate, a second groove-type capacitor, a first interlayer dielectric layer and a second electrode structure, the second capacitor structure comprises a second substrate, a first groove type capacitor, a second interlayer dielectric layer and a second electrode structure, the first capacitor structure and the second capacitor structure are bonded so that the first groove type capacitor and the second groove type capacitor can be connected in parallel, and a plurality of metal protruding blocks arranged at intervals are formed on the second face of the first substrate; and the metal bumps are electrically connected with the first electrode structure through the TSV metal columns, or a plurality of metal bumps arranged at intervals are formed on the second surface of the second substrate, and the metal bumps are electrically connected with the second electrode structure through the TSV metal columns. The capacitor structure provided by the invention can realize a higher capacitance value under a limited chip area.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and relates to a capacitor structure and its preparation method. Background Technology

[0002] Silicon-based capacitor technology emerged alongside the development of semiconductor manufacturing processes. As semiconductor technology progressed, these processes were gradually incorporated into capacitor manufacturing, driving the development and evolution of silicon-based capacitors. Silicon-based capacitors can achieve high capacitance values ​​within a relatively small chip area, which is crucial for electronic devices requiring high integration. Furthermore, they possess high reliability and stability, can operate normally under harsh environmental conditions, and are seamlessly compatible with existing semiconductor manufacturing processes, facilitating integration into integrated circuits.

[0003] However, as electronic devices increasingly demand higher capacitance values, it is necessary to achieve higher capacitance values ​​within a limited chip area. Currently, methods such as multiple depositions or increasing the depth of deep trench etching are commonly used to increase capacitance. However, due to process bottlenecks, simply increasing the aspect ratio of the trench cannot infinitely increase the capacitance value; the capacitance density of deep trench capacitor (DTC) technology has an upper limit.

[0004] Therefore, how to provide a capacitor structure and its fabrication method to achieve higher capacitance values ​​within a limited chip area to meet customer needs has become an important problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a capacitor structure and its fabrication method to solve the problem that deep trench capacitors are difficult to further increase capacitance on a limited chip area.

[0007] To achieve the above and other related objectives, the present invention provides a method for preparing a capacitor structure, characterized by comprising the following steps:

[0008] A first capacitor structure is formed, the first capacitor structure including a first substrate, a first trench capacitor, a first interlayer dielectric layer and a first electrode structure. The first substrate includes a first surface and a second surface disposed opposite to each other. The first trench capacitor is located on the first surface of the first substrate and extends into the first substrate. The first interlayer dielectric layer is located on the first surface of the first substrate and covers the first trench capacitor. The first electrode structure is located in the first interlayer dielectric layer and includes a first lower electrode bonding pad and a first upper electrode bonding pad exposed on the surface of the first interlayer dielectric layer. The first lower electrode bonding pad is electrically connected to the lower electrode layer of the first trench capacitor, and the first upper electrode bonding pad is electrically connected to the upper electrode layer of the first trench capacitor.

[0009] A second capacitor structure is formed, the second capacitor structure including a second substrate, a second trench capacitor, a second interlayer dielectric layer and a second electrode structure. The second substrate includes a first surface and a second surface disposed opposite to each other. The second trench capacitor is located on the first surface of the second substrate and extends into the second substrate. The second interlayer dielectric layer is located on the first surface of the second substrate and covers the second trench capacitor. The second electrode structure is located in the second interlayer dielectric layer and includes a second lower electrode bonding pad and a second upper electrode bonding pad exposed on the surface of the second interlayer dielectric layer. The second lower electrode bonding pad is electrically connected to the lower electrode layer of the second trench capacitor, and the second upper electrode bonding pad is electrically connected to the upper electrode layer of the second trench capacitor.

[0010] The first capacitor structure and the second capacitor structure are bonded to make the first trench capacitor and the second trench capacitor connected in parallel, wherein the first lower electrode bonding pad and the second lower electrode bonding pad are aligned and connected to each other, and the first upper electrode bonding pad and the second upper electrode bonding pad are aligned and connected to each other.

[0011] A plurality of spaced metal bumps are formed on the second surface of the first substrate, and the metal bumps are electrically connected to the first electrode structure through TSV metal pillars; or a plurality of spaced metal bumps are formed on the second surface of the second substrate, and the metal bumps are electrically connected to the second electrode structure through TSV metal pillars.

[0012] Optionally, the step of forming the first capacitor structure includes:

[0013] A first groove is formed on the first surface of the first substrate;

[0014] A first conductive layer structure is formed, the first conductive layer structure is located in the first groove and extends to the substrate surface outside the first groove, the first conductive structure includes a first insulating layer, a first lower electrode layer, a first dielectric layer and a first upper electrode layer stacked in sequence;

[0015] The first conductive layer structure is graphically represented to obtain the first trench capacitor, wherein the portion of the first lower electrode layer located outside the first groove has a first lower electrode lead that protrudes horizontally beyond the first dielectric layer and the first upper electrode layer.

[0016] A first interlayer dielectric layer covering the first trench capacitor is formed on the first surface of the first substrate;

[0017] The first electrode structure is formed in the first interlayer dielectric layer. The first electrode structure further includes a first lower electrode contact portion and a first upper electrode contact portion. One end of the first lower electrode contact portion is connected to the first lower electrode lead-out portion, and the other end is connected to the first lower electrode bonding pad. One end of the first upper electrode contact portion is connected to the first upper electrode layer, and the other end is connected to the first upper electrode bonding pad.

[0018] Optionally, the aspect ratio of the first groove is in the range of 18 to 22.

[0019] Optionally, the number of the first grooves is one or more. When the number of the first grooves is multiple, the multiple first grooves have the same width or at least two of the first grooves have different widths.

[0020] Optionally, the step of forming the first electrode structure includes:

[0021] A first stepped opening and a second stepped opening are formed in the first interlayer dielectric layer. The bottom of the first stepped opening exposes a portion of the first upper electrode layer, and the bottom of the second stepped opening exposes a portion of the first lower electrode lead-out portion.

[0022] Metal is deposited in the first stepped opening to form the first upper electrode contact portion and the first upper electrode bonding pad, and metal is deposited in the second stepped opening to form the first lower electrode contact portion and the first lower electrode bonding pad.

[0023] Optionally, the step of forming the second capacitor structure includes:

[0024] A second groove is formed in the second substrate;

[0025] A second conductive layer structure is formed, the second conductive layer structure is located in the second groove and extends to the substrate surface outside the second groove, the second conductive layer structure includes a second insulating layer, a second lower electrode layer, a second dielectric layer and a second upper electrode layer stacked in sequence;

[0026] The second conductive layer structure is graphically represented to obtain the second trench capacitor, wherein the portion of the second lower electrode layer located outside the second groove has a second lower electrode lead that protrudes horizontally beyond the second dielectric layer and the second upper electrode layer.

[0027] A second interlayer dielectric layer covering the second trench capacitor is formed on the first surface of the second substrate;

[0028] A second electrode structure is formed in the second interlayer dielectric layer. The second electrode structure further includes a second lower electrode contact portion and a second upper electrode contact portion. One end of the second lower electrode contact portion is connected to the second lower electrode lead-out portion, and the other end is connected to the second lower electrode bonding pad. One end of the second upper electrode contact portion is connected to the second upper electrode layer, and the other end is connected to the second upper electrode bonding pad.

[0029] Optionally, the aspect ratio of the second groove is in the range of 18 to 22.

[0030] Optionally, the number of the second grooves is one or more. When the number of the second grooves is multiple, the multiple second grooves have the same width or at least two of the second grooves have different widths.

[0031] Optionally, the step of forming the second electrode structure includes:

[0032] A third and a fourth stepped opening are formed in the second interlayer dielectric layer. The bottom of the third stepped opening exposes a portion of the second upper electrode layer, and the bottom of the fourth stepped opening exposes a portion of the second lower electrode lead-out.

[0033] Metal is deposited in the third stepped opening to form the second upper electrode contact portion and the second upper electrode bonding pad, and metal is deposited in the fourth stepped opening to form the second lower electrode contact portion and the second lower electrode bonding pad.

[0034] The present invention also provides a capacitor structure, characterized in that it comprises:

[0035] A first capacitor structure includes a first substrate, a first trench capacitor, a first interlayer dielectric layer, and a first electrode structure. The first substrate includes a first surface and a second surface disposed opposite to each other. The first trench capacitor is located on the first surface of the first substrate and extends into the first substrate. The first interlayer dielectric layer is located on the first surface of the first substrate and covers the first trench capacitor. The first electrode structure is located in the first interlayer dielectric layer and includes a first lower electrode bonding pad and a first upper electrode bonding pad exposed on the surface of the first interlayer dielectric layer. The first lower electrode bonding pad is electrically connected to the lower electrode layer of the first trench capacitor, and the first upper electrode bonding pad is electrically connected to the upper electrode layer of the first trench capacitor.

[0036] The second capacitor structure includes a second substrate, a second trench capacitor, a second interlayer dielectric layer, and a second electrode structure. The second substrate includes a first surface and a second surface disposed opposite to each other. The second trench capacitor is located on the first surface of the second substrate and extends into the second substrate. The second interlayer dielectric layer is located on the first surface of the second substrate and covers the second trench capacitor. The second electrode structure is located in the second interlayer dielectric layer and includes a second lower electrode bonding pad and a second upper electrode bonding pad exposed on the surface of the second interlayer dielectric layer. The second lower electrode bonding pad is electrically connected to the lower electrode layer of the second trench capacitor, and the second upper electrode bonding pad is electrically connected to the upper electrode layer of the second trench capacitor. The second capacitor structure is bonded to the first capacitor structure to connect the first trench capacitor and the second trench capacitor in parallel. The first lower electrode bonding pad and the second lower electrode bonding pad are aligned and connected to each other, and the first upper electrode bonding pad and the second upper electrode bonding pad are aligned and connected to each other.

[0037] Multiple metal bumps and multiple TVS metal pillars are provided. The multiple metal bumps are spaced apart on the second surface of the first substrate or the second surface of the second substrate. The metal bumps are electrically connected to the first electrode structure or the second electrode structure through the TSV metal pillars.

[0038] Optionally, the first electrode structure further includes a first lower electrode contact portion and a first upper electrode contact portion. One end of the first lower electrode contact portion is connected to the first lower electrode lead-out portion, and the other end is connected to the first lower electrode bonding pad. One end of the first upper electrode contact portion is connected to the first upper electrode layer, and the other end is connected to the first upper electrode bonding pad.

[0039] Optionally, the second electrode structure further includes a second lower electrode contact portion and a second upper electrode contact portion. One end of the second lower electrode contact portion is connected to the second lower electrode lead-out portion, and the other end is connected to the second lower electrode bonding pad. One end of the second upper electrode contact portion is connected to the second upper electrode layer, and the other end is connected to the second upper electrode bonding pad.

[0040] As described above, the present invention provides a capacitor structure and its fabrication method. The fabrication method includes the following steps: forming a first capacitor structure, the first capacitor structure including a first substrate, a first trench capacitor, a first interlayer dielectric layer, and a first electrode structure; forming a second capacitor structure, the second capacitor structure including a second substrate, a first trench capacitor, a second interlayer dielectric layer, and a second electrode structure; bonding the first capacitor structure and the second capacitor structure to connect the first trench capacitor and the second trench capacitor in parallel; forming a plurality of spaced metal bumps on the second surface of the first substrate, the metal bumps being electrically connected to the first electrode structure via TSV metal pillars; or forming a plurality of spaced metal bumps on the second surface of the second substrate, the metal bumps being electrically connected to the second electrode structure via TSV metal pillars. The capacitor structure of the present invention can achieve a higher capacitance value within a limited chip area. Attached Figure Description

[0041] Figure 1 The diagram shows a process flow chart of the method for preparing the capacitor structure of the present invention.

[0042] Figure 2 The diagram shown is a schematic of the first capacitor structure formed in the method for preparing the capacitor structure of the present invention.

[0043] Figure 3 The diagram shows a schematic of the structure obtained after providing a first substrate and forming a first groove in the method for preparing the capacitor structure of the present invention.

[0044] Figure 4 The diagram shown is a schematic diagram of the structure obtained after forming the first conductive layer structure in the method for preparing the capacitor structure of the present invention.

[0045] Figure 5 The diagram shown is a schematic diagram of the structure obtained after forming the first lower electrode lead-out portion in the method for preparing the capacitor structure of the present invention.

[0046] Figure 6 The diagram shown is a schematic diagram of the structure obtained after forming the first interlayer dielectric layer in the method for preparing the capacitor structure of the present invention.

[0047] Figure 7 The diagram shown is a schematic diagram of the structure obtained after forming the first electrode structure in the method for preparing the capacitor structure of the present invention.

[0048] Figure 8 The diagram shown is a schematic of the structure obtained after forming the first and second stepped openings in the method for preparing the capacitor structure of the present invention.

[0049] Figure 9 The diagram shown is a schematic of the second capacitor structure formed in the method for preparing the capacitor structure of the present invention.

[0050] Figure 10 The diagram shows a schematic of the structure obtained after providing a second substrate and forming a second groove in the method for preparing the capacitor structure of the present invention.

[0051] Figure 11 The diagram shown is a schematic diagram of the structure obtained after forming the second conductive layer structure in the method for preparing the capacitor structure of the present invention.

[0052] Figure 12 The diagram shown is a schematic of the structure obtained after forming the second lower electrode lead-out portion in the method for preparing the capacitor structure of the present invention.

[0053] Figure 13 The diagram shown is a schematic of the structure obtained after forming the second interlayer dielectric layer in the method for preparing the capacitor structure of the present invention.

[0054] Figure 14 The diagram shown is a schematic diagram of the structure obtained after forming the second electrode structure in the method for preparing the capacitor structure of the present invention.

[0055] Figure 15 The diagram shown is a schematic of the structure obtained after forming the third and fourth step openings in the method for preparing the capacitor structure of the present invention.

[0056] Figure 16 The diagram shown is a schematic diagram of the structure obtained by bonding the first capacitor structure and the second capacitor structure in the method for preparing the capacitor structure of the present invention.

[0057] Figure 17 The diagram shown is a schematic of the structure obtained after forming metal bumps and TSV metal pillars in the method for preparing the capacitor structure of the present invention.

[0058] Figure 18 This is another schematic diagram showing the structure obtained after forming metal bumps and TSV metal pillars in the method for preparing the capacitor structure of the present invention.

[0059] Explanation of reference numerals in the attached figures

[0060] 1. First Capacitor Structure

[0061] 101 First Substrate

[0062] 102 First trench capacitor

[0063] 1020 First Groove

[0064] 1021 First Insulation Layer

[0065] 1022 First lower electrode layer

[0066] 1023 First Dielectric Layer

[0067] 1024 First upper electrode layer

[0068] 103 First Interlayer Dielectric Layer

[0069] 104 First Electrode Structure

[0070] 1041 First lower electrode bonding pad

[0071] 1042 First upper electrode bonding pad

[0072] 1043 First upper electrode contact portion

[0073] 1044 First lower electrode contact portion

[0074] 105 First lower electrode lead-out section

[0075] 106 First-step opening

[0076] 107 Second trapezoidal opening

[0077] 2. Second capacitor structure

[0078] 201 Second Substrate

[0079] 202 Second trench capacitor

[0080] 2020 Second Groove

[0081] 2021 Second Insulation Layer

[0082] 2022 Second Lower Electrode Layer

[0083] 2023 Second Dielectric Layer

[0084] 2024 Second Upper Electrode Layer

[0085] 203 Second Interlayer Dielectric Layer

[0086] 204 Second Electrode Structure

[0087] 2041 Second lower electrode bonding pad

[0088] 2042 Second upper electrode bonding pad

[0089] 2043 Second upper electrode contact portion

[0090] 2044 Second lower electrode contact part

[0091] 205 Second lower electrode lead-out section

[0092] 206 Third-step trapezoidal opening

[0093] 207 Fourth-step opening

[0094] 3 metal bumps

[0095] 4 TSV metal pillars

[0096] Steps S1-S4 Detailed Implementation

[0097] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0098] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0099] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0100] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0101] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0102] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0103] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0104] Please see Figure 1 The diagram shows a process flow chart of the method for preparing the capacitor structure of the present invention, which includes the following steps:

[0105] S1: Form a first capacitor structure, the first capacitor structure including a first substrate, a first trench capacitor, a first interlayer dielectric layer and a first electrode structure, the first substrate including a first surface and a second surface disposed opposite to each other, the first trench capacitor being located on the first surface of the first substrate and extending into the first substrate, the first interlayer dielectric layer being located on the first surface of the first substrate and covering the first trench capacitor, the first electrode structure being located in the first interlayer dielectric layer and including a first lower electrode bonding pad and a first upper electrode bonding pad exposed on the surface of the first interlayer dielectric layer, the first lower electrode bonding pad being electrically connected to the lower electrode layer of the first trench capacitor, and the first upper electrode bonding pad being electrically connected to the upper electrode layer of the first trench capacitor;

[0106] S2: Form a second capacitor structure, the second capacitor structure including a second substrate, a second trench capacitor, a second interlayer dielectric layer and a second electrode structure, the second substrate including a first surface and a second surface disposed opposite to each other, the second trench capacitor being located on the first surface of the second substrate and extending into the second substrate, the second interlayer dielectric layer being located on the first surface of the second substrate and covering the second trench capacitor, the second electrode structure being located in the second interlayer dielectric layer and including a second lower electrode bonding pad and a second upper electrode bonding pad exposed on the surface of the second interlayer dielectric layer, the second lower electrode bonding pad being electrically connected to the lower electrode layer of the second trench capacitor, and the second upper electrode bonding pad being electrically connected to the upper electrode layer of the second trench capacitor;

[0107] S3: Bond the first capacitor structure to the second capacitor structure so that the first trench capacitor and the second trench capacitor are connected in parallel, wherein the first lower electrode bonding pad and the second lower electrode bonding pad are aligned and connected to each other, and the first upper electrode bonding pad and the second upper electrode bonding pad are aligned and connected to each other.

[0108] S4: A plurality of spaced metal bumps are formed on the second surface of the first substrate, and the metal bumps are electrically connected to the first electrode structure through TSV metal pillars; or a plurality of spaced metal bumps are formed on the second surface of the second substrate, and the metal bumps are electrically connected to the second electrode structure through TSV metal pillars.

[0109] The following will combine Figures 2 to 17 The various steps of the method for preparing the capacitor structure of the present invention are described in detail.

[0110] Please refer to the following first. Figure 2 Step S1 is executed: a first capacitor structure 1 is formed. The first capacitor structure 1 includes a first substrate 101, a first trench capacitor 102, a first interlayer dielectric layer 103, and a first electrode structure 104. The first substrate 101 includes a first surface and a second surface disposed opposite to each other. The first trench capacitor 102 is located on the first surface of the first substrate 101 and extends into the first substrate 101. The first interlayer dielectric layer 103 is located on the first surface of the first substrate 101 and covers the first trench capacitor 102. The first electrode structure 104 is located in the first interlayer dielectric layer 103 and includes a first lower electrode bonding pad 1041 and a first upper electrode bonding pad 1042 exposed on the surface of the first interlayer dielectric layer 103. The first lower electrode bonding pad 1041 is electrically connected to the lower electrode layer of the first trench capacitor 102, and the first upper electrode bonding pad 1042 is electrically connected to the upper electrode layer of the first trench capacitor 102.

[0111] As an example, the steps for forming the first capacitor structure 1 include:

[0112] (1) Please refer to Figure 3 A first groove 1020 is formed on the first surface of the first substrate 101;

[0113] (2) Please refer to Figure 4 A first conductive layer structure is formed, which is located in the first groove 1020 and extends to the substrate surface outside the first groove 1020. The first conductive structure includes a first insulating layer 1021, a first lower electrode layer 1022, a first dielectric layer 1023 and a first upper electrode layer 1024 stacked sequentially.

[0114] (3) Please refer to Figure 5 The first conductive layer structure is graphically represented to obtain the first trench capacitor 102, wherein the portion of the first lower electrode layer 1022 located outside the first groove 1020 has a first lower electrode lead-out portion 105 that protrudes horizontally from the first dielectric layer 1023 and the first upper electrode layer 1024.

[0115] (4) Please refer to Figure 6 The first interlayer dielectric layer 103 covering the first trench capacitor is formed on the first surface of the first substrate 101.

[0116] (5) Please refer to Figure 7 The first electrode structure 104 is formed in the first interlayer dielectric layer 103. The first electrode structure 104 further includes a first lower electrode contact portion 1044 and a first upper electrode contact portion 1043. One end of the first lower electrode contact portion 1044 is connected to the first lower electrode lead-out portion 105, and the other end is connected to the first lower electrode bonding pad 1041. One end of the first upper electrode contact portion 1043 is connected to the first upper electrode layer 1024, and the other end is connected to the first upper electrode bonding pad 1042.

[0117] As an example, the aspect ratio of the first groove 1020 is in the range of 18 to 22. In this embodiment, the aspect ratio of the first groove 1020 is preferably 20. In other embodiments, the aspect ratio of the first groove 1020 can also be other suitable values.

[0118] As an example, the number of the first grooves 1020 is one or more. When the number of the first grooves 1020 is multiple, the multiple first grooves 1020 have the same width or at least two of the first grooves 1020 have different widths.

[0119] As an example, the steps for forming the first electrode structure 104 include:

[0120] (1) Please refer to Figure 8 A first stepped opening 106 and a second stepped opening 107 are formed in the first interlayer dielectric layer 103. The bottom of the first stepped opening 106 exposes the first upper electrode layer 1024, and the bottom of the second stepped opening 107 exposes the first lower electrode lead-out portion 105.

[0121] (2) Please refer to the following: Figure 7Metal is deposited in the first stepped opening 106 to form the first upper electrode contact 1043 and the first upper electrode bonding pad 1042, and metal is deposited in the second stepped opening 107 to form the first lower electrode contact 1044 and the first lower electrode bonding pad 1041.

[0122] Please see Figure 9 Step S2 is executed: a second capacitor structure 2 is formed. The second capacitor structure 2 includes a second substrate 201, a second trench capacitor 202, a second interlayer dielectric layer 203, and a second electrode structure 204. The second substrate 201 includes a first surface and a second surface disposed opposite to each other. The second trench capacitor 202 is located on the first surface of the second substrate 201 and extends into the second substrate 201. The second interlayer dielectric layer 203 is located on the first surface of the second substrate 201 and covers the second trench capacitor 202. The second electrode structure 204 is located in the second interlayer dielectric layer 203 and includes a second lower electrode bonding pad 2041 and a second upper electrode bonding pad 2042 exposed on the surface of the second interlayer dielectric layer 203. The second lower electrode bonding pad 2041 is electrically connected to the lower electrode layer of the second trench capacitor 202, and the second upper electrode bonding pad 2042 is electrically connected to the upper electrode layer of the second trench capacitor 202.

[0123] As an example, the steps for forming the second capacitor structure 2 include:

[0124] (1) Please refer to Figure 10 A second groove 2020 is formed in the second substrate 201;

[0125] (2) Please refer to Figure 11 A second conductive layer structure is formed, which is located in the second groove 2020 and extends to the substrate surface outside the second groove 2020. The second conductive layer structure includes a second insulating layer 2021, a second lower electrode layer 2022, a second dielectric layer 2023 and a second upper electrode layer 2024 stacked in sequence.

[0126] (3) Please refer to Figure 12 The second conductive layer structure is graphically represented to obtain the second trench capacitor 202, wherein the portion of the second lower electrode layer 2022 located outside the second groove 2020 has a second lower electrode lead-out portion 205 that protrudes horizontally from the second dielectric layer 2023 and the second upper electrode layer 2024.

[0127] (4) Please refer to Figure 13 A second interlayer dielectric layer 203 covering the second trench capacitor 202 is formed on the first surface of the second substrate 201.

[0128] (5) Please refer to Figure 14 A second electrode structure 204 is formed in the second interlayer dielectric layer 203. The second electrode structure 204 further includes a second lower electrode contact portion 2044 and a second upper electrode contact portion 2043. One end of the second lower electrode contact portion 2044 is connected to the second lower electrode lead-out portion 205, and the other end is connected to the second lower electrode bonding pad 2041. One end of the second upper electrode contact portion 2043 is connected to the second upper electrode layer 2024, and the other end is connected to the second upper electrode bonding pad 2042.

[0129] As an example, the aspect ratio of the second groove 2020 is in the range of 18 to 22. In this embodiment, the aspect ratio of the second groove 2020 is preferably 20. In other embodiments, the aspect ratio of the second groove 2020 can also be other suitable values.

[0130] As an example, the number of the second groove 2020 is one or more. When the number of the second groove 2020 is multiple, the multiple second grooves 2020 have the same width or at least two second grooves 2020 have different widths.

[0131] As an example, the steps for forming the second electrode structure 204 include:

[0132] (1) Please refer to Figure 15 A third stepped opening 206 and a fourth stepped opening 207 are formed in the second interlayer dielectric layer 203. The bottom of the third stepped opening 206 exposes the second upper electrode layer 2024, and the bottom of the fourth stepped opening 207 exposes the second lower electrode lead-out portion 205.

[0133] (2) Please refer to the following: Figure 14 Metal is deposited in the third stepped opening 206 to form the second upper electrode contact 2043 and the second upper electrode bonding pad 2042, and metal is deposited in the fourth stepped opening 207 to form the second lower electrode contact 2044 and the second lower electrode bonding pad 2041.

[0134] Please see Figure 16 Step S3: Bond the first capacitor structure 1 and the second capacitor structure 2 to connect the first trench capacitor 102 and the second trench capacitor 202 in parallel, wherein the first lower electrode bonding pad 1041 and the second lower electrode bonding pad 2041 are aligned and connected to each other, and the first upper electrode bonding pad 1042 and the second upper electrode bonding pad 2042 are aligned and connected to each other.

[0135] Specifically, the first capacitor structure 1 and the second capacitor structure 2 are mirror-symmetrical with respect to the bonding surface (i.e., the first surface of the first capacitor structure 1 or the first surface of the second capacitor structure 2), which facilitates the alignment and connection of the first lower electrode bonding pad 1041 and the second lower electrode bonding pad 2041, and the alignment and connection of the second upper electrode bonding pad 2042, thereby ensuring the interconnection of the first lower electrode layer 1022 of the first capacitor structure 1 and the second lower electrode layer 2022 of the second capacitor structure 2, and the interconnection of the first upper electrode layer 1022 of the first capacitor structure 1. 4 is interconnected with the second upper electrode layer 2024 of the second capacitor structure 2, thereby realizing the parallel connection of the first trench capacitor 102 and the second trench capacitor 202. That is to say, the operator only needs to align the first surface of the first capacitor structure 1 with the first surface of the second capacitor structure 2, and then align the two sides of the first capacitor structure 1 with the two sides of the second capacitor structure 2 to achieve the bonding of the first capacitor structure 1 and the second capacitor structure 2. There is no need to specifically check the mutual alignment between the second upper electrode bonding pad 2042 and the second upper electrode bonding pad 2042, which facilitates the fabrication of the capacitor structure.

[0136] As an example, after depositing metal in the first stepped opening 106, the second stepped opening 107, the third stepped opening 206, and the fourth stepped opening 207, the method further includes a step of chemical mechanical polishing of the metal layers on the first interlayer dielectric layer 103 and the second interlayer dielectric layer 203 to expose the first upper electrode bonding pad 1042, the first lower electrode bonding pad 1041, the second upper electrode bonding pad 2042, and the second lower electrode bonding pad 2041.

[0137] Please see Figures 17 to 18 Step S4 is executed as follows: A plurality of spaced-apart metal bumps 3 are formed on the second surface of the first substrate 101, and the metal bumps 3 are electrically connected to the first electrode structure 104 via TSV metal pillars 4; or a plurality of spaced-apart metal bumps 3 are formed on the second surface of the second substrate 201, and the metal bumps 3 are electrically connected to the second electrode structure 204 via TSV metal pillars 4, wherein... Figure 17 This diagram illustrates a structure obtained after forming the metal bump 3 and the TSV metal pillar 4 in the method for preparing the capacitor structure of the present invention. Figure 18 This is another schematic diagram showing the structure obtained after forming the metal bump 3 and the TSV metal pillar 4 in the method for preparing the capacitor structure of the present invention.

[0138] Specifically, the method for preparing the capacitor structure of the present invention connects the first capacitor structure 1 and the second capacitor structure 2 by bonding, thereby realizing the parallel connection of the first trench capacitor 101 and the second trench capacitor 102, increasing the capacitance of the capacitor within a limited area, that is, improving the capacitance density and capacitance of the capacitor within a limited area.

[0139] This completes the fabrication of a capacitor structure. Please refer to [link / reference]. Figures 17 to 18 The capacitor structure includes: a first capacitor structure 1, a second capacitor structure 2, multiple metal bumps 3, and multiple TVS metal pillars.

[0140] Specifically, the first capacitor structure 1 includes a first substrate 101, a first trench capacitor 102, a first interlayer dielectric layer 103, and a first electrode structure 104. The first substrate 101 includes a first surface and a second surface disposed opposite to each other. The first trench capacitor is located on the first surface of the first substrate 101 and extends into the first substrate 101. The first interlayer dielectric layer 103 is located on the first surface of the first substrate 101 and covers the first trench capacitor 102. The first electrode structure 104 is located in the first interlayer dielectric layer 103 and includes a first lower electrode bonding pad 1041 and a first upper electrode bonding pad 1042 exposed on the surface of the first interlayer dielectric layer 103. The first lower electrode bonding pad 1041 is electrically connected to the lower electrode layer of the first trench capacitor 102, and the first upper electrode bonding pad 1042 is electrically connected to the upper electrode layer of the first trench capacitor 102.

[0141] Specifically, the second capacitor structure 2 includes a second substrate 201, a second trench capacitor 202, a second interlayer dielectric layer 203, and a second electrode structure 204. The second substrate 201 includes a first surface and a second surface disposed opposite to each other. The second trench capacitor 202 is located on the first surface of the second substrate 201 and extends into the second substrate 201. The second interlayer dielectric layer 203 is located on the first surface of the second substrate 201 and covers the second trench capacitor 202. The second electrode structure 204 is located in the second interlayer dielectric layer 203 and includes a second lower electrode bonding pad 2041 exposed on the surface of the second interlayer dielectric layer 203. The second upper electrode bonding pad 2042, the second lower electrode bonding pad 2041 is electrically connected to the lower electrode layer of the second trench capacitor 202, and the second upper electrode bonding pad 2042 is electrically connected to the upper electrode layer of the second trench capacitor 202. The second capacitor structure 2 is bonded to the first capacitor structure 1 so that the first trench capacitor 102 and the second trench capacitor 202 are connected in parallel. The first lower electrode bonding pad 1041 and the second lower electrode bonding pad 2041 are aligned and connected to each other, and the second upper electrode bonding pad 2042 is aligned and connected to each other.

[0142] Specifically, a plurality of metal bumps 3 are spaced apart on the second surface of the first substrate 101 or the second surface of the second substrate 201, and the metal bumps 3 are electrically connected to the first electrode structure 104 or the second electrode structure 204 through the TSV metal pillars 4.

[0143] As an example, the first electrode structure 104 further includes a first lower electrode contact portion 1044 and a first upper electrode contact portion 1043. One end of the first lower electrode contact portion 1044 is connected to the first lower electrode lead-out portion 105, and the other end is connected to the first lower electrode bonding pad 1041. One end of the first upper electrode contact portion 1043 is connected to the first upper electrode layer 1024, and the other end is connected to the first upper electrode bonding pad 1042.

[0144] As an example, the second electrode structure 204 further includes a second lower electrode contact portion 2044 and a second upper electrode contact portion 2043. One end of the second lower electrode contact portion 2044 is connected to the second lower electrode lead-out portion 205, and the other end is connected to the second lower electrode bonding pad 2042. Two ends of the second upper electrode contact portion 2043 are connected to the second upper electrode layer 2024, and the other two ends are connected to the second upper electrode bonding pad 2042.

[0145] In summary, this invention provides a capacitor structure and its fabrication method. The fabrication method includes the following steps: forming a first capacitor structure, the first capacitor structure including a first substrate, a first trench capacitor, a first interlayer dielectric layer, and a first electrode structure; forming a second capacitor structure, the second capacitor structure including a second substrate, a first trench capacitor, a second interlayer dielectric layer, and a second electrode structure; bonding the first capacitor structure and the second capacitor structure to connect the first trench capacitor and the second trench capacitor in parallel; forming a plurality of spaced metal bumps on the second surface of the first substrate, the metal bumps being electrically connected to the first electrode structure via TSV metal pillars; or forming a plurality of spaced metal bumps on the second surface of the second substrate, the metal bumps being electrically connected to the second electrode structure via TSV metal pillars. The capacitor structure of this invention can achieve a higher capacitance value within a limited chip area. Therefore, this invention effectively overcomes various shortcomings of the prior art and has high industrial applicability.

[0146] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a capacitor structure, characterized in that, Includes the following steps: A first capacitor structure is formed, the first capacitor structure including a first substrate, a first trench capacitor, a first interlayer dielectric layer and a first electrode structure. The first substrate includes a first surface and a second surface disposed opposite to each other. The first trench capacitor is located on the first surface of the first substrate and extends into the first substrate. The first interlayer dielectric layer is located on the first surface of the first substrate and covers the first trench capacitor. The first electrode structure is located in the first interlayer dielectric layer and includes a first lower electrode bonding pad and a first upper electrode bonding pad exposed on the surface of the first interlayer dielectric layer. The first lower electrode bonding pad is electrically connected to the lower electrode layer of the first trench capacitor, and the first upper electrode bonding pad is electrically connected to the upper electrode layer of the first trench capacitor. A second capacitor structure is formed, the second capacitor structure including a second substrate, a second trench capacitor, a second interlayer dielectric layer and a second electrode structure. The second substrate includes a first surface and a second surface disposed opposite to each other. The second trench capacitor is located on the first surface of the second substrate and extends into the second substrate. The second interlayer dielectric layer is located on the first surface of the second substrate and covers the second trench capacitor. The second electrode structure is located in the second interlayer dielectric layer and includes a second lower electrode bonding pad and a second upper electrode bonding pad exposed on the surface of the second interlayer dielectric layer. The second lower electrode bonding pad is electrically connected to the lower electrode layer of the second trench capacitor, and the second upper electrode bonding pad is electrically connected to the upper electrode layer of the second trench capacitor. The first capacitor structure and the second capacitor structure are bonded to make the first trench capacitor and the second trench capacitor connected in parallel, wherein the first lower electrode bonding pad and the second lower electrode bonding pad are aligned and connected to each other, and the first upper electrode bonding pad and the second upper electrode bonding pad are aligned and connected to each other. A plurality of spaced metal bumps are formed on the second surface of the first substrate, and the metal bumps are electrically connected to the first electrode structure through TSV metal pillars; or a plurality of spaced metal bumps are formed on the second surface of the second substrate, and the metal bumps are electrically connected to the second electrode structure through TSV metal pillars.

2. The method for preparing the capacitor structure according to claim 1, characterized in that, The steps for forming the first capacitor structure include: A first groove is formed on the first surface of the first substrate; A first conductive layer structure is formed, the first conductive layer structure is located in the first groove and extends to the substrate surface outside the first groove, the first conductive structure includes a first insulating layer, a first lower electrode layer, a first dielectric layer and a first upper electrode layer stacked in sequence; The first conductive layer structure is graphically represented to obtain the first trench capacitor, wherein the portion of the first lower electrode layer located outside the first groove has a first lower electrode lead that protrudes horizontally beyond the first dielectric layer and the first upper electrode layer. A first interlayer dielectric layer covering the first trench capacitor is formed on the first surface of the first substrate; The first electrode structure is formed in the first interlayer dielectric layer. The first electrode structure further includes a first lower electrode contact portion and a first upper electrode contact portion. One end of the first lower electrode contact portion is connected to the first lower electrode lead-out portion, and the other end is connected to the first lower electrode bonding pad. One end of the first upper electrode contact portion is connected to the first upper electrode layer, and the other end is connected to the first upper electrode bonding pad.

3. The method for preparing the capacitor structure according to claim 2, characterized in that: The aspect ratio of the first groove is in the range of 18 to 22.

4. The method for preparing the capacitor structure according to claim 2, characterized in that: The number of the first grooves is one or more. When the number of the first grooves is multiple, the multiple first grooves have the same width or at least two of the first grooves have different widths.

5. The method for preparing the capacitor structure according to claim 2, characterized in that, The steps for forming the first electrode structure include: A first stepped opening and a second stepped opening are formed in the first interlayer dielectric layer. The bottom of the first stepped opening exposes a portion of the first upper electrode layer, and the bottom of the second stepped opening exposes a portion of the first lower electrode lead-out portion. Metal is deposited in the first stepped opening to form the first upper electrode contact portion and the first upper electrode bonding pad, and metal is deposited in the second stepped opening to form the first lower electrode contact portion and the first lower electrode bonding pad.

6. The method for preparing the capacitor structure according to claim 1, characterized in that, The steps for forming the second capacitor structure include: A second groove is formed in the second substrate; A second conductive layer structure is formed, the second conductive layer structure is located in the second groove and extends to the substrate surface outside the second groove, the second conductive layer structure includes a second insulating layer, a second lower electrode layer, a second dielectric layer and a second upper electrode layer stacked in sequence; The second conductive layer structure is graphically represented to obtain the second trench capacitor, wherein the portion of the second lower electrode layer located outside the second groove has a second lower electrode lead that protrudes horizontally beyond the second dielectric layer and the second upper electrode layer. A second interlayer dielectric layer covering the second trench capacitor is formed on the first surface of the second substrate; A second electrode structure is formed in the second interlayer dielectric layer. The second electrode structure further includes a second lower electrode contact portion and a second upper electrode contact portion. One end of the second lower electrode contact portion is connected to the second lower electrode lead-out portion, and the other end is connected to the second lower electrode bonding pad. One end of the second upper electrode contact portion is connected to the second upper electrode layer, and the other end is connected to the second upper electrode bonding pad.

7. The method for preparing the capacitor structure according to claim 6, characterized in that: The aspect ratio of the second groove is in the range of 18 to 22.

8. The method for preparing the capacitor structure according to claim 6, characterized in that: The number of the second grooves is one or more. When the number of the second grooves is multiple, the multiple second grooves have the same width or at least two second grooves have different widths.

9. The method for preparing the capacitor structure according to claim 6, characterized in that, The steps for forming the second electrode structure include: A third and a fourth stepped opening are formed in the second interlayer dielectric layer. The bottom of the third stepped opening exposes a portion of the second upper electrode layer, and the bottom of the fourth stepped opening exposes a portion of the second lower electrode lead-out. Metal is deposited in the third stepped opening to form the second upper electrode contact portion and the second upper electrode bonding pad, and metal is deposited in the fourth stepped opening to form the second lower electrode contact portion and the second lower electrode bonding pad.

10. A capacitor structure, characterized in that, include: A first capacitor structure includes a first substrate, a first trench capacitor, a first interlayer dielectric layer, and a first electrode structure. The first substrate includes a first surface and a second surface disposed opposite to each other. The first trench capacitor is located on the first surface of the first substrate and extends into the first substrate. The first interlayer dielectric layer is located on the first surface of the first substrate and covers the first trench capacitor. The first electrode structure is located in the first interlayer dielectric layer and includes a first lower electrode bonding pad and a first upper electrode bonding pad exposed on the surface of the first interlayer dielectric layer. The first lower electrode bonding pad is electrically connected to the lower electrode layer of the first trench capacitor, and the first upper electrode bonding pad is electrically connected to the upper electrode layer of the first trench capacitor. The second capacitor structure includes a second substrate, a second trench capacitor, a second interlayer dielectric layer, and a second electrode structure. The second substrate includes a first surface and a second surface disposed opposite to each other. The second trench capacitor is located on the first surface of the second substrate and extends into the second substrate. The second interlayer dielectric layer is located on the first surface of the second substrate and covers the second trench capacitor. The second electrode structure is located in the second interlayer dielectric layer and includes a second lower electrode bonding pad and a second upper electrode bonding pad exposed on the surface of the second interlayer dielectric layer. The second lower electrode bonding pad is electrically connected to the lower electrode layer of the second trench capacitor, and the second upper electrode bonding pad is electrically connected to the upper electrode layer of the second trench capacitor. The second capacitor structure is bonded to the first capacitor structure to connect the first trench capacitor and the second trench capacitor in parallel. The first lower electrode bonding pad and the second lower electrode bonding pad are aligned and connected to each other, and the first upper electrode bonding pad and the second upper electrode bonding pad are aligned and connected to each other. Multiple metal bumps and multiple TVS metal pillars are provided. The multiple metal bumps are spaced apart on the second surface of the first substrate or the second surface of the second substrate. The metal bumps are electrically connected to the first electrode structure or the second electrode structure through the TSV metal pillars.

11. The capacitor structure according to claim 10, characterized in that: The first electrode structure further includes a first lower electrode contact portion and a first upper electrode contact portion. One end of the first lower electrode contact portion is connected to the first lower electrode lead-out portion, and the other end is connected to the first lower electrode bonding pad. One end of the first upper electrode contact portion is connected to the first upper electrode layer, and the other end is connected to the first upper electrode bonding pad.

12. The capacitor structure according to claim 10, characterized in that: The second electrode structure further includes a second lower electrode contact portion and a second upper electrode contact portion. One end of the second lower electrode contact portion is connected to the second lower electrode lead-out portion, and the other end is connected to the second lower electrode bonding pad. One end of the second upper electrode contact portion is connected to the second upper electrode layer, and the other end is connected to the second upper electrode bonding pad.

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