Silicon carbide MOSFET device, manufacturing method and chip

Abstract

The embodiment of the invention provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, a manufacturing method and a chip. The silicon carbide MOSFET device comprises an N + type substrate; an epitaxial layer; the current expansion layer is provided with a first groove and a second groove, the second groove is located at the bottom of the first groove, and the width of the bottom of the second groove is smaller than that of the bottom of the first groove; the P-type base region is arranged in the current expansion layer; the P-type buried layer is arranged in the current expansion layer and located at the bottom of the second groove; the first groove and the second groove are combined to be equivalent to a step-shaped groove, the step-shaped groove is arranged in the current expansion layer, when source electrode metal of the silicon carbide MOSFET device is in contact with silicon carbide through the step-shaped groove, a Schottky diode can be formed, the Schottky diode has the fast recovery characteristic, reverse conduction voltage drop can be reduced, and the voltage drop of the silicon carbide MOSFET device can be reduced. In addition, due to the stepped grooves, the Schottky contact area is larger, and the reverse conduction voltage drop can be reduced to a greater extent.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a silicon carbide MOSFET device, manufacturing method, and chip. Background Technology

[0002] With the development of wide bandgap semiconductor material technology, silicon carbide (SiC) has become an ideal material for next-generation high-performance power devices due to its advantages such as wide bandgap, high breakdown electric field, high thermal conductivity, and excellent chemical stability. Metal-oxide-semiconductor field-effect transistors (MOSFETs) based on SiC materials have been widely used in high-reliability, high-efficiency power electronic systems such as new energy vehicles, smart grids, industrial power supplies, and rail transportation due to their low on-resistance, high switching speed, and good high-temperature operating performance. However, in practical applications, existing SiC MOSFET devices generally suffer from high on-state voltage drop and poor recovery characteristics during reverse conduction. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a silicon carbide MOSFET device, manufacturing method and chip that overcomes or at least partially solves the above problems.

[0004] To address the aforementioned problems, this invention discloses a silicon carbide MOSFET device, the device comprising:

[0005] N+ type substrate;

[0006] An epitaxial layer is disposed on one side of the N+ type substrate;

[0007] A current spreading layer is disposed above the epitaxial layer; the current spreading layer has a first trench and a second trench, the second trench is located at the bottom of the first trench, and the width of the bottom of the second trench is smaller than the width of the bottom of the first trench;

[0008] A P-type base region is disposed within the current spreading layer;

[0009] A P-type buried layer is disposed within the current spreading layer and located at the bottom of the second trench;

[0010] The N+ region and the P+ region are respectively disposed in the P-type base region. The surfaces of the N+ region and the P+ region are flush with the surface of the current spreading layer. The N+ region and the P+ region are laterally adjacent and have the same depth.

[0011] The gate is disposed in the first trench, and a gate oxide layer is provided on the bottom and side, and one side is connected to the side of the N+ region and the P-type base region through the gate oxide layer.

[0012] Optionally, the device further includes:

[0013] An interlayer dielectric layer is disposed on the surface of the gate and on the portion of the N+ region adjacent to the gate;

[0014] Holes are provided on the surface of the N+ region where no interlayer dielectric layer is provided and on the surface of the P+ region.

[0015] Optionally, the device further includes:

[0016] A source metal layer is disposed above the current spreading layer, the first trench, the second trench, the interlayer dielectric layer, and the hole;

[0017] A drain metal layer is disposed on the other side of the N+ type substrate.

[0018] Optionally, the device further includes:

[0019] The P-type pillar region is vertically disposed within the epitaxial layer and the current spreading layer, and the surface of the P-type pillar region is in contact with the source metal layer.

[0020] Accordingly, this invention discloses a method for manufacturing a silicon carbide MOSFET device, used to manufacture the aforementioned silicon carbide MOSFET device, the method comprising:

[0021] Provide N+ type substrate;

[0022] An epitaxial layer is grown on one side of the N+ type substrate;

[0023] A current-spreading layer is epitaxially grown on the epitaxial layer;

[0024] P-type ions are implanted into the current-spreading layer to form a P-type base region;

[0025] A first trench is etched on the current spreading layer, and one side of the first trench is connected to the P-type base region;

[0026] A second trench is formed by etching at the bottom of the first trench;

[0027] P-type ions are injected into the bottom of the second trench to form a P-type buried layer;

[0028] A gate oxide layer is formed on the surface of the current spreading layer and the P-type base region, and inside the first trench and the second trench;

[0029] A portion of the gate oxide layer within the first trench and close to the P-type base region is etched into a gate trench, and a gate dielectric is deposited within the gate trench to form a gate.

[0030] Remove the gate oxide layer from the surface of the P-type base region, the surface of the current spreading layer, the first trench, and the second trench, while retaining the gate oxide layer that surrounds the side and bottom of the gate. Implant P-type ions and N-type ions into the P-type base region to form N+ and P+ regions respectively, wherein the N+ regions are laterally adjacent to the P+ regions and have the same implantation depth.

[0031] Optionally, the method further includes:

[0032] An interlayer dielectric layer is deposited on the surfaces of the current spreading layer, the first trench, the gate, the N+ region, and the P+ region;

[0033] The interlayer dielectric layer is etched to retain the gate surface and a portion of the N+ region surface, and a hole is formed on the P+ region and a portion of the N+ region adjacent to the P+ region.

[0034] Optionally, the method further includes:

[0035] A source metal layer is formed above the current spreading layer, the first trench, the second trench, the interlayer dielectric layer, the N+ region, and the P+ region;

[0036] On the other side of the N+ type substrate, a drain metal layer is formed.

[0037] Optionally, before removing the gate oxide layer on the surface of the P-type base region, the surface of the current spreading layer, and within the first and second trenches, while retaining the gate oxide layer covering the gate sides and bottom, the method further includes:

[0038] The current spreading layer, epitaxial layer and gate oxide layer on the side away from the P-type base region are etched to form a P-type pillar region trench, and P-type silicon carbide is filled in the P-type pillar region trench to form a P-type pillar region.

[0039] The deposition of an interlayer dielectric layer on the surfaces of the current spreading layer, the first trench, the gate, the N+ region, and the P+ region includes:

[0040] An interlayer dielectric layer is deposited on the surfaces of the P-type pillar region, the current spreading layer, the first trench, the gate, the N+ region, and the P+ region.

[0041] The formation of a source metal layer above the current spreading layer, the first trench, the second trench, the interlayer dielectric layer, the N+ region, and the P+ region includes:

[0042] A source metal layer is formed above the P-type pillar region, the current spreading layer, the first trench, the second trench, the interlayer dielectric layer, the N+ region, and the P+ region.

[0043] Optionally, before forming the gate oxide layer on the surface of the current spreading layer and the P-type base region, and inside the first trench and the second trench, the method further includes:

[0044] A sacrificial oxide layer is formed on the surface of the current spreading layer, the first trench, the second trench, and the P-type base region;

[0045] Remove the sacrificial oxide layer.

[0046] Optionally, etching the first trench on the current spreading layer includes:

[0047] A dielectric layer is deposited on the surface of the current spreading layer and the P-type base region;

[0048] The dielectric layer is photolithographically and etched according to the mask of the first trench to form the first trench window;

[0049] Using the first trench window as a mask, the first trench is etched on the current spreading layer to form the first trench.

[0050] Remove the dielectric layer.

[0051] Accordingly, an embodiment of the present invention discloses a chip including the aforementioned silicon carbide MOSFET device.

[0052] The embodiments of the present invention have the following advantages:

[0053] The silicon carbide MOSFET device of this invention includes an N+ type substrate; an epitaxial layer disposed on one side of the N+ type substrate; a current spreading layer disposed above the epitaxial layer; the current spreading layer having a first trench and a second trench, the second trench being located at the bottom of the first trench, and the width of the bottom of the second trench being smaller than the width of the bottom of the first trench; a P-type base region disposed within the current spreading layer; a P-type buried layer disposed within the current spreading layer and located at the bottom of the second trench; an N+ region and a P+ region respectively disposed within the P-type base region, the surfaces of the N+ region and the P+ region being flush with the surface of the current spreading layer, the N+ region and the P+ region being laterally adjacent and having the same depth; and a gate disposed within the first trench, with gate oxide layers provided at the bottom and sides, and one side being connected to the side of the N+ region and the P-type base region through the gate oxide layers. In this embodiment of the invention, the second trench is located at the bottom of the first trench, and the width of the bottom of the second trench is smaller than the width of the bottom of the first trench. That is, the first trench and the second trench are equivalent to a stepped trench. This stepped trench is located within the current spreading layer, which contains silicon carbide. When the source metal of the silicon carbide MOSFET device contacts the silicon carbide through this stepped trench, a Schottky diode can be formed. The Schottky diode has fast recovery characteristics, which can reduce the reverse conduction voltage drop. Furthermore, the stepped trench makes the Schottky contact area larger, which can further reduce the reverse conduction voltage drop. Attached Figure Description

[0054] Figure 1 This is a schematic diagram of the structure of a silicon carbide MOSFET device according to an embodiment of the present invention;

[0055] Figure 2 This is a schematic diagram of another silicon carbide MOSFET device according to an embodiment of the present invention;

[0056] Figure 3 This is a schematic diagram of the body diode and Schottky diode of a silicon carbide MOSFET device according to an embodiment of the present invention;

[0057] Figure 4 This is a schematic diagram of the JFET region structure of a silicon carbide MOSFET device according to an embodiment of the present invention;

[0058] Figure 5 This is an equivalent circuit diagram of a silicon carbide MOSFET device according to an embodiment of the present invention;

[0059] Figure 6 This is an embodiment of the electric field distribution of a silicon carbide MOSFET device under forward breakdown voltage.

[0060] Figure 7 This is an embodiment of the electric field distribution of a common MOSFET device under forward breakdown voltage.

[0061] Figure 8 This is a flowchart illustrating the steps of a method for manufacturing a silicon carbide MOSFET device according to an embodiment of the present invention.

[0062] Figure 9 This is a schematic diagram of the structure of a silicon carbide MOSFET device manufactured according to an embodiment of the present invention;

[0063] Figure 10 This is a schematic diagram of another silicon carbide MOSFET device fabrication according to an embodiment of the present invention;

[0064] Figure 11 This is a schematic diagram of another silicon carbide MOSFET device fabrication according to an embodiment of the present invention;

[0065] Figure 12 This is a schematic diagram of another silicon carbide MOSFET device fabrication according to an embodiment of the present invention;

[0066] Figure 13 This is a schematic diagram of another silicon carbide MOSFET device fabrication according to an embodiment of the present invention;

[0067] Figure 14 This is a schematic diagram of another silicon carbide MOSFET device fabrication according to an embodiment of the present invention;

[0068] Figure 15 This is a schematic diagram of another silicon carbide MOSFET device fabrication according to an embodiment of the present invention;

[0069] Figure 16 This is a schematic diagram of another silicon carbide MOSFET device fabrication according to an embodiment of the present invention;

[0070] Figure 17 This is a schematic diagram of another silicon carbide MOSFET device according to an embodiment of the present invention.

[0071] Reference numerals: N+ type substrate 10, epitaxial layer 11, current spreading layer 12, first trench 13, second trench 14, P-type base region 15, P-type buried layer 16, N+ region 17, P+ region 18, gate 19, gate oxide layer 20, interlayer dielectric layer 21, via 22, source metal layer 23, drain metal layer 24, P-type pillar region 25, first body diode 26, second body diode 27, Schottky diode 28. Detailed Implementation

[0072] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0073] With the development of wide bandgap semiconductor material technology, silicon carbide (SiC) has become an ideal material for next-generation high-performance power devices due to its advantages such as wide bandgap, high breakdown electric field, high thermal conductivity, and excellent chemical stability. Metal-oxide-semiconductor field-effect transistors (MOSFETs) based on SiC materials have been widely used in high-reliability, high-efficiency power electronic systems such as new energy vehicles, smart grids, industrial power supplies, and rail transportation due to their low on-resistance, high switching speed, and good high-temperature operating performance.

[0074] However, in practical applications, existing SiC MOSFET devices generally suffer from high on-state voltage drop and poor recovery characteristics during reverse conduction. This not only increases the conduction loss of the system but also brings greater thermal management pressure, affecting the further improvement of overall energy efficiency and power density.

[0075] One of the core concepts of this invention is that the second trench is located at the bottom of the first trench, and the width of the bottom of the second trench is smaller than the width of the bottom of the first trench. That is, the first trench and the second trench are equivalent to a stepped trench. This stepped trench is located within the current spreading layer, which contains silicon carbide. When the source metal of the silicon carbide MOSFET device contacts the silicon carbide through this stepped trench, a Schottky diode can be formed. The Schottky diode has fast recovery characteristics, which can reduce the reverse conduction voltage drop. Furthermore, the stepped trench makes the Schottky contact area larger, which can further reduce the reverse conduction voltage drop.

[0076] Reference Figure 1 The diagram illustrates a structural schematic of a silicon carbide MOSFET device according to an embodiment of the present invention, which may specifically include the following structure:

[0077] N+ type substrate 10.

[0078] The N+ type substrate 10 is a substrate with a high concentration of N-type doping in silicon carbide. It can grow epitaxial layers and can also achieve fast electric field cutoff, similar to the field cutoff layer of IGBT (Insulated Gate Bipolar Transistor).

[0079] Epitaxial layer 11 is disposed on one side of N+ type substrate 10.

[0080] The epitaxial layer 11 is N-type doped, with a doping concentration lower than that of the N- epitaxial layer on the N+ substrate. The epitaxial layer 11 can withstand the electric field distribution under high voltage, similar to the N-type drift region of IGBT.

[0081] A current spreading layer 12 is disposed above the epitaxial layer 11; the current spreading layer 12 has a first trench 13 and a second trench 14, the second trench 14 is located at the bottom of the first trench 13, and the width of the bottom of the second trench 14 is smaller than the width of the bottom of the first trench 13.

[0082] The doping concentration of the current spreading layer 12 is greater than that of the epitaxial layer 11, which can reduce the JFET (Junction Field-Effect Transistor) effect. The second trench 14 is located at the bottom of the first trench 13, and the width of the bottom of the second trench 14 is smaller than the width of the bottom of the first trench 13. This means that the first trench 13 and the second trench 14 together form a stepped trench. This stepped trench can be filled with source metal, which contacts the silicon carbide through this stepped trench, forming a Schottky barrier diode.

[0083] A Schottky barrier diode (SBD) is a diode that uses the Schottky barrier formed at the metal-semiconductor contact to achieve rectification. Unlike traditional PN junction diodes, it features a low forward voltage drop and fast switching characteristics. When a forward voltage is applied, an external electric field lowers the Schottky barrier height, allowing electrons to easily overcome the barrier and enter the metal, thus generating current. Because it does not rely on minority carrier diffusion like a PN junction, its forward voltage drop is lower. When a reverse voltage is applied, the barrier widens, preventing electrons from flowing from the metal to the semiconductor.

[0084] The P-type base region 15 is located within the current spreading layer 12.

[0085] The P-type base region 15 is P-type doped and is the core region used to form the channel in a silicon carbide MOSFET device. When the gate voltage is higher than the threshold voltage, an inversion layer will be induced on the surface of the P-type base region. This inversion layer is the conductive channel connecting the source and the drain.

[0086] The P-type buried layer 16 is disposed within the current spreading layer 12 and is located at the bottom of the second trench 14.

[0087] The P-type buried layer 16 is P-type doped. Since the P-type buried layer is located inside the current spreading layer 12, which is located above the epitaxial layer 11, the P-type buried layer 16 can form a PN junction with the epitaxial layer 11. Since the P-type buried layer 16 can adjust the internal electric field distribution of the device under voltage, the main function of the P-type buried layer 16 is to significantly reduce the electric field strength near the corner of the gate trench and increase the reliability of the device.

[0088] N+ region 17 and P+ region 18 are respectively located in P-type base region 15. The surfaces of N+ region 17 and P+ region 16 are flush with the surface of current extension layer 12. N+ region 17 and P+ region 18 are laterally adjacent and have the same depth.

[0089] N+ region 17 is formed by high-concentration N-type implantation and is used to provide electrons during forward conduction. P+ region 18 is formed by high-concentration P-type implantation and is used to form an ohmic contact. An ohmic contact is a non-rectifying contact formed between a metal and a semiconductor, meaning that current can flow bidirectionally, and the voltage drop and resistance are low. When the semiconductor is intrinsic or lightly doped, the carrier concentration is low, and the metal is easy to form a Schottky barrier when in contact with it. However, when a highly doped P+ region is used in contact with the metal, the hole concentration is extremely high, the depletion layer is extremely thin, and the electron tunneling effect is significantly enhanced, which can effectively destroy the Schottky barrier and thus achieve an ohmic contact.

[0090] Gate 19 is disposed within the first trench 13, with gate oxide layers 20 on its bottom and sides, and one side is connected to the side of the N+ region 17 and the P-type base region 15 through the gate oxide layers 20. Gate 19 is used to connect to the gate metal.

[0091] The silicon carbide MOSFET device of this invention includes an N+ type substrate; an epitaxial layer disposed on one side of the N+ type substrate; a current spreading layer disposed above the epitaxial layer; the current spreading layer having a first trench and a second trench, the second trench being located at the bottom of the first trench, and the width of the bottom of the second trench being smaller than the width of the bottom of the first trench; a P-type base region disposed within the current spreading layer; a P-type buried layer disposed within the current spreading layer and located at the bottom of the second trench; an N+ region and a P+ region respectively disposed within the P-type base region, the surfaces of the N+ region and the P+ region being flush with the surface of the current spreading layer, the N+ region and the P+ region being laterally adjacent and having the same depth; and a gate disposed within the first trench, with gate oxide layers provided at the bottom and sides, and one side being connected to the side of the N+ region and the P-type base region through the gate oxide layers. In this embodiment of the invention, the second trench is located at the bottom of the first trench, and the width of the bottom of the second trench is smaller than the width of the bottom of the first trench. That is, the first trench and the second trench are equivalent to a stepped trench. This stepped trench is located within the current spreading layer, which contains silicon carbide. When the source metal of the silicon carbide MOSFET device contacts the silicon carbide through this stepped trench, a Schottky diode can be formed. The Schottky diode has fast recovery characteristics, which can reduce the reverse conduction voltage drop. Furthermore, the stepped trench makes the Schottky contact area larger, which can further reduce the reverse conduction voltage drop.

[0092] Reference Figure 2 The diagram illustrates another silicon carbide MOSFET device according to an embodiment of the present invention, which may specifically include the following structure:

[0093] Interlayer dielectric layer 21 is disposed on the surface of gate 19 and the portion of the surface of N+ region 17 adjacent to gate 19.

[0094] Hole 22 is provided on the surface of N+ region 17 where no interlayer dielectric layer 21 is provided and on the surface of P+ region 18.

[0095] The interlayer dielectric layer 21 serves as an isolation and insulation layer, and the hole 22 is a contact hole used to connect the source metal with the contact areas of the P+ and N+ regions.

[0096] In this embodiment of the invention, the device further includes:

[0097] The source metal layer 23 is disposed above the current spreading layer 12, the first trench 13, the second trench 14, the interlayer dielectric layer 21, and the hole 20.

[0098] Drain metal layer 24 is disposed on the other side of N+ type substrate 10.

[0099] The source metal layer 23 is the front electrode metal connected to the source, and the drain metal layer 24 is the back electrode metal connected to the drain, used to receive electrons.

[0100] In this embodiment of the invention, the device further includes:

[0101] P-type pillar region 25 is vertically disposed within epitaxial layer 11 and current spreading layer 12, and the surface of P-type pillar region 25 is in contact with source metal layer 24.

[0102] P-type pillar region 25 is a strip / pillar-shaped P+ doped structure used to form a superjunction structure. The superjunction structure is a special vertical PN alternating doped structure that breaks through the limiting relationship between Ron·A (on-resistance × area) and breakdown voltage of traditional unipolar devices. In other words, it can significantly reduce on-resistance while maintaining high voltage withstand capability, thereby realizing high-performance power devices.

[0103] Because a P-type pillar region 25 is added in the vertical direction of the device, a lateral electric field modulation effect is generated in the drift region under the blocking voltage operating state. This effect completely depletes the excess charge carriers laterally, and the originally tilted electric field distribution is approximately flattened, thereby increasing the breakdown voltage of the device. Furthermore, because more charge carriers can be depleted laterally, the doping concentration of the device can be greatly increased, which in turn reduces the on-resistance of the device. That is, reducing the on-resistance does not reduce the breakdown voltage of the device, and may even increase it accordingly.

[0104] Reference Figure 3This diagram illustrates the structure of the body diode and Schottky diode of a silicon carbide MOSFET device according to an embodiment of the present invention. A first body diode 26 is formed by a P-type pillar region 25 and an epitaxial layer 11. A second body diode 27 is formed by a P-type base region 15 and a current spreading layer 12. The source metal layer 23 contacts the current spreading layer 12 through a first trench 13 and a second trench 14, forming a Schottky diode 28. In a MOSFET device, the body diode is a parasitic PN junction diode.

[0105] Reference Figure 4 The diagram shows a schematic representation of the JFET region structure of a silicon carbide MOSFET device according to an embodiment of the present invention. Figure 4 for Figure 2 The image below is obtained by mirroring the left side as the axis of symmetry. The JFET region consists of a left P-type buried layer 16, a current spreading layer 12, and a right P-type buried layer 16. The resistance of the JFET region is the JFET resistance, and the magnitude of the JFET resistance is related to the length, doping, and width of the JFET region.

[0106] Reference Figure 5 The diagram illustrates an equivalent circuit diagram of a silicon carbide MOSFET device according to an embodiment of the present invention. When the gate is grounded or has a negative voltage, the drain is connected to a high level, and the source is grounded, i.e., when the device is in a forward blocking state, the P-type pillar region 25 generates a lateral electric field modulation effect on the epitaxial layer 11, which completely depletes the original excess charge carriers laterally, and the originally tilted electric field distribution is approximately flattened, thereby increasing the breakdown voltage of the device. In addition, the P-type buried layer 16 at the bottom of the Schottky diode 28 can modulate the electric field distribution at the gate trench, increasing its reliability. The P-type buried layer 16 is connected to the source metal layer 23 and is not floating. Therefore, during reverse breakdown, the P-type buried layer 16 is equivalent to 0 potential, which can better shield the electric field distribution near the corner of the gate trench. If the P-type buried layer 16 is not connected to the source metal layer 23, i.e., it is floating, the potential at the P-type buried layer 16 is greater than 0, and the ability to shield the electric field at the trench is poor.

[0107] When the gate voltage is greater than the threshold voltage, the drain is connected to a high level, and the source is connected to a low level, that is, when the device is in the forward conduction state, the lateral electric field formed by the P-type pillar region 25 and the epitaxial layer 11 helps to deplete the carriers laterally. Therefore, the doping concentration of the device substrate can be increased during the design, thereby further reducing the on-state voltage drop.

[0108] When the gate is grounded or has a negative voltage, the drain is connected to a low level, and the source is connected to a high level, i.e. when the device is in reverse conduction, a current is generated flowing from the source to the drain. Figure 3The dashed line represents the Schottky contact. Due to the stepped shape of the trench, the Schottky contact area is larger, resulting in a smaller reverse conduction voltage drop. When the source voltage is low but greater than the turn-on voltage of the Schottky diode 28, the Schottky diode 28 enters freewheeling mode, and the current flows from the Schottky contact to the epitaxial layer 11, finally being collected at the drain. At this time, the device is in unipolar conduction mode. As the source forward bias continues to increase, the first body diode 26 and the second body diode 27 turn on. At this time, the current is divided into two parts flowing to the drain: one part is the current generated by the Schottky diode, flowing from the Schottky contact through the epitaxial layer 11 to the drain; the other part is the current from the source through the P-type base region 15 and the epitaxial layer 11 to the drain. At this time, the device is in bipolar conduction mode. The introduction of the Schottky diode 28 avoids the bipolar degradation phenomenon of the device and improves the reverse recovery characteristics of the device.

[0109] Both the first body diode 26 and the second body diode 27 exhibit bipolar conduction in reverse conduction (the conduction current consists of both electron and hole currents). During forward conduction of the body diode, electrons are injected from the N-region to the P-region, and holes are injected from the P-region to the N-region, forming a carrier injection and diffusion mechanism, hence the term bipolar conduction. Because stacking faults exist in silicon carbide epitaxial wafers—a type of extended defect in the SiC lattice, a two-dimensional planar defect that may be caused by stress, impurities, or process damage during growth—electrons and holes meet and recombine in the drift region during bipolar conduction. The energy released by this recombination may activate stacking fault regions. The activated stacking faults may further expand or migrate, leading to a decrease in the device's conductivity and reliability. The Schottky contact formed by the source metal layer 23 and silicon carbide has a current consisting only of electrons when it is conducting, so there are no problems that occur when bipolar conduction. The Schottky contact relies solely on electron conduction, which is unipolar conduction. This avoids the problems of carrier recombination and stacking fault activation, resulting in better stability and efficiency.

[0110] The silicon carbide MOSFET device of this invention improves short-circuit resistance while reducing the on-state voltage drop during reverse conduction, thus optimizing the losses in the prior art to a certain extent.

[0111] Reference Figure 6 and Figure 7The diagram illustrates the electric field distribution at the same location as in the forward breakdown voltage scenario of this invention. The superjunction structure of this embodiment makes the electric field distribution inside the device more uniform (along A-A', the electric field lines are approximately flattened; the area enclosed by the electric field in the figure below represents the breakdown voltage of the device). In conventional planar gate MOSFETs, the electric field distribution in the drift region is uneven, easily forming high field strengths in certain areas, limiting the device's breakdown voltage capability. The superjunction structure, through lateral depletion region expansion, allows for a more uniform electric field distribution in both vertical and parallel directions. This uniform electric field distribution avoids the decrease in breakdown voltage caused by excessively strong local electric fields, thus allowing for further optimization of the doping concentration and thickness of the drift region without sacrificing breakdown voltage performance, reducing on-resistance and decreasing on-state voltage drop.

[0112] Reference Figure 8 The diagram illustrates a step-by-step flowchart of a method for manufacturing a conventional MOSFET device according to an embodiment of the present invention, which may specifically include the following steps:

[0113] Step 101: Provide an N+ type substrate.

[0114] Step 102: Epitaxial layer is grown on one side of the N+ type substrate.

[0115] Step 103: Epitaxially grow a current-spreading layer on the epitaxial layer.

[0116] Step 104: P-type ions are implanted into the current-spreading layer to form a P-type base region.

[0117] Step 105: A first trench is etched on the current spreading layer, and one side of the first trench is connected to the P-type base region.

[0118] Step 106: Etch the bottom of the first trench to form a second trench.

[0119] Step 107: P-type ions are injected into the bottom of the second trench to form a P-type buried layer.

[0120] Step 108: A gate oxide layer is formed on the surface of the current spreading layer and the P-type base region, and inside the first trench and the second trench.

[0121] Step 109: Etch a portion of the gate oxide layer within the first trench and near the P-type base region to form a gate trench, and deposit the gate dielectric within the gate trench to form a gate.

[0122] Step 110: Remove the gate oxide layer from the surface of the P-type base region, the surface of the current spread layer, the first trench, and the second trench, while retaining the gate oxide layer covering the side and bottom of the gate. Implant P-type ions and N-type ions into the P-type base region to form N+ and P+ regions respectively. The N+ and P+ regions are laterally adjacent and have the same implantation depth.

[0123] The silicon carbide MOSFET device of this invention includes an N+ type substrate; an epitaxial layer disposed on one side of the N+ type substrate; a current spreading layer disposed above the epitaxial layer; the current spreading layer having a first trench and a second trench, the second trench being located at the bottom of the first trench, and the width of the bottom of the second trench being smaller than the width of the bottom of the first trench; a P-type base region disposed within the current spreading layer; a P-type buried layer disposed within the current spreading layer and located at the bottom of the second trench; an N+ region and a P+ region respectively disposed within the P-type base region, the surfaces of the N+ region and the P+ region being flush with the surface of the current spreading layer, the N+ region and the P+ region being laterally adjacent and having the same depth; and a gate disposed within the first trench, with gate oxide layers provided at the bottom and sides, and one side being connected to the side of the N+ region and the P-type base region through the gate oxide layers. In this embodiment of the invention, the second trench is located at the bottom of the first trench, and the width of the bottom of the second trench is smaller than the width of the bottom of the first trench. That is, the first trench and the second trench are equivalent to a stepped trench. This stepped trench is located within the current spreading layer, which contains silicon carbide. When the source metal of the silicon carbide MOSFET device contacts the silicon carbide through this stepped trench, a Schottky diode can be formed. The Schottky diode has fast recovery characteristics, which can reduce the reverse conduction voltage drop. Furthermore, the stepped trench makes the Schottky contact area larger, which can further reduce the reverse conduction voltage drop.

[0124] In this embodiment of the invention, the method further includes:

[0125] An interlayer dielectric layer is deposited on the surfaces of the current spreading layer, the first trench, the gate, the N+ region, and the P+ region.

[0126] The interlayer dielectric layer is etched, retaining the gate surface and part of the N+ region surface, and holes are formed on the P+ region and part of the N+ region adjacent to the P+ region.

[0127] In this embodiment of the invention, the method further includes:

[0128] A source metal layer is formed above the current spreading layer, the first trench, the second trench, the interlayer dielectric layer, the N+ region, and the P+ region;

[0129] On the other side of the N+ type substrate, a drain metal layer is formed.

[0130] In this embodiment of the invention, the method further includes:

[0131] Before removing the gate oxide layer on the surface of the P-type base region, the surface of the current spread layer, and within the first and second trenches, while retaining the gate oxide layer covering the gate sides and bottom, the method further includes:

[0132] The current spreading layer, epitaxial layer and gate oxide layer on the side away from the P-type base region are etched to form a P-type pillar region trench. The P-type pillar region trench is filled with P-type silicon carbide to form a P-type pillar region.

[0133] An interlayer dielectric layer is deposited on the surfaces of the current spreading layer, the first trench, the gate, the N+ region, and the P+ region, comprising:

[0134] An interlayer dielectric layer is deposited on the surfaces of the P-type pillar region, the current spreading layer, the first trench, the gate, the N+ region, and the P+ region.

[0135] A source metal layer is formed above the current spreading layer, the first trench, the second trench, the interlayer dielectric layer, the N+ region, and the P+ region, including:

[0136] A source metal layer is formed above the P-type pillar region, the current spreading layer, the first trench, the second trench, the interlayer dielectric layer, the N+ region, and the P+ region.

[0137] Reference Figure 9 An N+ type semiconductor is used as the substrate material to form an N+ type substrate 10; an epitaxial layer 11 and a current spreading layer 12 are sequentially grown on the N+ type substrate 10; a P-type base region 15 is formed in the current spreading layer 12 by ion implantation. Due to the special properties of SiC material, 2 to 5 ion implantations are performed at this location.

[0138] Reference Figure 10 ,exist Figure 9 Based on this, a first trench 13 is etched on the current spreading layer 12, and one side of the first trench 13 is connected to the P-type base region 15.

[0139] Reference Figure 11 ,exist Figure 10 Based on the above, and with the help of a mask, a second trench is formed by secondary etching at the bottom of the first trench using plasma etching technology. Then, a P-type buried layer 16 is implanted using ion implantation. Due to the special properties of SiC material, 1 to 3 ion implantations are performed at this location. The bottom of the P-type buried layer 16 may or may not be in contact with the epitaxial layer 11. The implantation of the P-type buried layer 16 cannot penetrate into the epitaxial layer 11.

[0140] Reference Figure 12 ,exist Figure 11 Based on this, a high-quality gate oxide layer is formed using a dry oxygen thermal oxidation method. Subsequently, the first trench 13 and the second trench 14 are filled with gate oxide dielectric (silicon dioxide) to form the gate oxide layer 20.

[0141] Reference Figure 13 ,exist Figure 12Based on this, and with the help of a mask, the gate oxide layer 20 is etched into trenches using plasma etching technology, and the gate dielectric (such as polysilicon) is deposited in the gate trenches by LPCVD (Low Pressure Chemical Vapor Deposition) to form the gate 19.

[0142] Reference Figure 14 ,exist Figure 13 Based on this, plasma etching technology is used to etch the epitaxial layer 11, the current spreading layer 12 and the gate oxide layer 20 to form P-type pillar trenches. P-type SiC is then filled into the P-type pillar trenches to form P-type pillar regions.

[0143] Excess silicon oxide is then removed by etching; high concentrations of P-type and N-type ions are implanted into the P-type base region 15 through a mask to form P+ region 18 and N+ region 17. Due to the special properties of SiC material, 1 to 3 ion implantations are performed in this area.

[0144] Subsequently, an interlayer dielectric layer 21 is deposited and etched to form a hole 22.

[0145] Reference Figure 15 ,exist Figure 14 Based on this, the contact metal of the source electrode is formed as the source metal layer 23 and the contact metal of the drain electrode is formed as the drain metal layer 24 by deposition or sputtering. The source metal layer 23 in the first trench 13 and the second trench 14 needs to form a Schottky contact with SiC, and the drain metal layer 24 of the drain electrode needs to form an ohmic contact with SiC.

[0146] In this embodiment of the invention, before forming the gate oxide layer on the surface of the current spreading layer and the P-type base region, and inside the first trench and the second trench, the following steps are further included:

[0147] A sacrificial oxide layer is formed on the surface of the current spreading layer, the first trench, the second trench, and the P-type base region;

[0148] Remove the sacrificial oxide layer.

[0149] Reference Figure 16 ,exist Figure 11 Based on this, a high-quality sacrificial oxide layer of several hundred angstroms is generated on the entire surface of the device, namely the current spreading layer, the first trench, the second trench, and the P-type base region, using a dry oxygen thermal oxidation method. Figure 16The black lines indicate that dry oxygen thermal oxidation is an oxidation process that uses dry oxygen to react with silicon at high temperatures (typically 800–1200°C) to produce silicon dioxide. The sacrificial oxide layer is then removed by etching it to eliminate interface damage caused by implantation and etching.

[0150] In an embodiment of the present invention, etching the first trench on the current spreading layer includes:

[0151] A dielectric layer is deposited on the surface of the current spreading layer and the P-type base region;

[0152] The dielectric layer is photolithographically and etched according to the mask of the first trench to form the first trench window;

[0153] Using the first trench window as a mask, the first trench is etched on the current spreading layer to form the first trench.

[0154] Remove the dielectric layer.

[0155] In practical applications, a dielectric layer LPTEOS is first deposited on the surface of the current spreading layer 12 and the P-type base region 15. LPTEOS refers to a silicon dioxide (SiO2) thin film deposited at low temperature (typically 650-800℃) using tetraethoxysilane (TEOS) as a precursor gas through low-pressure chemical vapor deposition (LPCVD). The thickness of the dielectric layer LPTEOS can be... It could also be This invention does not limit the thickness of the LPTEOS dielectric layer, as long as it can be used to form the window for etching trenches. In SiC trench etching, the LPTEOS dielectric layer acts as a hard mask, protecting areas that do not need etching and providing excellent photolithographic pattern definition capabilities. Compared to photoresist, LPTEOS is more resistant to high-energy ion bombardment and is suitable for deep trench etching.

[0156] Then, a layer of photoresist is coated on the surface of the dielectric layer LPTEOS to define the first trench pattern. Exposure is performed, and the first trench pattern is defined on the photoresist through a mask. Then, development is performed to remove the photoresist in the exposed area, exposing the underlying LPTEOS area. The LPTEOS is etched to transfer the pattern defined by the photoresist onto the LPTEOS layer, forming the first trench window.

[0157] The first trench structure is etched on the exposed SiC surface (current spread layer), the LPTEOS layer used as a temporary mask is removed, and the surface state of the current spread layer is restored.

[0158] In this embodiment of the invention, superjunction may be omitted, i.e., there is no P-type column region 25, as shown in the reference. Figure 17The P-type column region 25 can be replaced by the P+ region located within the current extension layer 12.

[0159] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0160] This invention also provides a chip including the aforementioned silicon carbide MOSFET device.

[0161] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0162] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0163] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0164] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0165] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0166] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0167] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0168] The foregoing has provided a detailed description of a silicon carbide MOSFET device, manufacturing method, and chip provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A silicon carbide MOSFET device, characterized in that, The device includes: N+ type substrate; An epitaxial layer is disposed on one side of the N+ type substrate; A current spreading layer is disposed above the epitaxial layer; the current spreading layer has a first trench and a second trench, the second trench is located at the bottom of the first trench, and the width of the bottom of the second trench is smaller than the width of the bottom of the first trench; A P-type base region is disposed within the current spreading layer; A P-type buried layer is disposed within the current spreading layer and located at the bottom of the second trench; The N+ region and the P+ region are respectively disposed in the P-type base region. The surfaces of the N+ region and the P+ region are flush with the surface of the current spreading layer. The N+ region and the P+ region are laterally adjacent and have the same depth. The gate is disposed in the first trench, surrounded by a gate oxide layer, and one side is connected to the side of the N+ region and the P-type base region through the gate oxide layer.

2. The silicon carbide MOSFET device according to claim 1, characterized in that, The device also includes: An interlayer dielectric layer is disposed on the surface of the gate and on the portion of the N+ region adjacent to the gate. Holes are provided on the surface of the N+ region where no interlayer dielectric layer is provided and on the surface of the P+ region.

3. The silicon carbide MOSFET device according to claim 2, characterized in that, The device also includes: A source metal layer is disposed above the current spreading layer, the first trench, the second trench, the interlayer dielectric layer, and the hole; A drain metal layer is disposed on the other side of the N+ type substrate.

4. The silicon carbide MOSFET device according to claim 3, characterized in that, The device also includes: The P-type pillar region is vertically disposed within the epitaxial layer and the current spreading layer, and the surface of the P-type pillar region is in contact with the source metal layer.

5. A method for manufacturing a silicon carbide MOSFET device, characterized in that, The method for manufacturing a silicon carbide MOSFET device as described in any one of claims 1 to 4 comprises: Provide N+ type substrate; An epitaxial layer is grown on one side of the N+ type substrate; A current-spreading layer is epitaxially grown on the epitaxial layer; P-type ions are implanted into the current-spreading layer to form a P-type base region; A first trench is etched on the current spreading layer, and one side of the first trench is connected to the P-type base region; A second trench is formed by etching at the bottom of the first trench; P-type ions are injected into the bottom of the second trench to form a P-type buried layer; A gate oxide layer is formed on the surface of the current spreading layer and the P-type base region, and inside the first trench and the second trench; A portion of the gate oxide layer within the first trench and close to the P-type base region is etched into a gate trench, and a gate dielectric is deposited within the gate trench to form a gate. Remove the gate oxide layer from the surface of the P-type base region, the surface of the current spreading layer, the first trench, and the second trench, while retaining the gate oxide layer that surrounds the side and bottom of the gate. Implant P-type ions and N-type ions into the P-type base region to form N+ and P+ regions respectively, wherein the N+ regions are laterally adjacent to the P+ regions and have the same implantation depth.

6. The method for manufacturing a silicon carbide MOSFET device according to claim 5, characterized in that, The method further includes: An interlayer dielectric layer is deposited on the surfaces of the current spreading layer, the first trench, the gate, the N+ region, and the P+ region; The interlayer dielectric layer is etched to retain the gate surface and a portion of the N+ region surface, and a hole is formed on the P+ region and a portion of the N+ region adjacent to the P+ region.

7. The method for manufacturing a silicon carbide MOSFET device according to claim 6, characterized in that, The method further includes: A source metal layer is formed above the current spreading layer, the first trench, the second trench, the interlayer dielectric layer, the N+ region, and the P+ region; On the other side of the N+ type substrate, a drain metal layer is formed.

8. The method for manufacturing a silicon carbide MOSFET device according to claim 5, characterized in that, Before removing the gate oxide layers on the surface of the P-type base region, the surface of the current spreading layer, within the first trench, and within the second trench, while retaining the gate oxide layers surrounding the gate sides and bottom, the method further includes: The current spreading layer, epitaxial layer and gate oxide layer on the side away from the P-type base region are etched to form a P-type pillar region trench, and P-type silicon carbide is filled in the P-type pillar region trench to form a P-type pillar region. The deposition of an interlayer dielectric layer on the surfaces of the current spreading layer, the first trench, the gate, the N+ region, and the P+ region includes: An interlayer dielectric layer is deposited on the surfaces of the P-type pillar region, the current spreading layer, the first trench, the gate, the N+ region, and the P+ region. The formation of a source metal layer above the current spreading layer, the first trench, the second trench, the interlayer dielectric layer, the N+ region, and the P+ region includes: A source metal layer is formed above the P-type pillar region, the current spreading layer, the first trench, the second trench, the interlayer dielectric layer, the N+ region, and the P+ region.

9. The method for manufacturing a silicon carbide MOSFET device according to claim 5, characterized in that, Before forming the gate oxide layer on the surface of the current spreading layer and the P-type base region, and inside the first trench and the second trench, the method further includes: A sacrificial oxide layer is formed on the surface of the current spreading layer, the first trench, the second trench, and the P-type base region; Remove the sacrificial oxide layer.

10. The method for manufacturing a silicon carbide MOSFET device according to claim 5, characterized in that, The etching of the first trench on the current spreading layer includes: A dielectric layer is deposited on the surface of the current spreading layer and the P-type base region; The dielectric layer is photolithographically and etched according to the mask of the first trench to form the first trench window; Using the first trench window as a mask, the first trench is etched on the current spreading layer to form the first trench. Remove the dielectric layer.

11. A chip, characterized in that, Including the silicon carbide MOSFET device as described in any one of claims 1 to 4 above.

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