Transistor and preparation method thereof, integrated circuit and electronic equipment

Abstract

The embodiment of the invention discloses a transistor and a preparation method thereof, an integrated circuit and electronic equipment, and relates to the technical field of semiconductors. The transistor includes a gate, a channel layer, a first pole, and a second pole. The grid electrode comprises a plurality of first grid conductive layers which are stacked at intervals. The channel layer is located between two adjacent first gate conductive layers, and the channel layer is provided with a first end and a second end which extend out of the first gate conductive layers. The material of the channel layer comprises a two-dimensional semiconductor material. The first electrode and the second electrode are located on the two opposite sides of the grid electrode respectively. The first end of the channel layer is embedded in the first pole and is electrically connected with the first pole. And the second end of the channel layer is embedded into the second electrode and is electrically connected with the second electrode. And in the two adjacent channel layers, the parts between the grid electrode and the first electrode and / or between the grid electrode and the second electrode are separated by a first air gap. Therefore, the parasitic capacitance of the transistor can be reduced, the flatness of the channel layer is improved, and on the basis of reducing the contact resistance, the stability of the first air gap is maintained, and the performance of the transistor is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a transistor and its fabrication method, an integrated circuit, and an electronic device. Background Technology

[0002] With the development of Moore's Law and the continuous evolution of technology nodes, the number of transistors in integrated circuits has been increasing, leading to a continuous miniaturization of transistor size. Based on this, transistors have gradually evolved from two-dimensional (2D) planar structures to FinFET structures, and further to gate-all-around (GAA) structures, nanosheet structures, and nanowire structures.

[0003] A transistor consists of a gate, source, and drain. Parasitic capacitances are generated between these three terminals. As transistor structures have evolved, the impact of parasitic capacitances on transistor performance has gradually increased, severely affecting its performance. Summary of the Invention

[0004] This application provides a transistor, its fabrication method, an integrated circuit, and an electronic device, which are used to improve the internal parasitic effects of transistors and enhance transistor performance.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a transistor is provided, comprising: a gate, a plurality of channel layers, a first electrode, and a second electrode. The gate includes a plurality of first gate conductive layers electrically connected to each other, the plurality of first gate conductive layers being sequentially stacked at intervals. Each of the plurality of channel layers is located between two adjacent first gate conductive layers, and each channel layer has a first end and a second end extending out of the first gate conductive layers. The channel layers are made of a two-dimensional semiconductor material. The first electrode and the second electrode are located on opposite sides of the gate and are spaced apart from the gate. The first end of each channel layer is embedded in the first electrode and electrically connected to the first electrode. The second end of each channel layer is embedded in the second electrode and electrically connected to the second electrode. In adjacent channel layers, portions located between the gate and the first electrode and / or between the gate and the second electrode are separated by a first air gap.

[0007] The transistors provided in some embodiments of this application, by setting a first air gap, can achieve electrical insulation between the gate and the first electrode and / or between the gate and the second electrode using the air in the first air gap. Since the dielectric constant of air is lower than that of low-k dielectric materials, the embodiments of this application can effectively reduce the parasitic capacitance between the gate and the first electrode and / or between the gate and the second electrode, effectively improve the internal parasitic effects of the transistor, and enhance the performance and operating speed of the transistor.

[0008] Meanwhile, the embodiments of this application employ a two-dimensional semiconductor material with a high Young's modulus to form the channel layer, which enables the channel layer to have high rigidity. This prevents deformation of the channel layer at the first air gap location, ensuring the flatness of the channel layer and maintaining the structural stability of the first air gap. This not only avoids affecting the performance of the transistor but also improves the consistency between different transistors in the integrated circuit.

[0009] Furthermore, by embedding the first end of the channel layer into the first electrode and the second end of the channel layer into the second electrode, on the one hand, the contact area between the channel layer and the first and second electrodes can be increased, reducing the contact resistance between the channel layer and the first and second electrodes; on the other hand, the first electrode can be used to fix the relative position between the first ends of different channel layers, preventing relative displacement between the first ends of the channel layers and the first electrode. When the first air gap is located between the gate and the first electrode, the structural stability of the first air gap can be further maintained. Similarly, the second electrode can be used to fix the relative position between the second ends of different channel layers, preventing relative displacement between the second ends of the channel layers and the second electrode. When the first air gap is located between the gate and the second electrode, the structural stability of the first air gap can be further maintained. In this case, the size of the first air gap in the alignment direction of the first and second electrodes can be increased, further reducing the parasitic capacitance between the gate and the first electrode and / or between the gate and the second electrode, further improving the internal parasitic effects of the transistor, and further enhancing the transistor's performance.

[0010] In one possible design approach, the aforementioned plurality of channel layers includes at least one first channel layer and at least one second channel layer. The material of the first channel layer includes an N-type two-dimensional semiconductor material, and the material of the second channel layer includes a P-type two-dimensional semiconductor material. The first electrode includes a first electrode portion and a second electrode portion that are electrically connected, the first electrode portion being electrically connected to the first channel layer, and the second electrode portion being electrically connected to the second channel layer. The second electrode includes a third electrode portion and a fourth electrode portion that are insulated from each other, the third electrode portion being electrically connected to the first channel layer, and the fourth electrode portion being electrically connected to the second channel layer. In this case, the transistor can be a complementary field-effect transistor composed of stacked N-type and P-type transistors, and this transistor can be used to construct an inverter. This is beneficial for improving the integration density of integrated circuits.

[0011] In one possible design approach, a second air gap exists between the third and fourth electrode portions. This reduces the parasitic capacitance between the third and fourth electrode portions, thereby improving transistor performance.

[0012] In one possible design approach, the transistor also includes a support layer located between the third electrode portion and the fourth electrode portion. This provides support for the fourth electrode portion, maintaining the structural stability and good performance of the transistor.

[0013] In one possible design approach, the third and fourth electrode portions are made of different materials. This reduces the contact resistance between the third electrode portion and the first channel layer, and reduces the contact resistance between the fourth electrode portion and the second channel layer, thereby improving transistor performance.

[0014] In one possible design approach, the first electrode portion and the second electrode portion are integrally formed. This simplifies the transistor fabrication process. Alternatively, the first electrode portion and the second electrode portion may be made of different materials. This reduces the contact resistance between the first electrode portion and the first channel layer, and also reduces the contact resistance between the second electrode portion and the second channel layer, thereby improving transistor performance.

[0015] In one possible design approach, the gate further includes a second gate conductive layer connecting multiple first gate conductive layers, the second gate conductive layer being located on one side or opposite sides of the multiple first gate conductive layers. When the second gate conductive layer is located on one side of the multiple first gate conductive layers, the size and area of ​​the transistor can be reduced, and the integration density of the integrated circuit can be improved, while still meeting gate control requirements.

[0016] In one possible design approach, the transistor further includes a first dielectric layer located between adjacent channel layers and the first gate conductive layer. Two first dielectric layers located on opposite sides of the same channel layer are connected at the end closest to the second gate conductive layer. This achieves electrical insulation between adjacent channel layers and the first and second gate conductive layers, while avoiding an increase in parasitic capacitance between the gate and the first electrode and / or between the gate and the second electrode.

[0017] In one possible design approach, the portion of the channel layer facing the first gate conductive layer is semiconductor; the portions of the channel layer embedded in the first electrode and embedded in the second electrode are doped compared to the portion of the channel layer facing the first gate conductive layer. This ensures the channel layer functions correctly while reducing the contact resistance between the channel layer and the first and second electrodes, thereby improving transistor performance.

[0018] In one possible design approach, the transistor further includes a substrate having a first surface. A first electrode, a gate electrode, and a second electrode are both located on the first surface and are spaced apart sequentially along a direction parallel to the first surface. This facilitates the subsequent outgoing of the first electrode, gate electrode, and second electrode, reducing the complexity of internal interconnection within the integrated circuit.

[0019] In one possible design approach, the transistor further includes a second dielectric layer, a portion of which is located between the first electrode and the gate, and between the second electrode and the gate, and contacts the sides of each channel layer and the upper surface of the channel layer furthest from the substrate. This prevents subsequently formed structures from falling into the first air gap, affecting the internal parasitic effects of the transistor, and thus avoiding impacts on transistor performance.

[0020] In one possible design approach, the transistor further includes a substrate having a first surface. A first electrode is located on the first surface, and a gate and a second electrode are sequentially spaced on the first electrode along a direction perpendicular to the first surface. In this case, the transistor can be configured as a vertical transistor. This is beneficial for reducing the transistor area and improving the integration density of the integrated circuit.

[0021] In a second aspect, a method for fabricating a transistor is provided, the method comprising: forming a stacked structure; the stacked structure comprising a plurality of composite layers and a plurality of channel layers, the plurality of composite layers being sequentially stacked at intervals, the channel layers being located between adjacent composite layers, and the channel layers having a first end and a second end extending out of the composite layers; the channel layers being made of a two-dimensional semiconductor material; the composite layers comprising a first sacrificial layer, a second sacrificial layer, and a first gate conductive layer, the first gate conductive layer being located between the first sacrificial layer and the second sacrificial layer; the plurality of first gate conductive layers being electrically connected to each other to form a gate. Forming a first electrode and a second electrode; the first electrode being located on the side of the first sacrificial layer away from the first gate conductive layer, the first end of each channel layer being embedded in the first electrode and electrically connected to the first electrode; the second electrode being located on the side of the second sacrificial layer away from the first gate conductive layer, the second end of each channel layer being embedded in the second electrode and electrically connected to the second electrode. Removing the first sacrificial layer and / or the second sacrificial layer to form a first air gap.

[0022] In a possible design approach in the second aspect, the above-mentioned stacked structure is formed by alternating layers to form composite layers and channel layers.

[0023] In a second possible design approach, the fabrication method for forming the aforementioned stacked structure further includes: forming a first dielectric layer before forming a channel layer on the composite layer and after forming the channel layer on the composite layer. The first dielectric layer is located between the first sacrificial layer and the second sacrificial layer and covers the first gate conductive layer.

[0024] In a possible design approach in the second aspect, the fabrication method further includes forming a second gate conductive layer on one side or opposite sides of a plurality of first gate conductive layers during the formation of the first and second electrodes. The second gate conductive layer connects to the plurality of first gate conductive layers.

[0025] Thirdly, an integrated circuit is provided, comprising: a package structure, and a transistor as described in any embodiment of the first aspect. The transistor is packaged within the package structure.

[0026] Fourthly, an electronic device is provided, comprising: a circuit board, and an integrated circuit as described in any embodiment of the third aspect. The circuit board is electrically connected to the integrated circuit.

[0027] The technical effects of the transistor fabrication method in the second aspect, the integrated circuit in the third aspect, and the electronic device in the fourth aspect can be found in the technical effects of the different design methods in the first aspect, and will not be repeated here. Attached Figure Description

[0028] Figure 1 An architectural diagram of an electronic device provided for an embodiment of this application;

[0029] Figure 2 A partial structural diagram of an electronic device provided for an embodiment of this application;

[0030] Figure 3 A structural diagram of an integrated circuit provided for an embodiment of this application;

[0031] Figure 4 A structural diagram of a GAA transistor provided for an embodiment of this application;

[0032] Figures 5a-5j for Figure 4 The structural diagrams corresponding to each step in the fabrication method of the GAA transistor are shown.

[0033] Figure 6 A structural diagram of a transistor provided for an embodiment of this application;

[0034] Figure 7a for Figure 6 The diagram shows a cross-sectional view of the transistor along the M1-M1 direction.

[0035] Figure 7b for Figure 6 The diagram shows a cross-sectional view of the transistor along the N1-N1 direction.

[0036] Figure 8 Another transistor structure diagram provided for embodiments of this application;

[0037] Figure 9a for Figure 8 The diagram shows a cross-sectional view of the transistor along the M2-M2 direction.

[0038] Figure 9b for Figure 8 The diagram shows a cross-sectional view of the transistor along the N2-N2 direction.

[0039] Figure 10 A structural diagram of another transistor provided for an embodiment of this application;

[0040] Figure 11 A structural diagram of another transistor provided for an embodiment of this application;

[0041] Figure 12a for Figure 11 The diagram shows a cross-sectional view of the transistor along the M3-M3 direction.

[0042] Figure 12b for Figure 11 Another cross-sectional view of the transistor along the M3-M3 direction is shown.

[0043] Figure 13 A structural diagram of another transistor provided for an embodiment of this application;

[0044] Figure 14a for Figure 13 The diagram shows a cross-sectional view of the transistor along the M4-M4 direction.

[0045] Figure 14b for Figure 13 Another cross-sectional view of the transistor along the M4-M4 direction is shown.

[0046] Figure 15 A structural diagram of another transistor provided for an embodiment of this application;

[0047] Figure 16a for Figure 15 The diagram shows a cross-sectional view of the transistor along the M5-M5 direction.

[0048] Figure 16b for Figure 15 The diagram shows a cross-sectional view of the transistor along the N5-N5 direction.

[0049] Figure 17 A flowchart illustrating a method for fabricating a transistor, provided as an embodiment of this application;

[0050] Figures 18-24 Cross-sectional structural diagrams corresponding to each step in a transistor fabrication method provided in an embodiment of this application. Detailed Implementation

[0051] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0052] In the description of this application, unless otherwise stated, "multiple" means two or more. "At least one" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0053] Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. Meanwhile, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0054] In the embodiments of this application, unless otherwise expressly specified and limited, the term "connection" can refer to a direct mechanical connection or an electrical connection, or an indirect mechanical connection or electrical connection via an intermediate medium. The mechanical connection here is not limited to whether it is used for transmitting electrical signals, while the electrical connection is used for transmitting electrical signals.

[0055] In the embodiments of this application, the terms "vertical" and "parallel" respectively indicate approximately vertical and approximately parallel within a certain error range. This error range can be a range where the deviation angle relative to absolute verticality and absolute parallelism is less than or equal to 5°, 8°, or 10°, respectively, and is not specifically limited here.

[0056] This application describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown in this application, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0057] Furthermore, the architecture and scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0058] This application provides an electronic device. This electronic device can be applied to various communication systems or protocols, such as Bluetooth (BT) communication technology, Global Positioning System (GPS) communication technology, Global System for Mobile Communication (GSM) communication technology, Wireless Fidelity (WiFi) communication technology, Wideband Code Division Multiple Access (WCDMA) communication technology, Long Term Evolution (LTE), 5G communication technology, and other future communication technologies.

[0059] The electronic devices in this application embodiment can be mobile phones, tablets, laptops, smart home devices, smart wearable devices (e.g., smartwatches, smart bracelets, smart glasses, smart helmets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, etc. Electronic devices can also be handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, in-vehicle devices, electronic devices in 5G networks, or electronic devices in future evolved public land mobile networks (PLMNs), etc., and this application embodiment is not limited in this regard.

[0060] Figure 1 This is a schematic diagram of the architecture of an electronic device provided in an embodiment of this application. For example... Figure 1 As shown, the electronic device 1000 includes components such as a memory 100, a processor 200, an input device 300, and an output device 400. Those skilled in the art will understand that... Figure 1 The structure of the electronic device shown does not constitute a limitation on the electronic device 1000, which may include, for example... Figure 1 The components shown may have more or fewer components, or may be combined as follows: Figure 1 Some of the components shown, or those that can be used with, for example Figure 1 The component arrangements shown are different.

[0061] The memory 100 is used to store software programs and modules. The memory 100 mainly includes a program storage area and a data storage area. The program storage area can store the operating system, application programs required for at least one function (such as sound playback, image playback, etc.), etc.; the data storage area can store data created based on the use of the electronic device (such as audio data, image data, phonebook, etc.). Furthermore, the memory 100 includes external memory 110 and internal memory 120. Data stored in external memory 110 and internal memory 120 can be transferred between each other. External memory 110 includes, for example, a hard disk, USB flash drive, floppy disk, etc. Internal memory 120 includes, for example, static random access memory (SRAM), dynamic random access memory (DRAM), read-only memory, etc.

[0062] The processor 200 is the control center of the aforementioned electronic device 1000. It connects to various parts of the electronic device 1000 via various interfaces and lines. By running or executing software programs and / or modules stored in the memory 100, and by calling data stored in the memory 100, it performs various functions and processes data of the electronic device 1000, thereby providing overall monitoring of the electronic device 1000. Optionally, the processor 200 may include one or more processing units. For example, the processor 200 may include a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (DSP), and a neural network processor, or it may be other application-specific integrated circuits (ASICs), etc. Figure 1 Taking processor 200 as an example (CPU), the CPU may include an arithmetic logic unit (ALU) 210 and a control unit 220. The ALU 210 retrieves data stored in the internal memory 120 and processes it; the processed result is typically sent back to the internal memory 120. The control unit 220 can control the ALU 210 to process the data, and it can also control the external memory 110 and the internal memory 120 to store or retrieve data. The memory 100 can store data generated by the processor 200.

[0063] Input device 300 is used to receive input digital or character information and generate key signal inputs related to user settings and function control of electronic device 1000. For example, input device 300 may include a touchscreen and other input devices. A touchscreen, also known as a touch panel, can collect touch operations performed by the user on or near the touchscreen (such as operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touchscreen) and drive corresponding connected devices according to a pre-set program. Optionally, the touchscreen may include two parts: a touch detection device and a touch controller. The touch detection device detects the user's touch position and the signal generated by the touch operation, transmitting the signal to the touch controller. The touch controller receives touch information from the touch detection device, converts it into touch point coordinates, sends it to processor 200, and can receive and execute commands from processor 200. Furthermore, touchscreens can be implemented using various types such as resistive, capacitive, infrared, and surface acoustic wave. Other input devices may include, but are not limited to, one or more of physical keyboards, function keys (such as volume control buttons, power switch buttons, etc.), trackballs, mice, and joysticks. The controller 220 in the processor 200 can also control the input device 300 to receive or not receive input signals. Furthermore, the input digital or character information received by the input device 300, as well as key signal inputs related to user settings and function control of the electronic device, can be stored in the internal memory 120.

[0064] Output device 400 is used to output signals corresponding to data input by input device 300 and stored in internal memory 120. For example, output device 400 outputs audio signals or video signals. The controller 220 in the processor 200 can also control output device 400 to output signals or not output signals.

[0065] It should be noted that, Figure 1 The thick arrows in the diagram are used to indicate data transmission, and the direction of the thick arrow indicates the direction of data transmission. For example, a one-way arrow between input device 300 and internal memory 120 indicates that data received by input device 300 is transmitted to internal memory 120. As another example, a two-way arrow between arithmetic unit 210 and internal memory 120 indicates that data stored in internal memory 120 can be transmitted to arithmetic unit 210, and data processed by arithmetic unit 210 can be transmitted to internal memory 120. Figure 1 The thin arrows in the diagram indicate components that the controller 220 can control. For example, the controller 220 can control external memory 110, internal memory 120, arithmetic unit 210, input device 300, and output device 400.

[0066] Optionally, such as Figure 1The electronic device 1000 shown may also include various sensors, such as gyroscope sensors, hygrometer sensors, infrared sensors, magnetometer sensors, etc., which will not be described in detail here. Optionally, the electronic device 1000 may also include a wireless fidelity (WiFi) module, a Bluetooth module, etc., which will not be described in detail here.

[0067] Figure 2 The diagram illustrates a partial structure of the electronic device 1000. For example... Figure 2 As shown, the aforementioned electronic device 1000 may further include a circuit board 500 and an integrated circuit 600, wherein the integrated circuit 600 is disposed on the circuit board 500 and electrically connected to the circuit board 500. The circuit board 500 includes, but is not limited to, a printed circuit board (PCB).

[0068] like Figure 2 As shown, the electronic device 1000 further includes a connector disposed between the circuit board 500 and the integrated circuit 600, the integrated circuit 600 being electrically connected to the circuit board 500 via the connector. The connector may be, for example, a ball grid array (BGA).

[0069] Optionally, other structures, such as a packaging substrate, can be provided between the connector and the circuit board 500. That is, the integrated circuit 600 can be packaged on the packaging substrate and then connected to the circuit board 500 through the packaging substrate.

[0070] The number of the aforementioned integrated circuits 600 can be one or more. When there are multiple integrated circuits 600, they can be arranged in a flat arrangement or stacked.

[0071] The integrated circuit 600 described above can be a wafer or a chip. When the integrated circuit 600 is a chip, the chip can be a bare chip (also called a die or particle) obtained by dicing a wafer, or a packaged chip obtained by packaging a bare chip. The integrated circuit 600 can be applied to logic devices (such as the aforementioned arithmetic unit 210, controller 220, sensor, etc.) or to memory devices (such as the aforementioned external memory 110, internal memory 120, etc.), and this application embodiment does not limit this.

[0072] Figure 3 The structure of an integrated circuit 600 is shown. The integrated circuit 600 may include transistors 610 and a package structure 620, with the transistors 610 packaged inside the package structure 620. The number of transistors 610 can be one or more. Figure 3A transistor 610 is illustrated. The transistor 610 is, for example, a complementary metal-oxide-semiconductor (CMOS) field-effect transistor, and the transistor 610 can be an NMOS transistor (NFET) or a PMOS transistor (PFET).

[0073] It is understood that the structure illustrated in the embodiments of this application does not constitute a specific limitation on the integrated circuit 600. In other embodiments of this application, the integrated circuit 600 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements.

[0074] In some examples, such as Figure 3 As shown, the above-mentioned packaging structure 620 may include a substrate 621 and a packaging shell 622, and the packaging shell 622 is bonded to the substrate 621 by an insulating adhesive.

[0075] For example, substrate 621 has high heat dissipation and electrical conductivity. The material of substrate 621 may include composite materials, and the structure of substrate 621 may be a stacked structure. Optionally, the material of substrate 621 may include copper and molybdenum, and substrate 621 is composed of sequentially stacked copper layers / molybdenum layers / copper layers.

[0076] For example, the transistor 610 described above can be bonded to the substrate 621 and encapsulated within the space formed by the package 622 and the substrate 621. Some electrodes of the transistor 610 (e.g., the source electrode) can be conductive to the substrate 621, and some electrodes of the transistor 610 (e.g., the drain and gate electrodes) can be bonded to pins via conductive leads. These pins are disposed on an insulating layer (e.g., insulating ceramic), which is bonded to the substrate 621 with an insulating adhesive. Furthermore, one end of the pin protrudes from the package structure 620 to connect to other circuits.

[0077] Understandably, as transistor structures evolve—for example, from two-dimensional planar structures to GAA structures—internal parasitic effects become increasingly severe. By incorporating low-k dielectric materials between the gate and source, and between the gate and drain, parasitic capacitances between the gate and source, and between the gate and drain, can be reduced, thereby improving transistor performance. Specifically, Figure 4 The structure of a GAA transistor is illustrated. Figures 5a-5j It indicates Figure 4 The diagram shows the structures corresponding to each step in a fabrication method of a GAA transistor.

[0078] For example, such as Figure 4As shown, the aforementioned GAA transistor includes multiple channel layers 1, a gate 2, a gate dielectric layer 3, sidewalls 4, a source S, and a drain D. The multiple channel layers 1 are stacked sequentially, with the gate 2 spanning across and surrounding each channel layer 1. The gate dielectric layer 3 is located between the gate 2 and the channel layer 1, and surrounds the gate 2. The source S and drain D are located on opposite sides of the channel layer 1 and are in contact with the sidewalls of the channel layer 1. The sidewalls 4 act as spacers, located between the gate dielectric layer 3 and the source S, and between the gate dielectric layer 3 and the drain D. The sidewalls 4 are made of low-k dielectric materials such as silicon dioxide (SiO2) and silicon nitride (SiN). These sidewalls 4 can reduce the parasitic capacitance between the gate 2 and the source S, and between the gate 2 and the drain D, thus improving the internal parasitic effects of the GAA transistor.

[0079] For example, such as Figures 5a-5j As shown, the method for fabricating the above-mentioned GAA transistor includes: S1-S10.

[0080] S1, as Figure 5a As shown, a stacked structure 6a is epitaxially grown on substrate 5. The stacked structure 6a includes an alternately stacked first sacrificial layer 61 and a channel layer 1. The material of the first sacrificial layer 61 is, for example, silicon (Si), and the material of the channel layer 1 is, for example, silicon germanium (SiGe). The channel layer 1 is, for example, a nanosheet channel.

[0081] S2, combined Figure 5a and Figure 5b The stacked structure 6a is etched to form a fin structure 6. Further, the substrate 5 can be etched to form a trench between two adjacent fin structures 6, and then a shallow trench isolation structure (STI) is formed within the trench. The shallow trench isolation structure is used to achieve isolation between two adjacent transistors.

[0082] S3, as Figure 5c As shown, a dummy gate 7 is formed across the fin structure 6, and sidewalls 4 are formed on opposite sides of the dummy gate 7. The sidewalls 4 expose opposite ends of the fin structure 6. The material of the sidewalls 4 is, for example, a low-k dielectric material such as silicon dioxide or silicon nitride.

[0083] S4, combined Figure 5c and Figure 5d Based on the sidewall 4, the fin structure 6 is etched to remove the opposite ends of the fin structure 6 that are not covered by the sidewall 4.

[0084] S5, such as Figure 5e As shown, the first sacrificial layer 61 is removed, forming a void G between two adjacent channel layers 1.

[0085] S6, combined Figure 5e and Figure 5fAn insulating material is deposited, which covers the dummy gate 7 and the sidewalls 4, and fills the voids G. The insulating material is, for example, silicon nitride.

[0086] S7, combined Figure 5f and Figure 5g Part of the insulating material covering the pseudo-gate 7 and sidewalls 4 is removed, while the remaining insulating material within each gap G is retained, exposing two opposing sides of the fin structure 6. The insulating material within each gap G constitutes the second sacrificial layer 62.

[0087] S8, combined Figure 5g and Figure 5h Selective epitaxial growth and doping of silicon and germanium are performed on two opposite sides of the fin structure 6 to form the source S and drain D, and then an interlayer dielectric layer (ILD) 8 is formed covering the source S, drain D, pseudo gate 7 and sidewall 4.

[0088] S9, combined Figure 5h and Figure 5i Remove the dummy gate 7 and the second sacrificial layer 62, and release the channel layer 1. Among these, Figure 5i (b) in the middle is Figure 5i The structure shown in (a) is a cross-sectional view along the AA direction.

[0089] S10, combined Figure 5i and Figure 5h First, the gate dielectric material is filled, followed by the metal material; then, part of the metal material and gate dielectric material of the overlay interlayer dielectric layer 8 are removed to obtain the gate dielectric layer 3 and the gate 2. Figure 5j In (b), the gate dielectric layer 3 surrounds the gate 2, in Figure 5j In (c), the gate dielectric layer 3 surrounds the channel layer 1. The sidewall 4 acts as a spacer, separating the gate dielectric layer 3 from the source S, and also separating the gate dielectric layer 3 from the drain D, to reduce parasitic capacitance. Figure 5j (b) in the middle is Figure 5j The structure shown in (a) is a cross-sectional view along the BB direction. Figure 5j (c) in the middle is Figure 5j The structure shown in (a) is a cross-sectional view along the CC direction.

[0090] Understandably, as integrated circuits develop, transistors become smaller and smaller, and consequently, the size of the spacers also decreases. Consequently, the placement of spacers becomes less effective at mitigating internal parasitic effects in transistors, thus hindering performance improvement. Therefore, addressing these parasitic effects and enhancing transistor performance has become a significant challenge.

[0091] Based on this, some embodiments of this application also provide a transistor in which the gate, source, and drain are separated by an air gap. Since the dielectric constant of air is lower than that of the aforementioned low-k dielectric material, the internal parasitic effects of the transistor can be reduced to a greater extent, thereby improving the transistor's performance. This transistor can be applied to the aforementioned integrated circuit 600, and can also be applied to an electronic device 1000 including the integrated circuit 600.

[0092] The structure of the transistor provided in the embodiments of this application will be schematically described below with reference to the accompanying drawings. Figure 6 , Figure 8 , Figure 10 , Figure 11 , Figure 13 and Figure 15 The structure of one type of transistor is illustrated. Figure 7a It indicates Figure 6 The diagram shows a cross-sectional view of the transistor along the M1-M1 direction. Figure 7b It indicates Figure 6 The transistor shown is a cross-sectional view along the N1-N1 direction. Figure 9a It indicates Figure 8 The diagram shows a cross-sectional view of the transistor along the M2-M2 direction. Figure 9b It indicates Figure 8 The transistor shown is a cross-sectional view along the N2-N2 direction. Figure 12a and Figure 12b They respectively indicated Figure 11 The transistor shown is a cross-sectional view along the M3-M3 direction. Figure 14a and Figure 14b They respectively indicated Figure 13 The diagram shows a cross-sectional view of the transistor along the M4-M4 direction. Figure 16a It indicates Figure 15 The transistor shown is a cross-sectional view along the M5-M5 direction. Figure 16b It indicates Figure 15 The transistor shown is a cross-sectional view along the N5-N5 direction.

[0093] In some examples, such as Figure 6 As shown, the transistor 610 includes a channel layer 1, a gate 2, a first electrode 9, and a second electrode 10. One of the first electrode 9 and the second electrode 10 is the source, and the other is the drain. Further, the transistor 610 also includes a substrate 5. The substrate 5 has a first surface A1, which is, for example, a plane. Optionally, the channel layer 1, the gate 2, the first electrode 9, and the second electrode 10 are all located on the first surface A1.

[0094] like Figure 6 , Figure 7a and Figure 7bAs shown, there are multiple channel layers 1. Specifically, there can be two, three, or even more channel layers 1. The structure of the channel layer 1 includes various types, which can be selected and configured according to actual needs. Optionally, the channel layer 1 is a nanosheet channel. Of course, the channel layer 1 can also be composed of multiple nanowire channels arranged at intervals. The embodiments and accompanying drawings of this application are all described using a nanosheet channel as an example.

[0095] For example, the material of channel layer 1 includes a two-dimensional semiconductor material. The two-dimensional semiconductor material refers to a semiconductor material having a two-dimensional crystal structure, and may have a single-layer or multi-layer structure; each layer constituting the two-dimensional semiconductor material may have an atomic-level thickness. Optionally, the two-dimensional semiconductor material includes one or more of the following: transition metal sulfides, transition metal oxides, transition metal selenides, oxide semiconductors, graphene, two-dimensional perovskite thin films, topological insulators, Dirac half-metals, etc. The aforementioned transition metal sulfides include, but are not limited to, molybdenum disulfide (MoS2), tungsten diselenide (WSe2), and tungsten disulfide (WS2), etc., and the aforementioned oxide semiconductors include, but are not limited to, indium, gallium, and zinc oxides. The materials of the multiple channel layers 1 may be the same or different.

[0096] like Figure 6 , Figure 7a and Figure 7b As shown, the gate 2 includes a plurality of first gate conductive layers 21. Optionally, the material of the first gate conductive layer 21 includes one or more of the following: metal, half-metal, conductive oxide, conductive nitride, conductive carbide, etc.

[0097] Continue reading Figure 6 , Figure 7a and Figure 7b The aforementioned plurality of first gate conductive layers 21 are stacked sequentially at intervals and electrically connected to each other. The stacking orientation of the plurality of first gate conductive layers 21 can include various methods, such as... Figure 7a As shown, the stacking direction of the plurality of first gate conductive layers 21 is perpendicular to the substrate 5, and this stacking direction can be referred to as the first direction Z. For example, as... Figure 10 As shown, the stacking direction of the plurality of first gate conductive layers 21 is parallel to the substrate 5, and this stacking direction can be referred to as the second direction Y.

[0098] The plane containing the channel layer 1 is perpendicular to the stacking direction of the plurality of first gate conductive layers 21. In the plurality of channel layers 1, each channel layer 1 is located between two adjacent first gate conductive layers 21. Specifically, as... Figure 7a and Figure 7b As shown, along the stacking direction of the plurality of first gate conductive layers 21, the channel layer 1 and the first gate conductive layer 21 are alternately arranged, with one first gate conductive layer 21 disposed between every two adjacent channel layers 1. Further, as... Figure 7aand Figure 7b As shown, for example, a channel layer 1 is provided between every two adjacent first gate conductive layers 21; or, as... Figure 10 As shown, for example, two channel layers 1 are provided between each two adjacent first gate conductive layers 21.

[0099] Among them, such as Figure 6 and Figure 7a As shown, along the stacking direction of the plurality of first gate conductive layers 21, the middle portion of the channel layer 1 is positioned directly opposite the first gate conductive layer 21, and the opposite ends of the channel layer 1 extend beyond the first gate conductive layer 21 without overlapping with it. The opposite ends of the channel layer 1 can be referred to as the first end 1a and the second end 1b, respectively. This means that, along the direction from the first end 1a to the second end 1b of the channel layer 1, the size of the channel layer 1 is larger than the size of the first gate conductive layer 21.

[0100] like Figure 6 and Figure 7a As shown, the first electrode 9 and the second electrode 10 are located on opposite sides of the gate 2. The first electrode 9 is electrically connected to the first end 1a of the channel layer 1, and the second electrode 10 is electrically connected to the second end 1b of the channel layer 1. The material of either the first electrode 9 or the second electrode 10 may include one or more of the following: metal, half-metal (such as antimony Sb), conductive oxide, conductive nitride, or conductive carbide. The materials of the first electrode 9 and the second electrode 10 may be the same or different.

[0101] For example, combining Figure 6 and Figure 7a Along the direction from the first end 1a of the channel layer 1 to its second end 1b, the first electrode 9, the gate 2, and the second electrode 10 are arranged sequentially at intervals. The first end 1a of each channel layer 1 is embedded within the first electrode 9, and the first electrode 9 encloses the first end 1a of each channel layer 1 and directly contacts multiple surfaces of the channel layer 1 to form an electrical connection. This increases the contact area between the first end 1a of the channel layer 1 and the first electrode 9, reducing the contact resistance between the channel layer 1 and the first electrode 9. The second end 1b of each channel layer 1 is embedded within the second electrode 10, and the second electrode 10 encloses the second end 1b of each channel layer 1 and directly contacts multiple surfaces of the channel layer 1 to form an electrical connection. This increases the contact area between the second end 1b of the channel layer 1 and the second electrode 10, reducing the contact resistance between the channel layer 1 and the second electrode 10.

[0102] Continue reading Figure 7aIn two adjacent channel layers 1, the portions located between the gate 2 and the first electrode 9 and / or between the gate 2 and the second electrode 10 are separated by a first air gap G1. That is, the first air gap G1 is located between two adjacent channel layers 1; at the same time, the first air gap G1 is also located between the gate 2 and the first electrode 9, or between the gate 2 and the second electrode 10, or simultaneously between the gate 2 and the first electrode 9 and between the gate 2 and the second electrode 10.

[0103] by Figure 7a Taking the structure shown as an example, the first air gap G1 includes a first sidewall G11, a second sidewall G12, a third sidewall G13, and a fourth sidewall G14 connected end to end. The first sidewall G11 is formed by the side of the first gate conductive layer 21 that is directly opposite to the first electrode 9 (or the second electrode 10). The second sidewall G12 is formed by a portion of the surface of one of the two adjacent channel layers 1. The third sidewall G13 is formed by the groove of the side of the first electrode 9 (or the second electrode 10) that is directly opposite to the first gate conductive layer 21. The fourth sidewall G14 is formed by a portion of the surface of the other of the two adjacent channel layers 1.

[0104] The aforementioned first air gap G1 is, for example, filled with air. This means that no spacer is provided between the gate 2 and the first electrode 9, but they are separated by air; and / or, no spacer is provided between the gate 2 and the second electrode 10, but they are separated by air. The Young's modulus of two-dimensional semiconductor materials is much higher than that of silicon. Thus, the channel layer 1 in this embodiment has higher rigidity, and the suspended position of the channel layer 1 is not easily deformed, thereby maintaining better flatness and supporting the realization of the first air gap G1.

[0105] Understandably, the dielectric constant of low-k dielectric materials is typically around 2-3, while the dielectric constant of air is 1, making air's dielectric constant 2-3 times lower than that of low-k dielectric materials. Figure 4 In the structure shown, the sidewall 4, in this embodiment of the application, utilizes air to separate the gate 2 and the first electrode 9, and / or utilizes air to separate the gate 2 and the second electrode 10, which can greatly reduce parasitic capacitance and improve the internal parasitic effect of the transistor 610.

[0106] Therefore, the transistor 610 provided in some embodiments of this application, by providing a first air gap G1 between two adjacent channel layers 1, and between the gate 2 and the first electrode 9 and / or between the gate 2 and the second electrode 10, can achieve electrical insulation between the gate 2 and the first electrode 9 and / or between the gate 2 and the second electrode 10 using the air in the first air gap G1. Since the dielectric constant of air is lower than that of low-k dielectric materials, the embodiments of this application can effectively reduce the parasitic capacitance between the gate 2 and the first electrode 9 and / or between the gate 2 and the second electrode 10, effectively improve the internal parasitic effects of the transistor 610, and enhance the performance and operating speed of the transistor 610.

[0107] Meanwhile, in this embodiment, a two-dimensional semiconductor material with a high Young's modulus is used to form the channel layer 1, which gives the channel layer 1 high rigidity. This prevents deformation of the channel layer 1 at the first air gap G1, ensuring the flatness of the channel layer 1 and maintaining the structural stability of the first air gap G1. This not only avoids affecting the performance of the transistor 610, but also improves the consistency between different transistors 610 in the integrated circuit 600.

[0108] Furthermore, by embedding the first end 1a of the channel layer 1 into the first electrode 9 and the second end 1b of the channel layer 1 into the second electrode 10, on the one hand, the contact area between the channel layer 1 and the first electrode 9 and the second electrode 10 can be increased, and the contact resistance between the channel layer 1 and the first electrode 9 and the second electrode 10 can be reduced; on the other hand, the first electrode 9 can be used to fix the relative position between the first ends 1a of different channel layers 1, avoiding relative displacement between the first ends 1a of the channel layer 1 and the first electrode 9. When the first air gap G1 is located between the gate 2 and the first electrode 9, the structural stability of the first air gap G1 can be further maintained; and the second electrode 10 can be used to fix the relative position between the second ends 1b of different channel layers 1, avoiding relative displacement between the second ends 1b of the channel layer 1 and the second electrode 10. When the first air gap G1 is located between the gate 2 and the second electrode 10, the structural stability of the first air gap G1 can be further maintained. In this case, the size of the first air gap G1 can be increased in the arrangement direction of the first electrode 9 and the second electrode 10, further reducing the parasitic capacitance between the gate 2 and the first electrode 9 and / or between the gate 2 and the second electrode 10, further improving the internal parasitic effect of the transistor 610, and further enhancing the performance of the transistor 610.

[0109] In the transistor 610 described above, the stacking direction of the plurality of first gate conductive layers 21 includes various methods, and correspondingly, the arrangement of the first electrode 9 and the second electrode 10 includes various methods, which will be illustrated below with reference to the accompanying drawings.

[0110] In some embodiments, such as Figure 6 and Figure 7aAs shown, multiple first gate conductive layers 21 are stacked along the first direction Z. In this case, the direction (e.g., the third direction X) from the first end 1a of the channel layer 1 to its second end 1b is parallel to the first surface A1. The first electrode 9, the gate 2, and the second electrode 10 are located, for example, on the first surface A1 of the substrate 5 and are arranged sequentially at intervals along the third direction X.

[0111] At this time, as Figure 7b As shown, transistor 610 can be configured as a vertically stacked GAA transistor.

[0112] By placing the first electrode 9, the gate 2, and the second electrode 10 on the same plane, subsequent lead-out is facilitated, reducing the difficulty of internal interconnection of the integrated circuit 600.

[0113] In some examples, such as Figure 8 As shown, transistor 610 further includes a second dielectric layer 11, the material of which includes an insulating material. A portion of the second dielectric layer 11 covers the first electrode 9, the gate 2, and the second electrode 10, in combination with... Figure 9a and Figure 9b Another portion of the second dielectric layer 11 is located between the first electrode 9 and the gate 2, and between the second electrode 10 and the gate 2, and is in contact with the side surface of each channel layer 1, and with the upper surface of the channel layer 1 furthest from the substrate 5. Here, "side surface" refers, for example, to a portion of the surface connecting the upper and lower surfaces of the channel layer 1, which is parallel to the stacking direction of the plurality of channel layers 1.

[0114] In other words, the second dielectric layer 11 encapsulates the first electrode 9, the gate 2, the second electrode 10, and the channel layer 1, and seals the first air gap G1. This prevents subsequently formed structures from falling into the first air gap G1, affecting the internal parasitic effects of the transistor 610, and thus avoiding impacting the performance of the transistor 610.

[0115] In other embodiments, such as Figure 10 As shown, multiple first gate conductive layers 21 are stacked along the second direction Y. In this case, the direction from the first end 1a of the channel layer 1 to its second end 1b is the first direction Z. The first electrode 9 is located, for example, on the first surface A1 of the substrate 5, and the gate 2 and the second electrode 10 are sequentially and spaced apart on the first electrode 9 along the first direction Z.

[0116] At this point, channel layer 1 forms vertical channels. For example... Figure 10 As shown, transistor 610 can be configured as a vertical transistor. This helps to reduce the area of ​​transistor 610 and increase the integration density of integrated circuit 600.

[0117] The accompanying drawings referenced in the following embodiments are all schematic examples of multiple first gate conductive layers 21 stacked along the first direction Z, but this should not be considered as a limitation on the application scenarios of the following embodiments.

[0118] In some embodiments, such as Figure 6 As shown, the gate 2 further includes a second gate conductive layer 22, which connects to the plurality of first gate conductive layers 21. For example, the second gate conductive layer 22 is in direct contact with the plurality of first gate conductive layers 21, so that the plurality of first gate conductive layers 21 can be electrically connected to each other through the second gate conductive layer 22.

[0119] Optionally, the material of the second gate conductive layer 22 includes one or more of the following: metal, half-metal, conductive oxide, conductive nitride, and conductive carbide. The material of the second gate conductive layer 22 and the material of the first gate conductive layer 21 may be the same or different.

[0120] Here, Figure 7b (a) and (b) in the text respectively illustrate Figure 6 The transistor shown is a cross-sectional view along the N1-N1 direction.

[0121] In some examples, such as Figure 7b As shown in (b), there are two second gate conductive layers 22, which are located between the first electrode 9 and the second electrode 10, and on opposite sides of the plurality of first gate conductive layers 21. Here, "opposite sides" refers to the opposite sides of the first gate conductive layers 21 along their stacking direction. Furthermore, the plurality of channel layers 1 are also located between the two second gate conductive layers 22.

[0122] exist Figure 7b In the cross-sectional view shown in (b), two second gate conductive layers 22 and multiple first gate conductive layers 21 form a closed structure, surrounding each channel layer 1.

[0123] In other examples, such as Figure 7b As shown in (a), there is one second gate conductive layer 22, which is located between the first electrode 9 and the second electrode 10, and on one side of the plurality of first gate conductive layers 21. Here, "one side" refers to one side of the first gate conductive layer 21 along its stacking direction. Furthermore, the plurality of channel layers 1 are also located on one side of the second gate conductive layer 22.

[0124] exist Figure 7b In the cross-sectional view shown in (a), the second gate conductive layer 22 and the plurality of first gate conductive layers 21 form a comb-like structure, forming a semi-enclosure for each channel layer 1.

[0125] Compared to a channel layer formed using silicon (with a thickness greater than 5 nm), the channel layer 1 formed using a two-dimensional semiconductor material has a smaller thickness (for example, about 1 nm). Thus, by setting the first gate conductive layer 21 on opposite sides of the channel layer 1, good gate control requirements can be met.

[0126] This means that the embodiments of this application can reduce the amount of the second gate conductive layer 22, such as... Figure 7b As shown in (a), when the second gate conductive layer 22 is located on one side of the plurality of first gate conductive layers 21, it can realize the mutual electrical connection between the plurality of first gate conductive layers 21, obtain good gate control capability, and reduce the size of transistor 610, reduce the area of ​​transistor 610, and improve the integration of integrated circuit 600.

[0127] In some embodiments, such as Figure 6 As shown, transistor 610 further includes a first dielectric layer 12. Optionally, the material of the first dielectric layer 12 includes one or more of the following insulating materials: hexagonal boron nitride (BN), silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, hafnium zirconium oxide, aluminum scandium nitride, mica, calcium fluoride, strontium titanate, barium titanate, yttrium oxide, titanium oxide, silicon nitride, indium-doped copper sulfide phosphide (CuI nP2S6), tantalum oxide, etc.

[0128] The number of the first dielectric layers 12 is multiple, and each first dielectric layer 12 is located between adjacent channel layers 1 and first gate conductive layers 21 to achieve electrical insulation between adjacent channel layers 1 and first gate conductive layers 21.

[0129] like Figure 7b As shown in (a) and (b), two first dielectric layers 12 located on opposite sides of the same channel layer 1 are connected at one end near the second gate conductive layer 22. This achieves electrical insulation between the channel layer 1 and the second gate conductive layer 22. For example, in Figure 7b In the cross-sectional views shown in (a) and (b), two first dielectric layers 12 located on opposite sides of the same channel layer 1 are connected to form a ring structure surrounding the channel layer 1.

[0130] Furthermore, in Figure 7a In the cross-sectional view shown, along the arrangement direction of the first electrode 9 and the second electrode 10, the size of the channel layer 1 is larger than the size of the first dielectric layer 12. The size of the first dielectric layer 12 is, for example, equal to the size of the first gate conductive layer 21. The two first dielectric layers 12 located on opposite sides of the same first gate conductive layer 21 are not connected and expose the side surface of the first gate conductive layer 21. The first sidewall G11 of the first air gap G1 also includes the side surface of the first dielectric layer 12 that is directly opposite the first electrode 9 (or the second electrode 10).

[0131] The dielectric constant of air is lower than that of the material of the first dielectric layer 12. By adopting the above arrangement, the parasitic capacitance between the gate 2 and the first electrode 9 and / or between the gate 2 and the second electrode 10 can be avoided because the first dielectric layer 12 wraps around the side of the first gate conductive layer 21.

[0132] In some embodiments, each of the plurality of channel layers 1 included in the transistor 610 has a doped region and an undoped region. The undoped region, for example, is directly opposite the first gate conductive layer 21, and the doped region, for example, is located within the first electrode 9 and the second electrode 10. A certain distance exists between the undoped region and the doped region. Of course, the undoped region and the doped region can also be adjacent; that is, the portion of the channel layer 1 outside the undoped region can all be located within the doped region.

[0133] The channel layer 1 has two parts: the undoped portion, which may be undoped; and the doped portion, which may be doped. Doping methods include, but are not limited to, atomic substitution doping and interface doping. Atomic substitution doping refers to directly doping the portion of the channel layer 1 located within the doped region, adjusting the carrier concentration by replacing donor or acceptor atoms in the two-dimensional semiconductor material (e.g., doping niobium (Nb) in MoS2). Interface doping refers to covering the surface of the portion of the channel layer 1 located within the doped region with a doped layer, achieving charge transfer doping through the doped layer. The material of the doped layer is, for example, an oxide, including but not limited to aluminum oxide (AlOx).

[0134] This means that the portion of channel layer 1 facing the first gate conductive layer 21 is semiconductor-like. This ensures that channel layer 1 can function properly. Furthermore, the portions of channel layer 1 embedded in the first electrode 9 and the portions embedded in the second electrode 10 are doped compared to the portion of channel layer 1 facing the first gate conductive layer 21. This reduces the contact resistance between channel layer 1 and the first electrode 9 and the second electrode 10, improving the performance of transistor 610.

[0135] The portion of the channel layer 1 located within the doped region can be N-type doped or P-type doped. Correspondingly, the two-dimensional semiconductor material included in the channel layer 1 can be either an N-type two-dimensional semiconductor material or a P-type two-dimensional semiconductor material.

[0136] Understandably, in the transistor 610 described above, the first electrode 9 or the second electrode 10 can be configured in multiple ways, and the configuration can be selected according to actual needs.

[0137] In some embodiments, the first pole 9 is used to connect to the same signal, and the second pole 10 is used to connect to the same signal. For example, as... Figure 7a and Figure 9aAs shown, the first electrode 9 is a single-piece structure, and the second electrode 10 is a single-piece structure. At this time, transistor 610 constitutes an independent transistor.

[0138] In other embodiments, the first pole 9 is used to connect the same signal, and the second pole 10 is used to connect two different signals. For example, as... Figure 11 , Figure 12a and Figure 12b As shown, the second electrode 10 includes two mutually insulated conductive blocks. Optionally, as... Figure 12b As shown, a portion of the second dielectric layer 11 is located, for example, between the two conductive blocks. In this case, the transistor 610 can be considered to be composed of two transistors sharing a common gate 2 and a first electrode 9.

[0139] In this case, such as Figure 11 As shown, the materials of the multiple channel layers 1 included in transistor 610 can all be P-type two-dimensional semiconductor materials, or they can all be N-type two-dimensional semiconductor materials, or, as shown in the figure, the materials of the multiple channel layers 1 ... included in transistor 610 can all be P-type two-dimensional semiconductor materials, or they can Figure 13 and Figure 15 As shown, part of the channel layer 1 is made of P-type two-dimensional semiconductor material, and the other part of the channel layer 1 is made of N-type two-dimensional semiconductor material.

[0140] Optionally, such as Figure 13 and Figure 15 As shown, the aforementioned plurality of channel layers 1 include at least one first channel layer 1c and at least one second channel layer 1d. The material of each first channel layer 1c includes an N-type two-dimensional semiconductor material (e.g., MoS2), and the material of each second channel layer 1d includes a P-type two-dimensional semiconductor material (e.g., WSe2). For example, the number of first channel layers 1c can be one, two, or even more, and the number of second channel layers 1d can be one, two, or even more. Figure 13 and Figure 15 Both diagrams illustrate two first channel layers 1c and two second channel layers 1d. For example, the two first channel layers 1c are disposed between the substrate 5 and the two second channel layers 1d.

[0141] Furthermore, such as Figure 14a and Figure 14b As shown, the first electrode 9 includes a first electrode portion 91 and a second electrode portion 92 that are electrically connected, wherein the first electrode portion 91 is electrically connected to the first channel layer 1c, and the second electrode portion 92 is electrically connected to the second channel layer 1d. The second electrode 10 includes a third electrode portion 101 and a fourth electrode portion 102 that are insulated from each other, wherein the third electrode portion 101 is electrically connected to the first channel layer 1c, and the fourth electrode portion 102 is electrically connected to the second channel layer 1d.

[0142] Continue reading Figure 14a and Figure 14bThe first electrode portion 91, the third electrode portion 101, and the first channel layer 1c can be part of an N-type transistor; the second electrode portion 92, the fourth electrode portion 102, and the second channel layer 1d can be part of a P-type transistor. Furthermore, the P-type transistor is superimposed on the side of the N-type transistor away from the substrate 5. In this case, the transistor 610 can be called a complementary field-effect transistor (CFET).

[0143] For example, the transistor 610 described above can be used to construct an inverter (or a NOT gate). For instance, gate 2 can serve as a control terminal, receiving a control signal Vin; the third electrode 101 can serve as a first input terminal, receiving a first voltage signal Vss or GND; the fourth electrode 102 can serve as a second input terminal, receiving a second voltage signal Vdd; the first electrode 91 and the second electrode 92 can both serve as output terminals, outputting the signals received by both (the first voltage signal or the second voltage signal) as an output signal Vout.

[0144] By adopting the above configuration, two types of transistors can be stacked and integrated together as a CFET. This simplifies the structure of the inverter built by the CFET, reduces the area of ​​the inverter built by the CFET, and thus improves the integration density of the integrated circuit 600.

[0145] In the aforementioned first electrode 9, there are various ways to arrange the first electrode portion 91 and the second electrode portion 92, which can be selected according to actual needs.

[0146] In some examples, such as Figure 14a and Figure 16a As shown, the first electrode portion 91 and the second electrode portion 92 are integrally formed. That is, the first electrode portion 91 and the second electrode portion 92 are continuous and unbroken. The first electrode portion 91 and the second electrode portion 92 are made of the same material and are formed in the same patterning process. This simplifies the fabrication process of the transistor 610.

[0147] In other examples, such as Figure 14b As shown, the first electrode portion 91 and the second electrode portion 92 are made of different materials. The first electrode portion 91 and the second electrode portion 92 are formed using different patterning processes, and they can be in direct contact or electrically connected through other conductive materials.

[0148] The contact resistance between different two-dimensional semiconductor materials and different conductive materials varies. By using different materials to form the first electrode portion 91 and the second electrode portion 92, the material of the first electrode portion 91 can be adapted to the material of the first channel layer 1c, and the material of the second electrode portion 92 can be adapted to the material of the second channel layer 1d. This results in a lower contact resistance between the first electrode portion 91 and the first channel layer 1c, and a lower contact resistance between the second electrode portion 92 and the second channel layer 1d, which can effectively improve the performance of the transistor 610.

[0149] In the second electrode 10 described above, there are various insulation methods between the third electrode section 101 and the fourth electrode section 102, which can be selected and set according to actual needs.

[0150] In some examples, the space between the third electrode portion 101 and the fourth electrode portion 102 is filled with insulating material, thereby achieving insulation between the third electrode portion 101 and the fourth electrode portion 102.

[0151] In other examples, such as Figure 14a , Figure 14b , Figure 16a and Figure 16b As shown, a second air gap G2 exists between the third electrode section 101 and the fourth electrode section 102. The third electrode section 101 and the fourth electrode section 102 are separated by at least the second air gap G2.

[0152] The second air gap G2 mentioned above is, for example, filled with air. That is, the third electrode portion 101 and the fourth electrode portion 102 are insulated from each other at least by air. Since air has a relatively low dielectric constant, the parasitic capacitance between the third electrode portion 101 and the fourth electrode portion 102 can be effectively reduced, the internal parasitic effects of the transistor 610 can be improved, and the performance of the transistor 610 can be enhanced.

[0153] For example, the first air gap G1 and the second air gap G2 are connected.

[0154] In yet another example, combined Figure 16a and Figure 16b A second air gap G2 is provided between the third electrode portion 101 and the fourth electrode portion 102. Furthermore, the transistor 610 also includes a support layer 13 located between the third electrode portion 101 and the fourth electrode portion 102.

[0155] The arrangement and position of the support layer 13 between the third electrode portion 101 and the fourth electrode portion 102 can be selected according to actual needs, and this application embodiment does not limit this. For example, Figure 16b As shown, there are two support layers 13, and the second air gap G2 is located between the two support layers 13, so that the two support layers 13 are spaced apart.

[0156] The support layer 13 is used to support the third electrode portion 101 and the fourth electrode portion 102, and fixes the relative position between the third electrode portion 101 and the fourth electrode portion 102 to avoid relative displacement between the third electrode portion 101 and the fourth electrode portion 102, thereby maintaining the structural stability of the second air gap G2 and maintaining the structural stability and good performance of the transistor 610.

[0157] For example, the support layer 13 is made of an insulating material to prevent short circuits between the third electrode portion 101 and the fourth electrode portion 102. Optionally, the material of the support layer 13 is the same as the material of the second dielectric layer 11. For example, the support layer 13 is connected to the second dielectric layer 11. Further, as... Figure 16b As shown, the support layer 13 and the second dielectric layer 11 can be an integral structure.

[0158] The materials of the third electrode portion 101 and the fourth electrode portion 102 described above can be the same or different. Optionally, in Figure 14b In the structure shown, the third electrode portion 101 and the fourth electrode portion 102 are made of different materials. This allows the material of the third electrode portion 101 to be adapted to the material of the first channel layer 1c, and the material of the fourth electrode portion 102 to be adapted to the material of the second channel layer 1d. Consequently, the third electrode portion 101 and the first channel layer 1c have lower contact resistance, and the fourth electrode portion 102 and the second channel layer 1d have lower contact resistance, thus effectively improving the performance of the transistor 610.

[0159] Some embodiments of this application also provide a method for fabricating a transistor, such as for fabricating the transistor 610 described in any of the above embodiments. Figure 17 A flowchart illustrating a method for fabricating a transistor is shown; Figure 18 , Figure 19a , Figure 20a , Figure 21a , Figure 22a , Figure 23a and Figure 24 The diagram illustrates a cross-sectional structure corresponding to each step in a transistor fabrication method. Figure 19b , Figure 20b , Figure 21b , Figure 22b and Figure 23b Each step in a transistor fabrication method is illustrated with an alternative cross-sectional structure. It should be understood that... Figure 17 The steps shown are not exclusive; more steps can be taken at other times. Figure 17Other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps may be performed simultaneously, or they may be performed in a sequence different from the steps described. Figure 17 The execution is performed in the order shown.

[0160] The fabrication method of the memory array is illustrated below with reference to the accompanying drawings. Figure 17 As shown, the preparation method includes: S100-S300.

[0161] S100, combined with Figure 22a and Figure 22b This forms a stacked structure (S). The stacked structure S includes multiple composite layers 14 and multiple channel layers 1, which are sequentially stacked at intervals. Each channel layer 1 is located between adjacent composite layers 14 and has a first end 1a and a second end 1b extending out of each composite layer 14. The channel layer 1 is made of a two-dimensional semiconductor material. Each composite layer 14 includes a first sacrificial layer 141, a second sacrificial layer 142, and a first gate conductive layer 21, which is located between the first sacrificial layer 141 and the second sacrificial layer 142. The multiple first gate conductive layers 21 are electrically connected to each other, forming a gate 2.

[0162] For example, such as Figure 18 As shown, before forming the stacked structure S, the above-mentioned fabrication method further includes providing a substrate 5. The substrate 5 has a first surface A1. At this time, the stacked structure S is formed on the first surface A1 of the substrate 5. The accompanying drawings of the fabrication method provided in this application embodiment illustrate the stacking of multiple composite layers 14 along a first direction Z perpendicular to the first surface A1, but this should not be considered a limitation on the stacking direction of the multiple composite layers 14.

[0163] For example, in the above S100, forming a stacked structure S includes: alternately stacking a composite layer 14 and a channel layer 1. Specifically, as Figure 19a and Figure 19b As shown, in this embodiment of the application, a composite layer 14 can first be formed on the first surface A1 of the substrate 5, and then, as... Figure 20a and Figure 20b As shown, a two-dimensional semiconductor material is grown on the composite layer 14 using a growth process to form a channel layer 1, or the channel layer 1 grown at other locations is transferred onto the composite layer 14; subsequently, as... Figure 21a , Figure 21b , Figure 22a and Figure 22b As shown, this process is repeated to alternately form composite layer 14 and channel layer 1 to obtain stacked structure S.

[0164] For example, the process of forming the composite layer 14 includes: selectively growing a first sacrificial layer 141, a second sacrificial layer 142 and a first gate conductive layer 21 on a first surface A1 of the substrate 5; or, growing a sacrificial film on the first surface A1 of the substrate 5, then etching the sacrificial film to obtain a first sacrificial layer 141 and a second sacrificial layer 142 spaced apart, and then forming a first gate conductive layer 21 between the first sacrificial layer 141 and the second sacrificial layer 142.

[0165] Understandable, Figures 5a-5j The fabrication of a GAA transistor requires complex processes, including the formation and etching of the stacked structure 6a, the formation and removal of the dummy gate 7, the release of the channel layer 1, and the filling of the gate 2. During the etching process of the stacked structure 6a, the roughness of the channel layer 1 can be easily affected; moreover, the release of the channel layer 1 can lead to stress release issues, causing deformation of the channel layer 1 and affecting its flatness.

[0166] In this embodiment, the stacked structure S can be formed by growing or transferring layers one by one. In the subsequent fabrication process, there is no need to etch the stacked structure S, nor is it necessary to go through complex processes such as the formation and removal of the dummy gate, the release of the channel layer, and the filling of the gate. This not only greatly simplifies the fabrication process of the transistor 610, but also avoids affecting the roughness and flatness of the channel layer 1, thereby improving the performance of the fabricated transistor 610.

[0167] Continue reading Figure 20a and Figure 20b The direction from the first end 1a of the channel layer 1 to its second end 1b is, for example, a third direction X, which is perpendicular to the second direction Y, and the second direction Y is parallel to the first surface A1 of the substrate 5.

[0168] Along the second direction Y, the dimensions of the first sacrificial layer 141, the second sacrificial layer 142, and the first gate conductive layer 21 are, for example, equal, while the dimension of the channel layer 1 is, for example, smaller than the dimension of the first gate conductive layer 21.

[0169] Along the third direction X, the size of the channel layer 1 is larger than the size of the composite layer 14, and the first end 1a and the second end 1b of the channel layer 1 are suspended relative to the composite layer 14. Because the two-dimensional semiconductor material has a high Young's modulus, the channel layer 1 has high rigidity. Therefore, even when the first end 1a and the second end 1b of the channel layer 1 are suspended, they are not easily deformed, resulting in high flatness of the channel layer 1 and ensuring that the fabricated transistor 610 has good performance.

[0170] Optionally, along the third direction X, the dimensions of the first sacrificial layer 141 and the second sacrificial layer 142 may be equal or unequal. Specifically, this can be determined based on the dimensions of the subsequently formed first air gap G1.

[0171] In some examples, combined Figure 20a and Figure 21a In the process of forming the above-mentioned stacked structure S, the above-mentioned preparation method further includes: forming a first dielectric layer 12 before forming the channel layer 1 on the composite layer 14 and after forming the channel layer 1 on the composite layer 14. The first dielectric layer 12 is located between the first sacrificial layer 141 and the second sacrificial layer 142, and covers the first gate conductive layer 21.

[0172] For example, such as Figure 21a and Figure 21b As shown, the orthographic projection of the first dielectric layer 12 onto the first surface A1 coincides with the orthographic projection of the first gate conductive layer 21 onto the first surface A1. Correspondingly, along the second direction Y, the size of the channel layer 1 is smaller than the size of the first dielectric layer 12. Thus, in Figure 21b In the cross-sectional view shown, the first dielectric layer 12 formed after the channel layer 1 is connected to the first dielectric layer 12 formed before the channel layer 1, for example, surrounding the channel layer 1. Figure 21a In the cross-sectional view shown, along the third direction X, the size of the channel layer 1 is larger than the size of the first dielectric layer 12, so that the first dielectric layer 12 formed after the channel layer 1 and the first dielectric layer 12 formed before the channel layer 1 are separated by the channel layer 1.

[0173] The first dielectric layer 12 described above can achieve electrical insulation between the first gate conductive layer 21 and the channel layer 1.

[0174] S200, such as Figure 23a As shown, a first electrode 9 and a second electrode 10 are formed. The first electrode 9 is located on the side of the first sacrificial layer 141 away from the first gate conductive layer 21, and the first end 1a of each channel layer 1 is embedded in the first electrode 9 and electrically connected to the first electrode 9. The second electrode 10 is located on the side of the second sacrificial layer 142 away from the first gate conductive layer 21, and the second end 1b of each channel layer 1 is embedded in the second electrode 10 and electrically connected to the second electrode 10.

[0175] For example, a growth process can be used to grow a first electrode 9 and a second electrode 10 at the locations of the first end 1a and the second end 1b of each channel layer 1, respectively.

[0176] The material of the first electrode 9 is grown not only on the side of the first end 1a of the channel layer 1 away from the first gate conductive layer 21, but also between the first ends 1a of two adjacent channel layers 1, contacting the first sacrificial layer 141, so that the first electrode 9 encloses the first end 1a of the channel layer 1. The first sacrificial layer 141 separates each first gate conductive layer 21 and the first electrode 9. This increases the contact area between the channel layer 1 and the first electrode 9, which not only reduces the contact resistance between the channel layer 1 and the first electrode 9, but also improves the connection stability between the channel layer 1 and the first electrode 9.

[0177] The material of the second electrode 10 is grown not only on the side of the second end 1b of the channel layer 1 away from the first gate conductive layer 21, but also between the second ends 1b of two adjacent channel layers 1, contacting the second sacrificial layer 142, so that the second electrode 10 wraps around the second end 1b of the channel layer 1. The second sacrificial layer 142 separates each first gate conductive layer 21 and the second electrode 10. This increases the contact area between the channel layer 1 and the second electrode 10, which not only reduces the contact resistance between the channel layer 1 and the second electrode 10, but also improves the connection stability between the channel layer 1 and the second electrode 10.

[0178] The first electrode 9 and the second electrode 10 described above can be formed in the same fabrication process or separately in different fabrication processes. Furthermore, the first electrode 9 (or the second electrode 10) can be formed in the same fabrication process or separately in different fabrication processes. The specific configuration can be selected based on the type and structure of the transistor 610 being fabricated; this embodiment does not limit this selection.

[0179] In some examples, combined Figure 23a and Figure 23b In the process of forming the first electrode 9 and the second electrode 10, the above-described fabrication method further includes forming a second gate conductive layer 22 on one side or opposite sides of the plurality of first gate conductive layers 21. The second gate conductive layer 22 connects to the plurality of first gate conductive layers 21. At this time, the second gate conductive layer 22 and the plurality of first gate conductive layers 21 together constitute the gate 2. When the second gate conductive layer 22 is formed on one side of the plurality of first gate conductive layers 21, the gate 2 has, for example, a comb-like structure.

[0180] In this case, the first electrode 9, the second electrode 10, and the second gate conductive layer 22 are formed, for example, in the same fabrication process, and all three are made of the same material. The transistor 610 formed is, for example, an N-type transistor, or a P-type transistor, to reduce the contact resistance between the channel layer 1 and the first electrode 9 and the second electrode 10.

[0181] This simplifies the transistor fabrication process and reduces the difficulty of transistor fabrication.

[0182] S300, combined with Figure 23aand Figure 24 Remove the first sacrificial layer 141 and / or the second sacrificial layer 142 to form the first air gap G1.

[0183] For example, only the first sacrificial layer 141 can be removed. In this case, the space used to accommodate the first sacrificial layer 141 constitutes the first air gap G1, which is located between two adjacent channel layers 1 and between the first electrode 9 and the gate 2. Alternatively, only the second sacrificial layer 142 can be removed. In this case, the space used to accommodate the second sacrificial layer 142 constitutes the first air gap G1, which is located between two adjacent channel layers 1 and between the second electrode 10 and the gate 2. Alternatively, both the first sacrificial layer 141 and the second sacrificial layer 142 can be removed simultaneously. In this case, the spaces used to accommodate both the first sacrificial layer 141 and the second sacrificial layer 142 constitute the first air gap G1, which is located between two adjacent channel layers 1 and between the first electrode 9 and the gate 2, as well as between the second electrode 10 and the gate 2.

[0184] The first air gap G1 mentioned above is, for example, filled with air. Since the dielectric constant of air is lower than that of low-k dielectric materials, the parasitic capacitance between the gate 2 and the first electrode 9 and / or between the gate 2 and the second electrode 10 can be effectively reduced, thereby effectively improving the internal parasitic effects of the transistor 610 and enhancing the performance and operating speed of the transistor 610.

[0185] Furthermore, the first electrode 9 can fix the relative positions between the first ends 1a of different channel layers 1, preventing relative displacement between the first ends 1a of channel layer 1 and the first electrode 9. When the first air gap G1 is located between the gate 2 and the first electrode 9, this helps maintain the structural stability of the first air gap G1. Similarly, the second electrode 10 can fix the relative positions between the second ends 1b of different channel layers 1, preventing relative displacement between the second ends 1b of channel layer 1 and the second electrode 10. When the first air gap G1 is located between the gate 2 and the second electrode 10, this helps maintain the structural stability of the first air gap G1. In this case, the size of the first air gap G1 in the third direction X can be increased, further reducing the parasitic capacitance between the gate 2 and the first electrode 9 and / or between the gate 2 and the second electrode 10, further improving the internal parasitic effect of the transistor 610, and further enhancing the performance of the transistor 610.

[0186] In addition, during the fabrication of the transistor, there is no need to etch the channel layer 1, nor is it necessary to go through complex processes such as releasing the channel layer 1 and replacing the gate. This can avoid affecting the roughness and flatness of the channel layer 1, which is beneficial to improving the performance of the fabricated transistor 610 and improving the consistency between different transistors 610 in the integrated circuit 600.

[0187] In some embodiments, after removing the first sacrificial layer 141 and / or the second sacrificial layer 142, a dielectric material may be deposited on the gate 2, the first electrode 9, and the second electrode 10 to form a second dielectric layer. The structure of the second dielectric layer 11 is as follows: Figure 8 , Figure 9a and Figure 9b As shown.

[0188] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A transistor, characterized in that, The transistor includes: The gate includes a plurality of first gate conductive layers that are electrically connected to each other; the plurality of first gate conductive layers are stacked in sequence at intervals. Multiple channel layers are provided, each channel layer being located between two adjacent first gate conductive layers, each channel layer having a first end and a second end extending out of the first gate conductive layer; the material of the channel layer includes a two-dimensional semiconductor material. The first electrode and the second electrode are located on opposite sides of the gate and are spaced apart from the gate. The first end of each channel layer is embedded in the first electrode and electrically connected to the first electrode. The second end of each channel layer is embedded in the second electrode and electrically connected to the second electrode. In two adjacent channel layers, the portions located between the gate and the first electrode and / or between the gate and the second electrode are separated by a first air gap.

2. The transistor according to claim 1, characterized in that, The plurality of channel layers include at least one first channel layer and at least one second channel layer, wherein the material of the first channel layer includes an N-type two-dimensional semiconductor material, and the material of the second channel layer includes a P-type two-dimensional semiconductor material; The first electrode includes a first electrode portion and a second electrode portion that are electrically connected, the first electrode portion being electrically connected to the first channel layer, and the second electrode portion being electrically connected to the second channel layer; The second electrode includes a third electrode portion and a fourth electrode portion that are insulated from each other. The third electrode portion is electrically connected to the first channel layer, and the fourth electrode portion is electrically connected to the second channel layer.

3. The transistor according to claim 2, characterized in that, A second air gap exists between the third electrode portion and the fourth electrode portion.

4. The transistor according to claim 3, characterized in that, The transistor further includes a support layer located between the third electrode portion and the fourth electrode portion.

5. The transistor according to any one of claims 2-4, characterized in that, The third electrode section and the fourth electrode section are made of different materials.

6. The transistor according to any one of claims 2-5, characterized in that, The first electrode portion and the second electrode portion are integrally formed; or, The first electrode portion and the second electrode portion are made of different materials.

7. The transistor according to any one of claims 1-6, characterized in that, The gate also includes a second gate conductive layer that connects multiple first gate conductive layers, the second gate conductive layer being located on one side or opposite sides of the multiple first gate conductive layers.

8. The transistor according to claim 7, characterized in that, The transistor further includes a first dielectric layer located between adjacent channel layers and the first gate conductive layer; The two first dielectric layers located on opposite sides of the same channel layer are connected at one end near the second gate conductive layer.

9. The transistor according to any one of claims 1-8, characterized in that, The portion of the channel layer that is directly opposite the first gate conductive layer has semiconductor properties. The portions of the channel layer embedded in the first electrode and the portions embedded in the second electrode are doped compared to the portion of the channel layer directly opposite the first gate conductive layer.

10. The transistor according to any one of claims 1-9, characterized in that, The transistor further includes a substrate having a first surface; The first electrode, the gate electrode, and the second electrode are all located on the first surface and are arranged at intervals in a direction parallel to the first surface.

11. The transistor according to claim 10, characterized in that, The transistor further includes a second dielectric layer, a portion of which is located between the first electrode and the gate, and between the second electrode and the gate, and is in contact with the sidewalls of each of the channel layers and with the upper surface of the channel layer furthest from the substrate.

12. The transistor according to any one of claims 1-9, characterized in that, The transistor further includes a substrate having a first surface; The first electrode is located on the first surface, and the gate and the second electrode are sequentially spaced on the first electrode along a direction perpendicular to the first surface.

13. A method for fabricating a transistor, characterized in that, The preparation method includes: A stacked structure is formed; the stacked structure includes multiple composite layers and multiple channel layers, the multiple composite layers are stacked sequentially at intervals, the channel layers are located between two adjacent composite layers, and the channel layers have a first end and a second end extending out of the composite layers; the material of the channel layers includes a two-dimensional semiconductor material; the composite layers include a first sacrificial layer, a second sacrificial layer and a first gate conductive layer, the first gate conductive layer is located between the first sacrificial layer and the second sacrificial layer; the multiple first gate conductive layers are electrically connected to each other to form a gate; A first electrode and a second electrode are formed; the first electrode is located on the side of the first sacrificial layer away from the first gate conductive layer, and the first end of each of the channel layers is embedded in the first electrode and electrically connected to the first electrode; the second electrode is located on the side of the second sacrificial layer away from the first gate conductive layer, and the second end of each of the channel layers is embedded in the second electrode and electrically connected to the second electrode. Remove the first sacrificial layer and / or the second sacrificial layer to form a first air gap.

14. The preparation method according to claim 13, characterized in that, The formation of the stacked structure includes: The composite layer and the channel layer are formed by alternating layers.

15. The preparation method according to claim 14, characterized in that, In the process of forming the stacked structure, the preparation method further includes: A first dielectric layer is formed before and after the channel layer is formed on the composite layer; the first dielectric layer is located between the first sacrificial layer and the second sacrificial layer and covers the first gate conductive layer.

16. The preparation method according to any one of claims 13-15, characterized in that, In the process of forming the first electrode and the second electrode, the preparation method further includes: A second gate conductive layer is formed on one side of the plurality of first gate conductive layers; the second gate conductive layer is connected to the plurality of first gate conductive layers.

17. An integrated circuit, characterized in that, The integrated circuit includes: Packaging structure; A transistor, packaged within the package structure; the transistor includes any one of claims 1-12.

18. An electronic device, characterized in that, The electronic device includes: Circuit board; An integrated circuit is electrically connected to the circuit board; the integrated circuit includes the integrated circuit as claimed in claim 17.

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