Structure and manufacturing method for improving gate oxide reliability of silicon carbide MOSFET (Metal Oxide Semiconductor Field Effect Transistor)

Abstract

The invention discloses a structure for improving the gate oxide reliability of a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a manufacturing method. The structure comprises an N-drift region, and an interconnection metal layer is deposited on the top surface of the N-drift region; performing ion implantation in the middle of the top end of the N-drift region to form a P well; an N + source region is formed in the P well in an injection mode, the two sides and the bottom face of the N + source region make contact with the P well, the N + source region comprises a heavily-doped region and a lightly-doped region, and the heavily-doped region is located in the middle close to the P well and makes contact with the interconnection metal layer; and depositing a gate oxide layer and an isolation oxide layer on two sides of the top surfaces of the N-drift region and the P well, wherein the bottom surface of the gate oxide layer is in contact with the top surface of the N-drift region. According to the invention, the step injection structure is introduced into the N + source region, and the N + source region is divided into the heavily doped region and the lightly doped region, so that the problem of overlapping of the N + source region and the grid electrode is fundamentally solved by reducing the contact resistance through the heavily doped region and relieving the electric field concentration through the lightly doped region, and high requirements for photoetching alignment are not required.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a structure and manufacturing method for improving the gate oxide reliability of silicon carbide MOSFETs. Background Technology

[0002] The reliability of the gate oxide in a silicon carbide MOSFET depends on the oxidation temperature, annealing temperature, SiC quality (defect density), surface roughness, and device area. The breakdown electric field strength of the SiC gate oxide is 9-13 MV / cm.

[0003] In planar gate SiC type MOSFETs, since the gate is formed after implantation, a portion of the gate in the final structure overlaps with the highly implanted N+ source region (typically 0.5µm). The gate oxide quality on the heavily doped N+ source region is poor due to surface roughness and other reasons, resulting in a lower-than-expected breakdown electric field strength of the SiC gate oxide.

[0004] Current common methods aim to reduce the overlap between the gate and N+ source regions, making the overlap area less than 0.5µm, in order to improve the breakdown electric field strength and reliability of the gate oxide. However, this method not only places higher demands on photolithography alignment but also fails to fundamentally solve the problem of overlap between the N+ source and gate regions. Therefore, this paper proposes a structure and manufacturing method to improve the gate oxide reliability of silicon carbide MOSFETs, thereby addressing the aforementioned issues. Summary of the Invention

[0005] The purpose of this invention is to provide a structure and manufacturing method for improving the gate oxide reliability of silicon carbide MOSFETs, so as to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a structure for improving the gate oxide reliability of silicon carbide MOSFETs, comprising:

[0007] N-drift region, wherein an interconnect metal layer is deposited on the top surface of the N-drift region;

[0008] A P-well is formed by ion implantation at the top center of the N-drift region, and the P-well is located between the N-drift region and the middle of the interconnect metal layer;

[0009] The N+ source region is formed by implantation in the P-well. The two sides and the bottom of the N+ source region are in contact with the P-well. The N+ source region includes a heavily doped region and a lightly doped region. The heavily doped region is located near the middle of the P-well and is in contact with the interconnect metal layer.

[0010] A gate oxide layer and an isolation oxide layer are deposited on both sides of the top surface of the N-drift region and the P-well. The isolation oxide layer covers the top surface and one side of the gate oxide layer. The bottom surface of the isolation oxide layer is in contact with the top surface of the heavily doped region and the top surface of the lightly doped region. The side of the isolation oxide layer away from the gate oxide layer is in contact with the interconnect metal layer. The bottom surface of the gate oxide layer is in contact with the top surface of the N-drift region.

[0011] Preferably, the implantation depth of the P-well in the N-drift region is 0.5 μm-1.5 μm, and the doping concentration of the P-well on the surface of the N-drift region is 1E16 / cm. 3 -1E17 / cm 3 The doping concentration of the P-well on the surface far from the N-drift region is 1E18 / cm². 3 -1E19 / cm 3 .

[0012] Preferably, channel regions are formed at both ends of the P-well near the gate oxide layer, and one side of the channel region is in contact with the side of the lightly doped region away from the heavily doped region.

[0013] Preferably, a gate polycrystalline material is disposed between the isolation oxide layer and the gate oxide layer. The side of the gate polycrystalline material closest to the isolation oxide layer is oxidized to form a polycrystalline oxide layer. The polycrystalline oxide layer covers the top surface of the gate polycrystalline material and the side closest to the isolation oxide layer. The side of the polycrystalline oxide layer away from the gate polycrystalline material contacts the isolation oxide layer. The polycrystalline oxide layer is used to isolate the gate polycrystalline material and the isolation oxide layer.

[0014] A method for manufacturing a structure to improve the gate oxide reliability of a silicon carbide MOSFET, the method comprising the following steps:

[0015] S1, trivalent element ions are injected into the top surface of the N-drift region at 450℃-500℃ to form a P-well. Gradient doping is used to inject 0.5um-1.5um to form a channel region on both sides of the top surface of the P-well.

[0016] S2, plan the N+ source region at the P well, and define the region near the center of the P well as the heavily doped region and the region far from the center of the P well as the lightly doped region. Then, use pentavalent element ions to implant to a depth of 0.1um-0.5um at 300℃-800℃ to form the heavily doped region and the lightly doped region respectively.

[0017] S3, a gate oxide layer is deposited on the top surface at both ends of the N-drift region and the top surface of the channel region, and then a gate polycrystalline layer is formed on the top surface of the gate oxide layer by chemical vapor deposition;

[0018] S4, an isolation oxide layer is deposited on the top and side surfaces of the gate polycrystalline material and the side surface of the gate oxide layer to form an isolation oxide layer. Then, contact holes are formed on the surface of the isolation oxide layer by photolithography and etching. Finally, an interconnect metal layer is formed by metal deposition.

[0019] Preferably, the formation of the P-well specifically includes the following steps:

[0020] S101, the top surface of the N-drift zone is treated by first using RCA standard cleaning to remove organic and metallic contaminants, and then using hydrofluoric acid rinsing to remove native oxides.

[0021] S102, spin-coat photoresist on the top surface of the cleaned N-drift region, and perform ultraviolet photolithography on the coated area using a mask that conforms to the P-well pattern to form an open injection window;

[0022] S103, after heating the N-drift region to 450℃-550℃, a high-temperature ion implanter is used, with the implantation energy set to 300keV-600keV. Trivalent element ions are implanted into the implantation window in two stages. The implantation concentration in the first stage is controlled at 1E18 / cm³. 3 -1E19 / cm 3 The injection depth was 0.3µm-1.4µm, and the second-stage injection concentration was controlled at 1E16 / cm³. 3 -1E17 / cm 3 The implantation depth is 0.1um-0.2um, and the total implantation depth is 0.5um-1.5um;

[0023] S104 was subjected to rapid thermal annealing to activate trivalent ions, and the annealing was carried out in an argon atmosphere at 1700℃ for 3 to 8 minutes.

[0024] Preferably, the concentration of the trivalent element ion implanted into the P-trap is calculated as follows:

[0025]

[0026] Where C(z,t) represents the total concentration at time t and depth z, and R p,i Q represents the average projected range of the i-th injection. i σ represents the dose of trivalent element ions injected in the i-th injection. i Let represent the standard deviation after diffusion of the i-th injection, D represent the diffusion coefficient, and Dt represent the diffusion width of the trivalent ion within time t.

[0027] Preferably, the formation of the N+ source region specifically includes the following operations:

[0028] S201, firstly, an N+ source region is planned on the top surface of the P-well, and the planned junction depth is 0.1um-0.5um. The N+ source region is divided into a heavily doped region and a lightly doped region, and the lightly doped region is adjacent to the channel region.

[0029] S202 uses photolithography. First, a mask is used to cover the area of ​​the P-well that does not require N+ implantation. After exposing the planned area of ​​the entire N+ source region, pentavalent element ions are used for the first doping at 300℃-800℃, with a doping concentration of 0-1E18 / cm³. 3 Then, a second mask was applied to expose only the heavily doped region, and a second doping was performed using the same implantation conditions, with a doping concentration of 5E18 / cm³. 3 -5E20 / cm 3 ;

[0030] S203 undergoes annealing after the second doping is completed.

[0031] Preferably, the gate oxide layer and the isolation oxide layer are both made of silicon dioxide, and the deposition width of the gate polycrystalline layer is the same as the width of the gate oxide layer.

[0032] Preferably, a polycrystalline oxide layer is formed on the top surface and one side of the gate polycrystalline layer, and then an isolation oxide layer is deposited on one side of the top surface of the polycrystalline oxide layer.

[0033] The technical effects and advantages of this invention are as follows:

[0034] This invention introduces a stepped injection structure into the N+ source region, dividing it into heavily doped and lightly doped regions. It ensures low injection in the area overlapping with the gate to achieve good gate oxide quality, while high injection is used in other areas to achieve good ohmic injection. This reduces contact resistance through the heavily doped region and alleviates electric field concentration through the lightly doped region. By adjusting the doping concentration in these regions, the problem of N+ source region overlapping with the gate is fundamentally solved. This eliminates the need for stringent requirements on photolithography alignment, making the operation and implementation simpler. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the structure for improving the gate oxide reliability of silicon carbide MOSFETs according to the present invention.

[0036] Figure 2 This is a flowchart illustrating the manufacturing method of the silicon carbide MOSFET gate oxide reliability structure according to the present invention.

[0037] Figure 3 This is a flowchart illustrating the operation of forming the P-trap in this invention.

[0038] Figure 4 This is a flowchart illustrating the operation of forming the N+ source region in this invention.

[0039] Figure 5 This is a flowchart illustrating the formation process of the gate oxide layer and gate polycrystalline structure of the present invention.

[0040] Figure 6 This is a flowchart illustrating the formation process of the isolation oxide layer and interconnect layer of the present invention.

[0041] In the figure: 1. N- drift region; 2. P- well; 3. N+ source region; 301. Heavily doped region; 302. Lightly doped region; 4. Gate oxide layer; 5. Gate polycrystalline layer; 501. Polycrystalline oxide layer; 6. Isolation oxide layer; 7. Interconnect metal layer; 8. Channel region. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] Example 1: The present invention provides as follows Figure 1 The structure shown here for improving the gate oxide reliability of a silicon carbide MOSFET includes:

[0044] N-drift region 1, with an interconnect metal layer 7 deposited on the top surface of N-drift region 1;

[0045] It should be noted that N-drift region 1 refers to the N-type region with a low doping concentration, which is below 1E18 / cm². 3 The low carrier concentration in this region creates a resistance.

[0046] Ion implantation is performed at the top center of N-drift region 1 to form P-well 2, which is located between N-drift region 1 and the middle of interconnect metal layer 7.

[0047] Specifically, the implantation depth of P-well 2 in N-drift region 1 is 0.5µm-1.5µm, and the doping concentration of P-well 2 on the surface of N-drift region 1 is 1E16 / cm. 3 -1E17 / cm 3 The doping concentration of P-well 2 on the surface far from N-drift region 1 is 1E18 / cm². 3 -1E19 / cm 3 .

[0048] It should be noted that P-well 2 was formed by high-temperature (500℃) ion implantation with trivalent element (Al). The implantation depth was 0.5µm-1.5µm, and the surface doping concentration (0.1-0.2µm thickness) was relatively low (1E16 / cm²).3 -1E17 / cm 3 ), far from areas with high surface doping concentration (1E18 / cm) 3 -1E19 / cm 3 ).

[0049] N+ source region 3 is formed by implantation in P well 2. The two sides and bottom surface of N+ source region 3 are in contact with P well 2. N+ source region 3 includes heavily doped region 301 and lightly doped region 302. The heavily doped region 301 is located near the middle of P well 2 and is in contact with interconnect metal layer 7.

[0050] It should be noted that the N+ source region 3 is located inside the P-well 2, and the three sides (left, right and bottom) of the N+ source region 3 are surrounded by the P-well 2. The N+ source region 3 is formed by high-temperature implantation and by implantation of pentavalent element (N) ions, and the final junction depth is 0.1-0.5 μm.

[0051] Specifically, channel regions 8 are formed at both ends of the P-well 2 near the gate oxide layer 4, and one side of the channel region 8 is in contact with the side of the lightly doped region 302 away from the heavily doped region 301.

[0052] It should be noted that the channel region 8 is located on the top side of the P-well 2, adjacent to the gate oxide layer 4, and has a thickness of 0.1 μm. The left side of the channel region 8 is adjacent to the N- drift region 1, and the right side is adjacent to the N+ source region 3. The area near the channel region 8 is lightly doped (region 302), while the area near the interconnect metal layer 7 is heavily doped (region 301). The doping concentration of the lightly doped region 302 is less than 1E18 / cm². 3 The doping concentration in the heavily doped region 301 is greater than 5E18 / cm. 3 The gate oxide layer 4 at the top of the lightly doped region 302 is of better quality than that of the heavily doped region 301, which improves the reliability of the gate oxide layer 4.

[0053] A gate oxide layer 4 and an isolation oxide layer 6 are deposited on both sides of the top surface of the N-drift region 1 and the P-well 2. The isolation oxide layer 6 covers the top surface and one side of the gate oxide layer 4, and the top side of the N+ source region 3 is adjacent to the gate oxide layer 4. The bottom surface of the isolation oxide layer 6 is in contact with the top surface of the heavily doped region 301 and the top surface of the lightly doped region 302. The side of the isolation oxide layer 6 away from the gate oxide layer 4 is in contact with the interconnect metal layer 7. The bottom surface of the gate oxide layer 4 is in contact with the top surface of the N-drift region 1.

[0054] Specifically, a gate polycrystalline 5 is disposed between the isolation oxide layer 6 and the gate oxide layer 4. The side of the gate polycrystalline 5 closest to the isolation oxide layer 6 is oxidized to form a polycrystalline oxide layer 501. The polycrystalline oxide layer 501 covers the top surface of the gate polycrystalline 5 and the side close to the isolation oxide layer 6. The side of the polycrystalline oxide layer 501 away from the gate polycrystalline 5 is in contact with the isolation oxide layer 6. The polycrystalline oxide layer 501 is used to isolate the gate polycrystalline 5 and the isolation oxide layer 6.

[0055] It should be noted that the polycrystalline oxide layer 501 is formed on the surface of the gate polycrystalline 5 using an oxidation process to form a silicon dioxide thin film. During the oxidation process of the gate polycrystalline 5, the formation of the polycrystalline oxide layer 501 will consume 0.1 μm of the gate polycrystalline 5. The oxidation of the gate polycrystalline 5 is only used to consume the overlapping part between the gate polycrystalline 5 and the N+ source region 3. If the overlap between the gate polycrystalline 5 and the N+ source region 3 is 0.5 μm, then the polycrystalline oxide layer 501 is less than 0.5 μm to ensure that the gate oxide layer 4 overlaps with the N+ source region 3. This reduces the overlap between the gate polycrystalline 5 and the heavily doped region 301, which means reducing the area of ​​the gate oxide layer 4. In MOSFET devices, the quality of the gate oxide layer 4 is a weak point. Reducing the area of ​​the gate oxide layer 4 reduces the probability of failure, thereby improving reliability. That is, the width of the gate polycrystalline 5 should be reduced as much as possible, but the overlap between the gate oxide layer 4 and the N+ source region 3 should be guaranteed to be zero.

[0056] Example 2: The present invention provides as follows Figure 2 The method shown is for manufacturing a structure to improve the gate oxide reliability of a silicon carbide MOSFET, used to prepare the structure of the silicon carbide MOSFET with improved gate oxide reliability in Example 1. The manufacturing method includes the following steps:

[0057] S1, trivalent element ions are injected into the top surface of N-drift region 1 at 450℃-500℃ to form P-well 2. Gradient doping is used to inject 0.5um-1.5um to form channel regions 8 on both sides of the top surface of P-well 2.

[0058] For details, please refer to Figure 3 As shown, the formation of P-well 2 specifically includes the following steps:

[0059] S101, the top surface of N-drift zone 1 is treated by first using RCA standard cleaning to remove organic and metallic contaminants, and then using hydrofluoric acid rinsing to remove native oxides.

[0060] It should be noted that the RCA standard cleaning procedure includes the following steps:

[0061] A1. Organic contamination cleaning: First, prepare deionized water, sodium hydroxide or ammonia, and hydrogen peroxide in a ratio of 5:1:1. Then, mix the solutions. In a well-ventilated environment, mix sodium hydroxide (or ammonia) and hydrogen peroxide, add deionized water, and stir well. Next, immerse the wafer with the N-drift region 1 marked in the organic cleaning solution in the solution for 10-15 minutes. Finally, rinse the wafer and N-drift region 1 thoroughly with deionized water to ensure the removal of cleaning solution and residual contaminants.

[0062] A2, Inorganic Contamination Cleaning: First, prepare deionized water, hydrochloric acid, and nitric acid in a ratio of 5:1:1. Then, mix the solutions in a fume hood by adding deionized water after mixing hydrochloric acid and nitric acid, and stirring until homogeneous. Next, immerse the wafer with the N-drift region 1 defined in the inorganic cleaning solution in the solution for 10-15 minutes. Finally, thoroughly rinse the wafer and N-drift region 1 with deionized water to ensure the removal of cleaning solution and any residual contaminants.

[0063] A3, Final Rinse and Dry: After cleaning organic and inorganic contaminants, rinse the wafer and N-drift region 1 again with deionized water to ensure complete removal of all chemicals; finally, dry the wafer and N-drift region 1 with nitrogen or in a dryer to avoid water droplets leaving traces.

[0064] The removal of native oxides begins with preparing an HF solution using diluted hydrofluoric acid (1% HF). The wafer, after RCA standard cleaning, is then immersed in the HF solution, or sprayed evenly onto the surface of N-drift region 1, and held for 1–2 minutes to ensure effective removal of the native oxides. Finally, the wafer and N-drift region 1 are thoroughly rinsed with deionized water to remove residual HF solution and any dissolved oxides, preventing any impact on subsequent steps. The chemical reaction equation for this operation is as follows:

[0065] SiO2 + 4HF = SiF4↑ + 2H2O

[0066] The silicon tetrafluoride (SiF4) generated by the reaction escapes in gaseous form, and water molecules are also removed. The native oxide layer is effectively removed by rinsing with hydrofluoric acid, resulting in a clean silicon surface, which provides a good foundation for subsequent processes (doping, oxidation, or deposition). If the wafer does not require immediate processing after the operation, a 50nm sacrificial oxide layer will be grown on the surface of the wafer, which will be removed before subsequent ion implantation.

[0067] S102, spin-coating photoresist onto the top surface of the cleaned N-drift region 1, and performing ultraviolet photolithography on the coated area using a mask that conforms to the pattern of P-well 2 to form an open injection window. The size of the injection window matches the design of the cross-sectional area of ​​P-well 2.

[0068] It should be noted that the photoresist used for spin coating is a high-temperature resist photoresist (polyimide type). First, a few hundred microliters of photoresist (depending on the wafer size and photoresist properties) are dropped onto the top surface of the N-drift region 1. Then, the spin coater is used with the spin coating parameters set, including rotation speed and time: the initial speed is set to 500-1000 RPM to ensure uniform distribution of the photoresist; the acceleration time is 1-3 seconds, with slow acceleration to prevent photoresist splattering; finally, the spin coater is rotated at 3000-6000 RPM. To form a uniform thin film, the process takes 30–60 seconds. Then, the spin coater is started, and the wafer begins to rotate. Under centrifugal force, the photoresist is uniformly coated onto the surface of the N-drift region 1. After spin coating, pre-baking is performed to remove the solvent from the photoresist. The wafer is then heated on a hot plate, with the temperature and time determined according to the photoresist's instructions (90–120°C, 1–5 minutes). Finally, a film thickness gauge (reflectometer or ellipsometry) is used to check the photoresist film thickness to ensure it meets design requirements.

[0069] S103, after heating the N-drift region 1 to 450℃-550℃, a high-temperature ion implanter was used, with the implantation energy set to 300keV-600keV. Trivalent element (Al) ions were implanted into the implantation window in two stages. The implantation concentration in the first stage was controlled at 1E18 / cm³. 3 -1E19 / cm 3 The injection depth was 0.3µm-1.4µm, and the second-stage injection concentration was controlled at 1E16 / cm³. 3 -1E17 / cm 3 1E16-17 / cm 3 The concentration is lower than that of intrinsic silicon carbide carriers, which can effectively suppress the depletion layer punch-through under gate voltage. The implantation depth is 0.1um-0.2um, and the total implantation depth is 0.5um-1.5um. If the total depth is less than 0.5um, it will lead to insufficient breakdown voltage. If the total depth is greater than 1.5um, it will increase the process difficulty.

[0070] It should be noted that the implanted element is aluminum (Al), which is a trivalent acceptor with a lower activation energy than boron, making it suitable for SiC materials. During high-temperature ion implantation, the key parameter is set between 300–600 keV to control the junction depth. The implantation dose can be subdivided into three stages in actual operation: high-energy implantation 1E14 / cm². 2 To form a deep, high-concentration zone, medium-energy injection of 5E13 / cm 2 To form a transition region, low-energy injection of 1E13 / cm 2 To control surface concentration, the wafer needs to be heated to 500°C to prevent lattice damage, and a high-temperature ion implanter equipped with a wafer heating stage is used for the operation. Furthermore, a carbon cap layer must be applied after implantation to prevent high-temperature decomposition of the SiC surface.

[0071] High-temperature ion implanters utilize an electric field to accelerate ions, bombarding the wafer surface with high energy. Dopant elements are then embedded into the crystal structure through ion implantation. Under high-temperature conditions, implanted ions move and orient more easily within the crystal lattice, reducing lattice damage and improving doping activity. The components include: an ion source to generate the desired ions (nitrogen, phosphorus, arsenic, aluminum), using either a gas or solid source; an accelerator to accelerate the ions to the required energy (between 50 keV and 200 keV) to control the implantation depth; a high-temperature furnace to heat the wafer, reaching 500°C to 1000°C to promote dopant activation and lattice repair; a vacuum chamber to maintain a low-pressure environment to reduce collisions between ions and gas molecules during implantation; and a positioning system to ensure the wafer remains precisely positioned during implantation, guaranteeing uniformity and accuracy.

[0072] S104 was subjected to rapid thermal annealing to activate trivalent ions. The annealing was carried out under an argon atmosphere at 1700℃ for 3-8 minutes. This step aimed to repair lattice damage and activate aluminum acceptors, ensuring an activation rate greater than 80%. The final concentration distribution was: surface (0-0.2 μm) concentration of 1E16–1E17 / cm³. 3 This resulted in low-concentration channel zones; while the concentration in areas with a depth ≥0.5μm was 1E18–1E19 / cm³. 3 This forms a low-resistance ohmic contact area.

[0073] Furthermore, the concentration calculation for the trivalent element ion implantation in P-trap 2 is expressed as follows:

[0074]

[0075] Where C(z,t) represents the total concentration at time t and depth z, and R p,i Q represents the average projected range of the i-th injection. i σ represents the dose of trivalent element ions injected in the i-th injection. i Let represent the standard deviation after diffusion of the i-th injection, D represent the diffusion coefficient, and Dt represent the diffusion width of the trivalent ion within time t.

[0076] After the injection is divided into three stages, the concentration is calculated according to the injection energy and metering table in Table 1 below;

[0077] Table 1. Injected Energy and Measurement Table

[0078] stage Energy (keV) <![CDATA[Energy Q i (cm -2 )]]> <![CDATA[R p (nm)]]> <![CDATA[ΔR p (nm)]]> 1 60 <![CDATA[2.0X10 13 ]]> 200 60 2 120 <![CDATA[5.0X10 12 ]]> 400 100 3 180 <![CDATA[3.0X10 13 ]]> 600 140

[0079] Assume the annealing conditions are 1100℃ (1373K), t = 1h = 3600s;

[0080] The diffusion coefficient D is calculated as follows:

[0081]

[0082] After each diffusion step, σ i The calculation is as follows:

[0083]

[0084] Concentration distribution is calculated as follows:

[0085]

[0086] After substituting the above calculation results, output the total result:

[0087] Surface concentration C s ≈1.3×10 17 cm -3 .

[0088] S2, plan an N+ source region 3 at P well 2, and define the region near the center of P well 2 as the heavily doped region 301 and the region far from the center of P well 2 as the lightly doped region 302. Then, implant pentavalent element ions at 300℃-800℃ to a depth of 0.1um-0.5um to form the heavily doped region 301 and the lightly doped region 302 respectively.

[0089] It should be noted that N+ implantation is performed on the top surface of P-well 2, and the N+ source region 3 is located inside P-well 2, surrounded by P-well 2 on three sides (left, right, and bottom), with the top side adjacent to the gate oxide layer 4. The formation of N+ source region 3 adopts high-temperature ion implantation technology, mainly using pentavalent elements (nitrogen) for ion implantation, with a final junction depth of 0.1-0.5 μm, ensuring its suitability for subsequent device structures.

[0090] For details, please refer to Figure 4 As shown, the formation of N+ source region 3 specifically includes the following operations:

[0091] S201, firstly, an N+ source region 3 is planned on the top surface of P-well 2, with a planned junction depth of 0.1um-0.5um. The N+ source region 3 is divided into a heavily doped region 301 and a lightly doped region 302, with the lightly doped region 302 adjacent to the channel region 8. The first mask is used to define the lightly doped region 302 (covering the heavily doped region 301), and the second mask is used to define the heavily doped region 301 (with a window smaller than the lightly doped region 302, and a shrinkage of 0.2μm).

[0092] S202 uses photolithography. First, a mask is used to cover the area of ​​P-well 2 that does not require N+ implantation. After exposing the planned area of ​​the entire N+ source region 3, pentavalent element ions are used for the first doping at 300℃-800℃, with a doping concentration of 0-1E18 / cm³. 3Afterwards, a second mask was applied to expose only the heavily doped region 301, and a second doping was performed using the same implantation conditions, with a doping concentration of 5E18 / cm³. 3 -5E20 / cm 3 ;

[0093] S203 undergoes annealing after the second doping is completed. Rapid thermal annealing is performed at a temperature range of 1650℃-1700℃ for 2 minutes (under nitrogen atmosphere), with a gradient heating method of 20℃ / s to prevent surface decomposition.

[0094] It should be noted that, through the partitioned injection design of light and heavy doping, the core functions of the lightly doped region 302 include electric field modulation, reducing the electric field strength at the end of the channel region 8 (from greater than 2.5MV / cm to less than 1.8MV / cm); suppressing hot carrier injection, and reducing the probability of electron tunneling through the gate oxide (improving reliability by 3 times).

[0095] The necessity of the heavily doped region 301 includes contact resistance optimization, with a specific contact resistance of less than 1E. -5 Ω·cm 2 (Meets high current requirements); suppresses parasitic resistance, reducing the series resistance of N+ source region 3 by 50%.

[0096] refer to Figure 5 As shown in Figure S3, a gate oxide layer 4 is deposited on the top surface at both ends of the N-drift region 1 and the top surface of the channel region 8, and then a gate polycrystalline layer 5 is formed on the top surface of the gate oxide layer 4 by chemical vapor deposition.

[0097] It should be noted that the specific operational steps for forming the gate oxide layer 4 and the gate polycrystalline layer 5 are as follows:

[0098] If the wafer has been left for a period of time after the N+ source region 3 is prepared, the wafer needs to undergo surface pretreatment. The wafer is first cleaned by RCA standard (removal of organic residues → removal of metal ions), then immersed in 0.5% hydrofluoric acid (HF) solution for 30 seconds to thoroughly remove native oxides until the surface water contact angle is greater than 85°. After drying with nitrogen, it is immediately transferred to a vacuum reaction chamber. Then, in-situ hydrogen annealing is performed in a hydrogen atmosphere (purity greater than 99.999%), with the temperature increased to 1100°C at 20°C / s and held for 10 min (pressure 100 mTorr) to repair surface atomic steps and reduce the roughness to less than 0.2 nm (verified by AFM).

[0099] For the growth of gate oxide layer 4, dry oxygen oxidation was first performed, with high-purity oxygen (5 standard liters / min) introduced and reacted at 1300℃ for 30 min to form a dense SiO2 / SiC interface layer (thickness ≈20 nm). Then, wet oxygen oxidation was performed, switching to a wet oxygen atmosphere (H2O / O2 mixture, water-to-oxygen ratio 1.5) and continuing at 950℃ for 60 min to increase the total thickness to 50±1 nm (monitored in real-time by a laser ellipsometer). Following this, nitriding annealing was performed in a NO / N2O mixture (NO concentration 10%) at 1300℃ for 45 min, enriching nitrogen atoms at the SiO2 / SiC interface (peak concentration 5 × 10⁻⁶). 20 cm -3 Finally, a protective layer is deposited by growing a 10nm silicon nitride (SiN) capping layer through plasma-enhanced chemical vapor deposition (PECVD) to prevent contamination in subsequent processes.

[0100] Polycrystalline silicon gate deposition and doping were performed first. Deposition preparation involved removing the SiN protective layer and rinsing with diluted HF for 5 seconds to expose the clean oxide layer surface. Then, low-pressure chemical vapor deposition (LPCVD) was initiated, with silane (SiH4) introduced into the LPCVD reaction chamber. Polycrystalline silicon was deposited at 620℃ and 150 mTorr at a rate of 10 nm / min, achieving a total thickness of 400 nm (monitored in real-time using a quartz crystal microbalance). Finally, in-situ phosphorus doping was performed, with phosphine (PH3) introduced simultaneously at a gas flow rate of PH3:SiH4 = 0.5%, achieving uniform doping with a resistivity of less than 20 mΩ·cm (verified by a four-probe test).

[0101] Gate patterning begins with photolithography definition, followed by spin coating of chemical amplification resist (CAR, 0.5 μm thickness), and exposure using a 193 nm ArF excimer laser (dose 25 mJ / cm²). 2 The process involves developing a grid pattern (overlay accuracy ±30nm), followed by polysilicon etching. In reactive ion etching (RIE), a mixed gas of HBr / Cl2 / HeO2 (60 / 20 / 5 sccm) is used in the main etching stage, while N2 is introduced into the sidewalls to form a passivation layer. Endpoint detection is achieved by monitoring the emission line intensity of Si at 288nm, and the over-etching amount is controlled within 5%, ensuring a sidewall angle of 89°±0.5°. Finally, residue removal is performed using SF6 / O2 (20 / 2 sccm) for 10s over-etching to remove etching residues.

[0102] Post-processing and verification were performed first, including ashing and cleaning. O2 plasma ashing removed the photoresist, and megasonic cleaning (1MHz frequency) eliminated particle residue. Quality inspection was then conducted, including gate oxide thickness (49-point scan using a spectroscopic ellipsometry, tolerance ±1nm); and interface state density (DIT) was measured using a quasi-static CV method, requiring Dit < 5 × 10⁻⁶.10 cm -2 eV -1 Gate morphology: Linear roughness (3σ < 3nm) was measured using CD-SEM.

[0103] refer to Figure 6 As shown in step S4, an isolation oxide layer 6 is deposited on the top and side surfaces of the gate polycrystalline 5 and the side surfaces of the gate oxide layer 4. Then, contact holes are formed on the surface of the isolation oxide layer 6 by photolithography and etching. Finally, an interconnect metal layer 7 is formed by metal deposition.

[0104] Specifically, the gate oxide layer 4 and the isolation oxide layer 6 are both made of silicon dioxide. The deposition width of the gate polycrystalline layer 5 is the same as the width of the gate oxide layer 4. A polycrystalline oxide layer 501 is formed on the top surface and one side of the gate polycrystalline layer 5, and then the isolation oxide layer 6 is deposited on one side of the top surface of the polycrystalline oxide layer 501.

[0105] It should be noted that the entire manufacturing process of the isolation oxide layer 6 and the contact holes is as follows:

[0106] The formation of the polycrystalline oxide layer 501 involves first performing thermal oxidation growth. The wafer with the gate etched is placed in an oxidation furnace, and pure oxygen (O2 flow rate 5SLM) is introduced. The temperature is increased to 900℃ at 10℃ / min and held for 30min. Then, a 100±5nm silicon dioxide layer is formed on the top surface of the gate polycrystalline layer 501, and a 50±5nm asymmetric oxide layer is formed on the sidewall (thickness verified by SEM). Finally, the temperature is reduced to 600℃ and nitrogen protection is switched to prevent over-oxidation.

[0107] For the deposition of the isolation oxide layer 6, PECVD deposition was first performed using silane (SiH4: 200 sccm) and nitrous oxide (N2O: 400 sccm) as the reaction gases. The deposition was carried out at a constant temperature of 350℃, a reaction pressure of 1.5 Torr, a deposition rate of 50 nm / min, and a total thickness of 500 nm. Then, wafer rotation (30 rpm) was performed to ensure uniform coverage, with particular attention paid to the gate sidewalls (coverage >95%). Finally, annealing and densification were carried out at 800℃ for 30 minutes in a nitrogen atmosphere to eliminate film porosity (density from 2.0 g / cm³). 3 Increased to 2.2g / cm 3 ).

[0108] Contact hole photolithography and etching are performed first. A positive photoresist (AR-U4360, 1.2μm thickness) is spin-coated and soft-baked at 90℃ for 90s. Then, i-line exposure (365nm, 300mJ / cm²) is performed using a chromium mask (contact hole pattern). 2After development, a 0.8×0.8μm hole array was formed (overlay accuracy ±0.15μm); then oxide etching was performed, with trifluoromethane / argon / oxygen as the etching gas (CHF3 / Ar / O2=40 / 50 / 5sccm), and the parameters were set as follows: RF power 800W, bias voltage 100V, temperature 20℃, and the endpoint was controlled by real-time monitoring of the Si 288nm characteristic peak by plasma emission spectroscopy (OES). After the peak disappeared, over-etching continued for 10s; the final hole depth was 550nm (measured by SEM), and the heavily doped region 301 was exposed at the bottom.

[0109] The metallization process begins with pre-cleaning and deposition, using Ar... + Sputter cleaning, 300 eV ion bombardment for 60 s, removes oxides at the bottom of the pores (oxygen content verified as less than 5% by EDX); then magnetron sputtering deposition is performed, with a 30 nm titanium (Ti) adhesion layer (DC power 5 kW, Ar pressure 3 mTorr), a 50 nm titanium nitride (TiN) barrier layer (reactive sputtering, N2 flow rate 30 sccm), a 200 nm nickel (Ni) contact layer (rate 20 nm / min), and a 1 μm silver (Ag) conductive layer (rate 100 nm / min); finally, rapid thermal annealing is performed at 1000 °C ± 5 °C for 60 s in a nitrogen atmosphere to form Ni2Si ohmic contacts (contact resistance less than 5 × 10⁻⁶). ～6 Ω·cm 2 ).

[0110] Metal patterning is performed, interconnects are defined by photolithography, and Ag / Ni layers are etched by Cl2 / BCl3 (40 / 20 sccm) plasma etching (selectivity ratio greater than 100:1) to form an interconnect structure with a linewidth greater than or equal to 2 μm.

[0111] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A structure for improving the gate oxide reliability of silicon carbide MOSFETs, characterized in that, include: N-drift region (1), the top surface of which is deposited with an interconnect metal layer (7); A P-well (2) is formed by ion implantation at the top center of the N-drift region (1), and the P-well (2) is located between the N-drift region (1) and the middle of the interconnect metal layer (7); An N+ source region (3) is formed by implantation in the P-well (2). The two sides and the bottom surface of the N+ source region (3) are in contact with the P-well (2). The N+ source region (3) includes a heavily doped region (301) and a lightly doped region (302). The heavily doped region (301) is located near the middle of the P-well (2) and is in contact with the interconnect metal layer (7). A gate oxide layer (4) and an isolation oxide layer (6) are deposited on both sides of the top surface of the N-drift region (1) and the P-well (2). The isolation oxide layer (6) covers the top surface and one side of the gate oxide layer (4). The bottom surface of the isolation oxide layer (6) is in contact with the top surface of the heavily doped region (301) and the top surface of the lightly doped region (302). The side of the isolation oxide layer (6) away from the gate oxide layer (4) is in contact with the interconnect metal layer (7). The bottom surface of the gate oxide layer (4) is in contact with the top surface of the N-drift region (1).

2. The structure for improving the gate oxide reliability of a silicon carbide MOSFET according to claim 1, characterized in that, The implantation depth of the P-well (2) in the N-drift region (1) is 0.5 μm-1.5 μm, and the doping concentration of the P-well (2) on the surface of the N-drift region (1) is 1E16 / cm. 3 -1E17 / cm 3 The doping concentration of the P-well (2) on the surface away from the N-drift region (1) is 1E18 / cm. 3 -1E19 / cm 3 .

3. The structure for improving the gate oxide reliability of a silicon carbide MOSFET according to claim 1, characterized in that, The P-well (2) has channel regions (8) formed at both ends near the gate oxide layer (4), and one side of the channel region (8) is in contact with the side of the lightly doped region (302) away from the heavily doped region (301).

4. The structure for improving the gate oxide reliability of a silicon carbide MOSFET according to claim 1, characterized in that, A gate polycrystalline silicon (5) is disposed between the isolation oxide layer (6) and the gate oxide layer (4). The side of the gate polycrystalline silicon (5) close to the isolation oxide layer (6) is oxidized to form a polycrystalline oxide layer (501). The polycrystalline oxide layer (501) covers the top surface of the gate polycrystalline silicon (5) and the side close to the isolation oxide layer (6). The side of the polycrystalline oxide layer (501) away from the gate polycrystalline silicon (5) is in contact with the isolation oxide layer (6). The polycrystalline oxide layer (501) is used to isolate the gate polycrystalline silicon (5) and the isolation oxide layer (6).

5. A method for manufacturing a structure to improve the gate oxide reliability of a silicon carbide MOSFET, used to prepare a structure comprising the structure described in claims 1-4 for improving the gate oxide reliability of a silicon carbide MOSFET, characterized in that, The manufacturing method includes the following steps: S1, trivalent element ions are injected into the top surface of the N-drift region (1) at 450℃-500℃ to form a P-well (2). Gradient doping is used to inject 0.5um-1.5um to form a channel region (8) on both sides of the top surface of the P-well (2). S2, plan an N+ source region (3) at P well (2), and define the region near the center of P well (2) as the heavily doped region (301) and the region far from the center of P well (2) as the lightly doped region (302). Then, at 300℃-800℃, implant pentavalent element ions to a depth of 0.1um-0.5um to form the heavily doped region (301) and the lightly doped region (302) respectively. S3, a gate oxide layer (4) is deposited on the top surface of both ends of the N-drift region (1) and the top surface of the channel region (8), and then a gate polycrystalline layer (5) is formed on the top surface of the gate oxide layer (4) by chemical vapor deposition. S4, an isolation oxide layer (6) is deposited on the top and side of the gate polycrystalline (5) and the side of the gate oxide layer (4) to form an isolation oxide layer (6). Then, contact holes are formed on the surface of the isolation oxide layer (6) by photolithography and etching. Finally, an interconnect metal layer (7) is formed by metal deposition.

6. The method for manufacturing a structure to improve the gate oxide reliability of a silicon carbide MOSFET according to claim 5, characterized in that, The formation of the P-well (2) specifically includes the following steps: S101, the top surface of the N-drift zone (1) is treated by first cleaning with RCA standard to remove organic and metal contaminants, and then rinsing with hydrofluoric acid to remove native oxides. S102, spin-coat photoresist on the top surface of the cleaned N-drift region (1), and perform ultraviolet lithography on the coated area through a mask conforming to the pattern of the P-well (2) to form an open injection window; S103, after heating the N-drift region (1) to 450℃-550℃, a high-temperature ion implanter is used, and the implantation energy is set to 300keV-600keV. Trivalent element ions are implanted into the implantation window in two stages. The implantation concentration in the first stage is controlled at 1E18 / cm. 3 -1E19 / cm 3 The injection depth was 0.3µm-1.4µm, and the second-stage injection concentration was controlled at 1E16 / cm³. 3 -1E17 / cm 3 The implantation depth is 0.1um-0.2um, and the total implantation depth is 0.5um-1.5um; S104 was subjected to rapid thermal annealing to activate trivalent ions, and the annealing was carried out in an argon atmosphere at 1700℃ for 3 to 8 minutes.

7. The method for manufacturing a structure to improve the gate oxide reliability of a silicon carbide MOSFET according to claim 6, characterized in that, The concentration calculation for the trivalent element ion implantation in the P-trap (2) is expressed as follows: Where C(z,t) represents the total concentration at time t and depth z, and R p,i Q represents the average projected range of the i-th injection. i σ represents the dose of trivalent element ions injected in the i-th injection. i Let represent the standard deviation after diffusion of the i-th injection, D represent the diffusion coefficient, and Dt represent the diffusion width of the trivalent ion within time t.

8. The method for manufacturing a structure to improve the gate oxide reliability of a silicon carbide MOSFET according to claim 5, characterized in that, The formation of the N+ source region (3) specifically includes the following operations: S201, firstly, the region of N+ source region (3) is planned on the top surface of P well (2), and the junction depth is planned to be 0.1um-0.5um. The N+ source region (3) is divided into heavily doped region (301) and lightly doped region (302), and the lightly doped region (302) is adjacent to the channel region (8). S202, using photolithography, firstly, a mask is used to cover the area of ​​the P-well (2) that does not require N+ implantation. After exposing the planned area of ​​the entire N+ source region (3), pentavalent element ions are used for the first doping at 300℃-800℃, with a doping concentration of 0-1E18 / cm. 3 Then, a second mask was applied to expose only the heavily doped region (301), and a second doping was performed using the same implantation conditions, with a doping concentration of 5E18 / cm³. 3- 5E20 / cm 3 ; S203 undergoes annealing after the second doping is completed.

9. A method for manufacturing a structure to improve the gate oxide reliability of a silicon carbide MOSFET according to claim 5, characterized in that, The gate oxide layer (4) and the isolation oxide layer (6) are both made of silicon dioxide, and the deposition width of the gate polycrystalline layer (5) is the same as the width of the gate oxide layer (4).

10. A method for manufacturing a structure to improve the gate oxide reliability of a silicon carbide MOSFET according to claim 5, characterized in that, A polycrystalline oxide layer (501) is formed on the top surface and one side of the gate polycrystalline layer (5), and then an isolation oxide layer (6) is deposited on one side of the top surface of the polycrystalline oxide layer (501).

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