Semiconductor device

Abstract

The invention discloses a semiconductor device, which is provided with an IGBT (Insulated Gate Bipolar Translator) region, a transition region and an MOS (Metal Oxide Semiconductor) region, and comprises a semiconductor substrate, a drift layer arranged in the semiconductor substrate, and a base layer arranged in the semiconductor substrate; the IGBT region, the transition region and the MOS region respectively comprise a conductive structure which penetrates through the base layer and is partially positioned on the drift layer, the conductive structure is used as a trench gate in the IGBT region and the MOS region, and the conductive structure is used as a conductive trench in the transition region. The plurality of conductive grooves intersect and comprise a first conductive groove extending along a second direction and a second conductive groove extending along a third direction, the groove grid electrode of the IGBT region is electrically isolated from the conductive groove of the transition region, and the groove grid electrode of the MOS region is electrically connected with the conductive groove of the transition region. According to the invention, the advantages of the IGBT and the MOSFET are combined, the loss is reduced, and the overall efficiency can be optimized in a wider current and frequency range.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device. Background Technology

[0002] Typically, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) suffer higher losses compared to IGBTs (Insulated Gate Bipolar Transistors) under high current conditions, while IGBTs suffer higher losses compared to MOSFETs under low current or high frequency conditions. Therefore, modules that only incorporate MOSFET chips or only incorporate IGBT chips have limited current and frequency compatibility, making them unsuitable for widespread application. Summary of the Invention

[0003] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0004] This application addresses the deficiencies in the prior art, and its main objective is to provide a semiconductor device that can be used in a wide range of applications.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] To address the existing problems, embodiments of the present invention provide a semiconductor device having an IGBT region, a transition region, and a MOS region, wherein the transition region surrounds the MOS region, and the IGBT region surrounds the transition region. The semiconductor device includes:

[0007] A semiconductor substrate having a first main surface and a second main surface disposed opposite to each other along a first direction;

[0008] A drift layer is disposed within the semiconductor substrate and located between the first main surface and the second main surface, and has a first conductivity type;

[0009] A base layer, disposed within the semiconductor substrate and located on the side of the drift layer closer to the first main surface, has a second conductivity type; wherein,

[0010] The IGBT region, the transition region, and the MOS region each include a conductive structure that extends through the base layer from the first main surface and is partially located in the drift layer, wherein the sidewalls of the conductive structure are further surrounded by an insulating film.

[0011] Within the IGBT region and the MOS region, the conductive structure serves as a trench gate, and the insulating film serves as a gate dielectric layer.

[0012] Within the transition region, the conductive structure serves as a plurality of conductive trenches. In a top view of the semiconductor device, the plurality of conductive trenches intersect. Each conductive trench includes at least one first conductive trench extending along a second direction and at least one second conductive trench extending along a third direction. Both the second direction and the third direction are perpendicular to the first direction, and the first direction and the second direction intersect.

[0013] The trench gate of the IGBT region and the conductive trench of the transition region are electrically isolated, while the trench gate of the MOS region and the conductive trench of the transition region are electrically connected.

[0014] The above embodiments have the following beneficial effects: By simultaneously setting IGBT and MOS regions in the semiconductor device and providing a transition region between them, the IGBT and MOS regions are separated, thus combining the advantages of IGBTs and MOSFETs. MOSFETs handle high-frequency, low-current applications, while IGBTs handle low-frequency, high-current applications. When the current is high, the IGBT primarily operates; when the current is low or the frequency is high, the MOSFET primarily operates, reducing switching losses. This allows for automatic switching or coordination of the two under different operating conditions, optimizing overall efficiency over a wider range of current and frequency applications. Furthermore, the electrical isolation between the trench gate of the IGBT region and the conductive trench of the transition region reduces electric field interference between the IGBT and MOSFET regions, improving device stability and reliability. By electrically connecting the conductive trench of the transition region to the trench gate of the MOS region, the potential gradient can be adjusted through the transition region, thereby optimizing the electric field distribution.

[0015] In some embodiments, there is a gap between the conductive trench located around the transition region and the trench gate of the adjacent IGBT region.

[0016] The above embodiments have the following beneficial effects: by setting a gap between the conductive trench outside the transition region and the trench gate of the IGBT region, electrical isolation between the transition region and the IGBT region is achieved.

[0017] In some embodiments, in the top view of the semiconductor device, the MOS region has a plurality of first trench gates extending along the second direction and spaced apart along the third direction, and at least two second trench gates extending along the third direction and connected to the plurality of first trench gates, wherein the first trench gates and the second trench gates located at the boundary of the MOS region form a ring.

[0018] The above embodiments have the following beneficial effects: by setting multiple first trench gates and second trench gates in the MOS region, the number of trench gates in the horizontal and vertical directions can be increased, thereby increasing the number of conductive channels per unit area, thereby reducing the on-resistance. At the same time, the edge enclosure to form a ring helps to achieve uniform current distribution, reduce edge effects, and improve withstand voltage capability.

[0019] In some embodiments, in a top view of the semiconductor device, the MOS region has a first side and a second side opposite to each other along the second direction, and a third side and a fourth side opposite to each other along the third direction, wherein,

[0020] Outside the first side and outside the second side, the transition region includes a plurality of first conductive trenches and at least one second conductive trench, wherein the plurality of first conductive trenches and at least one second conductive trench located on the same side are connected.

[0021] Outside of the third side and the fourth side, the transition region includes a plurality of first conductive trenches electrically connected by at least one second conductive trench located outside the first side and / or the second side.

[0022] The above embodiments have the following beneficial effects: the first conductive trench provides a low-resistance lateral path, eliminating current congestion; the second conductive trench enhances longitudinal carrier injection; the arrangement of the first and second conductive trenches can optimize the current flow path and reduce on-resistance. Especially in the transition region, where the current needs to switch between the MOS region and the IGBT region, a good conductive trench design can reduce the impedance of the current path and reduce losses.

[0023] In some embodiments, in a top view, a plurality of first conductive trenches and a plurality of second conductive trenches are provided at the boundary of the transition region, and the plurality of first conductive trenches and the plurality of second conductive trenches form at least one annular trench.

[0024] The above embodiments have the following beneficial effects: by forming an annular trench through the first conductive trench and the second conductive trench, the electric field distribution can be adjusted to avoid excessively high local electric fields.

[0025] In some embodiments, part of the conductive structure also serves as a grounding trench, wherein, in the top view of the semiconductor device, the opposite ends of the first conductive trench at the outermost boundary of the transition region are respectively connected to the grounding trench, the grounding trench extends outward of the transition region along the second direction, wherein the width of the grounding trench is greater than the width of the conductive trench.

[0026] The above embodiments have the following beneficial effects: using a wider contact trench helps to reduce contact resistance, while placing the contact trench at the edge can reduce the electric field concentration in the IGBT area and avoid the risk of breakdown, while the thinner part in the middle helps to maintain an appropriate electric field gradient, thereby improving the overall withstand voltage energy.

[0027] In some embodiments, the grounding trench and the first conductive trench to which it is connected coincide along the centerline of the second direction; and / or, the width of the grounding trench is the same as the width of the trench gate of the respective adjacent IGBT region.

[0028] The above embodiments have the following beneficial effects: by making the width of the grounding trench the same as the width of the trench gate of the adjacent IGBT region, the electric field concentration in the IGBT region is reduced.

[0029] In some embodiments, the junction between the grounding trench and the first conductive trench to which it is connected is constructed in an arc shape.

[0030] The above embodiments have the following beneficial effects: the arc transition can make the current distribution more uniform at the junction, and reduce the electric field concentration at the junction of the grounding trench and the first conductive trench.

[0031] In some embodiments, in a top view, at least one conductive trench in the transition region and a gate trench in their respective corresponding MOS regions are integral straight trenches.

[0032] The above embodiments have the following beneficial effects: they can not only reduce manufacturing steps and lower costs, but also make the current transmission between the MOS region and the transition region smoother, reduce interface resistance, thereby reducing conduction losses. At the same time, they also help to improve the uniformity of electric field distribution, avoid electric field concentration caused by structural discontinuity, and thus improve withstand voltage capability.

[0033] In some embodiments, in the top view of the semiconductor device, the IGBT region has a plurality of third trench gates extending along the second direction and spaced apart along the third direction, and a plurality of fourth trench gates extending along the third direction, wherein, in the second direction, the plurality of third trench gates and the fourth trench gates spaced apart by the transition region intersect.

[0034] The above embodiments have the following beneficial effects: the arrangement of the third trench gate and the fourth trench gate can more effectively control the distribution of charge carriers, improve the conduction performance of the IGBT, and also make the current uniformly distributed in the IGBT region, avoid excessive local current density, reduce the risk of hot spots, and improve the reliability and stability of the device.

[0035] In some embodiments, in a top view of the semiconductor device, the MOS region has a plurality of first trench gates extending along the second direction and spaced apart along the third direction, and the IGBT region has a plurality of third trench gates extending along the second direction and spaced apart along the third direction, wherein...

[0036] The plurality of first trench gates and the plurality of third trench gates are offset in the third direction; and / or

[0037] At least one of the first trench gates and at least one of the third trench gates are aligned upwards on the third.

[0038] The above embodiments have the following beneficial effects: by staggering the multiple first trench gates and the multiple third trench gates in the third direction, the current density of the MOS region can be increased, while the aligned arrangement can reduce electric field concentration and simplify the manufacturing process.

[0039] In some embodiments, the width of the trench gate located in the IGBT region is greater than the width of the trench gate located in the MOS region, and the width of the trench gate located in the IGBT region is greater than the width of the conductive trench located in the transition region; or

[0040] The width of the trench gate in the IGBT region, the width of the trench gate in the MOS region, and the width of the conductive trench in the transition region are the same.

[0041] The above embodiments have the following beneficial effects: the width of the trench gate in the IGBT region is greater than the width of the trench gate in the MOS region, thereby increasing the current density in the MOS region. Furthermore, the width of the trench gate in the IGBT region is greater than the width of the conductive trench in the transition region, thereby enhancing the conductivity modulation effect of the trench gate in the IGBT region and reducing the on-state voltage drop. Since the width of the trench gate is the same as the width of the conductive trench, the complexity in the process steps is reduced, and the manufacturing process is simplified.

[0042] In some embodiments, the width of the trench gate located in the MOS region is equal to the width of the conductive trench located in the transition region.

[0043] The above embodiments have the following beneficial effects: they can reduce process steps, thereby simplifying the manufacturing process.

[0044] In some embodiments, in the second direction, the spacing between adjacent trench gates in the IGBT region is a first distance, the spacing between a trench gate extending along the second direction in the IGBT region and a first conductive trench in the adjacent transition region is a second distance, and the spacing between a trench gate extending along the second direction in the MOS region and a first conductive trench in the adjacent region is a third distance, wherein the second distance is greater than the first distance, and the first distance is greater than the third distance.

[0045] The above embodiments have the following beneficial effects: the second distance is greater than the first distance, which makes the trench gate in the IGBT region and the first conductive trench in the transition region better isolated. The first distance is greater than the third distance, so that while achieving electrical connection between the first conductive trench in the transition region and the trench gate in the MOS region, the total space occupied by the MOS region and the transition region can be reduced by using a smaller spacing.

[0046] In some embodiments, the depth of the trench gate in the IGBT region, the depth of the trench gate in the MOS region, and the depth of the conductive trench in the transition region are the same; or

[0047] The depth of the trench gate located in the IGBT region is greater than the depth of the trench gate located in the MOS region, and the depth of the trench gate located in the IGBT region is greater than the depth of the conductive trench located in the transition region. The depth of the base layer in the IGBT region is greater than the depth of the first conductive trench located at the junction of the transition region and the IGBT region.

[0048] The above embodiments have the following beneficial effects: a deeper trench gate in the IGBT region can enhance the conductivity modulation effect, reduce the on-state voltage drop, and guide the electric field to extend into the bulk, thereby reducing the surface electric field strength and increasing the breakdown voltage. Furthermore, the base layer 204 in the IGBT region has a depth greater than the depth of the first conductive trench at its boundary, which can block the lateral leakage path and improve the lateral withstand voltage. The fact that the depth of the trench gate is the same as the depth of the conductive trench can simplify the process steps, simplify manufacturing, and improve production efficiency.

[0049] In some embodiments, the base layer in the IGBT region, the base layer in the transition region, and the base layer in the MOS region have equal depths, or

[0050] The depth of the base layer in the transition region and the depth of the base layer in the MOS region are both less than the depth of the base layer in the IGBT region.

[0051] The above embodiments have the following beneficial effects: the IGBT region requires more hole injection to maintain conductance modulation, and a deeper base layer helps to store more carriers in the drift layer and reduce the on-state voltage drop. In the MOS region, a shallower base layer helps to reduce channel resistance, thereby reducing conduction losses, and also helps to improve switching speed by reducing carrier transit time. The same base layer depth can simplify the manufacturing process and improve production efficiency.

[0052] In some embodiments, the doping concentration of the base layer in the IGBT region is greater than the doping concentration of the base layer in the transition region and the base layer in the MOS region.

[0053] The above embodiments have the following beneficial effects: different doping concentrations result in different thresholds for the IGBT region and the MOS region. Since the thresholds are different, there is no need for complex timing control to coordinate the switching of the two regions, which is beneficial to the control of the drive circuit. This can reduce the complexity of the control circuit, reduce costs, and improve the system response speed.

[0054] In some embodiments, the semiconductor device further includes:

[0055] An emitter layer is disposed on the surface of the first main surface side of the base layer and located in the IGBT region and the MOS region. The trench gate also penetrates the emitter layer, and the emitter layer has a first conductivity type.

[0056] The above embodiments have the following beneficial effects: In the IGBT region, the emitter layer acts as a carrier injection source, injecting a small number of carriers (e.g., electrons) into the base of the IGBT region. The injected carriers drift and diffuse to the collector, forming a conduction current, thereby reducing the on-resistance and conduction loss. In the MOS region, the emitter layer acts as the source of the MOS region, providing a low-resistance current path, reducing the on-resistance of the MOS device, and reducing conduction loss.

[0057] In some embodiments, the semiconductor device further includes:

[0058] A cathode layer is disposed on the second main surface side of the semiconductor substrate relative to the drift layer and opposite to the MOS region, wherein the cathode layer has a first conductivity type and the area of ​​the cathode layer is smaller than the area of ​​the MOS region;

[0059] A collector layer is disposed on the second main surface side of the semiconductor substrate relative to the drift layer and opposite to the IGBT region, the transition region and part of the MOS region, and the collector layer has a second conductivity type.

[0060] The above embodiments have the following beneficial effects: In the MOS region, a cathode layer is provided on the second main surface corresponding to the region where the emitter layer is provided, thereby forming an effective MOS electron channel flow path. The area of ​​the cathode layer is smaller than the area of ​​the MOS region, so that the collector layer is located at the junction of the transition region and the IGBT region, thereby reducing the boundary region of the MOS region where holes flow in.

[0061] In some embodiments, the semiconductor device further includes:

[0062] An insulating isolation layer covers the first main surface of the semiconductor substrate. Multiple contact holes are respectively provided in the insulating isolation layer in the IGBT region and the MOS region, and each contact hole exposes a portion of the emitter layer.

[0063] A conductive metal layer covers the insulating isolation layer and fills the contact holes to electrically connect the emitter layer, wherein no contact holes are provided in the insulating isolation layer of the transition region, so that the base layer in the transition region is floating.

[0064] The above embodiments have the following beneficial effects: the insulating isolation layer isolates the trench gate from the conductive metal layer, while the conductive metal layer realizes the electrical connection with the emitter layer in the IGBT region and the MOS region, so as to realize the connection between the emitter layer in the IGBT region and the MOS region and the external circuit through the conductive metal layer. The floating base layer can prevent the carriers in the transition region from leaking to the external circuit through the contact hole, thereby reducing the static power consumption of the device and improving the overall energy efficiency.

[0065] In some embodiments, in the top view of the semiconductor device, the IGBT region has a plurality of third trench gates extending along the second direction and spaced apart along the third direction. The plurality of third trench gates include at least one dummy trench gate and a plurality of active trench gates, wherein the dummy trench gate and the active trench gate are electrically isolated, wherein the dummy trench gate is electrically connected to the emitter layer.

[0066] The above embodiments have the following beneficial effects: by setting a pseudo-trench gate as an electric field buffer structure and connecting it to the emitter (usually the emitter is connected to a low potential), the electric field lines around the trench gate are uniformly distributed, avoiding local peak electric fields and improving the blocking voltage of the device. Furthermore, although the pseudo-trench does not participate in conduction, it has the ability to adjust the lateral diffusion of charge carriers (electrons / holes) in the drift region, making the conduction current more uniform, reducing the conduction voltage drop, and improving thermal stability.

[0067] In some embodiments, the number of pseudo trench gates is multiple, the multiple pseudo trench gates are divided into multiple groups, the multiple groups of pseudo trench gates and the multiple active trench gates are alternately distributed in the third direction, and when each group of pseudo trench gates includes at least two adjacent pseudo trench gates, the side of each group of pseudo trench gates near the transition region is connected.

[0068] The above embodiments have the following beneficial effects: By arranging the pseudo trench gate in the above manner, the electric field lines around the trench gate can be evenly distributed, avoiding local peak electric fields and improving the blocking voltage of the device. Furthermore, by connecting two adjacent pseudo trench gates on the side near the transition region, the electric field concentration on the side of the pseudo trench gate near the transition region can be prevented.

[0069] In some embodiments, the IGBT region includes one or more MOS cell regions, each group of MOS cell regions including a MOS region and a transition region surrounding the MOS region.

[0070] The above embodiments have the following beneficial effects: the combined design of the MOS region and the transition region can optimize the accumulation and release of charge carriers during the switching process, reduce switching losses, and improve switching speed. Attached Figure Description

[0071] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0072] In the attached image:

[0073] Figure 1 A top view of a semiconductor device according to a specific embodiment of the present invention is shown;

[0074] Figure 2A Shown Figure 1 Enlarged view of the first embodiment within the dashed line portion;

[0075] Figure 2B Shown Figure 2A A magnified view of the arc-shaped structure at the boundary of the intermediate connection trench;

[0076] Figure 3 Shown Figure 1 Enlarged view of the first embodiment within the dashed line portion;

[0077] Figure 4 A cross-sectional view of a semiconductor device according to a specific embodiment of the present invention is shown in a third-party direction;

[0078] Figure 5 A top view of a semiconductor device according to another specific embodiment of the present invention is shown.

[0079] Figure label:

[0080] 10 IGBT area; 10a gate pad; 11 MOS cell area; 11a MOS region; 11b transition region; 12 grounding trench; 200 semiconductor substrate; 201 first main surface; 202 second main surface; 203 drift layer; 204 base layer; 205 trench gate; 2051 first trench gate; 2052 second trench gate; 2053 third trench gate; 2054 fourth trench gate; 2011 first side; 2012 second side; 2013 third side; 2014 fourth side; 206 conductive trench; 2061 first conductive trench; 2062 second conductive trench; 207 insulating film; 208 emitter layer; 209 diffusion layer; 210 collector layer; 211 cathode layer; 212 insulating isolation layer; 213 contact hole; 214 conductive metal layer; 215 buffer layer; 216 collector electrode; 2053a pseudo trench gate; 2053b active trench gate. Detailed Implementation

[0081] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0082] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0083] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0084] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotational or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0085] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0086] Generally, MOSFETs have higher losses than IGBT modules under high current conditions, while IGBTs have higher losses than MOSFETs under low current or high frequency conditions. Therefore, modules that only install MOSFET chips or only install IGBT chips have limited applicable current and frequency ranges, making them difficult to use in a wide range of applications.

[0087] In view of the above problems, this application provides a semiconductor device. (Reference) Figures 1 to 5 , Figure 1 This is a top view of a semiconductor device according to a specific embodiment of this application. Figure 1 As shown, the semiconductor device has an IGBT region 10, within which one or more island-shaped MOS cell regions 11 are included. Each MOS cell region 11 includes a MOS region 11a and a transition region 11b surrounding the MOS region. A gate pad 10a is provided at a portion of the IGBT region 10, through which electrical connections with external circuitry can be achieved. The combined design of the MOS region and the transition region optimizes the accumulation and release of charge carriers during the switching process, reduces switching losses, and improves switching speed.

[0088] The number of groups of MOS cell regions 11 can be reasonably set according to actual needs. When there are multiple groups of MOS cell regions 11, the multiple groups of MOS cell regions 11 can be arranged at equal intervals or at unequal intervals, or arranged in an array, or any other suitable arrangement.

[0089] Figure 2A yes Figure 1 An enlarged view of the dotted line portion, as shown below. Figure 2A As shown, the transition region 11b surrounds the MOS region 11a, and the IGBT region 10 surrounds the transition region 11b. The IGBT region 10 includes an IGBT device, and the MOS region 11a includes a MOSFET. The semiconductor device includes:

[0090] Semiconductor substrate 200 has a first main surface 201 and a second main surface 202 disposed opposite to each other along a first direction;

[0091] A drift layer 203 is disposed within the semiconductor substrate 200 and located between the first main surface 201 and the second main surface 202, and has a first conductivity type;

[0092] A base layer 204, disposed within the semiconductor substrate 200 and located on the side of the drift layer 203 near the first main surface 201, has a second conductivity type; wherein,

[0093] The IGBT region 10, the transition region 11b, and the MOS region 11a each include a conductive structure that extends from the first main surface 201 through the base layer and is partially located in the drift layer 203, wherein the sidewalls of the conductive structure are also surrounded by an insulating film 207.

[0094] Within the IGBT region 10 and the MOS region 11a, the conductive structure serves as the trench gate 205, and the insulating film 207 serves as the gate dielectric layer.

[0095] Within the transition region 11b, the conductive structure is used as a conductive trench 206. There are multiple conductive trenches 206. In the top view of the semiconductor device, the multiple conductive trenches 206 intersect. The multiple conductive trenches 206 include at least one first conductive trench 2061 extending along a second direction and at least one second conductive trench 2062 extending along a third direction. The second direction and the third direction are both perpendicular to the first direction. The first direction and the second direction intersect, for example, the first direction and the second direction are perpendicular.

[0096] By providing the transition region 11b between the IGBT region 10 and the MOS region 11a, the IGBT region 10 is separated from the MOS region 11a. The trench gate 205 of the IGBT region 10 and the conductive trench 206 of the transition region 11b are electrically isolated, while the trench gate 205 of the MOS region 11a and the conductive trench 206 of the transition region 11b are electrically connected.

[0097] For example, the conductive structure may include trenches filled in the semiconductor substrate, such as polysilicon, as a conductive material, and an insulating film 207 as a gate dielectric layer, the material of which includes, for example, silicon oxide or other suitable materials.

[0098] The above embodiments have the following beneficial effects: By simultaneously setting an IGBT region and a MOS region in the semiconductor device, and setting a transition region between the IGBT region and the MOS region, the IGBT region and the MOS region are separated, thereby combining the advantages of IGBT and MOSFET. The MOSFET is responsible for high frequency and low current, while the IGBT is responsible for low frequency and high current. When the current is high, the IGBT mainly operates; when the current is low or the frequency is high, the MOSFET mainly operates, reducing switching losses. In this way, the use of both can be automatically switched or coordinated under different operating conditions, thereby optimizing the overall efficiency over a wider range of current and frequency applications. It can cover a wider range of current and frequency applications. Furthermore, through the electrical isolation between the trench gate of the IGBT region and the conductive trench of the transition region, the electric field interference between the IGBT region and the MOS region can be reduced, improving the stability and reliability of the device. By electrically connecting the conductive trench of the transition region to the trench gate of the MOS region, the potential gradient can be adjusted through the transition region, thereby optimizing the electric field distribution.

[0099] The following is in conjunction with the appendix Figure 1 To be continued Figure 5 The above structures will be described in detail. In the following description, N and P represent the conductivity type of the semiconductor device. In the embodiments of this application, the first conductivity type is set as N-type and the second conductivity type is set as P-type.

[0100] For example, as shown in FIG2, there is a gap between the conductive trench 206 located around the transition region 11b and the trench gate of the adjacent IGBT region 10. By setting this gap, the transition region 11b is electrically isolated from the IGBT region 10. In some examples, the gap may also be filled with an insulating layer such as silicon oxide, silicon nitride, or other insulating layers.

[0101] For example, as shown in FIG2, in the top view of the semiconductor device, the MOS region 11a has a plurality of first trench gates 2051 extending along the second direction and spaced apart along the third direction, and at least two second trench gates 2052 extending along the third direction and connected to the plurality of first trench gates. The first trench gates 2051 and second trench gates 2052 located at the edge of the MOS region form a ring, and the plurality of strip-shaped first trench gates 2051 are surrounded by the ring. The two ends of the plurality of first trench gates 2051 are respectively connected to the inner wall of the ring. Optionally, the first trench gates 2051 and second trench gates 2052 located at the edge of the MOS region form a rectangular ring or other suitable shape. By providing a plurality of first trench gates 2051 and second trench gates 2052 in the MOS region 11a, the number of trench gates in the horizontal and vertical directions is increased, which can increase the number of conductive channels per unit area, thereby reducing the on-resistance. At the same time, the ring-shaped edge enclosure helps to achieve uniform current distribution, reduce edge effects, and improve withstand voltage capability.

[0102] Exemplarily, in the top view of the semiconductor device, the MOS region has a first side 2011 and a second side 2012 opposite to each other along the second direction, and a third side 2013 and a fourth side 2014 opposite to each other along the third direction. Outside the first side 2011 and the second side 2012, the transition region 11b includes a plurality of first conductive trenches 2061 and at least one second conductive trench 2062, with the plurality of first conductive trenches 2061 and at least one second conductive trench located on the same side... The transition region 11b, outside the third side 2013 and outside the fourth side 2014, includes a plurality of first conductive trenches 2061, which are electrically connected by at least one second conductive trench 2062 located outside the first side 2011 and / or the second side 2012, and has a plurality of first conductive trenches 2061 and a plurality of second conductive trenches 2062 at the boundary of the transition region 11b, which together form at least one annular trench. The first conductive trench 2061 provides a low-resistance lateral path to eliminate current congestion, while the second conductive trench 2062 enhances longitudinal carrier injection. The arrangement of the first conductive trench 2061 and the second conductive trench 2062 can optimize the current flow path and reduce on-resistance, especially in the transition region 11b, where the current needs to switch between the MOS region 11a and the IGBT region 10. A good conductive trench design can reduce the impedance of the current path and reduce losses. Furthermore, the annular trench formed by the first conductive trench 2061 and the second conductive trench 2062 can adjust the electric field distribution and avoid excessively high local electric fields.

[0103] Optionally, for example, Figure 2A As shown, there are multiple first conductive trenches 2061 and multiple second conductive trenches 2062 at the boundary of the transition region 11b. The multiple first conductive trenches 2061 and multiple second conductive trenches 2062 form two annular trenches, and the two annular trenches have a generally same center. One of them surrounds the other and is spaced apart from each other. The two ends of the first conductive trench 2061 located in the inner annular trench can also extend and connect to the annular trench located in the outer annular trench. In addition, there are multiple first conductive trenches 2061 connected to the trench gate of the outer annular trench of the MOS region outside the first side and the second side of the MOS region. The multiple first conductive trenches 2061 are arranged at intervals in the third direction. The interval can be equal or unequal.

[0104] Exemplarily, a portion of the conductive structure also serves as a grounding trench 12, thereby reducing the area at the junction. In the top view of the semiconductor device, the opposite ends of the first conductive trench 2061 at the outermost boundary of the transition region 11b are respectively connected to the grounding trench 12. The grounding trench 12 extends outward along the second direction towards the transition region 11b. The width of the grounding trench 12 is greater than the width of the conductive trench 206. That is, the grounding trench 12 connected to the opposite ends of the first conductive trench 2061 at the outermost boundary is wider than the first conductive trench 2061 at the outermost boundary. By using a wider grounding trench, it is helpful to reduce contact resistance. At the same time, placing the grounding trench at the edge can reduce electric field concentration in the IGBT area and avoid the risk of breakdown. The thinner portion in the middle corresponds to the conductive trench in the transition region, which helps to maintain an appropriate electric field gradient, thereby improving the overall withstand voltage energy. Exemplarily, as Figure 2B The junction between the grounding trench 12 and the first conductive trench 2061 to which it is connected is constructed in an arc shape (the structural shape within the dashed elliptical box in Figure 2). This arc-shaped transition allows for a more uniform current distribution at the junction, reducing electric field concentration at the junction of the grounding trench and the first conductive trench. The grounding trench 12 allows the trench gate of the MOS region and the conductive trench of the transition region to be led out, facilitating the electrical connection between the trench gate of the MOS region, the conductive trench of the transition region, and external circuitry. Optionally, the grounding trench 12 can also be used to electrically connect the transition regions of two adjacent MOS cell regions.

[0105] In some examples, the centerline of the grounding trench 12 and the first conductive trench 2061 to which it is connected coincides along the second direction. By making them coincide, a larger contact area between them can be ensured as much as possible, thereby reducing the contact resistance between them. In other examples, the centerline of the grounding trench 12 and the first conductive trench 2061 to which it is connected may not coincide along the second direction.

[0106] Optionally, the width of the grounding trench 12 is the same as the width of the trench gate 205 of the adjacent IGBT regions to reduce the electric field concentration in the IGBT regions. It is worth mentioning that "same" here means "largely the same" or "basically the same".

[0107] In one exemplary embodiment, at least one conductive trench 206 in the transition region 11b and a gate trench in their respective corresponding MOS region 11a are integrally formed as a straight trench. For example, the two ends of a straight trench are considered as conductive trenches 206, and the middle region of the straight trench is considered as a gate trench in the MOS region 11a. This not only reduces manufacturing steps and lowers costs, but also makes the current transmission between the MOS region 11a and the transition region 11b smoother, reduces interface resistance, thereby reducing conduction losses. At the same time, it also helps to improve the uniformity of the electric field distribution, avoids electric field concentration caused by structural discontinuity, and thus improves the withstand voltage capability. In another example, at least some of the conductive trenches in the transition region 11b and at least some of the trench gates in the MOS region 11a share the same conductive structure. For example, a plurality of first conductive trenches 2061 extending along the second direction in the transition region 11b and a plurality of trench gates 205 extending along the second direction in the MOS region 11a share the same conductive structure. This not only reduces manufacturing steps and lowers costs, but also makes the current transmission between the MOS region 11a and the transition region 11b smoother, reduces interface resistance, thereby reducing conduction losses. At the same time, it also helps to improve the uniformity of the electric field distribution, avoids electric field concentration caused by structural discontinuity, and thus improves the withstand voltage capability.

[0108] For example, such as Figure 2A As shown, the IGBT region 10 has a plurality of third trench gates 2053 extending along a second direction and spaced apart along a third direction, and a plurality of fourth trench gates 2054 extending along the third direction. In the second direction, the plurality of third trench gates 2053 and fourth trench gates 2054, spaced apart by a transition region 11b, intersect. This arrangement of the third and fourth trench gates allows for more effective control of carrier distribution, improving the IGBT's conduction performance. Furthermore, it ensures a uniform current distribution within the IGBT region, avoiding excessively high local current density, reducing the risk of hotspots, and improving the device's reliability and stability.

[0109] It is worth mentioning that within the IGBT region, multiple third trench gates 2053 can all be active trench gates, meaning they can all be connected to external circuits. The external circuits can then control the active trench gates to control the IGBT's on or off state.

[0110] In other examples, such as Figure 5As shown, the plurality of third trench gates 2053 include at least one dummy trench gate 2053a and a plurality of active trench gates 2053b, wherein the dummy trench gate 2053a and the active trench gate 2053b are electrically isolated, and the dummy trench gate 2053a is electrically connected to the emitter layer 208. For example, a plurality of contact holes can be provided in the insulating isolation layer on the emitter layer 208 and the dummy trench gate 2053a, respectively exposing a portion of the emitter layer 208 and at least a portion of the dummy trench gate 2053a. A conductive metal layer (sometimes also called an emitter metal layer) covers the insulating isolation layer and fills the contact holes to electrically connect the emitter layer and the dummy trench gate 2053a, that is, the electrical connection between the dummy trench gate 2053a and the emitter layer 208 is achieved through the conductive metal layer. By setting a pseudo-trench gate as an electric field buffer structure and connecting it to the emitter (which is usually connected to a low potential), the electric field lines around the trench gate are uniformly distributed, avoiding local peak electric fields and improving the blocking voltage of the device. Furthermore, although the pseudo-trench does not participate in conduction, it can adjust the lateral diffusion of charge carriers (electrons / holes) in the drift region, making the conduction current more uniform, reducing the conduction voltage drop, and improving thermal stability.

[0111] like Figure 5 As shown, the dummy trench gate 2053a and the active trench gate 2053a can be arranged in any suitable manner. For example, there can be multiple dummy trench gates 2053a, which are divided into multiple groups. The multiple groups of dummy trench gates 2053a and the multiple active trench gates 2053a are distributed alternately in the third direction. Each group of dummy trench gates 2053a has at least one dummy trench gate 2053a.

[0112] Optionally, such as Figure 5 As shown, each group of dummy trench gates 2053a is connected on the side near the transition region. For example, each group of dummy trench gates includes two adjacent dummy trench gates 2053a connected on the side near the transition region. For example, the two adjacent dummy trench gates 2053a are connected on the side near the transition region through a trench gate that extends in a third direction. The two adjacent dummy trench gates 2053a refer to those that are spaced apart and closely adjacent, with no active trench gate between them. Arranging the dummy trench gates in this way allows for a uniform distribution of the electric field lines around the trench gate, avoiding local peak electric fields and improving the device's blocking voltage. Furthermore, connecting two adjacent dummy trench gates 2053a on the side near the transition region prevents electric field concentration on that side.

[0113] In one example, such as Figure 2AAs shown, the MOS region 11a has a plurality of first trench gates 2051 extending along the second direction and spaced apart along the third direction, and the IGBT region 10 has a plurality of third trench gates 2053 extending along the second direction and spaced apart along the third direction. The plurality of first trench gates 2051 and the plurality of third trench gates 2053 are staggered in the third direction to improve the current density of the MOS region 11a.

[0114] In another example, at least one of the first trench gates 2051 and at least one of the third trench gates 2053 are aligned upwards on the third side to reduce electric field concentration and also to simplify the manufacturing process.

[0115] In one example, the width of the conductive trench 206 in the transition region 11b is equal to the width of the trench gate 205 in the MOS region 11a, thereby reducing complexity in process steps, such as etching. The same photomask can be used, reducing manufacturing costs and improving yield. The consistency between the width of the conductive trench 206 in the transition region 11b and the width of the trench gate 205 in the MOS region 11a may contribute to a more uniform electric field distribution, reducing local electric field concentration and thus improving breakdown voltage. If the trench gate 205 in the MOS region 11a and the conductive trench 206 in the transition region 11b have the same width, structural continuity can be achieved, for example, forming a monolithic straight trench as described above. This reduces abrupt changes in the electric field at the interface, thereby enhancing the overall breakdown voltage performance of the device and potentially allowing for smoother carrier flow, reducing resistance. For example, in the on-state, the movement paths of electrons or holes are more uniform, avoiding current congestion effects caused by width variations, thereby reducing conduction losses.

[0116] In one example, the width of the trench gate 205 in IGBT region 10 is greater than the width of the trench gate 205 in MOS region 11a, thereby increasing the current density in MOS region 11a. Furthermore, the width of the trench gate 205 in IGBT region 10 is greater than the width of the conductive trench 206 in transition region 11b, thereby enhancing the conductivity modulation effect of the trench gate 205 in IGBT region 10 and reducing the on-state voltage drop. In another example, such as... Figure 3 As shown, the width of the trench gate 205 in the IGBT region 10, the width of the trench gate in the MOS region, and the width of the conductive trench in the transition region are the same. This can also reduce the number of process steps, thereby simplifying the manufacturing process.

[0117] Figure 4 This is a cross-sectional view of a semiconductor device according to a specific embodiment of the present invention, exemplarily, as shown below. Figure 4As shown, within the IGBT region 10, the spacing between adjacent trench gates 205 is a first distance A, and the spacing between the trench gate 205 extending along the second direction and the first conductive trench 2061 of the adjacent transition region 11b is a second distance B. Within the MOS region 11a, the spacing between the trench gate 205 extending along the second direction and the first conductive trench 2061 of the adjacent first conductive trench is a third distance C. The second distance B is greater than the first distance A, which allows for better isolation between the trench gate 205 in the IGBT region 10 and the first conductive trench 2061 in the transition region 11b. The first distance A is greater than the third distance C, so that while achieving electrical connection between the first conductive trench 2061 of the transition region 11b and the trench gate 205 in the MOS region 11a, the total space occupied by the MOS region 11a and the transition region 11b can be reduced by using a smaller spacing.

[0118] like Figure 4 As shown, in the IGBT region 10, a trench extends from the first main surface 201 side of the semiconductor substrate 200 through the base layer 204 to a portion of the drift layer 203. The trench is filled with conductive material through an insulating film 207 to form a trench gate 205. The conductive structural material includes, but is not limited to, polysilicon, and the insulating film 207 includes, but is not limited to, silicon dioxide.

[0119] A base layer 204 of a second conductivity type and a conductive trench 206 are provided in the transition region 11b. The trench in the transition region 11b, like the trench in the IGBT region, is located in a region extending from the first main surface 201 side of the semiconductor substrate 200 through the base layer 204 to a portion of the drift layer 203. The conductive trench 206 is formed by filling the trench in the transition region 11b with a conductive structural material through an insulating film 207. For example... Figure 2A As shown, there are multiple conductive trenches 206. In the top view of the semiconductor device, the multiple conductive trenches 206 intersect each other. The multiple conductive trenches 206 include at least one first conductive trench 2061 extending along a second direction and at least one second conductive trench 2062 extending along a third direction.

[0120] For example, the doping concentration of the base layer 204 in the transition region 11b is equal to the doping concentration of the base layer 204 in the MOS region 11a, while the doping concentration of the base layer 204 (body layer) in the IGBT region 10 is greater than the doping concentration of the base layer 204 in the transition region 11b. This results in different threshold values ​​for the IGBT region 10 and the MOS region 11a. Since the threshold values ​​are different, there is no need for complex timing control to coordinate the switching of the two regions, which is beneficial for the control of the drive circuit. This may reduce the complexity of the control circuit, reduce costs, and improve the system response speed.

[0121] For example, the depth of the base layer 204 in transition region 11b is equal to the depth of the base layer 204 in MOS region 11a, while the depth of the base layer 204 (body layer) in IGBT region 10 is greater than the depth of the base layer 204 in transition region 11b, and neither the base layer 204 depth nor the base layer 204 depth exceeds the corresponding trench depth. IGBT region 10 requires more hole injection to maintain conduction modulation. A deeper base layer 204 helps store more carriers in drift layer 203, reducing on-state voltage drop. In MOS region 11a, a shallower base layer 204 helps reduce channel resistance, thereby reducing conduction losses, and also helps improve switching speed by reducing carrier transit time. In another example, the depths of the base layer 204 in IGBT region 10, the base layer 204 in transition region 11b, and the base layer 204 in MOS region 11a are equal to simplify the manufacturing process and improve production efficiency.

[0122] For example, such as Figure 4 As shown, the depth of the trench gate 205 located in the IGBT region 10 is greater than the depth of the trench gate 205 located in the MOS region 11a, and the depth of the trench gate 205 located in the IGBT region 10 is greater than the depth of the conductive trench 206 located in the transition region 11b. The depth of the base layer 204 within the IGBT region 10 is greater than the depth of the first conductive trench 2061 located at the junction of the transition region 11b and the IGBT region 10. The deeper trench gate 205 in the IGBT region 10 can enhance the conductivity modulation effect, reduce the on-state voltage drop, and guide the electric field to extend into the bulk, thereby reducing the surface electric field strength and increasing the breakdown voltage. The greater depth of the base layer 204 in the IGBT region 10 than the depth of the first conductive trench 2061 at its junction can block the lateral leakage path and increase the lateral withstand voltage.

[0123] In another example, the depth of the trench gate 205 in the IGBT region 10, the depth of the trench gate 205 in the MOS region 11a, and the depth of the conductive trench 206 in the transition region 11b are the same, thereby simplifying the process steps, making manufacturing simple, and improving production efficiency.

[0124] like Figure 4As shown, the IGBT region 10 and the MOS region 11a have an emitter layer 208 of a first conductivity type, a diffusion layer 209 of a second conductivity type, and a trench gate 205. In the IGBT region 10 and the MOS region 11a, the emitter layer 208 is disposed on the surface layer of the base layer 204 on the first main surface 201 side, and the trench gate 205 penetrates the emitter layer 208. In the IGBT region, the emitter layer acts as a carrier injection source, injecting a minority of carriers (e.g., electrons) into the base of the IGBT region. The injected carriers drift and diffuse to the collector, forming a conduction current, thereby reducing the on-resistance and conduction loss. In the MOS region, the emitter layer acts as the source of the MOS region, providing a low-resistance current path, reducing the on-resistance of the MOS device, and reducing conduction loss.

[0125] like Figure 4 As shown, the semiconductor device also includes a collector layer 210 of a second conductivity type and a cathode layer 211 of a second conductivity type. The collector layer 210 is disposed on the second main surface 202 side opposite to the drift layer 203, and the collector layer 210 is opposite to the IGBT region 10, the transition region 11b, and part of the MOS region 11a. The cathode layer 211 is disposed on the second main surface 202 side opposite to the drift layer 203, and the cathode layer 211 is opposite to the MOS region 11a, and the area of ​​the cathode layer 211 is smaller than the area of ​​the MOS region 11a. In the MOS region 11a, the cathode layer 211 is disposed on the second main surface 202 corresponding to the region where the emitter layer 208 is disposed, thereby forming an effective MOS electron channel flow path. The area of ​​the cathode layer 211 is smaller than the area of ​​the MOS region, so that the collector layer 210 of the IGBT region extends across the transition region to cover the boundary between the transition region and the IGBT region, thereby reducing the boundary region of hole inflow into the MOS region. In some examples, the cathode layer 211 and the MOS region 11a may be opposite each other, and the area of ​​the cathode layer 211 may be approximately equal to the area of ​​the MOS region 11a.

[0126] For example, when the trench depth of the IGBT region 10 is equal to the trench depth of the transition region 11b, an emitter layer 208 is provided on the side of the trench where the IGBT region 10 and the transition region 11b are connected. Since a collector layer 210 is provided on the corresponding second main surface 202, the trench can be fully utilized, thereby improving the current carrying capacity of the IGBT.

[0127] It is worth mentioning that, in this application, the width and depth of the trench gate in the IGBT region 10, the conductive trench in the transition region, and the trench gate in the MOS region can be reasonably adjusted according to actual needs.

[0128] For example, the semiconductor device further includes an insulating isolation layer and a conductive metal layer, such as Figure 4 As shown, an insulating isolation layer 212 covering the first main surface 201 of the semiconductor substrate 200 is formed. Multiple contact holes 213 are respectively provided in the insulating isolation layer 212 in the IGBT region 10 and the MOS region, and each contact hole 213 exposes a portion of the emitter layer 208.

[0129] The conductive metal layer 214 covers the insulating isolation layer 212 and fills the contact hole 213. The conductive metal layer 214 is electrically connected to the emitter layer 208. The conductive metal layer 214 includes, but is not limited to, aluminum alloy. A dopant of the second conductivity type is injected into the corresponding contact hole 213 in the base layer 204 in the IGBT region 10 and the MOS region 11a to form a diffusion layer 209. The diffusion layer 209 serves as the lead-out region of the base layer 204. Due to its high conductivity, it can provide a low-resistance path, which is beneficial to reducing the on-resistance of the device.

[0130] No contact holes are provided in the insulating isolation layer 212 of the transition region 11b, thereby allowing the base layer 204 in the transition region 11a to float. The insulating isolation layer 212 isolates the trench gate from the conductive metal layer, while the conductive metal layer enables electrical connection with the emitter layers in the IGBT region and MOS region. This facilitates the connection between the emitter layers in the IGBT region and MOS region and external circuits through the conductive metal layer. The floating base layer prevents carriers in the transition region from leaking to external circuits through contact holes, thereby reducing the static power consumption of the device and improving overall energy efficiency.

[0131] For example, the semiconductor device further includes: a buffer layer 215 disposed on the second main surface 202 and extending toward the drift layer 203, the buffer layer 215 covering the collector layer 210 and the cathode layer 211, and a collector electrode 216 covering the collector layer 210 and the cathode layer 211 disposed on the side of the second main surface 202 away from the drift layer 203.

[0132] In the semiconductor device of this application, for an IGBT, operation is achieved by applying a positive voltage to the trench gate 205 to form an n-type channel region in a portion of the base layer 204, and by applying a positive voltage to the collector electrode 216.

[0133] When an IGBT is in operation, it accumulates electron and hole carriers in the drift layer 203, thereby reducing the on-resistance through conductivity modulation. In order to reduce the on-voltage of the IGBT, it is necessary to improve the carrier accumulation effect.

[0134] In the MOS region 11a, one of the conductive metal layer 214 and the collector electrode 216 functions as the drain electrode, and the other functions as the source electrode.

[0135] The following describes the state of the IGBT when it is turned on. An IGBT is a bipolar device that operates using electron and hole carriers. By applying a positive voltage to the IGBT's trench gate and collector, and grounding or applying a negative voltage to the emitter, the IGBT is turned on. Electrons flow from the conductive metal layer (i.e., the emitter metal layer) into the semiconductor substrate, pass through the collector layer, and flow into the collector electrode. Holes flow from the collector layer through the buffer layer to the emitter layer, generating conductivity modulation. Within the IGBT region 11, the current flows along the path of the p-type collector layer, n-type buffer layer, n-type drift layer, p-type base layer, and n+ type emitter layer. When the IGBT operates, electron and hole carriers accumulate in the drift layer, reducing the on-resistance through conductivity modulation. To reduce the IGBT's on-voltage, it is necessary to improve the carrier accumulation effect.

[0136] The following explanation uses the MOSFET in MOS region 11a as an example. The MOSFET has an n-channel MOS gate structure with the base layer 204, emitter layer 208, insulating film 207, trench gate 205, and drift layer 203 as the main structural elements. When the IGBT is turned on, a positive voltage is also applied to the trench gate of the MOSFET in the MOS region, the MOS channel is turned on, and electron carriers flow from the drift layer 203 through the buffer layer 215 and the cathode layer 211 to the collector electrode 216, forming a current path.

[0137] During the freewheeling phase, the IGBT's trench gate is connected to a negative voltage, and the emitter is connected to a positive voltage. When the IGBT is in the off state, hole carriers are injected from the base layer 204 to the drift layer 203, and electron carriers are injected from the cathode layer 211 to the drift layer 203. That is, in the MOS region 11a, without applying a positive voltage to the trench gate 205, the body diode can operate and undertake the freewheeling function. The electron flow direction is from bottom to top (from the emitter side to the collector side), forming a freewheeling path through the MOS transistor's body diode. If a positive voltage is still applied to the MOSFET's trench gate during freewheeling, the MOSFET channel will also conduct, working in parallel with the body diode to further reduce freewheeling losses.

[0138] During the reverse recovery phase, if the trench gate of the MOSFET remains positively charged, the MOSFET channel rapidly attracts holes from the drift region, promoting the recombination of holes and electrons. This accelerates the reverse recovery speed and reduces reverse recovery power consumption. Therefore, by controlling the voltage of the MOSFET's trench gate, the reverse recovery process can be optimized, and power consumption reduced.

[0139] This concludes the description of the structure of the semiconductor device of this application. A complete semiconductor device may also include other components, which will not be elaborated here.

[0140] The semiconductor device of this application simultaneously sets up an IGBT region and a MOS region within the semiconductor device, and sets up a transition region between the IGBT region and the MOS region, thus separating the IGBT region from the MOS region. This combines the advantages of IGBT and MOSFET. The MOSFET is responsible for high-frequency, low-current applications, while the IGBT is responsible for low-frequency, high-current applications. When the current is high, the IGBT mainly operates; when the current is low or the frequency is high, the MOSFET mainly operates, reducing switching losses. This allows for automatic switching or coordination of the use of both under different operating conditions, thereby optimizing overall efficiency over a wider range of current and frequency applications. It can cover a wider range of current and frequency applications. Furthermore, through electrical isolation between the trench gate of the IGBT region and the conductive trench of the transition region, the electric field interference between the IGBT region and the MOS region can be reduced, improving the stability and reliability of the device. By electrically connecting the conductive trench of the transition region to the trench gate of the MOS region, the potential gradient can be adjusted through the transition region, thereby optimizing the electric field distribution.

[0141] This application has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of this invention, all of which fall within the scope of protection claimed by this invention. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, The semiconductor device has an IGBT region (10), a transition region (11b), and a MOS region (11a), wherein the transition region (11b) surrounds the MOS region (11a), and the IGBT region (10) surrounds the transition region (11b). The semiconductor device includes: A semiconductor substrate (200) having a first main surface (201) and a second main surface (202) disposed opposite to each other along a first direction; A drift layer (203) is disposed within the semiconductor substrate (200) and located between the first main surface (201) and the second main surface (202), and has a first conductivity type; A base layer (204), disposed within the semiconductor substrate (200) and located on the side of the drift layer (203) near the first main surface (201), has a second conductivity type; wherein, The IGBT region (10), the transition region (11b), and the MOS region (11a) each include a conductive structure extending from the first main surface (201) through the base layer (204) and partially located in the drift layer (203), wherein the sidewalls of the conductive structure are further surrounded by an insulating film (207). Within the IGBT region (10) and the MOS region (11a), the conductive structure serves as a trench gate (205), and the insulating film (207) serves as a gate dielectric layer. Within the transition region (11b), the conductive structure serves as a conductive trench (206). There are multiple conductive trenches (206). In a top view of the semiconductor device, the multiple conductive trenches (206) intersect. Each conductive trench (206) includes at least one first conductive trench (2061) extending along a second direction and at least one second conductive trench (2062) extending along a third direction. Both the second direction and the third direction are perpendicular to the first direction, and the first direction and the second direction intersect. The trench gate (205) of the IGBT region (10) and the conductive trench (205) of the transition region (11b) are electrically isolated, while the trench gate (205) of the MOS region (11a) and the conductive trench (206) of the transition region (11b) are electrically connected.

2. The semiconductor device as claimed in claim 1, characterized in that, There is a gap between the conductive trench (206) located on the periphery of the transition region (11b) and the trench gate (205) of the adjacent IGBT region (10).

3. The semiconductor device as claimed in claim 1, characterized in that, In the top view of the semiconductor device, the MOS region (11a) has a plurality of first trench gates (2051) extending along the second direction and spaced apart along the third direction, and at least two second trench gates (2052) extending along the third direction and connected to the plurality of first trench gates (2051). The first trench gates (2051) and the second trench gates (2052) located at the boundary of the MOS region (11a) form a ring.

4. The semiconductor device as claimed in claim 1 or 3, characterized in that, In a top view of the semiconductor device, the MOS region has a first side (2011) and a second side (2012) opposite each other along the second direction, and a third side (2013) and a fourth side (2014) opposite each other along the third direction, wherein, Outside the first side (2011) and outside the second side (2012), the transition region (11b) includes a plurality of first conductive trenches (2061) and at least one second conductive trench (2062), with the plurality of first conductive trenches (2061) and at least one second conductive trench (2062) located on the same side connected together. Outside of the third side (2013) and the fourth side (2014), the transition region (11b) includes a plurality of first conductive trenches (2061) electrically connected by at least one second conductive trench (2062) located outside the first side (2011) and / or the second side (2012).

5. The semiconductor device as claimed in claim 4, characterized in that, In a top view, a plurality of first conductive trenches (2061) and a plurality of second conductive trenches (2062) are provided at the boundary of the transition region (11b), and the plurality of first conductive trenches (2061) and the plurality of second conductive trenches (2062) form at least one annular trench.

6. The semiconductor device as claimed in claim 4, characterized in that, The conductive structure also serves as a grounding trench (12). In the top view of the semiconductor device, the opposite ends of the first conductive trench (2061) at the outermost boundary of the transition region (11b) are respectively connected to the grounding trench (12). The grounding trench (12) extends outward from the transition region (11b) along the second direction, wherein the width of the grounding trench (12) is greater than the width of the conductive trench (206).

7. The semiconductor device as claimed in claim 6, characterized in that, The grounding trench (12) and the first conductive trench (2061) to which it is connected coincide along the centerline of the second direction, and / or the width of the grounding trench (12) is the same as the width of the trench gate (205) of the respective adjacent IGBT region (10).

8. The semiconductor device as claimed in claim 6, characterized in that, The junction between the electrical contact trench (12) and the first conductive trench (2061) to which it is connected is constructed in an arc shape.

9. The semiconductor device according to claim 1, characterized in that, In a top view, at least one conductive trench (206) in the transition region (11b) and a gate trench in their respective corresponding MOS region (11a) are integral straight trenches.

10. The semiconductor device as claimed in claim 1, characterized in that, In the top view of the semiconductor device, the IGBT region (10) has a plurality of third trench gates (2053) extending along the second direction and spaced apart along the third direction, and a plurality of fourth trench gates (2054) extending along the third direction, wherein, in the second direction, the plurality of third trench gates (2053) and the fourth trench gates (2054) spaced apart by the transition region (11b) intersect.

11. The semiconductor device as claimed in claim 1, characterized in that, In a top view of the semiconductor device, the MOS region (11a) has a plurality of first trench gates (2051) extending along the second direction and spaced apart along the third direction, and the IGBT region (10) has a plurality of third trench gates (2053) extending along the second direction and spaced apart along the third direction, wherein The plurality of first trench gates (2051) and the plurality of third trench gates (2053) are offset upwards from the third trench gate; and / or At least one of the first trench gates (2051) and at least one of the third trench gates (2053) are aligned upwards on the third.

12. The semiconductor device as claimed in claim 1, characterized in that, The width of the trench gate (205) located in the IGBT region (10) is greater than the width of the trench gate (205) located in the MOS region (11a), and the width of the trench gate (205) located in the IGBT region (10) is greater than the width of the conductive trench (206) located in the transition region (11b). or The width of the trench gate (205) located in the IGBT region (10), the width of the trench gate (205) located in the MOS region (11a), and the width of the conductive trench (206) located in the transition region (11b) are the same.

13. The semiconductor device as claimed in claim 1, characterized in that, The width of the trench gate (206) located in the MOS region (11a) is equal to the width of the conductive trench (206) located in the transition region (11b).

14. The semiconductor device as claimed in claim 1, characterized in that, In the second direction, the spacing between adjacent trench gates (205) in the IGBT region (10) is a first distance, the spacing between a trench gate (206) extending along the second direction in the IGBT region (10) and the first conductive trench (2061) of the adjacent transition region (11b) is a second distance, and the spacing between a trench gate (205) extending along the second direction in the MOS region (11a) and the first conductive trench (2061) of the adjacent region is a third distance, wherein the second distance is greater than the first distance, and the first distance is greater than the third distance.

15. The semiconductor device as claimed in claim 1, characterized in that, The depth of the trench gate (205) in the IGBT region (10), the depth of the trench gate (205) in the MOS region (11a), and the depth of the conductive trench (206) in the transition region (11b) are the same. or The depth of the trench gate (205) located in the IGBT region (10) is greater than the depth of the trench gate (205) located in the MOS region (11a), and the depth of the trench gate (205) located in the IGBT region (10) is greater than the depth of the conductive trench (206) located in the transition region (11b). The depth of the base layer (204) in the IGBT region (10) is greater than the depth of the first conductive trench (2061) located at the junction of the transition region (11b) and the IGBT region (10).

16. The semiconductor device as claimed in claim 1, characterized in that, The base layer (204) in the IGBT region (10), the base layer (204) in the transition region (11b), and the base layer (204) in the MOS region (11a) have equal depths, or The depth of the base layer (204) in the transition region (11b) and the depth of the base layer (204) in the MOS region (11a) are both less than the depth of the base layer (204) in the IGBT region (10).

17. The semiconductor device as claimed in claim 1, characterized in that, The doping concentration of the base layer (204) in the IGBT region (10) is greater than that of the base layer (204) in the transition region (11b) and the base layer (204) in the MOS region (11a).

18. The semiconductor device as claimed in claim 1, characterized in that, Also includes: The emitter layer (208) is disposed on the surface of the base layer (204) on the first main surface (201) side and is located in the IGBT region (10) and the MOS region (11a). The trench gate (205) also penetrates the emitter layer (208). The emitter layer (208) has a first conductivity type.

19. The semiconductor device as claimed in claim 18, characterized in that, Also includes: A cathode layer (211) is disposed on the second main surface (202) side of the semiconductor substrate (200) opposite to the drift layer (203) and opposite to the MOS region (11a), wherein the cathode layer (211) has a first conductivity type and the area of ​​the cathode layer (211) is smaller than the area of ​​the MOS region; A collector layer (210) is disposed on the second main surface (202) side of the semiconductor substrate (200) opposite to the drift layer (203) and opposite to the IGBT region (10), the transition region (11b) and part of the MOS region (11a). The collector layer (210) has a second conductivity type.

20. The semiconductor device as claimed in claim 18, characterized in that, Also includes: An insulating isolation layer (212) covers the first main surface (201) of the semiconductor substrate (200). A plurality of contact holes (213) are respectively provided in the insulating isolation layer (212) in the IGBT region (10) and the MOS region (11a), and each contact hole (213) exposes a portion of the emitter layer (208). A conductive metal layer (214) covers the insulating isolation layer (212) and fills the contact hole (213) to electrically connect the emitter layer (208), wherein no contact hole (213) is provided in the insulating isolation layer (212) of the transition region (11b), so that the base layer (204) in the transition region (11b) is floating.

21. The semiconductor device as claimed in claim 18, characterized in that, In the top view of the semiconductor device, the IGBT region (10) has a plurality of third trench gates (2053) extending along the second direction and spaced apart along the third direction. The plurality of third trench gates (2053) include at least one dummy trench gate (2053a) and a plurality of active trench gates (2053b). The dummy trench gate (2053a) and the active trench gate (2053b) are electrically isolated. The dummy trench gate is electrically connected to the emitter layer (208).

22. The semiconductor device as claimed in claim 21, characterized in that, The number of pseudo trench gates (2053a) is multiple, and the multiple pseudo trench gates (2053a) are divided into multiple groups. The multiple groups of pseudo trench gates (2053a) and the multiple active trench gates (2053a) are alternately distributed in the third direction. When each group of pseudo trench gates (2053a) includes at least two adjacent pseudo trench gates (2053a), the side of each group of pseudo trench gates (2053a) closest to the transition region is connected.

23. The semiconductor device according to any one of claims 1 to 22, characterized in that, The IGBT region (10) includes one or more MOS cell regions (11), each group of MOS cell regions (1) includes a MOS region (11a) and a transition region (11b) surrounding the MOS region (11a).

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